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116 lines
4.0 KiB
Diff
116 lines
4.0 KiB
Diff
From 03b7b5f983091bca17e9c163832fcde56971d7d1 Mon Sep 17 00:00:00 2001
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From: Daniel Vetter <daniel.vetter@ffwll.ch>
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Date: Wed, 18 May 2016 18:47:11 +0200
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Subject: drm/i915/psr: Try to program link training times correctly
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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The default of 0 is 500us of link training, but that's not enough for
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some platforms. Decoding this correctly means we're using 2.5ms of
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link training on these platforms, which fixes flickering issues
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associated with enabling PSR.
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v2: Unbotch the math a bit.
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v3: Drop debug hunk.
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v4: Improve commit message.
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Tested-by: Lyude <cpaul@redhat.com>
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Cc: Lyude <cpaul@redhat.com>
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Cc: stable@vger.kernel.org
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Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95176
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Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
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Cc: Sonika Jindal <sonika.jindal@intel.com>
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Cc: Durgadoss R <durgadoss.r@intel.com>
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Cc: "Pandiyan, Dhinakaran" <dhinakaran.pandiyan@intel.com>
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Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
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Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
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Tested-by: fritsch@kodi.tv
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Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
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Link: http://patchwork.freedesktop.org/patch/msgid/1463590036-17824-2-git-send-email-daniel.vetter@ffwll.ch
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(cherry picked from commit 50db139018f9c94376d5f4db94a3bae65fdfac14)
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Signed-off-by: Jani Nikula <jani.nikula@intel.com>
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---
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drivers/gpu/drm/i915/intel_psr.c | 55 ++++++++++++++++++++++++++++++++++------
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1 file changed, 47 insertions(+), 8 deletions(-)
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diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
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index c3abae4..a788d1e 100644
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--- a/drivers/gpu/drm/i915/intel_psr.c
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+++ b/drivers/gpu/drm/i915/intel_psr.c
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@@ -280,7 +280,10 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
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* with the 5 or 6 idle patterns.
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*/
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uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
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- uint32_t val = 0x0;
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+ uint32_t val = EDP_PSR_ENABLE;
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+
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+ val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
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+ val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
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if (IS_HASWELL(dev))
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val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
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@@ -288,14 +291,50 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
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if (dev_priv->psr.link_standby)
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val |= EDP_PSR_LINK_STANDBY;
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- I915_WRITE(EDP_PSR_CTL, val |
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- max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
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- idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
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- EDP_PSR_ENABLE);
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+ if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
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+ val |= EDP_PSR_TP1_TIME_2500us;
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+ else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
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+ val |= EDP_PSR_TP1_TIME_500us;
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+ else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
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+ val |= EDP_PSR_TP1_TIME_100us;
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+ else
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+ val |= EDP_PSR_TP1_TIME_0us;
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+
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+ if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
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+ val |= EDP_PSR_TP2_TP3_TIME_2500us;
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+ else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
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+ val |= EDP_PSR_TP2_TP3_TIME_500us;
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+ else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
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+ val |= EDP_PSR_TP2_TP3_TIME_100us;
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+ else
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+ val |= EDP_PSR_TP2_TP3_TIME_0us;
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+
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+ if (intel_dp_source_supports_hbr2(intel_dp) &&
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+ drm_dp_tps3_supported(intel_dp->dpcd))
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+ val |= EDP_PSR_TP1_TP3_SEL;
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+ else
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+ val |= EDP_PSR_TP1_TP2_SEL;
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+
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+ I915_WRITE(EDP_PSR_CTL, val);
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+
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+ if (!dev_priv->psr.psr2_support)
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+ return;
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+
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+ /* FIXME: selective update is probably totally broken because it doesn't
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+ * mesh at all with our frontbuffer tracking. And the hw alone isn't
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+ * good enough. */
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+ val = EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
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+
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+ if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
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+ val |= EDP_PSR2_TP2_TIME_2500;
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+ else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
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+ val |= EDP_PSR2_TP2_TIME_500;
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+ else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
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+ val |= EDP_PSR2_TP2_TIME_100;
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+ else
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+ val |= EDP_PSR2_TP2_TIME_50;
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- if (dev_priv->psr.psr2_support)
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- I915_WRITE(EDP_PSR2_CTL, EDP_PSR2_ENABLE |
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- EDP_SU_TRACK_ENABLE | EDP_PSR2_TP2_TIME_100);
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+ I915_WRITE(EDP_PSR2_CTL, val);
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}
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static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
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--
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cgit v0.12
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