Initial Commit

thirdparty/capstone/arch/AArch64/AArch64AddressingModes.h

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+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically translated source file from LLVM. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Only small edits allowed. */
+/* For multiple similar edits, please create a Patch for the translator. */
+
+/* Capstone's C++ file translator: */
+/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
+
+//===- AArch64AddressingModes.h - AArch64 Addressing Modes ------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the AArch64 addressing mode implementation stuff.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64ADDRESSINGMODES_H
+#define LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64ADDRESSINGMODES_H
+
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+#include <capstone/platform.h>
+
+#include "../../MathExtras.h"
+#include <assert.h>
+#include "../../MathExtras.h"
+
+#define CONCAT(a, b) CONCAT_(a, b)
+#define CONCAT_(a, b) a##_##b
+
+/// AArch64_AM - AArch64 Addressing Mode Stuff
+// CS namespace begin: AArch64_AM
+
+//===----------------------------------------------------------------------===//
+// Shifts
+//
+typedef enum ShiftExtendType {
+	AArch64_AM_InvalidShiftExtend = -1,
+	AArch64_AM_LSL = 0,
+	AArch64_AM_LSR,
+	AArch64_AM_ASR,
+	AArch64_AM_ROR,
+	AArch64_AM_MSL,
+
+	AArch64_AM_UXTB,
+	AArch64_AM_UXTH,
+	AArch64_AM_UXTW,
+	AArch64_AM_UXTX,
+
+	AArch64_AM_SXTB,
+	AArch64_AM_SXTH,
+	AArch64_AM_SXTW,
+	AArch64_AM_SXTX,
+} AArch64_AM_ShiftExtendType;
+
+/// getShiftName - Get the string encoding for the shift type.
+static inline const char *
+AArch64_AM_getShiftExtendName(AArch64_AM_ShiftExtendType ST)
+{
+	switch (ST) {
+	default:
+		assert(0 && "unhandled shift type!");
+	case AArch64_AM_LSL:
+		return "lsl";
+	case AArch64_AM_LSR:
+		return "lsr";
+	case AArch64_AM_ASR:
+		return "asr";
+	case AArch64_AM_ROR:
+		return "ror";
+	case AArch64_AM_MSL:
+		return "msl";
+	case AArch64_AM_UXTB:
+		return "uxtb";
+	case AArch64_AM_UXTH:
+		return "uxth";
+	case AArch64_AM_UXTW:
+		return "uxtw";
+	case AArch64_AM_UXTX:
+		return "uxtx";
+	case AArch64_AM_SXTB:
+		return "sxtb";
+	case AArch64_AM_SXTH:
+		return "sxth";
+	case AArch64_AM_SXTW:
+		return "sxtw";
+	case AArch64_AM_SXTX:
+		return "sxtx";
+	}
+	return NULL;
+}
+
+/// getShiftType - Extract the shift type.
+static inline AArch64_AM_ShiftExtendType AArch64_AM_getShiftType(unsigned Imm)
+{
+	switch ((Imm >> 6) & 0x7) {
+	default:
+		return AArch64_AM_InvalidShiftExtend;
+	case 0:
+		return AArch64_AM_LSL;
+	case 1:
+		return AArch64_AM_LSR;
+	case 2:
+		return AArch64_AM_ASR;
+	case 3:
+		return AArch64_AM_ROR;
+	case 4:
+		return AArch64_AM_MSL;
+	}
+}
+
+/// getShiftValue - Extract the shift value.
+static inline unsigned AArch64_AM_getShiftValue(unsigned Imm)
+{
+	return Imm & 0x3f;
+}
+
+/// getShifterImm - Encode the shift type and amount:
+///   imm:     6-bit shift amount
+///   shifter: 000 ==> lsl
+///            001 ==> lsr
+///            010 ==> asr
+///            011 ==> ror
+///            100 ==> msl
+///   {8-6}  = shifter
+///   {5-0}  = imm
+static inline unsigned AArch64_AM_getShifterImm(AArch64_AM_ShiftExtendType ST,
+						unsigned Imm)
+{
+	unsigned STEnc = 0;
+	switch (ST) {
+	default:
+		assert(0 && "Invalid shift requested");
+	case AArch64_AM_LSL:
+		STEnc = 0;
+		break;
+	case AArch64_AM_LSR:
+		STEnc = 1;
+		break;
+	case AArch64_AM_ASR:
+		STEnc = 2;
+		break;
+	case AArch64_AM_ROR:
+		STEnc = 3;
+		break;
+	case AArch64_AM_MSL:
+		STEnc = 4;
+		break;
+	}
+	return (STEnc << 6) | (Imm & 0x3f);
+}
+
+//===----------------------------------------------------------------------===//
+// Extends
+//
+/// getArithShiftValue - get the arithmetic shift value.
+static inline unsigned AArch64_AM_getArithShiftValue(unsigned Imm)
+{
+	return Imm & 0x7;
+}
+
+/// getExtendType - Extract the extend type for operands of arithmetic ops.
+static inline AArch64_AM_ShiftExtendType AArch64_AM_getExtendType(unsigned Imm)
+{
+	switch (Imm) {
+	default:
+		assert(0 && "Compiler bug!");
+	case 0:
+		return AArch64_AM_UXTB;
+	case 1:
+		return AArch64_AM_UXTH;
+	case 2:
+		return AArch64_AM_UXTW;
+	case 3:
+		return AArch64_AM_UXTX;
+	case 4:
+		return AArch64_AM_SXTB;
+	case 5:
+		return AArch64_AM_SXTH;
+	case 6:
+		return AArch64_AM_SXTW;
+	case 7:
+		return AArch64_AM_SXTX;
+	}
+}
+
+static inline AArch64_AM_ShiftExtendType
+AArch64_AM_getArithExtendType(unsigned Imm)
+{
+	return AArch64_AM_getExtendType((Imm >> 3) & 0x7);
+}
+
+/// Mapping from extend bits to required operation:
+///   shifter: 000 ==> uxtb
+///            001 ==> uxth
+///            010 ==> uxtw
+///            011 ==> uxtx
+///            100 ==> sxtb
+///            101 ==> sxth
+///            110 ==> sxtw
+///            111 ==> sxtx
+static inline unsigned
+AArch64_AM_getExtendEncoding(AArch64_AM_ShiftExtendType ET)
+{
+	switch (ET) {
+	default:
+		assert(0 && "Invalid extend type requested");
+	case AArch64_AM_UXTB:
+		return 0;
+		break;
+	case AArch64_AM_UXTH:
+		return 1;
+		break;
+	case AArch64_AM_UXTW:
+		return 2;
+		break;
+	case AArch64_AM_UXTX:
+		return 3;
+		break;
+	case AArch64_AM_SXTB:
+		return 4;
+		break;
+	case AArch64_AM_SXTH:
+		return 5;
+		break;
+	case AArch64_AM_SXTW:
+		return 6;
+		break;
+	case AArch64_AM_SXTX:
+		return 7;
+		break;
+	}
+}
+
+/// getArithExtendImm - Encode the extend type and shift amount for an
+///                     arithmetic instruction:
+///   imm:     3-bit extend amount
+///   {5-3}  = shifter
+///   {2-0}  = imm3
+static inline unsigned
+AArch64_AM_getArithExtendImm(AArch64_AM_ShiftExtendType ET, unsigned Imm)
+{
+	return (AArch64_AM_getExtendEncoding(ET) << 3) | (Imm & 0x7);
+}
+
+/// getMemDoShift - Extract the "do shift" flag value for load/store
+/// instructions.
+static inline bool AArch64_AM_getMemDoShift(unsigned Imm)
+{
+	return (Imm & 0x1) != 0;
+}
+
+/// getExtendType - Extract the extend type for the offset operand of
+/// loads/stores.
+static inline AArch64_AM_ShiftExtendType
+AArch64_AM_getMemExtendType(unsigned Imm)
+{
+	return AArch64_AM_getExtendType((Imm >> 1) & 0x7);
+}
+
+/// getExtendImm - Encode the extend type and amount for a load/store inst:
+///   doshift:     should the offset be scaled by the access size
+///   shifter: 000 ==> uxtb
+///            001 ==> uxth
+///            010 ==> uxtw
+///            011 ==> uxtx
+///            100 ==> sxtb
+///            101 ==> sxth
+///            110 ==> sxtw
+///            111 ==> sxtx
+///   {3-1}  = shifter
+///   {0}  = doshift
+static inline unsigned AArch64_AM_getMemExtendImm(AArch64_AM_ShiftExtendType ET,
+						  bool DoShift)
+{
+	return (AArch64_AM_getExtendEncoding(ET) << 1) | (unsigned)DoShift;
+}
+
+static inline uint64_t AArch64_AM_ror(uint64_t elt, unsigned size)
+{
+	return ((elt & 1) << (size - 1)) | (elt >> 1);
+}
+
+/// processLogicalImmediate - Determine if an immediate value can be encoded
+/// as the immediate operand of a logical instruction for the given register
+/// size.  If so, return true with "encoding" set to the encoded value in
+/// the form N:immr:imms.
+static inline bool AArch64_AM_processLogicalImmediate(uint64_t Imm,
+						      unsigned RegSize,
+						      uint64_t *Encoding)
+{
+	if (Imm == 0ULL || Imm == ~0ULL ||
+	    (RegSize != 64 &&
+	     (Imm >> RegSize != 0 || Imm == (~0ULL >> (64 - RegSize)))))
+		return false;
+
+	// First, determine the element size.
+	unsigned Size = RegSize;
+
+	do {
+		Size /= 2;
+		uint64_t Mask = (1ULL << Size) - 1;
+
+		if ((Imm & Mask) != ((Imm >> Size) & Mask)) {
+			Size *= 2;
+			break;
+		}
+	} while (Size > 2);
+
+	// Second, determine the rotation to make the element be: 0^m 1^n.
+	uint32_t CTO, I;
+	uint64_t Mask = ((uint64_t)-1LL) >> (64 - Size);
+	Imm &= Mask;
+
+	if (isShiftedMask_64(Imm)) {
+		I = CountTrailingZeros_64(Imm);
+
+		CTO = CountTrailingOnes_64(Imm >> I);
+	} else {
+		Imm |= ~Mask;
+		if (!isShiftedMask_64(~Imm))
+			return false;
+
+		unsigned CLO = CountLeadingOnes_64(Imm);
+		I = 64 - CLO;
+		CTO = CLO + CountTrailingOnes_64(Imm) - (64 - Size);
+	}
+
+	// Encode in Immr the number of RORs it would take to get *from* 0^m 1^n
+	// to our target value, where I is the number of RORs to go the opposite
+	// direction.
+
+	unsigned Immr = (Size - I) & (Size - 1);
+
+	// If size has a 1 in the n'th bit, create a value that has zeroes in
+	// bits [0, n] and ones above that.
+	uint64_t NImms = ~(Size - 1) << 1;
+
+	// Or the CTO value into the low bits, which must be below the Nth bit
+	// bit mentioned above.
+	NImms |= (CTO - 1);
+
+	// Extract the seventh bit and toggle it to create the N field.
+	unsigned N = ((NImms >> 6) & 1) ^ 1;
+
+	*Encoding = (N << 12) | (Immr << 6) | (NImms & 0x3f);
+	return true;
+}
+
+/// isLogicalImmediate - Return true if the immediate is valid for a logical
+/// immediate instruction of the given register size. Return false otherwise.
+static inline bool AArch64_AM_isLogicalImmediate(uint64_t imm, unsigned regSize)
+{
+	uint64_t encoding = 0;
+	return AArch64_AM_processLogicalImmediate(imm, regSize, &encoding);
+}
+
+/// encodeLogicalImmediate - Return the encoded immediate value for a logical
+/// immediate instruction of the given register size.
+static inline uint64_t AArch64_AM_encodeLogicalImmediate(uint64_t imm,
+							 unsigned regSize)
+{
+	uint64_t encoding = 0;
+	bool res = AArch64_AM_processLogicalImmediate(imm, regSize, &encoding);
+
+	(void)res;
+	return encoding;
+}
+
+/// decodeLogicalImmediate - Decode a logical immediate value in the form
+/// "N:immr:imms" (where the immr and imms fields are each 6 bits) into the
+/// integer value it represents with regSize bits.
+static inline uint64_t AArch64_AM_decodeLogicalImmediate(uint64_t val,
+							 unsigned regSize)
+{
+	// Extract the N, imms, and immr fields.
+	unsigned N = (val >> 12) & 1;
+	unsigned immr = (val >> 6) & 0x3f;
+	unsigned imms = val & 0x3f;
+
+	int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f));
+	assert(len >= 1);
+
+	unsigned size = (1 << len);
+	unsigned R = immr & (size - 1);
+	unsigned S = imms & (size - 1);
+
+	uint64_t pattern = (1ULL << (S + 1)) - 1;
+	for (unsigned i = 0; i < R; ++i)
+		pattern = AArch64_AM_ror(pattern, size);
+
+	// Replicate the pattern to fill the regSize.
+	while (size != regSize) {
+		pattern |= (pattern << size);
+		size *= 2;
+	}
+	return pattern;
+}
+
+/// isValidDecodeLogicalImmediate - Check to see if the logical immediate value
+/// in the form "N:immr:imms" (where the immr and imms fields are each 6 bits)
+/// is a valid encoding for an integer value with regSize bits.
+static inline bool AArch64_AM_isValidDecodeLogicalImmediate(uint64_t val,
+							    unsigned regSize)
+{
+	// Extract the N and imms fields needed for checking.
+	unsigned N = (val >> 12) & 1;
+	unsigned imms = val & 0x3f;
+
+	if (regSize == 32 && N != 0) // undefined logical immediate encoding
+		return false;
+	int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f));
+	if (len < 0)		     // undefined logical immediate encoding
+		return false;
+	unsigned size = (1 << len);
+	unsigned S = imms & (size - 1);
+	if (S == size - 1) // undefined logical immediate encoding
+		return false;
+
+	return true;
+}
+
+//===----------------------------------------------------------------------===//
+// Floating-point Immediates
+//
+static inline float AArch64_AM_getFPImmFloat(unsigned Imm)
+{
+	// We expect an 8-bit binary encoding of a floating-point number here.
+
+	uint8_t Sign = (Imm >> 7) & 0x1;
+	uint8_t Exp = (Imm >> 4) & 0x7;
+	uint8_t Mantissa = Imm & 0xf;
+
+	//   8-bit FP    IEEE Float Encoding
+	//   abcd efgh   aBbbbbbc defgh000 00000000 00000000
+	//
+	// where B = NOT(b);
+
+	uint32_t I = 0;
+	I |= Sign << 31;
+	I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30;
+	I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25;
+	I |= (Exp & 0x3) << 23;
+	I |= Mantissa << 19;
+	return BitsToFloat(I);
+}
+
+//===--------------------------------------------------------------------===//
+// AdvSIMD Modified Immediates
+//===--------------------------------------------------------------------===//
+// 0x00 0x00 0x00 abcdefgh 0x00 0x00 0x00 abcdefgh
+static inline bool AArch64_AM_isAdvSIMDModImmType1(uint64_t Imm)
+{
+	return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
+	       ((Imm & 0xffffff00ffffff00ULL) == 0);
+}
+
+static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType1(uint64_t Imm)
+{
+	return (Imm & 0xffULL);
+}
+
+static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType1(uint8_t Imm)
+{
+	uint64_t EncVal = Imm;
+	return (EncVal << 32) | EncVal;
+}
+
+// 0x00 0x00 abcdefgh 0x00 0x00 0x00 abcdefgh 0x00
+static inline bool AArch64_AM_isAdvSIMDModImmType2(uint64_t Imm)
+{
+	return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
+	       ((Imm & 0xffff00ffffff00ffULL) == 0);
+}
+
+static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType2(uint64_t Imm)
+{
+	return (Imm & 0xff00ULL) >> 8;
+}
+
+static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType2(uint8_t Imm)
+{
+	uint64_t EncVal = Imm;
+	return (EncVal << 40) | (EncVal << 8);
+}
+
+// 0x00 abcdefgh 0x00 0x00 0x00 abcdefgh 0x00 0x00
+static inline bool AArch64_AM_isAdvSIMDModImmType3(uint64_t Imm)
+{
+	return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
+	       ((Imm & 0xff00ffffff00ffffULL) == 0);
+}
+
+static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType3(uint64_t Imm)
+{
+	return (Imm & 0xff0000ULL) >> 16;
+}
+
+static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType3(uint8_t Imm)
+{
+	uint64_t EncVal = Imm;
+	return (EncVal << 48) | (EncVal << 16);
+}
+
+// abcdefgh 0x00 0x00 0x00 abcdefgh 0x00 0x00 0x00
+static inline bool AArch64_AM_isAdvSIMDModImmType4(uint64_t Imm)
+{
+	return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
+	       ((Imm & 0x00ffffff00ffffffULL) == 0);
+}
+
+static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType4(uint64_t Imm)
+{
+	return (Imm & 0xff000000ULL) >> 24;
+}
+
+static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType4(uint8_t Imm)
+{
+	uint64_t EncVal = Imm;
+	return (EncVal << 56) | (EncVal << 24);
+}
+
+// 0x00 abcdefgh 0x00 abcdefgh 0x00 abcdefgh 0x00 abcdefgh
+static inline bool AArch64_AM_isAdvSIMDModImmType5(uint64_t Imm)
+{
+	return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
+	       (((Imm & 0x00ff0000ULL) >> 16) == (Imm & 0x000000ffULL)) &&
+	       ((Imm & 0xff00ff00ff00ff00ULL) == 0);
+}
+
+static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType5(uint64_t Imm)
+{
+	return (Imm & 0xffULL);
+}
+
+static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType5(uint8_t Imm)
+{
+	uint64_t EncVal = Imm;
+	return (EncVal << 48) | (EncVal << 32) | (EncVal << 16) | EncVal;
+}
+
+// abcdefgh 0x00 abcdefgh 0x00 abcdefgh 0x00 abcdefgh 0x00
+static inline bool AArch64_AM_isAdvSIMDModImmType6(uint64_t Imm)
+{
+	return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
+	       (((Imm & 0xff000000ULL) >> 16) == (Imm & 0x0000ff00ULL)) &&
+	       ((Imm & 0x00ff00ff00ff00ffULL) == 0);
+}
+
+static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType6(uint64_t Imm)
+{
+	return (Imm & 0xff00ULL) >> 8;
+}
+
+static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType6(uint8_t Imm)
+{
+	uint64_t EncVal = Imm;
+	return (EncVal << 56) | (EncVal << 40) | (EncVal << 24) | (EncVal << 8);
+}
+
+// 0x00 0x00 abcdefgh 0xFF 0x00 0x00 abcdefgh 0xFF
+static inline bool AArch64_AM_isAdvSIMDModImmType7(uint64_t Imm)
+{
+	return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
+	       ((Imm & 0xffff00ffffff00ffULL) == 0x000000ff000000ffULL);
+}
+
+static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType7(uint64_t Imm)
+{
+	return (Imm & 0xff00ULL) >> 8;
+}
+
+static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType7(uint8_t Imm)
+{
+	uint64_t EncVal = Imm;
+	return (EncVal << 40) | (EncVal << 8) | 0x000000ff000000ffULL;
+}
+
+// 0x00 abcdefgh 0xFF 0xFF 0x00 abcdefgh 0xFF 0xFF
+static inline bool AArch64_AM_isAdvSIMDModImmType8(uint64_t Imm)
+{
+	return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
+	       ((Imm & 0xff00ffffff00ffffULL) == 0x0000ffff0000ffffULL);
+}
+
+static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType8(uint8_t Imm)
+{
+	uint64_t EncVal = Imm;
+	return (EncVal << 48) | (EncVal << 16) | 0x0000ffff0000ffffULL;
+}
+
+static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType8(uint64_t Imm)
+{
+	return (Imm & 0x00ff0000ULL) >> 16;
+}
+
+// abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh
+static inline bool AArch64_AM_isAdvSIMDModImmType9(uint64_t Imm)
+{
+	return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
+	       ((Imm >> 48) == (Imm & 0x0000ffffULL)) &&
+	       ((Imm >> 56) == (Imm & 0x000000ffULL));
+}
+
+static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType9(uint64_t Imm)
+{
+	return (Imm & 0xffULL);
+}
+
+static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType9(uint8_t Imm)
+{
+	uint64_t EncVal = Imm;
+	EncVal |= (EncVal << 8);
+	EncVal |= (EncVal << 16);
+	EncVal |= (EncVal << 32);
+	return EncVal;
+}
+
+// aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg hhhhhhhh
+// cmode: 1110, op: 1
+static inline bool AArch64_AM_isAdvSIMDModImmType10(uint64_t Imm)
+{
+#if defined(_MSC_VER) && _MSC_VER == 1937 && !defined(__clang__) && \
+	defined(_M_ARM64)
+	// The MSVC compiler 19.37 for ARM64 has an optimization bug that
+	// causes an incorrect behavior with the orignal version. Work around
+	// by using a slightly different variation.
+	// https://developercommunity.visualstudio.com/t/C-ARM64-compiler-optimization-bug/10481261
+	constexpr uint64_t Mask = 0xFFULL;
+	uint64_t ByteA = (Imm >> 56) & Mask;
+	uint64_t ByteB = (Imm >> 48) & Mask;
+	uint64_t ByteC = (Imm >> 40) & Mask;
+	uint64_t ByteD = (Imm >> 32) & Mask;
+	uint64_t ByteE = (Imm >> 24) & Mask;
+	uint64_t ByteF = (Imm >> 16) & Mask;
+	uint64_t ByteG = (Imm >> 8) & Mask;
+	uint64_t ByteH = Imm & Mask;
+
+	return (ByteA == 0ULL || ByteA == Mask) &&
+	       (ByteB == 0ULL || ByteB == Mask) &&
+	       (ByteC == 0ULL || ByteC == Mask) &&
+	       (ByteD == 0ULL || ByteD == Mask) &&
+	       (ByteE == 0ULL || ByteE == Mask) &&
+	       (ByteF == 0ULL || ByteF == Mask) &&
+	       (ByteG == 0ULL || ByteG == Mask) &&
+	       (ByteH == 0ULL || ByteH == Mask);
+#else
+	uint64_t ByteA = Imm & 0xff00000000000000ULL;
+	uint64_t ByteB = Imm & 0x00ff000000000000ULL;
+	uint64_t ByteC = Imm & 0x0000ff0000000000ULL;
+	uint64_t ByteD = Imm & 0x000000ff00000000ULL;
+	uint64_t ByteE = Imm & 0x00000000ff000000ULL;
+	uint64_t ByteF = Imm & 0x0000000000ff0000ULL;
+	uint64_t ByteG = Imm & 0x000000000000ff00ULL;
+	uint64_t ByteH = Imm & 0x00000000000000ffULL;
+
+	return (ByteA == 0ULL || ByteA == 0xff00000000000000ULL) &&
+	       (ByteB == 0ULL || ByteB == 0x00ff000000000000ULL) &&
+	       (ByteC == 0ULL || ByteC == 0x0000ff0000000000ULL) &&
+	       (ByteD == 0ULL || ByteD == 0x000000ff00000000ULL) &&
+	       (ByteE == 0ULL || ByteE == 0x00000000ff000000ULL) &&
+	       (ByteF == 0ULL || ByteF == 0x0000000000ff0000ULL) &&
+	       (ByteG == 0ULL || ByteG == 0x000000000000ff00ULL) &&
+	       (ByteH == 0ULL || ByteH == 0x00000000000000ffULL);
+#endif
+}
+
+static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType10(uint64_t Imm)
+{
+	uint8_t BitA = (Imm & 0xff00000000000000ULL) != 0;
+	uint8_t BitB = (Imm & 0x00ff000000000000ULL) != 0;
+	uint8_t BitC = (Imm & 0x0000ff0000000000ULL) != 0;
+	uint8_t BitD = (Imm & 0x000000ff00000000ULL) != 0;
+	uint8_t BitE = (Imm & 0x00000000ff000000ULL) != 0;
+	uint8_t BitF = (Imm & 0x0000000000ff0000ULL) != 0;
+	uint8_t BitG = (Imm & 0x000000000000ff00ULL) != 0;
+	uint8_t BitH = (Imm & 0x00000000000000ffULL) != 0;
+
+	uint8_t EncVal = BitA;
+	EncVal <<= 1;
+	EncVal |= BitB;
+	EncVal <<= 1;
+	EncVal |= BitC;
+	EncVal <<= 1;
+	EncVal |= BitD;
+	EncVal <<= 1;
+	EncVal |= BitE;
+	EncVal <<= 1;
+	EncVal |= BitF;
+	EncVal <<= 1;
+	EncVal |= BitG;
+	EncVal <<= 1;
+	EncVal |= BitH;
+	return EncVal;
+}
+
+static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType10(uint8_t Imm)
+{
+	uint64_t EncVal = 0;
+	if (Imm & 0x80)
+		EncVal |= 0xff00000000000000ULL;
+	if (Imm & 0x40)
+		EncVal |= 0x00ff000000000000ULL;
+	if (Imm & 0x20)
+		EncVal |= 0x0000ff0000000000ULL;
+	if (Imm & 0x10)
+		EncVal |= 0x000000ff00000000ULL;
+	if (Imm & 0x08)
+		EncVal |= 0x00000000ff000000ULL;
+	if (Imm & 0x04)
+		EncVal |= 0x0000000000ff0000ULL;
+	if (Imm & 0x02)
+		EncVal |= 0x000000000000ff00ULL;
+	if (Imm & 0x01)
+		EncVal |= 0x00000000000000ffULL;
+	return EncVal;
+}
+
+// aBbbbbbc defgh000 0x00 0x00 aBbbbbbc defgh000 0x00 0x00
+static inline bool AArch64_AM_isAdvSIMDModImmType11(uint64_t Imm)
+{
+	uint64_t BString = (Imm & 0x7E000000ULL) >> 25;
+	return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
+	       (BString == 0x1f || BString == 0x20) &&
+	       ((Imm & 0x0007ffff0007ffffULL) == 0);
+}
+
+static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType11(uint64_t Imm)
+{
+	uint8_t BitA = (Imm & 0x80000000ULL) != 0;
+	uint8_t BitB = (Imm & 0x20000000ULL) != 0;
+	uint8_t BitC = (Imm & 0x01000000ULL) != 0;
+	uint8_t BitD = (Imm & 0x00800000ULL) != 0;
+	uint8_t BitE = (Imm & 0x00400000ULL) != 0;
+	uint8_t BitF = (Imm & 0x00200000ULL) != 0;
+	uint8_t BitG = (Imm & 0x00100000ULL) != 0;
+	uint8_t BitH = (Imm & 0x00080000ULL) != 0;
+
+	uint8_t EncVal = BitA;
+	EncVal <<= 1;
+	EncVal |= BitB;
+	EncVal <<= 1;
+	EncVal |= BitC;
+	EncVal <<= 1;
+	EncVal |= BitD;
+	EncVal <<= 1;
+	EncVal |= BitE;
+	EncVal <<= 1;
+	EncVal |= BitF;
+	EncVal <<= 1;
+	EncVal |= BitG;
+	EncVal <<= 1;
+	EncVal |= BitH;
+	return EncVal;
+}
+
+static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType11(uint8_t Imm)
+{
+	uint64_t EncVal = 0;
+	if (Imm & 0x80)
+		EncVal |= 0x80000000ULL;
+	if (Imm & 0x40)
+		EncVal |= 0x3e000000ULL;
+	else
+		EncVal |= 0x40000000ULL;
+	if (Imm & 0x20)
+		EncVal |= 0x01000000ULL;
+	if (Imm & 0x10)
+		EncVal |= 0x00800000ULL;
+	if (Imm & 0x08)
+		EncVal |= 0x00400000ULL;
+	if (Imm & 0x04)
+		EncVal |= 0x00200000ULL;
+	if (Imm & 0x02)
+		EncVal |= 0x00100000ULL;
+	if (Imm & 0x01)
+		EncVal |= 0x00080000ULL;
+	return (EncVal << 32) | EncVal;
+}
+
+// aBbbbbbb bbcdefgh 0x00 0x00 0x00 0x00 0x00 0x00
+static inline bool AArch64_AM_isAdvSIMDModImmType12(uint64_t Imm)
+{
+	uint64_t BString = (Imm & 0x7fc0000000000000ULL) >> 54;
+	return ((BString == 0xff || BString == 0x100) &&
+		((Imm & 0x0000ffffffffffffULL) == 0));
+}
+
+static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType12(uint64_t Imm)
+{
+	uint8_t BitA = (Imm & 0x8000000000000000ULL) != 0;
+	uint8_t BitB = (Imm & 0x0040000000000000ULL) != 0;
+	uint8_t BitC = (Imm & 0x0020000000000000ULL) != 0;
+	uint8_t BitD = (Imm & 0x0010000000000000ULL) != 0;
+	uint8_t BitE = (Imm & 0x0008000000000000ULL) != 0;
+	uint8_t BitF = (Imm & 0x0004000000000000ULL) != 0;
+	uint8_t BitG = (Imm & 0x0002000000000000ULL) != 0;
+	uint8_t BitH = (Imm & 0x0001000000000000ULL) != 0;
+
+	uint8_t EncVal = BitA;
+	EncVal <<= 1;
+	EncVal |= BitB;
+	EncVal <<= 1;
+	EncVal |= BitC;
+	EncVal <<= 1;
+	EncVal |= BitD;
+	EncVal <<= 1;
+	EncVal |= BitE;
+	EncVal <<= 1;
+	EncVal |= BitF;
+	EncVal <<= 1;
+	EncVal |= BitG;
+	EncVal <<= 1;
+	EncVal |= BitH;
+	return EncVal;
+}
+
+static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType12(uint8_t Imm)
+{
+	uint64_t EncVal = 0;
+	if (Imm & 0x80)
+		EncVal |= 0x8000000000000000ULL;
+	if (Imm & 0x40)
+		EncVal |= 0x3fc0000000000000ULL;
+	else
+		EncVal |= 0x4000000000000000ULL;
+	if (Imm & 0x20)
+		EncVal |= 0x0020000000000000ULL;
+	if (Imm & 0x10)
+		EncVal |= 0x0010000000000000ULL;
+	if (Imm & 0x08)
+		EncVal |= 0x0008000000000000ULL;
+	if (Imm & 0x04)
+		EncVal |= 0x0004000000000000ULL;
+	if (Imm & 0x02)
+		EncVal |= 0x0002000000000000ULL;
+	if (Imm & 0x01)
+		EncVal |= 0x0001000000000000ULL;
+	return (EncVal << 32) | EncVal;
+}
+
+/// Returns true if Imm is the concatenation of a repeating pattern of type T.
+#define DEFINE_isSVEMaskOfIdenticalElements(T) \
+	static inline bool CONCAT(AArch64_AM_isSVEMaskOfIdenticalElements, \
+				  T)(int64_t Imm) \
+	{ \
+		union { \
+			int64_t In; \
+			T Out[sizeof(int64_t) / sizeof(T)]; \
+		} U_Parts; \
+		U_Parts.In = Imm; \
+		T *Parts = U_Parts.Out; \
+		for (int i = 0; i < (sizeof(int64_t) / sizeof(T)); i++) { \
+			if (Parts[i] != Parts[0]) \
+				return false; \
+		} \
+		return true; \
+	}
+DEFINE_isSVEMaskOfIdenticalElements(int8_t);
+DEFINE_isSVEMaskOfIdenticalElements(int16_t);
+DEFINE_isSVEMaskOfIdenticalElements(int32_t);
+DEFINE_isSVEMaskOfIdenticalElements(int64_t);
+
+static inline bool isSVECpyImm8(int64_t Imm)
+{
+	bool IsImm8 = (int8_t)Imm == Imm;
+
+	return IsImm8 || (uint8_t)Imm == Imm;
+}
+
+static inline bool isSVECpyImm16(int64_t Imm)
+{
+	bool IsImm8 = (int8_t)Imm == Imm;
+	bool IsImm16 = (int16_t)(Imm & ~0xff) == Imm;
+
+	return IsImm8 || IsImm16 || (uint16_t)(Imm & ~0xff) == Imm;
+}
+
+static inline bool isSVECpyImm32(int64_t Imm)
+{
+	bool IsImm8 = (int8_t)Imm == Imm;
+	bool IsImm16 = (int16_t)(Imm & ~0xff) == Imm;
+
+	return IsImm8 || IsImm16;
+}
+
+static inline bool isSVECpyImm64(int64_t Imm)
+{
+	bool IsImm8 = (int8_t)Imm == Imm;
+	bool IsImm16 = (int16_t)(Imm & ~0xff) == Imm;
+
+	return IsImm8 || IsImm16;
+}
+
+/// Return true if Imm is valid for DUPM and has no single CPY/DUP equivalent.
+static inline bool
+AArch64_AM_isSVEMoveMaskPreferredLogicalImmediate(int64_t Imm)
+{
+	if (isSVECpyImm64(Imm))
+		return false;
+
+	union {
+		int64_t In;
+		int32_t Out[2];
+	} U_S;
+	U_S.In = Imm;
+	int32_t *S = U_S.Out;
+	union {
+		int64_t In;
+		int16_t Out[4];
+	} U_H;
+	U_H.In = Imm;
+	int16_t *H = U_H.Out;
+	union {
+		int64_t In;
+		int8_t Out[8];
+	} U_B;
+	U_B.In = Imm;
+	int8_t *B = U_B.Out;
+
+	if (CONCAT(AArch64_AM_isSVEMaskOfIdenticalElements, int32_t)(Imm) &&
+	    isSVECpyImm32(S[0]))
+		return false;
+	if (CONCAT(AArch64_AM_isSVEMaskOfIdenticalElements, int16_t)(Imm) &&
+	    isSVECpyImm16(H[0]))
+		return false;
+	if (CONCAT(AArch64_AM_isSVEMaskOfIdenticalElements, int8_t)(Imm) &&
+	    isSVECpyImm8(B[0]))
+		return false;
+	return AArch64_AM_isLogicalImmediate(Imm, 64);
+}
+
+inline static bool AArch64_AM_isAnyMOVZMovAlias(uint64_t Value, int RegWidth)
+{
+	for (int Shift = 0; Shift <= RegWidth - 16; Shift += 16)
+		if ((Value & ~(0xffffULL << Shift)) == 0)
+			return true;
+
+	return false;
+}
+
+inline static bool AArch64_AM_isMOVZMovAlias(uint64_t Value, int Shift,
+					     int RegWidth)
+{
+	if (RegWidth == 32)
+		Value &= 0xffffffffULL;
+
+	// "lsl #0" takes precedence: in practice this only affects "#0, lsl #0".
+	if (Value == 0 && Shift != 0)
+		return false;
+
+	return (Value & ~(0xffffULL << Shift)) == 0;
+}
+
+inline static bool AArch64_AM_isMOVNMovAlias(uint64_t Value, int Shift,
+					     int RegWidth)
+{
+	// MOVZ takes precedence over MOVN.
+	if (AArch64_AM_isAnyMOVZMovAlias(Value, RegWidth))
+		return false;
+
+	Value = ~Value;
+	if (RegWidth == 32)
+		Value &= 0xffffffffULL;
+
+	return AArch64_AM_isMOVZMovAlias(Value, Shift, RegWidth);
+}
+
+inline static bool AArch64_AM_isAnyMOVWMovAlias(uint64_t Value, int RegWidth)
+{
+	if (AArch64_AM_isAnyMOVZMovAlias(Value, RegWidth))
+		return true;
+
+	// It's not a MOVZ, but it might be a MOVN.
+	Value = ~Value;
+	if (RegWidth == 32)
+		Value &= 0xffffffffULL;
+
+	return AArch64_AM_isAnyMOVZMovAlias(Value, RegWidth);
+}
+
+// CS namespace end: AArch64_AM
+
+// end namespace AArch64_AM
+
+// end namespace llvm
+
+#endif

thirdparty/capstone/arch/AArch64/AArch64BaseInfo.c

@@ -0,0 +1,175 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically translated source file from LLVM. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Only small edits allowed. */
+/* For multiple similar edits, please create a Patch for the translator. */
+
+/* Capstone's C++ file translator: */
+/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
+
+//===-- AArch64BaseInfo.cpp - AArch64 Base encoding information------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file provides basic encoding and assembly information for AArch64.
+//
+//===----------------------------------------------------------------------===//
+#include <capstone/platform.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "AArch64BaseInfo.h"
+
+#define CONCAT(a, b) CONCAT_(a, b)
+#define CONCAT_(a, b) a##_##b
+
+#define GET_AT_IMPL
+#include "AArch64GenSystemOperands.inc"
+#undef GET_AT_IMPL
+
+#define GET_DBNXS_IMPL
+#include "AArch64GenSystemOperands.inc"
+#undef GET_DBNXS_IMPL
+
+#define GET_DB_IMPL
+#include "AArch64GenSystemOperands.inc"
+#undef GET_DB_IMPL
+
+#define GET_DC_IMPL
+#include "AArch64GenSystemOperands.inc"
+#undef GET_DC_IMPL
+
+#define GET_IC_IMPL
+#include "AArch64GenSystemOperands.inc"
+#undef GET_IC_IMPL
+
+#define GET_ISB_IMPL
+#include "AArch64GenSystemOperands.inc"
+#undef GET_ISB_IMPL
+
+#define GET_TSB_IMPL
+#include "AArch64GenSystemOperands.inc"
+#undef GET_TSB_IMPL
+
+#define GET_PRCTX_IMPL
+#include "AArch64GenSystemOperands.inc"
+#undef GET_PRCTX_IMPL
+
+#define GET_PRFM_IMPL
+#include "AArch64GenSystemOperands.inc"
+#undef GET_PRFM_IMPL
+
+#define GET_SVEPRFM_IMPL
+#include "AArch64GenSystemOperands.inc"
+#undef GET_SVEPRFM_IMPL
+
+#define GET_RPRFM_IMPL
+#include "AArch64GenSystemOperands.inc"
+#undef GET_RPRFM_IMPL
+
+// namespace AArch64RPRFM
+// namespace llvm
+
+#define GET_SVEPREDPAT_IMPL
+#include "AArch64GenSystemOperands.inc"
+#undef GET_SVEPREDPAT_IMPL
+
+#define GET_SVEVECLENSPECIFIER_IMPL
+#include "AArch64GenSystemOperands.inc"
+#undef GET_SVEVECLENSPECIFIER_IMPL
+
+// namespace AArch64SVEVecLenSpecifier
+// namespace llvm
+
+#define GET_EXACTFPIMM_IMPL
+#include "AArch64GenSystemOperands.inc"
+#undef GET_EXACTFPIMM_IMPL
+
+#define GET_PSTATEIMM0_15_IMPL
+#include "AArch64GenSystemOperands.inc"
+#undef GET_PSTATEIMM0_15_IMPL
+
+#define GET_PSTATEIMM0_1_IMPL
+#include "AArch64GenSystemOperands.inc"
+#undef GET_PSTATEIMM0_1_IMPL
+
+#define GET_PSB_IMPL
+#include "AArch64GenSystemOperands.inc"
+#undef GET_PSB_IMPL
+
+#define GET_BTI_IMPL
+#include "AArch64GenSystemOperands.inc"
+#undef GET_BTI_IMPL
+
+#define SysReg AArch64SysReg_SysReg
+#define GET_SYSREG_IMPL
+#include "AArch64GenSystemOperands.inc"
+#undef GET_SYSREG_IMPL
+
+#undef SysReg
+
+// return a string representing the number X
+// NOTE: result must be big enough to contain the data
+static void utostr(uint64_t X, bool isNeg, char *result)
+{
+	char Buffer[22];
+	char *BufPtr = Buffer + 21;
+
+	Buffer[21] = '\0';
+	if (X == 0)
+		*--BufPtr = '0'; // Handle special case...
+
+	while (X) {
+		*--BufPtr = X % 10 + '0';
+		X /= 10;
+	}
+
+	if (isNeg)
+		*--BufPtr = '-'; // Add negative sign...
+
+	// suppose that result is big enough
+	strncpy(result, BufPtr, sizeof(Buffer));
+}
+
+// NOTE: result must be big enough to contain the result
+void AArch64SysReg_genericRegisterString(uint32_t Bits, char *result)
+{
+	// assert(Bits < 0x10000);
+	char Op0Str[32], Op1Str[32], CRnStr[32], CRmStr[32], Op2Str[32];
+	int dummy;
+	uint32_t Op0 = (Bits >> 14) & 0x3;
+	uint32_t Op1 = (Bits >> 11) & 0x7;
+	uint32_t CRn = (Bits >> 7) & 0xf;
+	uint32_t CRm = (Bits >> 3) & 0xf;
+	uint32_t Op2 = Bits & 0x7;
+
+	utostr(Op0, false, Op0Str);
+	utostr(Op1, false, Op1Str);
+	utostr(Op2, false, Op2Str);
+	utostr(CRn, false, CRnStr);
+	utostr(CRm, false, CRmStr);
+
+	dummy = cs_snprintf(result, AARCH64_GRS_LEN, "s%s_%s_c%s_c%s_%s",
+			    Op0Str, Op1Str, CRnStr, CRmStr, Op2Str);
+	(void)dummy;
+}
+
+#define GET_TLBITable_IMPL
+
+#include "AArch64GenSystemOperands.inc"
+#undef GET_TLBITable_IMPL
+
+#define GET_SVCR_IMPL
+
+#include "AArch64GenSystemOperands.inc"
+#undef GET_SVCR_IMPL

thirdparty/capstone/arch/AArch64/AArch64BaseInfo.h

@@ -0,0 +1,983 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically translated source file from LLVM. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Only small edits allowed. */
+/* For multiple similar edits, please create a Patch for the translator. */
+
+/* Capstone's C++ file translator: */
+/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
+
+//===-- AArch64BaseInfo.h - Top level definitions for AArch64 ---*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains small standalone helper functions and enum definitions for
+// the AArch64 target useful for the compiler back-end and the MC libraries.
+// As such, it deliberately does not include references to LLVM core
+// code gen types, passes, etc..
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
+#define LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
+
+// FIXME: Is it easiest to fix this layering violation by moving the .inc
+// #includes from AArch64MCTargetDesc.h to here?
+#include <capstone/platform.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "../../MCInstPrinter.h"
+
+#include "../../utils.h"
+#include "capstone/aarch64.h"
+
+#define GET_SUBTARGETINFO_ENUM
+#include "AArch64GenSubtargetInfo.inc"
+
+#define GET_REGINFO_ENUM
+#define GET_REGINFO_MC_DESC
+#include "AArch64GenRegisterInfo.inc"
+
+#define GET_INSTRINFO_ENUM
+#include "AArch64GenInstrInfo.inc"
+
+#define CONCAT(a, b) CONCAT_(a, b)
+#define CONCAT_(a, b) a##_##b
+
+static inline unsigned getWRegFromXReg(unsigned Reg)
+{
+	switch (Reg) {
+	case AArch64_X0:
+		return AArch64_W0;
+	case AArch64_X1:
+		return AArch64_W1;
+	case AArch64_X2:
+		return AArch64_W2;
+	case AArch64_X3:
+		return AArch64_W3;
+	case AArch64_X4:
+		return AArch64_W4;
+	case AArch64_X5:
+		return AArch64_W5;
+	case AArch64_X6:
+		return AArch64_W6;
+	case AArch64_X7:
+		return AArch64_W7;
+	case AArch64_X8:
+		return AArch64_W8;
+	case AArch64_X9:
+		return AArch64_W9;
+	case AArch64_X10:
+		return AArch64_W10;
+	case AArch64_X11:
+		return AArch64_W11;
+	case AArch64_X12:
+		return AArch64_W12;
+	case AArch64_X13:
+		return AArch64_W13;
+	case AArch64_X14:
+		return AArch64_W14;
+	case AArch64_X15:
+		return AArch64_W15;
+	case AArch64_X16:
+		return AArch64_W16;
+	case AArch64_X17:
+		return AArch64_W17;
+	case AArch64_X18:
+		return AArch64_W18;
+	case AArch64_X19:
+		return AArch64_W19;
+	case AArch64_X20:
+		return AArch64_W20;
+	case AArch64_X21:
+		return AArch64_W21;
+	case AArch64_X22:
+		return AArch64_W22;
+	case AArch64_X23:
+		return AArch64_W23;
+	case AArch64_X24:
+		return AArch64_W24;
+	case AArch64_X25:
+		return AArch64_W25;
+	case AArch64_X26:
+		return AArch64_W26;
+	case AArch64_X27:
+		return AArch64_W27;
+	case AArch64_X28:
+		return AArch64_W28;
+	case AArch64_FP:
+		return AArch64_W29;
+	case AArch64_LR:
+		return AArch64_W30;
+	case AArch64_SP:
+		return AArch64_WSP;
+	case AArch64_XZR:
+		return AArch64_WZR;
+	}
+	// For anything else, return it unchanged.
+	return Reg;
+}
+
+static inline unsigned getXRegFromWReg(unsigned Reg)
+{
+	switch (Reg) {
+	case AArch64_W0:
+		return AArch64_X0;
+	case AArch64_W1:
+		return AArch64_X1;
+	case AArch64_W2:
+		return AArch64_X2;
+	case AArch64_W3:
+		return AArch64_X3;
+	case AArch64_W4:
+		return AArch64_X4;
+	case AArch64_W5:
+		return AArch64_X5;
+	case AArch64_W6:
+		return AArch64_X6;
+	case AArch64_W7:
+		return AArch64_X7;
+	case AArch64_W8:
+		return AArch64_X8;
+	case AArch64_W9:
+		return AArch64_X9;
+	case AArch64_W10:
+		return AArch64_X10;
+	case AArch64_W11:
+		return AArch64_X11;
+	case AArch64_W12:
+		return AArch64_X12;
+	case AArch64_W13:
+		return AArch64_X13;
+	case AArch64_W14:
+		return AArch64_X14;
+	case AArch64_W15:
+		return AArch64_X15;
+	case AArch64_W16:
+		return AArch64_X16;
+	case AArch64_W17:
+		return AArch64_X17;
+	case AArch64_W18:
+		return AArch64_X18;
+	case AArch64_W19:
+		return AArch64_X19;
+	case AArch64_W20:
+		return AArch64_X20;
+	case AArch64_W21:
+		return AArch64_X21;
+	case AArch64_W22:
+		return AArch64_X22;
+	case AArch64_W23:
+		return AArch64_X23;
+	case AArch64_W24:
+		return AArch64_X24;
+	case AArch64_W25:
+		return AArch64_X25;
+	case AArch64_W26:
+		return AArch64_X26;
+	case AArch64_W27:
+		return AArch64_X27;
+	case AArch64_W28:
+		return AArch64_X28;
+	case AArch64_W29:
+		return AArch64_FP;
+	case AArch64_W30:
+		return AArch64_LR;
+	case AArch64_WSP:
+		return AArch64_SP;
+	case AArch64_WZR:
+		return AArch64_XZR;
+	}
+	// For anything else, return it unchanged.
+	return Reg;
+}
+
+static inline unsigned getXRegFromXRegTuple(unsigned RegTuple)
+{
+	switch (RegTuple) {
+	case AArch64_X0_X1_X2_X3_X4_X5_X6_X7:
+		return AArch64_X0;
+	case AArch64_X2_X3_X4_X5_X6_X7_X8_X9:
+		return AArch64_X2;
+	case AArch64_X4_X5_X6_X7_X8_X9_X10_X11:
+		return AArch64_X4;
+	case AArch64_X6_X7_X8_X9_X10_X11_X12_X13:
+		return AArch64_X6;
+	case AArch64_X8_X9_X10_X11_X12_X13_X14_X15:
+		return AArch64_X8;
+	case AArch64_X10_X11_X12_X13_X14_X15_X16_X17:
+		return AArch64_X10;
+	case AArch64_X12_X13_X14_X15_X16_X17_X18_X19:
+		return AArch64_X12;
+	case AArch64_X14_X15_X16_X17_X18_X19_X20_X21:
+		return AArch64_X14;
+	case AArch64_X16_X17_X18_X19_X20_X21_X22_X23:
+		return AArch64_X16;
+	case AArch64_X18_X19_X20_X21_X22_X23_X24_X25:
+		return AArch64_X18;
+	case AArch64_X20_X21_X22_X23_X24_X25_X26_X27:
+		return AArch64_X20;
+	case AArch64_X22_X23_X24_X25_X26_X27_X28_FP:
+		return AArch64_X22;
+	}
+	// For anything else, return it unchanged.
+	return RegTuple;
+}
+
+static inline unsigned getBRegFromDReg(unsigned Reg)
+{
+	switch (Reg) {
+	case AArch64_D0:
+		return AArch64_B0;
+	case AArch64_D1:
+		return AArch64_B1;
+	case AArch64_D2:
+		return AArch64_B2;
+	case AArch64_D3:
+		return AArch64_B3;
+	case AArch64_D4:
+		return AArch64_B4;
+	case AArch64_D5:
+		return AArch64_B5;
+	case AArch64_D6:
+		return AArch64_B6;
+	case AArch64_D7:
+		return AArch64_B7;
+	case AArch64_D8:
+		return AArch64_B8;
+	case AArch64_D9:
+		return AArch64_B9;
+	case AArch64_D10:
+		return AArch64_B10;
+	case AArch64_D11:
+		return AArch64_B11;
+	case AArch64_D12:
+		return AArch64_B12;
+	case AArch64_D13:
+		return AArch64_B13;
+	case AArch64_D14:
+		return AArch64_B14;
+	case AArch64_D15:
+		return AArch64_B15;
+	case AArch64_D16:
+		return AArch64_B16;
+	case AArch64_D17:
+		return AArch64_B17;
+	case AArch64_D18:
+		return AArch64_B18;
+	case AArch64_D19:
+		return AArch64_B19;
+	case AArch64_D20:
+		return AArch64_B20;
+	case AArch64_D21:
+		return AArch64_B21;
+	case AArch64_D22:
+		return AArch64_B22;
+	case AArch64_D23:
+		return AArch64_B23;
+	case AArch64_D24:
+		return AArch64_B24;
+	case AArch64_D25:
+		return AArch64_B25;
+	case AArch64_D26:
+		return AArch64_B26;
+	case AArch64_D27:
+		return AArch64_B27;
+	case AArch64_D28:
+		return AArch64_B28;
+	case AArch64_D29:
+		return AArch64_B29;
+	case AArch64_D30:
+		return AArch64_B30;
+	case AArch64_D31:
+		return AArch64_B31;
+	}
+	// For anything else, return it unchanged.
+	return Reg;
+}
+
+static inline unsigned getDRegFromBReg(unsigned Reg)
+{
+	switch (Reg) {
+	case AArch64_B0:
+		return AArch64_D0;
+	case AArch64_B1:
+		return AArch64_D1;
+	case AArch64_B2:
+		return AArch64_D2;
+	case AArch64_B3:
+		return AArch64_D3;
+	case AArch64_B4:
+		return AArch64_D4;
+	case AArch64_B5:
+		return AArch64_D5;
+	case AArch64_B6:
+		return AArch64_D6;
+	case AArch64_B7:
+		return AArch64_D7;
+	case AArch64_B8:
+		return AArch64_D8;
+	case AArch64_B9:
+		return AArch64_D9;
+	case AArch64_B10:
+		return AArch64_D10;
+	case AArch64_B11:
+		return AArch64_D11;
+	case AArch64_B12:
+		return AArch64_D12;
+	case AArch64_B13:
+		return AArch64_D13;
+	case AArch64_B14:
+		return AArch64_D14;
+	case AArch64_B15:
+		return AArch64_D15;
+	case AArch64_B16:
+		return AArch64_D16;
+	case AArch64_B17:
+		return AArch64_D17;
+	case AArch64_B18:
+		return AArch64_D18;
+	case AArch64_B19:
+		return AArch64_D19;
+	case AArch64_B20:
+		return AArch64_D20;
+	case AArch64_B21:
+		return AArch64_D21;
+	case AArch64_B22:
+		return AArch64_D22;
+	case AArch64_B23:
+		return AArch64_D23;
+	case AArch64_B24:
+		return AArch64_D24;
+	case AArch64_B25:
+		return AArch64_D25;
+	case AArch64_B26:
+		return AArch64_D26;
+	case AArch64_B27:
+		return AArch64_D27;
+	case AArch64_B28:
+		return AArch64_D28;
+	case AArch64_B29:
+		return AArch64_D29;
+	case AArch64_B30:
+		return AArch64_D30;
+	case AArch64_B31:
+		return AArch64_D31;
+	}
+	// For anything else, return it unchanged.
+	return Reg;
+}
+
+static inline bool atomicBarrierDroppedOnZero(unsigned Opcode)
+{
+	switch (Opcode) {
+	case AArch64_LDADDAB:
+	case AArch64_LDADDAH:
+	case AArch64_LDADDAW:
+	case AArch64_LDADDAX:
+	case AArch64_LDADDALB:
+	case AArch64_LDADDALH:
+	case AArch64_LDADDALW:
+	case AArch64_LDADDALX:
+	case AArch64_LDCLRAB:
+	case AArch64_LDCLRAH:
+	case AArch64_LDCLRAW:
+	case AArch64_LDCLRAX:
+	case AArch64_LDCLRALB:
+	case AArch64_LDCLRALH:
+	case AArch64_LDCLRALW:
+	case AArch64_LDCLRALX:
+	case AArch64_LDEORAB:
+	case AArch64_LDEORAH:
+	case AArch64_LDEORAW:
+	case AArch64_LDEORAX:
+	case AArch64_LDEORALB:
+	case AArch64_LDEORALH:
+	case AArch64_LDEORALW:
+	case AArch64_LDEORALX:
+	case AArch64_LDSETAB:
+	case AArch64_LDSETAH:
+	case AArch64_LDSETAW:
+	case AArch64_LDSETAX:
+	case AArch64_LDSETALB:
+	case AArch64_LDSETALH:
+	case AArch64_LDSETALW:
+	case AArch64_LDSETALX:
+	case AArch64_LDSMAXAB:
+	case AArch64_LDSMAXAH:
+	case AArch64_LDSMAXAW:
+	case AArch64_LDSMAXAX:
+	case AArch64_LDSMAXALB:
+	case AArch64_LDSMAXALH:
+	case AArch64_LDSMAXALW:
+	case AArch64_LDSMAXALX:
+	case AArch64_LDSMINAB:
+	case AArch64_LDSMINAH:
+	case AArch64_LDSMINAW:
+	case AArch64_LDSMINAX:
+	case AArch64_LDSMINALB:
+	case AArch64_LDSMINALH:
+	case AArch64_LDSMINALW:
+	case AArch64_LDSMINALX:
+	case AArch64_LDUMAXAB:
+	case AArch64_LDUMAXAH:
+	case AArch64_LDUMAXAW:
+	case AArch64_LDUMAXAX:
+	case AArch64_LDUMAXALB:
+	case AArch64_LDUMAXALH:
+	case AArch64_LDUMAXALW:
+	case AArch64_LDUMAXALX:
+	case AArch64_LDUMINAB:
+	case AArch64_LDUMINAH:
+	case AArch64_LDUMINAW:
+	case AArch64_LDUMINAX:
+	case AArch64_LDUMINALB:
+	case AArch64_LDUMINALH:
+	case AArch64_LDUMINALW:
+	case AArch64_LDUMINALX:
+	case AArch64_SWPAB:
+	case AArch64_SWPAH:
+	case AArch64_SWPAW:
+	case AArch64_SWPAX:
+	case AArch64_SWPALB:
+	case AArch64_SWPALH:
+	case AArch64_SWPALW:
+	case AArch64_SWPALX:
+		return true;
+	}
+	return false;
+}
+
+// MOVE-NOTICE: AArch64CC_CondCode : moved to aarch64.h
+// MOVE-NOTICE: AArch64CC_getCondCodeName : moved to aarch64.h
+// MOVE-NOTICE: AArch64CC_getInvertedCondCode : moved to aarch64.h
+// MOVE-NOTICE: AArch64CC_getNZCVToSatisfyCondCode : moved to aarch64.h
+
+typedef struct SysAlias {
+	const char *Name;
+	aarch64_sysop_alias SysAlias;
+	uint16_t Encoding;
+	aarch64_insn_group FeaturesRequired[3];
+} SysAlias;
+
+typedef struct SysAliasReg {
+	const char *Name;
+	aarch64_sysop_reg SysReg;
+	uint16_t Encoding;
+	bool NeedsReg;
+	aarch64_insn_group FeaturesRequired[3];
+} SysAliasReg;
+
+typedef struct SysAliasImm {
+	const char *Name;
+	aarch64_sysop_imm SysImm;
+	uint16_t ImmValue;
+	uint16_t Encoding;
+	aarch64_insn_group FeaturesRequired[3];
+} SysAliasImm;
+
+// CS namespace begin: AArch64SVCR
+
+#define AArch64SVCR_SVCR SysAlias
+
+#define GET_SVCR_DECL
+
+#include "AArch64GenSystemOperands.inc"
+
+// CS namespace end: AArch64SVCR
+
+// CS namespace begin: AArch64AT
+
+#define AArch64AT_AT SysAlias
+
+#define GET_AT_DECL
+
+#include "AArch64GenSystemOperands.inc"
+
+// CS namespace end: AArch64AT
+
+// CS namespace begin: AArch64DB
+
+#define AArch64DB_DB SysAlias
+
+#define GET_DB_DECL
+
+#include "AArch64GenSystemOperands.inc"
+
+// CS namespace end: AArch64DB
+
+// CS namespace begin: AArch64DBnXS
+
+#define AArch64DBnXS_DBnXS SysAliasImm
+
+#define GET_DBNXS_DECL
+
+#include "AArch64GenSystemOperands.inc"
+
+// CS namespace end: AArch64DBnXS
+
+// CS namespace begin: AArch64DC
+
+#define AArch64DC_DC SysAlias
+
+#define GET_DC_DECL
+
+#include "AArch64GenSystemOperands.inc"
+
+// CS namespace end: AArch64DC
+
+// CS namespace begin: AArch64IC
+
+#define AArch64IC_IC SysAliasReg
+
+#define GET_IC_DECL
+
+#include "AArch64GenSystemOperands.inc"
+
+// CS namespace end: AArch64IC
+
+// CS namespace begin: AArch64ISB
+
+#define AArch64ISB_ISB SysAlias
+
+#define GET_ISB_DECL
+
+#include "AArch64GenSystemOperands.inc"
+
+// CS namespace end: AArch64ISB
+
+// CS namespace begin: AArch64TSB
+
+#define AArch64TSB_TSB SysAlias
+
+#define GET_TSB_DECL
+
+#include "AArch64GenSystemOperands.inc"
+
+// CS namespace end: AArch64TSB
+
+// CS namespace begin: AArch64PRFM
+
+#define AArch64PRFM_PRFM SysAlias
+
+#define GET_PRFM_DECL
+
+#include "AArch64GenSystemOperands.inc"
+
+// CS namespace end: AArch64PRFM
+
+// CS namespace begin: AArch64SVEPRFM
+
+#define AArch64SVEPRFM_SVEPRFM SysAlias
+
+#define GET_SVEPRFM_DECL
+
+#include "AArch64GenSystemOperands.inc"
+
+// CS namespace end: AArch64SVEPRFM
+
+// CS namespace begin: AArch64RPRFM
+
+#define AArch64RPRFM_RPRFM SysAlias
+
+#define GET_RPRFM_DECL
+
+#include "AArch64GenSystemOperands.inc"
+
+// CS namespace end: AArch64RPRFM
+
+// CS namespace begin: AArch64SVEPredPattern
+
+typedef struct SVEPREDPAT {
+	const char *Name;
+	aarch64_sysop_alias SysAlias;
+	uint16_t Encoding;
+} AArch64SVEPredPattern_SVEPREDPAT;
+
+#define GET_SVEPREDPAT_DECL
+
+#include "AArch64GenSystemOperands.inc"
+
+// CS namespace end: AArch64SVEPredPattern
+
+// CS namespace begin: AArch64SVEVecLenSpecifier
+
+typedef struct SVEVECLENSPECIFIER {
+	const char *Name;
+	aarch64_sysop_alias SysAlias;
+	uint16_t Encoding;
+} AArch64SVEVecLenSpecifier_SVEVECLENSPECIFIER;
+
+#define GET_SVEVECLENSPECIFIER_DECL
+
+#include "AArch64GenSystemOperands.inc"
+
+// CS namespace end: AArch64SVEVecLenSpecifier
+
+// namespace AArch64SVEVecLenSpecifier
+
+/// Return the number of active elements for VL1 to VL256 predicate pattern,
+/// zero for all other patterns.
+static inline unsigned getNumElementsFromSVEPredPattern(unsigned Pattern)
+{
+	switch (Pattern) {
+	default:
+		return 0;
+	case AARCH64_SVEPREDPAT_VL1:
+	case AARCH64_SVEPREDPAT_VL2:
+	case AARCH64_SVEPREDPAT_VL3:
+	case AARCH64_SVEPREDPAT_VL4:
+	case AARCH64_SVEPREDPAT_VL5:
+	case AARCH64_SVEPREDPAT_VL6:
+	case AARCH64_SVEPREDPAT_VL7:
+	case AARCH64_SVEPREDPAT_VL8:
+		return Pattern;
+	case AARCH64_SVEPREDPAT_VL16:
+		return 16;
+	case AARCH64_SVEPREDPAT_VL32:
+		return 32;
+	case AARCH64_SVEPREDPAT_VL64:
+		return 64;
+	case AARCH64_SVEPREDPAT_VL128:
+		return 128;
+	case AARCH64_SVEPREDPAT_VL256:
+		return 256;
+	}
+}
+
+/// Return specific VL predicate pattern based on the number of elements.
+static inline unsigned getSVEPredPatternFromNumElements(unsigned MinNumElts)
+{
+	switch (MinNumElts) {
+	default:
+		return 0;
+	case 1:
+	case 2:
+	case 3:
+	case 4:
+	case 5:
+	case 6:
+	case 7:
+	case 8:
+		return MinNumElts;
+	case 16:
+		return AARCH64_SVEPREDPAT_VL16;
+	case 32:
+		return AARCH64_SVEPREDPAT_VL32;
+	case 64:
+		return AARCH64_SVEPREDPAT_VL64;
+	case 128:
+		return AARCH64_SVEPREDPAT_VL128;
+	case 256:
+		return AARCH64_SVEPREDPAT_VL256;
+	}
+}
+
+// CS namespace begin: AArch64ExactFPImm
+
+typedef struct ExactFPImm {
+	const char *Name;
+	aarch64_sysop_imm SysImm;
+	int Enum;
+	const char *Repr;
+} AArch64ExactFPImm_ExactFPImm;
+
+enum {
+	AArch64ExactFPImm_half = 1,
+	AArch64ExactFPImm_one = 2,
+	AArch64ExactFPImm_two = 3,
+	AArch64ExactFPImm_zero = 0,
+};
+
+#define GET_EXACTFPIMM_DECL
+
+#include "AArch64GenSystemOperands.inc"
+
+// CS namespace end: AArch64ExactFPImm
+
+// CS namespace begin: AArch64PState
+
+#define AArch64PState_PStateImm0_15 SysAlias
+
+#define GET_PSTATEIMM0_15_DECL
+
+#include "AArch64GenSystemOperands.inc"
+
+#define AArch64PState_PStateImm0_1 SysAlias
+
+#define GET_PSTATEIMM0_1_DECL
+
+#include "AArch64GenSystemOperands.inc"
+
+// CS namespace end: AArch64PState
+
+// CS namespace begin: AArch64PSBHint
+
+#define AArch64PSBHint_PSB SysAlias
+
+#define GET_PSB_DECL
+
+#include "AArch64GenSystemOperands.inc"
+
+// CS namespace end: AArch64PSBHint
+
+// CS namespace begin: AArch64BTIHint
+
+#define AArch64BTIHint_BTI SysAlias
+
+#define GET_BTI_DECL
+
+#include "AArch64GenSystemOperands.inc"
+
+// CS namespace end: AArch64BTIHint
+
+// CS namespace begin: AArch64SE
+
+typedef enum ShiftExtSpecifiers {
+	AArch64SE_Invalid = -1,
+	AArch64SE_LSL,
+	AArch64SE_MSL,
+	AArch64SE_LSR,
+	AArch64SE_ASR,
+	AArch64SE_ROR,
+
+	AArch64SE_UXTB,
+	AArch64SE_UXTH,
+	AArch64SE_UXTW,
+	AArch64SE_UXTX,
+
+	AArch64SE_SXTB,
+	AArch64SE_SXTH,
+	AArch64SE_SXTW,
+	AArch64SE_SXTX
+} AArch64SE_ShiftExtSpecifiers;
+
+// CS namespace end: AArch64SE
+
+// CS namespace begin: AArch64Layout
+
+// MOVE_NOTICE: AArch64Layout_VectorLayout - move to aarch64.h
+// MOVE_NOTICE: AArch64VectorLayoutToString - move to aarch64.h
+// MOVE_NOTICE: AArch64StringToVectorLayout - move to aarch64.h
+
+// CS namespace end: AArch64Layout
+
+// CS namespace begin: AArch64SysReg
+
+typedef struct SysReg {
+	const char *Name;
+	aarch64_sysop_reg SysReg;
+	const char *AltName;
+	aarch64_sysop_reg AliasReg;
+	unsigned Encoding;
+	bool Readable;
+	bool Writeable;
+	aarch64_insn_group FeaturesRequired[3];
+} AArch64SysReg_SysReg;
+
+#define GET_SYSREG_DECL
+
+#include "AArch64GenSystemOperands.inc"
+
+const AArch64SysReg_SysReg *AArch64SysReg_lookupSysRegByName(const char *Name);
+const AArch64SysReg_SysReg *
+AArch64SysReg_lookupSysRegByEncoding(uint16_t Encoding);
+#define AARCH64_GRS_LEN 128
+void AArch64SysReg_genericRegisterString(uint32_t Bits, char *result);
+
+// CS namespace end: AArch64SysReg
+
+// CS namespace begin: AArch64TLBI
+
+#define AArch64TLBI_TLBI SysAliasReg
+
+#define GET_TLBITable_DECL
+
+#include "AArch64GenSystemOperands.inc"
+
+// CS namespace end: AArch64TLBI
+
+// CS namespace begin: AArch64PRCTX
+
+#define AArch64PRCTX_PRCTX SysAliasReg
+
+#define GET_PRCTX_DECL
+
+#include "AArch64GenSystemOperands.inc"
+
+// CS namespace end: AArch64PRCTX
+
+// CS namespace begin: AArch64II
+
+/// Target Operand Flag enum.
+typedef enum TOF {
+	//===------------------------------------------------------------------===//
+	// AArch64 Specific MachineOperand flags.
+
+	AArch64II_MO_NO_FLAG,
+
+	AArch64II_MO_FRAGMENT = 0x7,
+
+	/// MO_PAGE - A symbol operand with this flag represents the pc-relative
+	/// offset of the 4K page containing the symbol.  This is used with the
+	/// ADRP instruction.
+	AArch64II_MO_PAGE = 1,
+
+	/// MO_PAGEOFF - A symbol operand with this flag represents the offset of
+	/// that symbol within a 4K page.  This offset is added to the page address
+	/// to produce the complete address.
+	AArch64II_MO_PAGEOFF = 2,
+
+	/// MO_G3 - A symbol operand with this flag (granule 3) represents the high
+	/// 16-bits of a 64-bit address, used in a MOVZ or MOVK instruction
+	AArch64II_MO_G3 = 3,
+
+	/// MO_G2 - A symbol operand with this flag (granule 2) represents the bits
+	/// 32-47 of a 64-bit address, used in a MOVZ or MOVK instruction
+	AArch64II_MO_G2 = 4,
+
+	/// MO_G1 - A symbol operand with this flag (granule 1) represents the bits
+	/// 16-31 of a 64-bit address, used in a MOVZ or MOVK instruction
+	AArch64II_MO_G1 = 5,
+
+	/// MO_G0 - A symbol operand with this flag (granule 0) represents the bits
+	/// 0-15 of a 64-bit address, used in a MOVZ or MOVK instruction
+	AArch64II_MO_G0 = 6,
+
+	/// MO_HI12 - This flag indicates that a symbol operand represents the bits
+	/// 13-24 of a 64-bit address, used in a arithmetic immediate-shifted-left-
+	/// by-12-bits instruction.
+	AArch64II_MO_HI12 = 7,
+
+	/// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the
+	/// reference is actually to the ".refptr.FOO" symbol.  This is used for
+	/// stub symbols on windows.
+	AArch64II_MO_COFFSTUB = 0x8,
+
+	/// MO_GOT - This flag indicates that a symbol operand represents the
+	/// address of the GOT entry for the symbol, rather than the address of
+	/// the symbol itself.
+	AArch64II_MO_GOT = 0x10,
+
+	/// MO_NC - Indicates whether the linker is expected to check the symbol
+	/// reference for overflow. For example in an ADRP/ADD pair of relocations
+	/// the ADRP usually does check, but not the ADD.
+	AArch64II_MO_NC = 0x20,
+
+	/// MO_TLS - Indicates that the operand being accessed is some kind of
+	/// thread-local symbol. On Darwin, only one type of thread-local access
+	/// exists (pre linker-relaxation), but on ELF the TLSModel used for the
+	/// referee will affect interpretation.
+	AArch64II_MO_TLS = 0x40,
+
+	/// MO_DLLIMPORT - On a symbol operand, this represents that the reference
+	/// to the symbol is for an import stub.  This is used for DLL import
+	/// storage class indication on Windows.
+	AArch64II_MO_DLLIMPORT = 0x80,
+
+	/// MO_S - Indicates that the bits of the symbol operand represented by
+	/// MO_G0 etc are signed.
+	AArch64II_MO_S = 0x100,
+
+	/// MO_PREL - Indicates that the bits of the symbol operand represented by
+	/// MO_G0 etc are PC relative.
+	AArch64II_MO_PREL = 0x200,
+
+	/// MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag
+	/// in bits 56-63.
+	/// On a FrameIndex operand, indicates that the underlying memory is tagged
+	/// with an unknown tag value (MTE); this needs to be lowered either to an
+	/// SP-relative load or store instruction (which do not check tags), or to
+	/// an LDG instruction to obtain the tag value.
+	AArch64II_MO_TAGGED = 0x400,
+
+	/// MO_ARM64EC_CALLMANGLE - Operand refers to the Arm64EC-mangled version
+	/// of a symbol, not the original. For dllimport symbols, this means it
+	/// uses "__imp_aux".  For other symbols, this means it uses the mangled
+	/// ("#" prefix for C) name.
+	AArch64II_MO_ARM64EC_CALLMANGLE = 0x800,
+} AArch64II_TOF;
+
+// CS namespace end: AArch64II
+
+// end namespace AArch64II
+
+//===----------------------------------------------------------------------===//
+// v8.3a Pointer Authentication
+//
+
+// CS namespace begin: AArch64PACKey
+
+typedef enum ID {
+	AArch64PACKey_IA = 0,
+	AArch64PACKey_IB = 1,
+	AArch64PACKey_DA = 2,
+	AArch64PACKey_DB = 3,
+	AArch64PACKey_LAST = AArch64PACKey_DB
+} AArch64PACKey_ID;
+
+// CS namespace end: AArch64PACKey
+
+// namespace AArch64PACKey
+
+/// Return 2-letter identifier string for numeric key ID.
+static inline const char *AArch64PACKeyIDToString(AArch64PACKey_ID KeyID)
+{
+	switch (KeyID) {
+	case AArch64PACKey_IA:
+		return "ia";
+	case AArch64PACKey_IB:
+		return "ib";
+	case AArch64PACKey_DA:
+		return "da";
+	case AArch64PACKey_DB:
+		return "db";
+	}
+	return NULL;
+}
+
+/// Return numeric key ID for 2-letter identifier string.
+static inline AArch64PACKey_ID AArch64StringToPACKeyID(const char *Name)
+{
+	if (strcmp(Name, "ia") == 0)
+		return AArch64PACKey_IA;
+	if (strcmp(Name, "ib") == 0)
+		return AArch64PACKey_IB;
+	if (strcmp(Name, "da") == 0)
+		return AArch64PACKey_DA;
+	if (strcmp(Name, "db") == 0)
+		return AArch64PACKey_DB;
+	assert(0 && "Invalid PAC key");
+	return AArch64PACKey_LAST;
+}
+
+// CS namespace begin: AArch64
+
+// The number of bits in a SVE register is architecturally defined
+// to be a multiple of this value.  If <M x t> has this number of bits,
+// a <n x M x t> vector can be stored in a SVE register without any
+// redundant bits.  If <M x t> has this number of bits divided by P,
+// a <n x M x t> vector is stored in a SVE register by placing index i
+// in index i*P of a <n x (M*P) x t> vector.  The other elements of the
+// <n x (M*P) x t> vector (such as index 1) are undefined.
+static const unsigned SVEBitsPerBlock = 128;
+
+static const unsigned SVEMaxBitsPerVector = 2048;
+
+// CS namespace end: AArch64
+
+// end namespace AArch64
+// end namespace llvm
+
+#endif

thirdparty/capstone/arch/AArch64/AArch64DisassemblerExtension.c

@@ -0,0 +1,24 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+/*    Rot127 <unisono@quyllur.org>, 2022-2023 */
+
+#include "AArch64DisassemblerExtension.h"
+#include "AArch64BaseInfo.h"
+
+bool AArch64_getFeatureBits(unsigned int mode, unsigned int feature)
+{
+	// we support everything
+	return true;
+}
+
+/// Tests a NULL terminated array of features if they are enabled.
+bool AArch64_testFeatureList(unsigned int mode, const unsigned int *features)
+{
+	int i = 0;
+	while (features[i]) {
+		if (!AArch64_getFeatureBits(mode, features[i]))
+			return false;
+		++i;
+	}
+	return true;
+}

thirdparty/capstone/arch/AArch64/AArch64DisassemblerExtension.h

@@ -0,0 +1,19 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+/*    Rot127 <unisono@quyllur.org>, 2022-2023 */
+
+#ifndef CS_AARCH64_DISASSEMBLER_EXTENSION_H
+#define CS_AARCH64_DISASSEMBLER_EXTENSION_H
+
+#include "../../MCDisassembler.h"
+#include "../../MCRegisterInfo.h"
+#include "../../MathExtras.h"
+#include "../../cs_priv.h"
+#include "AArch64AddressingModes.h"
+#include "capstone/aarch64.h"
+#include "capstone/capstone.h"
+
+bool AArch64_getFeatureBits(unsigned int mode, unsigned int feature);
+bool AArch64_testFeatureList(unsigned int mode, const unsigned int *features);
+
+#endif // CS_AARCH64_DISASSEMBLER_EXTENSION_H

thirdparty/capstone/arch/AArch64/AArch64GenCSAliasMnemMap.inc

@@ -0,0 +1,375 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+	{ AARCH64_INS_ALIAS_ADDPT, "addpt" },
+	{ AARCH64_INS_ALIAS_GCSB, "gcsb" },
+	{ AARCH64_INS_ALIAS_GCSPOPM, "gcspopm" },
+	{ AARCH64_INS_ALIAS_LDAPUR, "ldapur" },
+	{ AARCH64_INS_ALIAS_STLLRB, "stllrb" },
+	{ AARCH64_INS_ALIAS_STLLRH, "stllrh" },
+	{ AARCH64_INS_ALIAS_STLLR, "stllr" },
+	{ AARCH64_INS_ALIAS_STLRB, "stlrb" },
+	{ AARCH64_INS_ALIAS_STLRH, "stlrh" },
+	{ AARCH64_INS_ALIAS_STLR, "stlr" },
+	{ AARCH64_INS_ALIAS_STLUR, "stlur" },
+	{ AARCH64_INS_ALIAS_SUBPT, "subpt" },
+	{ AARCH64_INS_ALIAS_LDRAA, "ldraa" },
+	{ AARCH64_INS_ALIAS_ADD, "add" },
+	{ AARCH64_INS_ALIAS_CMN, "cmn" },
+	{ AARCH64_INS_ALIAS_ADDS, "adds" },
+	{ AARCH64_INS_ALIAS_AND, "and" },
+	{ AARCH64_INS_ALIAS_ANDS, "ands" },
+	{ AARCH64_INS_ALIAS_LDR, "ldr" },
+	{ AARCH64_INS_ALIAS_STR, "str" },
+	{ AARCH64_INS_ALIAS_LDRB, "ldrb" },
+	{ AARCH64_INS_ALIAS_STRB, "strb" },
+	{ AARCH64_INS_ALIAS_LDRH, "ldrh" },
+	{ AARCH64_INS_ALIAS_STRH, "strh" },
+	{ AARCH64_INS_ALIAS_PRFM, "prfm" },
+	{ AARCH64_INS_ALIAS_LDAPURB, "ldapurb" },
+	{ AARCH64_INS_ALIAS_STLURB, "stlurb" },
+	{ AARCH64_INS_ALIAS_LDUR, "ldur" },
+	{ AARCH64_INS_ALIAS_STUR, "stur" },
+	{ AARCH64_INS_ALIAS_PRFUM, "prfum" },
+	{ AARCH64_INS_ALIAS_LDTR, "ldtr" },
+	{ AARCH64_INS_ALIAS_STTR, "sttr" },
+	{ AARCH64_INS_ALIAS_LDP, "ldp" },
+	{ AARCH64_INS_ALIAS_STGP, "stgp" },
+	{ AARCH64_INS_ALIAS_LDNP, "ldnp" },
+	{ AARCH64_INS_ALIAS_STNP, "stnp" },
+	{ AARCH64_INS_ALIAS_STG, "stg" },
+	{ AARCH64_INS_ALIAS_MOV, "mov" },
+	{ AARCH64_INS_ALIAS_LD1, "ld1" },
+	{ AARCH64_INS_ALIAS_LD1R, "ld1r" },
+	{ AARCH64_INS_ALIAS_STADDLB, "staddlb" },
+	{ AARCH64_INS_ALIAS_STADDLH, "staddlh" },
+	{ AARCH64_INS_ALIAS_STADDL, "staddl" },
+	{ AARCH64_INS_ALIAS_STADDB, "staddb" },
+	{ AARCH64_INS_ALIAS_STADDH, "staddh" },
+	{ AARCH64_INS_ALIAS_STADD, "stadd" },
+	{ AARCH64_INS_ALIAS_PTRUE, "ptrue" },
+	{ AARCH64_INS_ALIAS_PTRUES, "ptrues" },
+	{ AARCH64_INS_ALIAS_CNTB, "cntb" },
+	{ AARCH64_INS_ALIAS_SQINCH, "sqinch" },
+	{ AARCH64_INS_ALIAS_INCB, "incb" },
+	{ AARCH64_INS_ALIAS_SQINCB, "sqincb" },
+	{ AARCH64_INS_ALIAS_UQINCB, "uqincb" },
+	{ AARCH64_INS_ALIAS_ORR, "orr" },
+	{ AARCH64_INS_ALIAS_DUPM, "dupm" },
+	{ AARCH64_INS_ALIAS_FMOV, "fmov" },
+	{ AARCH64_INS_ALIAS_EOR3, "eor3" },
+	{ AARCH64_INS_ALIAS_ST1B, "st1b" },
+	{ AARCH64_INS_ALIAS_ST2B, "st2b" },
+	{ AARCH64_INS_ALIAS_ST2Q, "st2q" },
+	{ AARCH64_INS_ALIAS_STNT1B, "stnt1b" },
+	{ AARCH64_INS_ALIAS_LD1B, "ld1b" },
+	{ AARCH64_INS_ALIAS_LDNT1B, "ldnt1b" },
+	{ AARCH64_INS_ALIAS_LD1RQB, "ld1rqb" },
+	{ AARCH64_INS_ALIAS_LD1RB, "ld1rb" },
+	{ AARCH64_INS_ALIAS_LDFF1B, "ldff1b" },
+	{ AARCH64_INS_ALIAS_LDNF1B, "ldnf1b" },
+	{ AARCH64_INS_ALIAS_LD2B, "ld2b" },
+	{ AARCH64_INS_ALIAS_LD1SB, "ld1sb" },
+	{ AARCH64_INS_ALIAS_PRFB, "prfb" },
+	{ AARCH64_INS_ALIAS_LDNT1SB, "ldnt1sb" },
+	{ AARCH64_INS_ALIAS_LD1ROB, "ld1rob" },
+	{ AARCH64_INS_ALIAS_LD1Q, "ld1q" },
+	{ AARCH64_INS_ALIAS_ST1Q, "st1q" },
+	{ AARCH64_INS_ALIAS_LD1W, "ld1w" },
+	{ AARCH64_INS_ALIAS_PMOV, "pmov" },
+	{ AARCH64_INS_ALIAS_SMSTART, "smstart" },
+	{ AARCH64_INS_ALIAS_SMSTOP, "smstop" },
+	{ AARCH64_INS_ALIAS_ZERO, "zero" },
+	{ AARCH64_INS_ALIAS_MOVT, "movt" },
+	{ AARCH64_INS_ALIAS_NOP, "nop" },
+	{ AARCH64_INS_ALIAS_YIELD, "yield" },
+	{ AARCH64_INS_ALIAS_WFE, "wfe" },
+	{ AARCH64_INS_ALIAS_WFI, "wfi" },
+	{ AARCH64_INS_ALIAS_SEV, "sev" },
+	{ AARCH64_INS_ALIAS_SEVL, "sevl" },
+	{ AARCH64_INS_ALIAS_DGH, "dgh" },
+	{ AARCH64_INS_ALIAS_ESB, "esb" },
+	{ AARCH64_INS_ALIAS_CSDB, "csdb" },
+	{ AARCH64_INS_ALIAS_BTI, "bti" },
+	{ AARCH64_INS_ALIAS_PSB, "psb" },
+	{ AARCH64_INS_ALIAS_CHKFEAT, "chkfeat" },
+	{ AARCH64_INS_ALIAS_PACIAZ, "paciaz" },
+	{ AARCH64_INS_ALIAS_PACIBZ, "pacibz" },
+	{ AARCH64_INS_ALIAS_AUTIAZ, "autiaz" },
+	{ AARCH64_INS_ALIAS_AUTIBZ, "autibz" },
+	{ AARCH64_INS_ALIAS_PACIASP, "paciasp" },
+	{ AARCH64_INS_ALIAS_PACIBSP, "pacibsp" },
+	{ AARCH64_INS_ALIAS_AUTIASP, "autiasp" },
+	{ AARCH64_INS_ALIAS_AUTIBSP, "autibsp" },
+	{ AARCH64_INS_ALIAS_PACIA1716, "pacia1716" },
+	{ AARCH64_INS_ALIAS_PACIB1716, "pacib1716" },
+	{ AARCH64_INS_ALIAS_AUTIA1716, "autia1716" },
+	{ AARCH64_INS_ALIAS_AUTIB1716, "autib1716" },
+	{ AARCH64_INS_ALIAS_XPACLRI, "xpaclri" },
+	{ AARCH64_INS_ALIAS_LDRAB, "ldrab" },
+	{ AARCH64_INS_ALIAS_PACM, "pacm" },
+	{ AARCH64_INS_ALIAS_CLREX, "clrex" },
+	{ AARCH64_INS_ALIAS_ISB, "isb" },
+	{ AARCH64_INS_ALIAS_SSBB, "ssbb" },
+	{ AARCH64_INS_ALIAS_PSSBB, "pssbb" },
+	{ AARCH64_INS_ALIAS_DFB, "dfb" },
+	{ AARCH64_INS_ALIAS_SYS, "sys" },
+	{ AARCH64_INS_ALIAS_MOVN, "movn" },
+	{ AARCH64_INS_ALIAS_MOVZ, "movz" },
+	{ AARCH64_INS_ALIAS_NGC, "ngc" },
+	{ AARCH64_INS_ALIAS_NGCS, "ngcs" },
+	{ AARCH64_INS_ALIAS_SUB, "sub" },
+	{ AARCH64_INS_ALIAS_CMP, "cmp" },
+	{ AARCH64_INS_ALIAS_SUBS, "subs" },
+	{ AARCH64_INS_ALIAS_NEG, "neg" },
+	{ AARCH64_INS_ALIAS_NEGS, "negs" },
+	{ AARCH64_INS_ALIAS_MUL, "mul" },
+	{ AARCH64_INS_ALIAS_MNEG, "mneg" },
+	{ AARCH64_INS_ALIAS_SMULL, "smull" },
+	{ AARCH64_INS_ALIAS_SMNEGL, "smnegl" },
+	{ AARCH64_INS_ALIAS_UMULL, "umull" },
+	{ AARCH64_INS_ALIAS_UMNEGL, "umnegl" },
+	{ AARCH64_INS_ALIAS_STCLRLB, "stclrlb" },
+	{ AARCH64_INS_ALIAS_STCLRLH, "stclrlh" },
+	{ AARCH64_INS_ALIAS_STCLRL, "stclrl" },
+	{ AARCH64_INS_ALIAS_STCLRB, "stclrb" },
+	{ AARCH64_INS_ALIAS_STCLRH, "stclrh" },
+	{ AARCH64_INS_ALIAS_STCLR, "stclr" },
+	{ AARCH64_INS_ALIAS_STEORLB, "steorlb" },
+	{ AARCH64_INS_ALIAS_STEORLH, "steorlh" },
+	{ AARCH64_INS_ALIAS_STEORL, "steorl" },
+	{ AARCH64_INS_ALIAS_STEORB, "steorb" },
+	{ AARCH64_INS_ALIAS_STEORH, "steorh" },
+	{ AARCH64_INS_ALIAS_STEOR, "steor" },
+	{ AARCH64_INS_ALIAS_STSETLB, "stsetlb" },
+	{ AARCH64_INS_ALIAS_STSETLH, "stsetlh" },
+	{ AARCH64_INS_ALIAS_STSETL, "stsetl" },
+	{ AARCH64_INS_ALIAS_STSETB, "stsetb" },
+	{ AARCH64_INS_ALIAS_STSETH, "stseth" },
+	{ AARCH64_INS_ALIAS_STSET, "stset" },
+	{ AARCH64_INS_ALIAS_STSMAXLB, "stsmaxlb" },
+	{ AARCH64_INS_ALIAS_STSMAXLH, "stsmaxlh" },
+	{ AARCH64_INS_ALIAS_STSMAXL, "stsmaxl" },
+	{ AARCH64_INS_ALIAS_STSMAXB, "stsmaxb" },
+	{ AARCH64_INS_ALIAS_STSMAXH, "stsmaxh" },
+	{ AARCH64_INS_ALIAS_STSMAX, "stsmax" },
+	{ AARCH64_INS_ALIAS_STSMINLB, "stsminlb" },
+	{ AARCH64_INS_ALIAS_STSMINLH, "stsminlh" },
+	{ AARCH64_INS_ALIAS_STSMINL, "stsminl" },
+	{ AARCH64_INS_ALIAS_STSMINB, "stsminb" },
+	{ AARCH64_INS_ALIAS_STSMINH, "stsminh" },
+	{ AARCH64_INS_ALIAS_STSMIN, "stsmin" },
+	{ AARCH64_INS_ALIAS_STUMAXLB, "stumaxlb" },
+	{ AARCH64_INS_ALIAS_STUMAXLH, "stumaxlh" },
+	{ AARCH64_INS_ALIAS_STUMAXL, "stumaxl" },
+	{ AARCH64_INS_ALIAS_STUMAXB, "stumaxb" },
+	{ AARCH64_INS_ALIAS_STUMAXH, "stumaxh" },
+	{ AARCH64_INS_ALIAS_STUMAX, "stumax" },
+	{ AARCH64_INS_ALIAS_STUMINLB, "stuminlb" },
+	{ AARCH64_INS_ALIAS_STUMINLH, "stuminlh" },
+	{ AARCH64_INS_ALIAS_STUMINL, "stuminl" },
+	{ AARCH64_INS_ALIAS_STUMINB, "stuminb" },
+	{ AARCH64_INS_ALIAS_STUMINH, "stuminh" },
+	{ AARCH64_INS_ALIAS_STUMIN, "stumin" },
+	{ AARCH64_INS_ALIAS_IRG, "irg" },
+	{ AARCH64_INS_ALIAS_LDG, "ldg" },
+	{ AARCH64_INS_ALIAS_STZG, "stzg" },
+	{ AARCH64_INS_ALIAS_ST2G, "st2g" },
+	{ AARCH64_INS_ALIAS_STZ2G, "stz2g" },
+	{ AARCH64_INS_ALIAS_BICS, "bics" },
+	{ AARCH64_INS_ALIAS_BIC, "bic" },
+	{ AARCH64_INS_ALIAS_EON, "eon" },
+	{ AARCH64_INS_ALIAS_EOR, "eor" },
+	{ AARCH64_INS_ALIAS_ORN, "orn" },
+	{ AARCH64_INS_ALIAS_MVN, "mvn" },
+	{ AARCH64_INS_ALIAS_TST, "tst" },
+	{ AARCH64_INS_ALIAS_ROR, "ror" },
+	{ AARCH64_INS_ALIAS_ASR, "asr" },
+	{ AARCH64_INS_ALIAS_SXTB, "sxtb" },
+	{ AARCH64_INS_ALIAS_SXTH, "sxth" },
+	{ AARCH64_INS_ALIAS_SXTW, "sxtw" },
+	{ AARCH64_INS_ALIAS_LSR, "lsr" },
+	{ AARCH64_INS_ALIAS_UXTB, "uxtb" },
+	{ AARCH64_INS_ALIAS_UXTH, "uxth" },
+	{ AARCH64_INS_ALIAS_UXTW, "uxtw" },
+	{ AARCH64_INS_ALIAS_CSET, "cset" },
+	{ AARCH64_INS_ALIAS_CSETM, "csetm" },
+	{ AARCH64_INS_ALIAS_CINC, "cinc" },
+	{ AARCH64_INS_ALIAS_CINV, "cinv" },
+	{ AARCH64_INS_ALIAS_CNEG, "cneg" },
+	{ AARCH64_INS_ALIAS_RET, "ret" },
+	{ AARCH64_INS_ALIAS_DCPS1, "dcps1" },
+	{ AARCH64_INS_ALIAS_DCPS2, "dcps2" },
+	{ AARCH64_INS_ALIAS_DCPS3, "dcps3" },
+	{ AARCH64_INS_ALIAS_LDPSW, "ldpsw" },
+	{ AARCH64_INS_ALIAS_LDRSH, "ldrsh" },
+	{ AARCH64_INS_ALIAS_LDRSB, "ldrsb" },
+	{ AARCH64_INS_ALIAS_LDRSW, "ldrsw" },
+	{ AARCH64_INS_ALIAS_LDURH, "ldurh" },
+	{ AARCH64_INS_ALIAS_LDURB, "ldurb" },
+	{ AARCH64_INS_ALIAS_LDURSH, "ldursh" },
+	{ AARCH64_INS_ALIAS_LDURSB, "ldursb" },
+	{ AARCH64_INS_ALIAS_LDURSW, "ldursw" },
+	{ AARCH64_INS_ALIAS_LDTRH, "ldtrh" },
+	{ AARCH64_INS_ALIAS_LDTRB, "ldtrb" },
+	{ AARCH64_INS_ALIAS_LDTRSH, "ldtrsh" },
+	{ AARCH64_INS_ALIAS_LDTRSB, "ldtrsb" },
+	{ AARCH64_INS_ALIAS_LDTRSW, "ldtrsw" },
+	{ AARCH64_INS_ALIAS_STP, "stp" },
+	{ AARCH64_INS_ALIAS_STURH, "sturh" },
+	{ AARCH64_INS_ALIAS_STURB, "sturb" },
+	{ AARCH64_INS_ALIAS_STLURH, "stlurh" },
+	{ AARCH64_INS_ALIAS_LDAPURSB, "ldapursb" },
+	{ AARCH64_INS_ALIAS_LDAPURH, "ldapurh" },
+	{ AARCH64_INS_ALIAS_LDAPURSH, "ldapursh" },
+	{ AARCH64_INS_ALIAS_LDAPURSW, "ldapursw" },
+	{ AARCH64_INS_ALIAS_STTRH, "sttrh" },
+	{ AARCH64_INS_ALIAS_STTRB, "sttrb" },
+	{ AARCH64_INS_ALIAS_BIC_4H, "bic_4h" },
+	{ AARCH64_INS_ALIAS_BIC_8H, "bic_8h" },
+	{ AARCH64_INS_ALIAS_BIC_2S, "bic_2s" },
+	{ AARCH64_INS_ALIAS_BIC_4S, "bic_4s" },
+	{ AARCH64_INS_ALIAS_ORR_4H, "orr_4h" },
+	{ AARCH64_INS_ALIAS_ORR_8H, "orr_8h" },
+	{ AARCH64_INS_ALIAS_ORR_2S, "orr_2s" },
+	{ AARCH64_INS_ALIAS_ORR_4S, "orr_4s" },
+	{ AARCH64_INS_ALIAS_SXTL_8H, "sxtl_8h" },
+	{ AARCH64_INS_ALIAS_SXTL, "sxtl" },
+	{ AARCH64_INS_ALIAS_SXTL_4S, "sxtl_4s" },
+	{ AARCH64_INS_ALIAS_SXTL_2D, "sxtl_2d" },
+	{ AARCH64_INS_ALIAS_SXTL2_8H, "sxtl2_8h" },
+	{ AARCH64_INS_ALIAS_SXTL2, "sxtl2" },
+	{ AARCH64_INS_ALIAS_SXTL2_4S, "sxtl2_4s" },
+	{ AARCH64_INS_ALIAS_SXTL2_2D, "sxtl2_2d" },
+	{ AARCH64_INS_ALIAS_UXTL_8H, "uxtl_8h" },
+	{ AARCH64_INS_ALIAS_UXTL, "uxtl" },
+	{ AARCH64_INS_ALIAS_UXTL_4S, "uxtl_4s" },
+	{ AARCH64_INS_ALIAS_UXTL_2D, "uxtl_2d" },
+	{ AARCH64_INS_ALIAS_UXTL2_8H, "uxtl2_8h" },
+	{ AARCH64_INS_ALIAS_UXTL2, "uxtl2" },
+	{ AARCH64_INS_ALIAS_UXTL2_4S, "uxtl2_4s" },
+	{ AARCH64_INS_ALIAS_UXTL2_2D, "uxtl2_2d" },
+	{ AARCH64_INS_ALIAS_LD2, "ld2" },
+	{ AARCH64_INS_ALIAS_LD3, "ld3" },
+	{ AARCH64_INS_ALIAS_LD4, "ld4" },
+	{ AARCH64_INS_ALIAS_ST1, "st1" },
+	{ AARCH64_INS_ALIAS_ST2, "st2" },
+	{ AARCH64_INS_ALIAS_ST3, "st3" },
+	{ AARCH64_INS_ALIAS_ST4, "st4" },
+	{ AARCH64_INS_ALIAS_LD2R, "ld2r" },
+	{ AARCH64_INS_ALIAS_LD3R, "ld3r" },
+	{ AARCH64_INS_ALIAS_LD4R, "ld4r" },
+	{ AARCH64_INS_ALIAS_CLRBHB, "clrbhb" },
+	{ AARCH64_INS_ALIAS_STILP, "stilp" },
+	{ AARCH64_INS_ALIAS_STL1, "stl1" },
+	{ AARCH64_INS_ALIAS_SYSP, "sysp" },
+	{ AARCH64_INS_ALIAS_LD1SW, "ld1sw" },
+	{ AARCH64_INS_ALIAS_LD1H, "ld1h" },
+	{ AARCH64_INS_ALIAS_LD1SH, "ld1sh" },
+	{ AARCH64_INS_ALIAS_LD1D, "ld1d" },
+	{ AARCH64_INS_ALIAS_LD1RSW, "ld1rsw" },
+	{ AARCH64_INS_ALIAS_LD1RH, "ld1rh" },
+	{ AARCH64_INS_ALIAS_LD1RSH, "ld1rsh" },
+	{ AARCH64_INS_ALIAS_LD1RW, "ld1rw" },
+	{ AARCH64_INS_ALIAS_LD1RSB, "ld1rsb" },
+	{ AARCH64_INS_ALIAS_LD1RD, "ld1rd" },
+	{ AARCH64_INS_ALIAS_LD1RQH, "ld1rqh" },
+	{ AARCH64_INS_ALIAS_LD1RQW, "ld1rqw" },
+	{ AARCH64_INS_ALIAS_LD1RQD, "ld1rqd" },
+	{ AARCH64_INS_ALIAS_LDNF1SW, "ldnf1sw" },
+	{ AARCH64_INS_ALIAS_LDNF1H, "ldnf1h" },
+	{ AARCH64_INS_ALIAS_LDNF1SH, "ldnf1sh" },
+	{ AARCH64_INS_ALIAS_LDNF1W, "ldnf1w" },
+	{ AARCH64_INS_ALIAS_LDNF1SB, "ldnf1sb" },
+	{ AARCH64_INS_ALIAS_LDNF1D, "ldnf1d" },
+	{ AARCH64_INS_ALIAS_LDFF1SW, "ldff1sw" },
+	{ AARCH64_INS_ALIAS_LDFF1H, "ldff1h" },
+	{ AARCH64_INS_ALIAS_LDFF1SH, "ldff1sh" },
+	{ AARCH64_INS_ALIAS_LDFF1W, "ldff1w" },
+	{ AARCH64_INS_ALIAS_LDFF1SB, "ldff1sb" },
+	{ AARCH64_INS_ALIAS_LDFF1D, "ldff1d" },
+	{ AARCH64_INS_ALIAS_LD3B, "ld3b" },
+	{ AARCH64_INS_ALIAS_LD4B, "ld4b" },
+	{ AARCH64_INS_ALIAS_LD2H, "ld2h" },
+	{ AARCH64_INS_ALIAS_LD3H, "ld3h" },
+	{ AARCH64_INS_ALIAS_LD4H, "ld4h" },
+	{ AARCH64_INS_ALIAS_LD2W, "ld2w" },
+	{ AARCH64_INS_ALIAS_LD3W, "ld3w" },
+	{ AARCH64_INS_ALIAS_LD4W, "ld4w" },
+	{ AARCH64_INS_ALIAS_LD2D, "ld2d" },
+	{ AARCH64_INS_ALIAS_LD3D, "ld3d" },
+	{ AARCH64_INS_ALIAS_LD4D, "ld4d" },
+	{ AARCH64_INS_ALIAS_LD2Q, "ld2q" },
+	{ AARCH64_INS_ALIAS_LD3Q, "ld3q" },
+	{ AARCH64_INS_ALIAS_LD4Q, "ld4q" },
+	{ AARCH64_INS_ALIAS_LDNT1H, "ldnt1h" },
+	{ AARCH64_INS_ALIAS_LDNT1W, "ldnt1w" },
+	{ AARCH64_INS_ALIAS_LDNT1D, "ldnt1d" },
+	{ AARCH64_INS_ALIAS_ST1H, "st1h" },
+	{ AARCH64_INS_ALIAS_ST1W, "st1w" },
+	{ AARCH64_INS_ALIAS_ST1D, "st1d" },
+	{ AARCH64_INS_ALIAS_ST3B, "st3b" },
+	{ AARCH64_INS_ALIAS_ST4B, "st4b" },
+	{ AARCH64_INS_ALIAS_ST2H, "st2h" },
+	{ AARCH64_INS_ALIAS_ST3H, "st3h" },
+	{ AARCH64_INS_ALIAS_ST4H, "st4h" },
+	{ AARCH64_INS_ALIAS_ST2W, "st2w" },
+	{ AARCH64_INS_ALIAS_ST3W, "st3w" },
+	{ AARCH64_INS_ALIAS_ST4W, "st4w" },
+	{ AARCH64_INS_ALIAS_ST2D, "st2d" },
+	{ AARCH64_INS_ALIAS_ST3D, "st3d" },
+	{ AARCH64_INS_ALIAS_ST4D, "st4d" },
+	{ AARCH64_INS_ALIAS_ST3Q, "st3q" },
+	{ AARCH64_INS_ALIAS_ST4Q, "st4q" },
+	{ AARCH64_INS_ALIAS_STNT1H, "stnt1h" },
+	{ AARCH64_INS_ALIAS_STNT1W, "stnt1w" },
+	{ AARCH64_INS_ALIAS_STNT1D, "stnt1d" },
+	{ AARCH64_INS_ALIAS_PRFH, "prfh" },
+	{ AARCH64_INS_ALIAS_PRFW, "prfw" },
+	{ AARCH64_INS_ALIAS_PRFD, "prfd" },
+	{ AARCH64_INS_ALIAS_CNTH, "cnth" },
+	{ AARCH64_INS_ALIAS_CNTW, "cntw" },
+	{ AARCH64_INS_ALIAS_CNTD, "cntd" },
+	{ AARCH64_INS_ALIAS_DECB, "decb" },
+	{ AARCH64_INS_ALIAS_INCH, "inch" },
+	{ AARCH64_INS_ALIAS_DECH, "dech" },
+	{ AARCH64_INS_ALIAS_INCW, "incw" },
+	{ AARCH64_INS_ALIAS_DECW, "decw" },
+	{ AARCH64_INS_ALIAS_INCD, "incd" },
+	{ AARCH64_INS_ALIAS_DECD, "decd" },
+	{ AARCH64_INS_ALIAS_SQDECB, "sqdecb" },
+	{ AARCH64_INS_ALIAS_UQDECB, "uqdecb" },
+	{ AARCH64_INS_ALIAS_UQINCH, "uqinch" },
+	{ AARCH64_INS_ALIAS_SQDECH, "sqdech" },
+	{ AARCH64_INS_ALIAS_UQDECH, "uqdech" },
+	{ AARCH64_INS_ALIAS_SQINCW, "sqincw" },
+	{ AARCH64_INS_ALIAS_UQINCW, "uqincw" },
+	{ AARCH64_INS_ALIAS_SQDECW, "sqdecw" },
+	{ AARCH64_INS_ALIAS_UQDECW, "uqdecw" },
+	{ AARCH64_INS_ALIAS_SQINCD, "sqincd" },
+	{ AARCH64_INS_ALIAS_UQINCD, "uqincd" },
+	{ AARCH64_INS_ALIAS_SQDECD, "sqdecd" },
+	{ AARCH64_INS_ALIAS_UQDECD, "uqdecd" },
+	{ AARCH64_INS_ALIAS_MOVS, "movs" },
+	{ AARCH64_INS_ALIAS_NOT, "not" },
+	{ AARCH64_INS_ALIAS_NOTS, "nots" },
+	{ AARCH64_INS_ALIAS_LD1ROH, "ld1roh" },
+	{ AARCH64_INS_ALIAS_LD1ROW, "ld1row" },
+	{ AARCH64_INS_ALIAS_LD1ROD, "ld1rod" },
+	{ AARCH64_INS_ALIAS_BCAX, "bcax" },
+	{ AARCH64_INS_ALIAS_BSL, "bsl" },
+	{ AARCH64_INS_ALIAS_BSL1N, "bsl1n" },
+	{ AARCH64_INS_ALIAS_BSL2N, "bsl2n" },
+	{ AARCH64_INS_ALIAS_NBSL, "nbsl" },
+	{ AARCH64_INS_ALIAS_LDNT1SH, "ldnt1sh" },
+	{ AARCH64_INS_ALIAS_LDNT1SW, "ldnt1sw" },

thirdparty/capstone/arch/AArch64/AArch64GenCSFeatureName.inc

@@ -0,0 +1,136 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+{ AARCH64_FEATURE_HASV8_0A, "HasV8_0a" },
+{ AARCH64_FEATURE_HASV8_1A, "HasV8_1a" },
+{ AARCH64_FEATURE_HASV8_2A, "HasV8_2a" },
+{ AARCH64_FEATURE_HASV8_3A, "HasV8_3a" },
+{ AARCH64_FEATURE_HASV8_4A, "HasV8_4a" },
+{ AARCH64_FEATURE_HASV8_5A, "HasV8_5a" },
+{ AARCH64_FEATURE_HASV8_6A, "HasV8_6a" },
+{ AARCH64_FEATURE_HASV8_7A, "HasV8_7a" },
+{ AARCH64_FEATURE_HASV8_8A, "HasV8_8a" },
+{ AARCH64_FEATURE_HASV8_9A, "HasV8_9a" },
+{ AARCH64_FEATURE_HASV9_0A, "HasV9_0a" },
+{ AARCH64_FEATURE_HASV9_1A, "HasV9_1a" },
+{ AARCH64_FEATURE_HASV9_2A, "HasV9_2a" },
+{ AARCH64_FEATURE_HASV9_3A, "HasV9_3a" },
+{ AARCH64_FEATURE_HASV9_4A, "HasV9_4a" },
+{ AARCH64_FEATURE_HASV8_0R, "HasV8_0r" },
+{ AARCH64_FEATURE_HASEL2VMSA, "HasEL2VMSA" },
+{ AARCH64_FEATURE_HASEL3, "HasEL3" },
+{ AARCH64_FEATURE_HASVH, "HasVH" },
+{ AARCH64_FEATURE_HASLOR, "HasLOR" },
+{ AARCH64_FEATURE_HASPAUTH, "HasPAuth" },
+{ AARCH64_FEATURE_HASPAUTHLR, "HasPAuthLR" },
+{ AARCH64_FEATURE_HASJS, "HasJS" },
+{ AARCH64_FEATURE_HASCCIDX, "HasCCIDX" },
+{ AARCH64_FEATURE_HASCOMPLXNUM, "HasComplxNum" },
+{ AARCH64_FEATURE_HASNV, "HasNV" },
+{ AARCH64_FEATURE_HASMPAM, "HasMPAM" },
+{ AARCH64_FEATURE_HASDIT, "HasDIT" },
+{ AARCH64_FEATURE_HASTRACEV8_4, "HasTRACEV8_4" },
+{ AARCH64_FEATURE_HASAM, "HasAM" },
+{ AARCH64_FEATURE_HASSEL2, "HasSEL2" },
+{ AARCH64_FEATURE_HASTLB_RMI, "HasTLB_RMI" },
+{ AARCH64_FEATURE_HASFLAGM, "HasFlagM" },
+{ AARCH64_FEATURE_HASRCPC_IMMO, "HasRCPC_IMMO" },
+{ AARCH64_FEATURE_HASFPARMV8, "HasFPARMv8" },
+{ AARCH64_FEATURE_HASNEON, "HasNEON" },
+{ AARCH64_FEATURE_HASSM4, "HasSM4" },
+{ AARCH64_FEATURE_HASSHA3, "HasSHA3" },
+{ AARCH64_FEATURE_HASSHA2, "HasSHA2" },
+{ AARCH64_FEATURE_HASAES, "HasAES" },
+{ AARCH64_FEATURE_HASDOTPROD, "HasDotProd" },
+{ AARCH64_FEATURE_HASCRC, "HasCRC" },
+{ AARCH64_FEATURE_HASCSSC, "HasCSSC" },
+{ AARCH64_FEATURE_HASLSE, "HasLSE" },
+{ AARCH64_FEATURE_HASRAS, "HasRAS" },
+{ AARCH64_FEATURE_HASRDM, "HasRDM" },
+{ AARCH64_FEATURE_HASFULLFP16, "HasFullFP16" },
+{ AARCH64_FEATURE_HASFP16FML, "HasFP16FML" },
+{ AARCH64_FEATURE_HASSPE, "HasSPE" },
+{ AARCH64_FEATURE_HASFUSEAES, "HasFuseAES" },
+{ AARCH64_FEATURE_HASSVE, "HasSVE" },
+{ AARCH64_FEATURE_HASSVE2, "HasSVE2" },
+{ AARCH64_FEATURE_HASSVE2P1, "HasSVE2p1" },
+{ AARCH64_FEATURE_HASSVE2AES, "HasSVE2AES" },
+{ AARCH64_FEATURE_HASSVE2SM4, "HasSVE2SM4" },
+{ AARCH64_FEATURE_HASSVE2SHA3, "HasSVE2SHA3" },
+{ AARCH64_FEATURE_HASSVE2BITPERM, "HasSVE2BitPerm" },
+{ AARCH64_FEATURE_HASB16B16, "HasB16B16" },
+{ AARCH64_FEATURE_HASSME, "HasSME" },
+{ AARCH64_FEATURE_HASSMEF64F64, "HasSMEF64F64" },
+{ AARCH64_FEATURE_HASSMEF16F16, "HasSMEF16F16" },
+{ AARCH64_FEATURE_HASSMEFA64, "HasSMEFA64" },
+{ AARCH64_FEATURE_HASSMEI16I64, "HasSMEI16I64" },
+{ AARCH64_FEATURE_HASSME2, "HasSME2" },
+{ AARCH64_FEATURE_HASSME2P1, "HasSME2p1" },
+{ AARCH64_FEATURE_HASFPMR, "HasFPMR" },
+{ AARCH64_FEATURE_HASFP8, "HasFP8" },
+{ AARCH64_FEATURE_HASFAMINMAX, "HasFAMINMAX" },
+{ AARCH64_FEATURE_HASFP8FMA, "HasFP8FMA" },
+{ AARCH64_FEATURE_HASSSVE_FP8FMA, "HasSSVE_FP8FMA" },
+{ AARCH64_FEATURE_HASFP8DOT2, "HasFP8DOT2" },
+{ AARCH64_FEATURE_HASSSVE_FP8DOT2, "HasSSVE_FP8DOT2" },
+{ AARCH64_FEATURE_HASFP8DOT4, "HasFP8DOT4" },
+{ AARCH64_FEATURE_HASSSVE_FP8DOT4, "HasSSVE_FP8DOT4" },
+{ AARCH64_FEATURE_HASLUT, "HasLUT" },
+{ AARCH64_FEATURE_HASSME_LUTV2, "HasSME_LUTv2" },
+{ AARCH64_FEATURE_HASSMEF8F16, "HasSMEF8F16" },
+{ AARCH64_FEATURE_HASSMEF8F32, "HasSMEF8F32" },
+{ AARCH64_FEATURE_HASSVEORSME, "HasSVEorSME" },
+{ AARCH64_FEATURE_HASSVE2ORSME, "HasSVE2orSME" },
+{ AARCH64_FEATURE_HASSVE2ORSME2, "HasSVE2orSME2" },
+{ AARCH64_FEATURE_HASSVE2P1_OR_HASSME, "HasSVE2p1_or_HasSME" },
+{ AARCH64_FEATURE_HASSVE2P1_OR_HASSME2, "HasSVE2p1_or_HasSME2" },
+{ AARCH64_FEATURE_HASSVE2P1_OR_HASSME2P1, "HasSVE2p1_or_HasSME2p1" },
+{ AARCH64_FEATURE_HASNEONORSME, "HasNEONorSME" },
+{ AARCH64_FEATURE_HASRCPC, "HasRCPC" },
+{ AARCH64_FEATURE_HASALTNZCV, "HasAltNZCV" },
+{ AARCH64_FEATURE_HASFRINT3264, "HasFRInt3264" },
+{ AARCH64_FEATURE_HASSB, "HasSB" },
+{ AARCH64_FEATURE_HASPREDRES, "HasPredRes" },
+{ AARCH64_FEATURE_HASCCDP, "HasCCDP" },
+{ AARCH64_FEATURE_HASBTI, "HasBTI" },
+{ AARCH64_FEATURE_HASMTE, "HasMTE" },
+{ AARCH64_FEATURE_HASTME, "HasTME" },
+{ AARCH64_FEATURE_HASETE, "HasETE" },
+{ AARCH64_FEATURE_HASTRBE, "HasTRBE" },
+{ AARCH64_FEATURE_HASBF16, "HasBF16" },
+{ AARCH64_FEATURE_HASMATMULINT8, "HasMatMulInt8" },
+{ AARCH64_FEATURE_HASMATMULFP32, "HasMatMulFP32" },
+{ AARCH64_FEATURE_HASMATMULFP64, "HasMatMulFP64" },
+{ AARCH64_FEATURE_HASXS, "HasXS" },
+{ AARCH64_FEATURE_HASWFXT, "HasWFxT" },
+{ AARCH64_FEATURE_HASLS64, "HasLS64" },
+{ AARCH64_FEATURE_HASBRBE, "HasBRBE" },
+{ AARCH64_FEATURE_HASSPE_EEF, "HasSPE_EEF" },
+{ AARCH64_FEATURE_HASHBC, "HasHBC" },
+{ AARCH64_FEATURE_HASMOPS, "HasMOPS" },
+{ AARCH64_FEATURE_HASCLRBHB, "HasCLRBHB" },
+{ AARCH64_FEATURE_HASSPECRES2, "HasSPECRES2" },
+{ AARCH64_FEATURE_HASITE, "HasITE" },
+{ AARCH64_FEATURE_HASTHE, "HasTHE" },
+{ AARCH64_FEATURE_HASRCPC3, "HasRCPC3" },
+{ AARCH64_FEATURE_HASLSE128, "HasLSE128" },
+{ AARCH64_FEATURE_HASD128, "HasD128" },
+{ AARCH64_FEATURE_HASCHK, "HasCHK" },
+{ AARCH64_FEATURE_HASGCS, "HasGCS" },
+{ AARCH64_FEATURE_HASCPA, "HasCPA" },
+{ AARCH64_FEATURE_USENEGATIVEIMMEDIATES, "UseNegativeImmediates" },
+{ AARCH64_FEATURE_HASCCPP, "HasCCPP" },
+{ AARCH64_FEATURE_HASPAN, "HasPAN" },
+{ AARCH64_FEATURE_HASPSUAO, "HasPsUAO" },
+{ AARCH64_FEATURE_HASPAN_RWV, "HasPAN_RWV" },
+{ AARCH64_FEATURE_HASCONTEXTIDREL2, "HasCONTEXTIDREL2" },

thirdparty/capstone/arch/AArch64/AArch64GenCSOpGroup.inc

@@ -0,0 +1,180 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+  AArch64_OP_GROUP_AMNoIndex = 0,
+  AArch64_OP_GROUP_AdrLabel = 1,
+  AArch64_OP_GROUP_AdrpLabel = 2,
+  AArch64_OP_GROUP_BTIHintOp = 3,
+  AArch64_OP_GROUP_ImplicitlyTypedVectorList = 4,
+  AArch64_OP_GROUP_InverseCondCode = 5,
+  AArch64_OP_GROUP_LogicalImm_int16_t = 6,
+  AArch64_OP_GROUP_LogicalImm_int8_t = 7,
+  AArch64_OP_GROUP_MatrixIndex_0 = 8,
+  AArch64_OP_GROUP_MatrixIndex_1 = 9,
+  AArch64_OP_GROUP_MatrixIndex_8 = 10,
+  AArch64_OP_GROUP_PSBHintOp = 11,
+  AArch64_OP_GROUP_PrefetchOp_1 = 12,
+  AArch64_OP_GROUP_SVELogicalImm_int16_t = 13,
+  AArch64_OP_GROUP_SVELogicalImm_int32_t = 14,
+  AArch64_OP_GROUP_SVELogicalImm_int64_t = 15,
+  AArch64_OP_GROUP_SVERegOp_0 = 16,
+  AArch64_OP_GROUP_VectorIndex_8 = 17,
+  AArch64_OP_GROUP_ZPRasFPR_128 = 18,
+  AArch64_OP_GROUP_Operand = 19,
+  AArch64_OP_GROUP_SVERegOp_b = 20,
+  AArch64_OP_GROUP_SVERegOp_d = 21,
+  AArch64_OP_GROUP_SVERegOp_h = 22,
+  AArch64_OP_GROUP_SVERegOp_s = 23,
+  AArch64_OP_GROUP_TypedVectorList_0_d = 24,
+  AArch64_OP_GROUP_TypedVectorList_0_s = 25,
+  AArch64_OP_GROUP_VRegOperand = 26,
+  AArch64_OP_GROUP_TypedVectorList_0_h = 27,
+  AArch64_OP_GROUP_VectorIndex_1 = 28,
+  AArch64_OP_GROUP_ImmRangeScale_2_1 = 29,
+  AArch64_OP_GROUP_AlignedLabel = 30,
+  AArch64_OP_GROUP_CondCode = 31,
+  AArch64_OP_GROUP_ExactFPImm_AArch64ExactFPImm_half_AArch64ExactFPImm_one = 32,
+  AArch64_OP_GROUP_TypedVectorList_0_b = 33,
+  AArch64_OP_GROUP_ExactFPImm_AArch64ExactFPImm_zero_AArch64ExactFPImm_one = 34,
+  AArch64_OP_GROUP_ImmRangeScale_4_3 = 35,
+  AArch64_OP_GROUP_ExactFPImm_AArch64ExactFPImm_half_AArch64ExactFPImm_two = 36,
+  AArch64_OP_GROUP_RegWithShiftExtend_0_8_x_d = 37,
+  AArch64_OP_GROUP_RegWithShiftExtend_1_8_w_d = 38,
+  AArch64_OP_GROUP_RegWithShiftExtend_0_8_w_d = 39,
+  AArch64_OP_GROUP_RegWithShiftExtend_1_8_w_s = 40,
+  AArch64_OP_GROUP_RegWithShiftExtend_0_8_w_s = 41,
+  AArch64_OP_GROUP_ImmScale_8 = 42,
+  AArch64_OP_GROUP_RegWithShiftExtend_0_64_x_d = 43,
+  AArch64_OP_GROUP_RegWithShiftExtend_1_64_w_d = 44,
+  AArch64_OP_GROUP_RegWithShiftExtend_0_64_w_d = 45,
+  AArch64_OP_GROUP_ImmScale_2 = 46,
+  AArch64_OP_GROUP_RegWithShiftExtend_0_16_x_d = 47,
+  AArch64_OP_GROUP_RegWithShiftExtend_1_16_w_d = 48,
+  AArch64_OP_GROUP_RegWithShiftExtend_0_16_w_d = 49,
+  AArch64_OP_GROUP_RegWithShiftExtend_1_16_w_s = 50,
+  AArch64_OP_GROUP_RegWithShiftExtend_0_16_w_s = 51,
+  AArch64_OP_GROUP_ImmScale_4 = 52,
+  AArch64_OP_GROUP_RegWithShiftExtend_0_32_x_d = 53,
+  AArch64_OP_GROUP_RegWithShiftExtend_1_32_w_d = 54,
+  AArch64_OP_GROUP_RegWithShiftExtend_0_32_w_d = 55,
+  AArch64_OP_GROUP_RegWithShiftExtend_1_32_w_s = 56,
+  AArch64_OP_GROUP_RegWithShiftExtend_0_32_w_s = 57,
+  AArch64_OP_GROUP_PredicateAsCounter_0 = 58,
+  AArch64_OP_GROUP_RegWithShiftExtend_0_8_x_0 = 59,
+  AArch64_OP_GROUP_RegWithShiftExtend_0_64_x_0 = 60,
+  AArch64_OP_GROUP_RegWithShiftExtend_0_16_x_0 = 61,
+  AArch64_OP_GROUP_RegWithShiftExtend_0_32_x_0 = 62,
+  AArch64_OP_GROUP_SVCROp = 63,
+  AArch64_OP_GROUP_ImmScale_16 = 64,
+  AArch64_OP_GROUP_MatrixTile = 65,
+  AArch64_OP_GROUP_Shifter = 66,
+  AArch64_OP_GROUP_AddSubImm = 67,
+  AArch64_OP_GROUP_ShiftedRegister = 68,
+  AArch64_OP_GROUP_ExtendedRegister = 69,
+  AArch64_OP_GROUP_ArithExtend = 70,
+  AArch64_OP_GROUP_Matrix_64 = 71,
+  AArch64_OP_GROUP_Matrix_32 = 72,
+  AArch64_OP_GROUP_Imm8OptLsl_uint8_t = 73,
+  AArch64_OP_GROUP_Imm8OptLsl_uint64_t = 74,
+  AArch64_OP_GROUP_Imm8OptLsl_uint16_t = 75,
+  AArch64_OP_GROUP_Imm8OptLsl_uint32_t = 76,
+  AArch64_OP_GROUP_AdrAdrpLabel = 77,
+  AArch64_OP_GROUP_RegWithShiftExtend_0_8_x_s = 78,
+  AArch64_OP_GROUP_RegWithShiftExtend_0_16_x_s = 79,
+  AArch64_OP_GROUP_RegWithShiftExtend_0_32_x_s = 80,
+  AArch64_OP_GROUP_RegWithShiftExtend_0_64_x_s = 81,
+  AArch64_OP_GROUP_LogicalImm_int32_t = 82,
+  AArch64_OP_GROUP_LogicalImm_int64_t = 83,
+  AArch64_OP_GROUP_ZPRasFPR_8 = 84,
+  AArch64_OP_GROUP_ZPRasFPR_64 = 85,
+  AArch64_OP_GROUP_ZPRasFPR_16 = 86,
+  AArch64_OP_GROUP_ZPRasFPR_32 = 87,
+  AArch64_OP_GROUP_Matrix_16 = 88,
+  AArch64_OP_GROUP_Imm = 89,
+  AArch64_OP_GROUP_ImmHex = 90,
+  AArch64_OP_GROUP_ComplexRotationOp_180_90 = 91,
+  AArch64_OP_GROUP_GPRSeqPairsClassOperand_32 = 92,
+  AArch64_OP_GROUP_GPRSeqPairsClassOperand_64 = 93,
+  AArch64_OP_GROUP_ComplexRotationOp_90_0 = 94,
+  AArch64_OP_GROUP_SVEPattern = 95,
+  AArch64_OP_GROUP_PredicateAsCounter_8 = 96,
+  AArch64_OP_GROUP_SVEVecLenSpecifier = 97,
+  AArch64_OP_GROUP_PredicateAsCounter_64 = 98,
+  AArch64_OP_GROUP_PredicateAsCounter_16 = 99,
+  AArch64_OP_GROUP_PredicateAsCounter_32 = 100,
+  AArch64_OP_GROUP_Imm8OptLsl_int8_t = 101,
+  AArch64_OP_GROUP_Imm8OptLsl_int64_t = 102,
+  AArch64_OP_GROUP_Imm8OptLsl_int16_t = 103,
+  AArch64_OP_GROUP_Imm8OptLsl_int32_t = 104,
+  AArch64_OP_GROUP_BarrierOption = 105,
+  AArch64_OP_GROUP_BarriernXSOption = 106,
+  AArch64_OP_GROUP_SVERegOp_q = 107,
+  AArch64_OP_GROUP_MatrixTileVector_0 = 108,
+  AArch64_OP_GROUP_MatrixTileVector_1 = 109,
+  AArch64_OP_GROUP_FPImmOperand = 110,
+  AArch64_OP_GROUP_TypedVectorList_0_q = 111,
+  AArch64_OP_GROUP_SImm_8 = 112,
+  AArch64_OP_GROUP_SImm_16 = 113,
+  AArch64_OP_GROUP_TypedVectorList_16_b = 114,
+  AArch64_OP_GROUP_PostIncOperand_64 = 115,
+  AArch64_OP_GROUP_TypedVectorList_1_d = 116,
+  AArch64_OP_GROUP_PostIncOperand_32 = 117,
+  AArch64_OP_GROUP_TypedVectorList_2_d = 118,
+  AArch64_OP_GROUP_TypedVectorList_2_s = 119,
+  AArch64_OP_GROUP_TypedVectorList_4_h = 120,
+  AArch64_OP_GROUP_TypedVectorList_4_s = 121,
+  AArch64_OP_GROUP_TypedVectorList_8_b = 122,
+  AArch64_OP_GROUP_TypedVectorList_8_h = 123,
+  AArch64_OP_GROUP_PostIncOperand_16 = 124,
+  AArch64_OP_GROUP_PostIncOperand_8 = 125,
+  AArch64_OP_GROUP_ImmScale_32 = 126,
+  AArch64_OP_GROUP_PostIncOperand_1 = 127,
+  AArch64_OP_GROUP_PostIncOperand_4 = 128,
+  AArch64_OP_GROUP_PostIncOperand_2 = 129,
+  AArch64_OP_GROUP_PostIncOperand_48 = 130,
+  AArch64_OP_GROUP_PostIncOperand_24 = 131,
+  AArch64_OP_GROUP_RegWithShiftExtend_0_128_x_0 = 132,
+  AArch64_OP_GROUP_ImmScale_3 = 133,
+  AArch64_OP_GROUP_PostIncOperand_3 = 134,
+  AArch64_OP_GROUP_PostIncOperand_12 = 135,
+  AArch64_OP_GROUP_PostIncOperand_6 = 136,
+  AArch64_OP_GROUP_GPR64x8 = 137,
+  AArch64_OP_GROUP_MemExtend_w_8 = 138,
+  AArch64_OP_GROUP_MemExtend_x_8 = 139,
+  AArch64_OP_GROUP_UImm12Offset_1 = 140,
+  AArch64_OP_GROUP_MemExtend_w_64 = 141,
+  AArch64_OP_GROUP_MemExtend_x_64 = 142,
+  AArch64_OP_GROUP_UImm12Offset_8 = 143,
+  AArch64_OP_GROUP_MemExtend_w_16 = 144,
+  AArch64_OP_GROUP_MemExtend_x_16 = 145,
+  AArch64_OP_GROUP_UImm12Offset_2 = 146,
+  AArch64_OP_GROUP_MemExtend_w_128 = 147,
+  AArch64_OP_GROUP_MemExtend_x_128 = 148,
+  AArch64_OP_GROUP_UImm12Offset_16 = 149,
+  AArch64_OP_GROUP_MemExtend_w_32 = 150,
+  AArch64_OP_GROUP_MemExtend_x_32 = 151,
+  AArch64_OP_GROUP_UImm12Offset_4 = 152,
+  AArch64_OP_GROUP_Matrix_0 = 153,
+  AArch64_OP_GROUP_TypedVectorList_0_0 = 154,
+  AArch64_OP_GROUP_SIMDType10Operand = 155,
+  AArch64_OP_GROUP_MRSSystemRegister = 156,
+  AArch64_OP_GROUP_MSRSystemRegister = 157,
+  AArch64_OP_GROUP_SystemPStateField = 158,
+  AArch64_OP_GROUP_RegWithShiftExtend_1_64_w_s = 159,
+  AArch64_OP_GROUP_RegWithShiftExtend_0_64_w_s = 160,
+  AArch64_OP_GROUP_PrefetchOp_0 = 161,
+  AArch64_OP_GROUP_RPRFMOperand = 162,
+  AArch64_OP_GROUP_GPR64as32 = 163,
+  AArch64_OP_GROUP_SysCROperand = 164,
+  AArch64_OP_GROUP_SyspXzrPair = 165,
+  AArch64_OP_GROUP_MatrixTileList = 166,

thirdparty/capstone/arch/AArch64/AArch64GenRegisterName.inc

@@ -0,0 +1,714 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+
+/// getRegisterName - This method is automatically generated by tblgen
+/// from the register set description.  This returns the assembler name
+/// for the specified register.
+static const char *getRegisterName(unsigned RegNo, unsigned AltIdx)
+{
+
+
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Woverlength-strings"
+#endif
+#ifndef CAPSTONE_DIET
+  static const char AsmStrsNoRegAltName[] = {
+  /* 0 */ "D7_D8_D9_D10\0"
+  /* 13 */ "Q7_Q8_Q9_Q10\0"
+  /* 26 */ "Z7_Z8_Z9_Z10\0"
+  /* 39 */ "b10\0"
+  /* 43 */ "d10\0"
+  /* 47 */ "h10\0"
+  /* 51 */ "p10\0"
+  /* 55 */ "q10\0"
+  /* 59 */ "s10\0"
+  /* 63 */ "w10\0"
+  /* 67 */ "x10\0"
+  /* 71 */ "z10\0"
+  /* 75 */ "D17_D18_D19_D20\0"
+  /* 91 */ "Q17_Q18_Q19_Q20\0"
+  /* 107 */ "Z17_Z18_Z19_Z20\0"
+  /* 123 */ "b20\0"
+  /* 127 */ "d20\0"
+  /* 131 */ "h20\0"
+  /* 135 */ "q20\0"
+  /* 139 */ "s20\0"
+  /* 143 */ "w20\0"
+  /* 147 */ "x20\0"
+  /* 151 */ "z20\0"
+  /* 155 */ "D27_D28_D29_D30\0"
+  /* 171 */ "Q27_Q28_Q29_Q30\0"
+  /* 187 */ "Z27_Z28_Z29_Z30\0"
+  /* 203 */ "b30\0"
+  /* 207 */ "d30\0"
+  /* 211 */ "h30\0"
+  /* 215 */ "q30\0"
+  /* 219 */ "s30\0"
+  /* 223 */ "w30\0"
+  /* 227 */ "x30\0"
+  /* 231 */ "z30\0"
+  /* 235 */ "D29_D30_D31_D0\0"
+  /* 250 */ "Q29_Q30_Q31_Q0\0"
+  /* 265 */ "Z29_Z30_Z31_Z0\0"
+  /* 280 */ "b0\0"
+  /* 283 */ "d0\0"
+  /* 286 */ "h0\0"
+  /* 289 */ "p0\0"
+  /* 292 */ "q0\0"
+  /* 295 */ "s0\0"
+  /* 298 */ "w0\0"
+  /* 301 */ "x0\0"
+  /* 304 */ "z0\0"
+  /* 307 */ "D8_D9_D10_D11\0"
+  /* 321 */ "Q8_Q9_Q10_Q11\0"
+  /* 335 */ "W10_W11\0"
+  /* 343 */ "X4_X5_X6_X7_X8_X9_X10_X11\0"
+  /* 369 */ "Z8_Z9_Z10_Z11\0"
+  /* 383 */ "b11\0"
+  /* 387 */ "d11\0"
+  /* 391 */ "h11\0"
+  /* 395 */ "p11\0"
+  /* 399 */ "q11\0"
+  /* 403 */ "s11\0"
+  /* 407 */ "w11\0"
+  /* 411 */ "x11\0"
+  /* 415 */ "z11\0"
+  /* 419 */ "D18_D19_D20_D21\0"
+  /* 435 */ "Q18_Q19_Q20_Q21\0"
+  /* 451 */ "W20_W21\0"
+  /* 459 */ "X14_X15_X16_X17_X18_X19_X20_X21\0"
+  /* 491 */ "Z18_Z19_Z20_Z21\0"
+  /* 507 */ "b21\0"
+  /* 511 */ "d21\0"
+  /* 515 */ "h21\0"
+  /* 519 */ "q21\0"
+  /* 523 */ "s21\0"
+  /* 527 */ "w21\0"
+  /* 531 */ "x21\0"
+  /* 535 */ "z21\0"
+  /* 539 */ "D28_D29_D30_D31\0"
+  /* 555 */ "Q28_Q29_Q30_Q31\0"
+  /* 571 */ "Z28_Z29_Z30_Z31\0"
+  /* 587 */ "b31\0"
+  /* 591 */ "d31\0"
+  /* 595 */ "h31\0"
+  /* 599 */ "q31\0"
+  /* 603 */ "s31\0"
+  /* 607 */ "z31\0"
+  /* 611 */ "D30_D31_D0_D1\0"
+  /* 625 */ "Q30_Q31_Q0_Q1\0"
+  /* 639 */ "W0_W1\0"
+  /* 645 */ "X0_X1\0"
+  /* 651 */ "Z30_Z31_Z0_Z1\0"
+  /* 665 */ "b1\0"
+  /* 668 */ "d1\0"
+  /* 671 */ "h1\0"
+  /* 674 */ "p1\0"
+  /* 677 */ "q1\0"
+  /* 680 */ "s1\0"
+  /* 683 */ "w1\0"
+  /* 686 */ "x1\0"
+  /* 689 */ "z1\0"
+  /* 692 */ "D9_D10_D11_D12\0"
+  /* 707 */ "Q9_Q10_Q11_Q12\0"
+  /* 722 */ "Z9_Z10_Z11_Z12\0"
+  /* 737 */ "b12\0"
+  /* 741 */ "d12\0"
+  /* 745 */ "h12\0"
+  /* 749 */ "p12\0"
+  /* 753 */ "q12\0"
+  /* 757 */ "s12\0"
+  /* 761 */ "w12\0"
+  /* 765 */ "x12\0"
+  /* 769 */ "z12\0"
+  /* 773 */ "D19_D20_D21_D22\0"
+  /* 789 */ "Q19_Q20_Q21_Q22\0"
+  /* 805 */ "Z19_Z20_Z21_Z22\0"
+  /* 821 */ "b22\0"
+  /* 825 */ "d22\0"
+  /* 829 */ "h22\0"
+  /* 833 */ "q22\0"
+  /* 837 */ "s22\0"
+  /* 841 */ "w22\0"
+  /* 845 */ "x22\0"
+  /* 849 */ "z22\0"
+  /* 853 */ "D31_D0_D1_D2\0"
+  /* 866 */ "Q31_Q0_Q1_Q2\0"
+  /* 879 */ "Z31_Z0_Z1_Z2\0"
+  /* 892 */ "b2\0"
+  /* 895 */ "d2\0"
+  /* 898 */ "h2\0"
+  /* 901 */ "p2\0"
+  /* 904 */ "q2\0"
+  /* 907 */ "s2\0"
+  /* 910 */ "w2\0"
+  /* 913 */ "x2\0"
+  /* 916 */ "z2\0"
+  /* 919 */ "D10_D11_D12_D13\0"
+  /* 935 */ "Q10_Q11_Q12_Q13\0"
+  /* 951 */ "W12_W13\0"
+  /* 959 */ "X6_X7_X8_X9_X10_X11_X12_X13\0"
+  /* 987 */ "Z10_Z11_Z12_Z13\0"
+  /* 1003 */ "b13\0"
+  /* 1007 */ "d13\0"
+  /* 1011 */ "h13\0"
+  /* 1015 */ "p13\0"
+  /* 1019 */ "q13\0"
+  /* 1023 */ "s13\0"
+  /* 1027 */ "w13\0"
+  /* 1031 */ "x13\0"
+  /* 1035 */ "z13\0"
+  /* 1039 */ "D20_D21_D22_D23\0"
+  /* 1055 */ "Q20_Q21_Q22_Q23\0"
+  /* 1071 */ "W22_W23\0"
+  /* 1079 */ "X16_X17_X18_X19_X20_X21_X22_X23\0"
+  /* 1111 */ "Z20_Z21_Z22_Z23\0"
+  /* 1127 */ "b23\0"
+  /* 1131 */ "d23\0"
+  /* 1135 */ "h23\0"
+  /* 1139 */ "q23\0"
+  /* 1143 */ "s23\0"
+  /* 1147 */ "w23\0"
+  /* 1151 */ "x23\0"
+  /* 1155 */ "z23\0"
+  /* 1159 */ "D0_D1_D2_D3\0"
+  /* 1171 */ "Q0_Q1_Q2_Q3\0"
+  /* 1183 */ "W2_W3\0"
+  /* 1189 */ "X2_X3\0"
+  /* 1195 */ "Z0_Z1_Z2_Z3\0"
+  /* 1207 */ "b3\0"
+  /* 1210 */ "d3\0"
+  /* 1213 */ "h3\0"
+  /* 1216 */ "p3\0"
+  /* 1219 */ "q3\0"
+  /* 1222 */ "s3\0"
+  /* 1225 */ "w3\0"
+  /* 1228 */ "x3\0"
+  /* 1231 */ "z3\0"
+  /* 1234 */ "D11_D12_D13_D14\0"
+  /* 1250 */ "Q11_Q12_Q13_Q14\0"
+  /* 1266 */ "Z11_Z12_Z13_Z14\0"
+  /* 1282 */ "b14\0"
+  /* 1286 */ "d14\0"
+  /* 1290 */ "h14\0"
+  /* 1294 */ "p14\0"
+  /* 1298 */ "q14\0"
+  /* 1302 */ "s14\0"
+  /* 1306 */ "w14\0"
+  /* 1310 */ "x14\0"
+  /* 1314 */ "z14\0"
+  /* 1318 */ "D21_D22_D23_D24\0"
+  /* 1334 */ "Q21_Q22_Q23_Q24\0"
+  /* 1350 */ "Z21_Z22_Z23_Z24\0"
+  /* 1366 */ "b24\0"
+  /* 1370 */ "d24\0"
+  /* 1374 */ "h24\0"
+  /* 1378 */ "q24\0"
+  /* 1382 */ "s24\0"
+  /* 1386 */ "w24\0"
+  /* 1390 */ "x24\0"
+  /* 1394 */ "z24\0"
+  /* 1398 */ "D1_D2_D3_D4\0"
+  /* 1410 */ "Q1_Q2_Q3_Q4\0"
+  /* 1422 */ "Z1_Z2_Z3_Z4\0"
+  /* 1434 */ "b4\0"
+  /* 1437 */ "d4\0"
+  /* 1440 */ "h4\0"
+  /* 1443 */ "p4\0"
+  /* 1446 */ "q4\0"
+  /* 1449 */ "s4\0"
+  /* 1452 */ "w4\0"
+  /* 1455 */ "x4\0"
+  /* 1458 */ "z4\0"
+  /* 1461 */ "D12_D13_D14_D15\0"
+  /* 1477 */ "Q12_Q13_Q14_Q15\0"
+  /* 1493 */ "W14_W15\0"
+  /* 1501 */ "X8_X9_X10_X11_X12_X13_X14_X15\0"
+  /* 1531 */ "Z12_Z13_Z14_Z15\0"
+  /* 1547 */ "b15\0"
+  /* 1551 */ "d15\0"
+  /* 1555 */ "h15\0"
+  /* 1559 */ "p15\0"
+  /* 1563 */ "q15\0"
+  /* 1567 */ "s15\0"
+  /* 1571 */ "w15\0"
+  /* 1575 */ "x15\0"
+  /* 1579 */ "z15\0"
+  /* 1583 */ "D22_D23_D24_D25\0"
+  /* 1599 */ "Q22_Q23_Q24_Q25\0"
+  /* 1615 */ "W24_W25\0"
+  /* 1623 */ "X18_X19_X20_X21_X22_X23_X24_X25\0"
+  /* 1655 */ "Z22_Z23_Z24_Z25\0"
+  /* 1671 */ "b25\0"
+  /* 1675 */ "d25\0"
+  /* 1679 */ "h25\0"
+  /* 1683 */ "q25\0"
+  /* 1687 */ "s25\0"
+  /* 1691 */ "w25\0"
+  /* 1695 */ "x25\0"
+  /* 1699 */ "z25\0"
+  /* 1703 */ "D2_D3_D4_D5\0"
+  /* 1715 */ "Q2_Q3_Q4_Q5\0"
+  /* 1727 */ "W4_W5\0"
+  /* 1733 */ "X4_X5\0"
+  /* 1739 */ "Z2_Z3_Z4_Z5\0"
+  /* 1751 */ "b5\0"
+  /* 1754 */ "d5\0"
+  /* 1757 */ "h5\0"
+  /* 1760 */ "p5\0"
+  /* 1763 */ "q5\0"
+  /* 1766 */ "s5\0"
+  /* 1769 */ "w5\0"
+  /* 1772 */ "x5\0"
+  /* 1775 */ "z5\0"
+  /* 1778 */ "D13_D14_D15_D16\0"
+  /* 1794 */ "Q13_Q14_Q15_Q16\0"
+  /* 1810 */ "Z13_Z14_Z15_Z16\0"
+  /* 1826 */ "b16\0"
+  /* 1830 */ "d16\0"
+  /* 1834 */ "h16\0"
+  /* 1838 */ "q16\0"
+  /* 1842 */ "s16\0"
+  /* 1846 */ "w16\0"
+  /* 1850 */ "x16\0"
+  /* 1854 */ "z16\0"
+  /* 1858 */ "D23_D24_D25_D26\0"
+  /* 1874 */ "Q23_Q24_Q25_Q26\0"
+  /* 1890 */ "Z23_Z24_Z25_Z26\0"
+  /* 1906 */ "b26\0"
+  /* 1910 */ "d26\0"
+  /* 1914 */ "h26\0"
+  /* 1918 */ "q26\0"
+  /* 1922 */ "s26\0"
+  /* 1926 */ "w26\0"
+  /* 1930 */ "x26\0"
+  /* 1934 */ "z26\0"
+  /* 1938 */ "D3_D4_D5_D6\0"
+  /* 1950 */ "Q3_Q4_Q5_Q6\0"
+  /* 1962 */ "Z3_Z4_Z5_Z6\0"
+  /* 1974 */ "b6\0"
+  /* 1977 */ "d6\0"
+  /* 1980 */ "h6\0"
+  /* 1983 */ "p6\0"
+  /* 1986 */ "q6\0"
+  /* 1989 */ "s6\0"
+  /* 1992 */ "w6\0"
+  /* 1995 */ "x6\0"
+  /* 1998 */ "z6\0"
+  /* 2001 */ "D14_D15_D16_D17\0"
+  /* 2017 */ "Q14_Q15_Q16_Q17\0"
+  /* 2033 */ "W16_W17\0"
+  /* 2041 */ "X10_X11_X12_X13_X14_X15_X16_X17\0"
+  /* 2073 */ "Z14_Z15_Z16_Z17\0"
+  /* 2089 */ "b17\0"
+  /* 2093 */ "d17\0"
+  /* 2097 */ "h17\0"
+  /* 2101 */ "q17\0"
+  /* 2105 */ "s17\0"
+  /* 2109 */ "w17\0"
+  /* 2113 */ "x17\0"
+  /* 2117 */ "z17\0"
+  /* 2121 */ "D24_D25_D26_D27\0"
+  /* 2137 */ "Q24_Q25_Q26_Q27\0"
+  /* 2153 */ "W26_W27\0"
+  /* 2161 */ "X20_X21_X22_X23_X24_X25_X26_X27\0"
+  /* 2193 */ "Z24_Z25_Z26_Z27\0"
+  /* 2209 */ "b27\0"
+  /* 2213 */ "d27\0"
+  /* 2217 */ "h27\0"
+  /* 2221 */ "q27\0"
+  /* 2225 */ "s27\0"
+  /* 2229 */ "w27\0"
+  /* 2233 */ "x27\0"
+  /* 2237 */ "z27\0"
+  /* 2241 */ "D4_D5_D6_D7\0"
+  /* 2253 */ "Q4_Q5_Q6_Q7\0"
+  /* 2265 */ "W6_W7\0"
+  /* 2271 */ "X0_X1_X2_X3_X4_X5_X6_X7\0"
+  /* 2295 */ "Z4_Z5_Z6_Z7\0"
+  /* 2307 */ "b7\0"
+  /* 2310 */ "d7\0"
+  /* 2313 */ "h7\0"
+  /* 2316 */ "p7\0"
+  /* 2319 */ "q7\0"
+  /* 2322 */ "s7\0"
+  /* 2325 */ "w7\0"
+  /* 2328 */ "x7\0"
+  /* 2331 */ "z7\0"
+  /* 2334 */ "D15_D16_D17_D18\0"
+  /* 2350 */ "Q15_Q16_Q17_Q18\0"
+  /* 2366 */ "Z15_Z16_Z17_Z18\0"
+  /* 2382 */ "b18\0"
+  /* 2386 */ "d18\0"
+  /* 2390 */ "h18\0"
+  /* 2394 */ "q18\0"
+  /* 2398 */ "s18\0"
+  /* 2402 */ "w18\0"
+  /* 2406 */ "x18\0"
+  /* 2410 */ "z18\0"
+  /* 2414 */ "D25_D26_D27_D28\0"
+  /* 2430 */ "Q25_Q26_Q27_Q28\0"
+  /* 2446 */ "Z25_Z26_Z27_Z28\0"
+  /* 2462 */ "b28\0"
+  /* 2466 */ "d28\0"
+  /* 2470 */ "h28\0"
+  /* 2474 */ "q28\0"
+  /* 2478 */ "s28\0"
+  /* 2482 */ "w28\0"
+  /* 2486 */ "x28\0"
+  /* 2490 */ "z28\0"
+  /* 2494 */ "D5_D6_D7_D8\0"
+  /* 2506 */ "Q5_Q6_Q7_Q8\0"
+  /* 2518 */ "Z5_Z6_Z7_Z8\0"
+  /* 2530 */ "b8\0"
+  /* 2533 */ "d8\0"
+  /* 2536 */ "h8\0"
+  /* 2539 */ "p8\0"
+  /* 2542 */ "q8\0"
+  /* 2545 */ "s8\0"
+  /* 2548 */ "w8\0"
+  /* 2551 */ "x8\0"
+  /* 2554 */ "z8\0"
+  /* 2557 */ "D16_D17_D18_D19\0"
+  /* 2573 */ "Q16_Q17_Q18_Q19\0"
+  /* 2589 */ "W18_W19\0"
+  /* 2597 */ "X12_X13_X14_X15_X16_X17_X18_X19\0"
+  /* 2629 */ "Z16_Z17_Z18_Z19\0"
+  /* 2645 */ "b19\0"
+  /* 2649 */ "d19\0"
+  /* 2653 */ "h19\0"
+  /* 2657 */ "q19\0"
+  /* 2661 */ "s19\0"
+  /* 2665 */ "w19\0"
+  /* 2669 */ "x19\0"
+  /* 2673 */ "z19\0"
+  /* 2677 */ "D26_D27_D28_D29\0"
+  /* 2693 */ "Q26_Q27_Q28_Q29\0"
+  /* 2709 */ "W28_W29\0"
+  /* 2717 */ "Z26_Z27_Z28_Z29\0"
+  /* 2733 */ "b29\0"
+  /* 2737 */ "d29\0"
+  /* 2741 */ "h29\0"
+  /* 2745 */ "q29\0"
+  /* 2749 */ "s29\0"
+  /* 2753 */ "w29\0"
+  /* 2757 */ "x29\0"
+  /* 2761 */ "z29\0"
+  /* 2765 */ "D6_D7_D8_D9\0"
+  /* 2777 */ "Q6_Q7_Q8_Q9\0"
+  /* 2789 */ "W8_W9\0"
+  /* 2795 */ "X2_X3_X4_X5_X6_X7_X8_X9\0"
+  /* 2819 */ "Z6_Z7_Z8_Z9\0"
+  /* 2831 */ "b9\0"
+  /* 2834 */ "d9\0"
+  /* 2837 */ "h9\0"
+  /* 2840 */ "p9\0"
+  /* 2843 */ "q9\0"
+  /* 2846 */ "s9\0"
+  /* 2849 */ "w9\0"
+  /* 2852 */ "x9\0"
+  /* 2855 */ "z9\0"
+  /* 2858 */ "X22_X23_X24_X25_X26_X27_X28_FP\0"
+  /* 2889 */ "W30_WZR\0"
+  /* 2897 */ "LR_XZR\0"
+  /* 2904 */ "za\0"
+  /* 2907 */ "za0.b\0"
+  /* 2913 */ "za0.d\0"
+  /* 2919 */ "za1.d\0"
+  /* 2925 */ "za2.d\0"
+  /* 2931 */ "za3.d\0"
+  /* 2937 */ "za4.d\0"
+  /* 2943 */ "za5.d\0"
+  /* 2949 */ "za6.d\0"
+  /* 2955 */ "za7.d\0"
+  /* 2961 */ "vg\0"
+  /* 2964 */ "za0.h\0"
+  /* 2970 */ "za1.h\0"
+  /* 2976 */ "z10_hi\0"
+  /* 2983 */ "z20_hi\0"
+  /* 2990 */ "z30_hi\0"
+  /* 2997 */ "z0_hi\0"
+  /* 3003 */ "z11_hi\0"
+  /* 3010 */ "z21_hi\0"
+  /* 3017 */ "z31_hi\0"
+  /* 3024 */ "z1_hi\0"
+  /* 3030 */ "z12_hi\0"
+  /* 3037 */ "z22_hi\0"
+  /* 3044 */ "z2_hi\0"
+  /* 3050 */ "z13_hi\0"
+  /* 3057 */ "z23_hi\0"
+  /* 3064 */ "z3_hi\0"
+  /* 3070 */ "z14_hi\0"
+  /* 3077 */ "z24_hi\0"
+  /* 3084 */ "z4_hi\0"
+  /* 3090 */ "z15_hi\0"
+  /* 3097 */ "z25_hi\0"
+  /* 3104 */ "z5_hi\0"
+  /* 3110 */ "z16_hi\0"
+  /* 3117 */ "z26_hi\0"
+  /* 3124 */ "z6_hi\0"
+  /* 3130 */ "z17_hi\0"
+  /* 3137 */ "z27_hi\0"
+  /* 3144 */ "z7_hi\0"
+  /* 3150 */ "z18_hi\0"
+  /* 3157 */ "z28_hi\0"
+  /* 3164 */ "z8_hi\0"
+  /* 3170 */ "z19_hi\0"
+  /* 3177 */ "z29_hi\0"
+  /* 3184 */ "z9_hi\0"
+  /* 3190 */ "wsp\0"
+  /* 3194 */ "za10.q\0"
+  /* 3201 */ "za0.q\0"
+  /* 3207 */ "za11.q\0"
+  /* 3214 */ "za1.q\0"
+  /* 3220 */ "za12.q\0"
+  /* 3227 */ "za2.q\0"
+  /* 3233 */ "za13.q\0"
+  /* 3240 */ "za3.q\0"
+  /* 3246 */ "za14.q\0"
+  /* 3253 */ "za4.q\0"
+  /* 3259 */ "za15.q\0"
+  /* 3266 */ "za5.q\0"
+  /* 3272 */ "za6.q\0"
+  /* 3278 */ "za7.q\0"
+  /* 3284 */ "za8.q\0"
+  /* 3290 */ "za9.q\0"
+  /* 3296 */ "ffr\0"
+  /* 3300 */ "wzr\0"
+  /* 3304 */ "xzr\0"
+  /* 3308 */ "za0.s\0"
+  /* 3314 */ "za1.s\0"
+  /* 3320 */ "za2.s\0"
+  /* 3326 */ "za3.s\0"
+  /* 3332 */ "nzcv\0"
+};
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+  static const uint16_t RegAsmOffsetNoRegAltName[] = {
+    3296, 2757, 227, 3332, 3191, 2961, 3190, 3300, 3304, 2904, 280, 665, 892, 1207,
+    1434, 1751, 1974, 2307, 2530, 2831, 39, 383, 737, 1003, 1282, 1547, 1826, 2089,
+    2382, 2645, 123, 507, 821, 1127, 1366, 1671, 1906, 2209, 2462, 2733, 203, 587,
+    283, 668, 895, 1210, 1437, 1754, 1977, 2310, 2533, 2834, 43, 387, 741, 1007,
+    1286, 1551, 1830, 2093, 2386, 2649, 127, 511, 825, 1131, 1370, 1675, 1910, 2213,
+    2466, 2737, 207, 591, 286, 671, 898, 1213, 1440, 1757, 1980, 2313, 2536, 2837,
+    47, 391, 745, 1011, 1290, 1555, 1834, 2097, 2390, 2653, 131, 515, 829, 1135,
+    1374, 1679, 1914, 2217, 2470, 2741, 211, 595, 289, 674, 901, 1216, 1443, 1760,
+    1983, 2316, 2539, 2840, 51, 395, 749, 1015, 1294, 1559, 292, 677, 904, 1219,
+    1446, 1763, 1986, 2319, 2542, 2843, 55, 399, 753, 1019, 1298, 1563, 1838, 2101,
+    2394, 2657, 135, 519, 833, 1139, 1378, 1683, 1918, 2221, 2474, 2745, 215, 599,
+    295, 680, 907, 1222, 1449, 1766, 1989, 2322, 2545, 2846, 59, 403, 757, 1023,
+    1302, 1567, 1842, 2105, 2398, 2661, 139, 523, 837, 1143, 1382, 1687, 1922, 2225,
+    2478, 2749, 219, 603, 298, 683, 910, 1225, 1452, 1769, 1992, 2325, 2548, 2849,
+    63, 407, 761, 1027, 1306, 1571, 1846, 2109, 2402, 2665, 143, 527, 841, 1147,
+    1386, 1691, 1926, 2229, 2482, 2753, 223, 301, 686, 913, 1228, 1455, 1772, 1995,
+    2328, 2551, 2852, 67, 411, 765, 1031, 1310, 1575, 1850, 2113, 2406, 2669, 147,
+    531, 845, 1151, 1390, 1695, 1930, 2233, 2486, 304, 689, 916, 1231, 1458, 1775,
+    1998, 2331, 2554, 2855, 71, 415, 769, 1035, 1314, 1579, 1854, 2117, 2410, 2673,
+    151, 535, 849, 1155, 1394, 1699, 1934, 2237, 2490, 2761, 231, 607, 2907, 2913,
+    2919, 2925, 2931, 2937, 2943, 2949, 2955, 2964, 2970, 3201, 3214, 3227, 3240, 3253,
+    3266, 3272, 3278, 3284, 3290, 3194, 3207, 3220, 3233, 3246, 3259, 3308, 3314, 3320,
+    3326, 2997, 3024, 3044, 3064, 3084, 3104, 3124, 3144, 3164, 3184, 2976, 3003, 3030,
+    3050, 3070, 3090, 3110, 3130, 3150, 3170, 2983, 3010, 3037, 3057, 3077, 3097, 3117,
+    3137, 3157, 3177, 2990, 3017, 619, 860, 1165, 1404, 1709, 1944, 2247, 2500, 2771,
+    6, 313, 699, 927, 1242, 1469, 1786, 2009, 2342, 2565, 83, 427, 781, 1047,
+    1326, 1591, 1866, 2129, 2422, 2685, 163, 547, 243, 1159, 1398, 1703, 1938, 2241,
+    2494, 2765, 0, 307, 692, 919, 1234, 1461, 1778, 2001, 2334, 2557, 75, 419,
+    773, 1039, 1318, 1583, 1858, 2121, 2414, 2677, 155, 539, 235, 611, 853, 857,
+    1162, 1401, 1706, 1941, 2244, 2497, 2768, 3, 310, 695, 923, 1238, 1465, 1782,
+    2005, 2338, 2561, 79, 423, 777, 1043, 1322, 1587, 1862, 2125, 2418, 2681, 159,
+    543, 239, 615, 633, 873, 1177, 1416, 1721, 1956, 2259, 2512, 2783, 19, 327,
+    714, 943, 1258, 1485, 1802, 2025, 2358, 2581, 99, 443, 797, 1063, 1342, 1607,
+    1882, 2145, 2438, 2701, 179, 563, 258, 1171, 1410, 1715, 1950, 2253, 2506, 2777,
+    13, 321, 707, 935, 1250, 1477, 1794, 2017, 2350, 2573, 91, 435, 789, 1055,
+    1334, 1599, 1874, 2137, 2430, 2693, 171, 555, 250, 625, 866, 870, 1174, 1413,
+    1718, 1953, 2256, 2509, 2780, 16, 324, 710, 939, 1254, 1481, 1798, 2021, 2354,
+    2577, 95, 439, 793, 1059, 1338, 1603, 1878, 2141, 2434, 2697, 175, 559, 254,
+    629, 2858, 2271, 2795, 343, 959, 1501, 2041, 2597, 459, 1079, 1623, 2161, 2889,
+    639, 1183, 1727, 2265, 2789, 335, 951, 1493, 2033, 2589, 451, 1071, 1615, 2153,
+    2709, 2897, 2882, 645, 1189, 1733, 2289, 2813, 361, 979, 1523, 2065, 2621, 483,
+    1103, 1647, 2185, 659, 886, 1201, 1428, 1745, 1968, 2301, 2524, 2825, 32, 375,
+    729, 995, 1274, 1539, 1818, 2081, 2374, 2637, 115, 499, 813, 1119, 1358, 1663,
+    1898, 2201, 2454, 2725, 195, 579, 273, 1195, 1422, 1739, 1962, 2295, 2518, 2819,
+    26, 369, 722, 987, 1266, 1531, 1810, 2073, 2366, 2629, 107, 491, 805, 1111,
+    1350, 1655, 1890, 2193, 2446, 2717, 187, 571, 265, 651, 879, 883, 1198, 1425,
+    1742, 1965, 2298, 2521, 2822, 29, 372, 725, 991, 1270, 1535, 1814, 2077, 2370,
+    2633, 111, 495, 809, 1115, 1354, 1659, 1894, 2197, 2450, 2721, 191, 575, 269,
+    655,
+  };
+
+
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Woverlength-strings"
+#endif
+  static const char AsmStrsvlist1[] = {
+  /* 0 */ "\0"
+};
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+  static const uint8_t RegAsmOffsetvlist1[] = {
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0,
+  };
+
+
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Woverlength-strings"
+#endif
+  static const char AsmStrsvreg[] = {
+  /* 0 */ "v10\0"
+  /* 4 */ "v20\0"
+  /* 8 */ "v30\0"
+  /* 12 */ "v0\0"
+  /* 15 */ "v11\0"
+  /* 19 */ "v21\0"
+  /* 23 */ "v31\0"
+  /* 27 */ "v1\0"
+  /* 30 */ "v12\0"
+  /* 34 */ "v22\0"
+  /* 38 */ "v2\0"
+  /* 41 */ "v13\0"
+  /* 45 */ "v23\0"
+  /* 49 */ "v3\0"
+  /* 52 */ "v14\0"
+  /* 56 */ "v24\0"
+  /* 60 */ "v4\0"
+  /* 63 */ "v15\0"
+  /* 67 */ "v25\0"
+  /* 71 */ "v5\0"
+  /* 74 */ "v16\0"
+  /* 78 */ "v26\0"
+  /* 82 */ "v6\0"
+  /* 85 */ "v17\0"
+  /* 89 */ "v27\0"
+  /* 93 */ "v7\0"
+  /* 96 */ "v18\0"
+  /* 100 */ "v28\0"
+  /* 104 */ "v8\0"
+  /* 107 */ "v19\0"
+  /* 111 */ "v29\0"
+  /* 115 */ "v9\0"
+};
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+  static const uint8_t RegAsmOffsetvreg[] = {
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+    12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41,
+    52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89,
+    100, 111, 8, 23, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 12, 27, 38, 49,
+    60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85,
+    96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23,
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+    3, 3, 3, 3, 3, 12, 27, 38, 49, 60, 71, 82, 93, 104,
+    115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34,
+    45, 56, 67, 78, 89, 100, 111, 8, 23, 12, 27, 38, 49, 60,
+    71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96,
+    107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 12,
+    27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52,
+    63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100,
+    111, 8, 23, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0,
+    15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56,
+    67, 78, 89, 100, 111, 8, 23, 12, 27, 38, 49, 60, 71, 82,
+    93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4,
+    19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 12, 27, 38,
+    49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74,
+    85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8,
+    23, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+    3,
+  };
+
+  switch(AltIdx) {
+  default:
+    return (const char *)(sizeof(RegAsmOffsetvreg)/sizeof(RegAsmOffsetvreg[0]));
+  case AArch64_NoRegAltName:
+    return AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1];
+  case AArch64_vlist1:
+    return AsmStrsvlist1+RegAsmOffsetvlist1[RegNo-1];
+  case AArch64_vreg:
+    return AsmStrsvreg+RegAsmOffsetvreg[RegNo-1];
+  }
+#else
+  return NULL;
+#endif
+}

thirdparty/capstone/arch/AArch64/AArch64GenSubtargetInfo.inc

@@ -0,0 +1,298 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+#ifdef GET_SUBTARGETINFO_ENUM
+#undef GET_SUBTARGETINFO_ENUM
+
+enum {
+  AArch64_FeatureAES = 0,
+  AArch64_FeatureALULSLFast = 1,
+  AArch64_FeatureAM = 2,
+  AArch64_FeatureAMVS = 3,
+  AArch64_FeatureAddrLSLFast = 4,
+  AArch64_FeatureAggressiveFMA = 5,
+  AArch64_FeatureAll = 6,
+  AArch64_FeatureAltFPCmp = 7,
+  AArch64_FeatureAlternateSExtLoadCVTF32Pattern = 8,
+  AArch64_FeatureAppleA7SysReg = 9,
+  AArch64_FeatureArithmeticBccFusion = 10,
+  AArch64_FeatureArithmeticCbzFusion = 11,
+  AArch64_FeatureAscendStoreAddress = 12,
+  AArch64_FeatureB16B16 = 13,
+  AArch64_FeatureBF16 = 14,
+  AArch64_FeatureBRBE = 15,
+  AArch64_FeatureBalanceFPOps = 16,
+  AArch64_FeatureBranchTargetId = 17,
+  AArch64_FeatureCCIDX = 18,
+  AArch64_FeatureCCPP = 19,
+  AArch64_FeatureCHK = 20,
+  AArch64_FeatureCLRBHB = 21,
+  AArch64_FeatureCONTEXTIDREL2 = 22,
+  AArch64_FeatureCPA = 23,
+  AArch64_FeatureCRC = 24,
+  AArch64_FeatureCSSC = 25,
+  AArch64_FeatureCacheDeepPersist = 26,
+  AArch64_FeatureCallSavedX8 = 27,
+  AArch64_FeatureCallSavedX9 = 28,
+  AArch64_FeatureCallSavedX10 = 29,
+  AArch64_FeatureCallSavedX11 = 30,
+  AArch64_FeatureCallSavedX12 = 31,
+  AArch64_FeatureCallSavedX13 = 32,
+  AArch64_FeatureCallSavedX14 = 33,
+  AArch64_FeatureCallSavedX15 = 34,
+  AArch64_FeatureCallSavedX18 = 35,
+  AArch64_FeatureCmpBccFusion = 36,
+  AArch64_FeatureComplxNum = 37,
+  AArch64_FeatureCrypto = 38,
+  AArch64_FeatureD128 = 39,
+  AArch64_FeatureDIT = 40,
+  AArch64_FeatureDisableLatencySchedHeuristic = 41,
+  AArch64_FeatureDisableLdp = 42,
+  AArch64_FeatureDisableStp = 43,
+  AArch64_FeatureDotProd = 44,
+  AArch64_FeatureEL2VMSA = 45,
+  AArch64_FeatureEL3 = 46,
+  AArch64_FeatureETE = 47,
+  AArch64_FeatureEnableSelectOptimize = 48,
+  AArch64_FeatureEnhancedCounterVirtualization = 49,
+  AArch64_FeatureExperimentalZeroingPseudos = 50,
+  AArch64_FeatureExynosCheapAsMoveHandling = 51,
+  AArch64_FeatureFAMINMAX = 52,
+  AArch64_FeatureFMV = 53,
+  AArch64_FeatureFP8 = 54,
+  AArch64_FeatureFP8DOT2 = 55,
+  AArch64_FeatureFP8DOT4 = 56,
+  AArch64_FeatureFP8FMA = 57,
+  AArch64_FeatureFP16FML = 58,
+  AArch64_FeatureFPARMv8 = 59,
+  AArch64_FeatureFPMR = 60,
+  AArch64_FeatureFRInt3264 = 61,
+  AArch64_FeatureFineGrainedTraps = 62,
+  AArch64_FeatureFixCortexA53_835769 = 63,
+  AArch64_FeatureFlagM = 64,
+  AArch64_FeatureForce32BitJumpTables = 65,
+  AArch64_FeatureFullFP16 = 66,
+  AArch64_FeatureFuseAES = 67,
+  AArch64_FeatureFuseAddSub2RegAndConstOne = 68,
+  AArch64_FeatureFuseAddress = 69,
+  AArch64_FeatureFuseAdrpAdd = 70,
+  AArch64_FeatureFuseArithmeticLogic = 71,
+  AArch64_FeatureFuseCCSelect = 72,
+  AArch64_FeatureFuseCryptoEOR = 73,
+  AArch64_FeatureFuseLiterals = 74,
+  AArch64_FeatureGCS = 75,
+  AArch64_FeatureHBC = 76,
+  AArch64_FeatureHCX = 77,
+  AArch64_FeatureHardenSlsBlr = 78,
+  AArch64_FeatureHardenSlsNoComdat = 79,
+  AArch64_FeatureHardenSlsRetBr = 80,
+  AArch64_FeatureITE = 81,
+  AArch64_FeatureJS = 82,
+  AArch64_FeatureLOR = 83,
+  AArch64_FeatureLS64 = 84,
+  AArch64_FeatureLSE = 85,
+  AArch64_FeatureLSE2 = 86,
+  AArch64_FeatureLSE128 = 87,
+  AArch64_FeatureLUT = 88,
+  AArch64_FeatureLdpAlignedOnly = 89,
+  AArch64_FeatureMEC = 90,
+  AArch64_FeatureMOPS = 91,
+  AArch64_FeatureMPAM = 92,
+  AArch64_FeatureMTE = 93,
+  AArch64_FeatureMatMulFP32 = 94,
+  AArch64_FeatureMatMulFP64 = 95,
+  AArch64_FeatureMatMulInt8 = 96,
+  AArch64_FeatureNEON = 97,
+  AArch64_FeatureNMI = 98,
+  AArch64_FeatureNV = 99,
+  AArch64_FeatureNoBTIAtReturnTwice = 100,
+  AArch64_FeatureNoNegativeImmediates = 101,
+  AArch64_FeatureNoSVEFPLD1R = 102,
+  AArch64_FeatureNoZCZeroingFP = 103,
+  AArch64_FeatureOutlineAtomics = 104,
+  AArch64_FeaturePAN = 105,
+  AArch64_FeaturePAN_RWV = 106,
+  AArch64_FeaturePAuth = 107,
+  AArch64_FeaturePAuthLR = 108,
+  AArch64_FeaturePRFM_SLC = 109,
+  AArch64_FeaturePerfMon = 110,
+  AArch64_FeaturePostRAScheduler = 111,
+  AArch64_FeaturePredRes = 112,
+  AArch64_FeaturePredictableSelectIsExpensive = 113,
+  AArch64_FeaturePsUAO = 114,
+  AArch64_FeatureRAS = 115,
+  AArch64_FeatureRASv2 = 116,
+  AArch64_FeatureRCPC = 117,
+  AArch64_FeatureRCPC3 = 118,
+  AArch64_FeatureRCPC_IMMO = 119,
+  AArch64_FeatureRDM = 120,
+  AArch64_FeatureRME = 121,
+  AArch64_FeatureRandGen = 122,
+  AArch64_FeatureReserveX1 = 123,
+  AArch64_FeatureReserveX2 = 124,
+  AArch64_FeatureReserveX3 = 125,
+  AArch64_FeatureReserveX4 = 126,
+  AArch64_FeatureReserveX5 = 127,
+  AArch64_FeatureReserveX6 = 128,
+  AArch64_FeatureReserveX7 = 129,
+  AArch64_FeatureReserveX9 = 130,
+  AArch64_FeatureReserveX10 = 131,
+  AArch64_FeatureReserveX11 = 132,
+  AArch64_FeatureReserveX12 = 133,
+  AArch64_FeatureReserveX13 = 134,
+  AArch64_FeatureReserveX14 = 135,
+  AArch64_FeatureReserveX15 = 136,
+  AArch64_FeatureReserveX18 = 137,
+  AArch64_FeatureReserveX20 = 138,
+  AArch64_FeatureReserveX21 = 139,
+  AArch64_FeatureReserveX22 = 140,
+  AArch64_FeatureReserveX23 = 141,
+  AArch64_FeatureReserveX24 = 142,
+  AArch64_FeatureReserveX25 = 143,
+  AArch64_FeatureReserveX26 = 144,
+  AArch64_FeatureReserveX27 = 145,
+  AArch64_FeatureReserveX28 = 146,
+  AArch64_FeatureReserveX30 = 147,
+  AArch64_FeatureSB = 148,
+  AArch64_FeatureSEL2 = 149,
+  AArch64_FeatureSHA2 = 150,
+  AArch64_FeatureSHA3 = 151,
+  AArch64_FeatureSM4 = 152,
+  AArch64_FeatureSME = 153,
+  AArch64_FeatureSME2 = 154,
+  AArch64_FeatureSME2p1 = 155,
+  AArch64_FeatureSMEF8F16 = 156,
+  AArch64_FeatureSMEF8F32 = 157,
+  AArch64_FeatureSMEF16F16 = 158,
+  AArch64_FeatureSMEF64F64 = 159,
+  AArch64_FeatureSMEFA64 = 160,
+  AArch64_FeatureSMEI16I64 = 161,
+  AArch64_FeatureSME_LUTv2 = 162,
+  AArch64_FeatureSPE = 163,
+  AArch64_FeatureSPECRES2 = 164,
+  AArch64_FeatureSPE_EEF = 165,
+  AArch64_FeatureSSBS = 166,
+  AArch64_FeatureSSVE_FP8DOT2 = 167,
+  AArch64_FeatureSSVE_FP8DOT4 = 168,
+  AArch64_FeatureSSVE_FP8FMA = 169,
+  AArch64_FeatureSVE = 170,
+  AArch64_FeatureSVE2 = 171,
+  AArch64_FeatureSVE2AES = 172,
+  AArch64_FeatureSVE2BitPerm = 173,
+  AArch64_FeatureSVE2SHA3 = 174,
+  AArch64_FeatureSVE2SM4 = 175,
+  AArch64_FeatureSVE2p1 = 176,
+  AArch64_FeatureSlowMisaligned128Store = 177,
+  AArch64_FeatureSlowPaired128 = 178,
+  AArch64_FeatureSlowSTRQro = 179,
+  AArch64_FeatureSpecRestrict = 180,
+  AArch64_FeatureStorePairSuppress = 181,
+  AArch64_FeatureStpAlignedOnly = 182,
+  AArch64_FeatureStrictAlign = 183,
+  AArch64_FeatureTHE = 184,
+  AArch64_FeatureTLBIW = 185,
+  AArch64_FeatureTLB_RMI = 186,
+  AArch64_FeatureTME = 187,
+  AArch64_FeatureTRACEV8_4 = 188,
+  AArch64_FeatureTRBE = 189,
+  AArch64_FeatureTaggedGlobals = 190,
+  AArch64_FeatureUseEL1ForTP = 191,
+  AArch64_FeatureUseEL2ForTP = 192,
+  AArch64_FeatureUseEL3ForTP = 193,
+  AArch64_FeatureUseROEL0ForTP = 194,
+  AArch64_FeatureUseRSqrt = 195,
+  AArch64_FeatureUseScalarIncVL = 196,
+  AArch64_FeatureVH = 197,
+  AArch64_FeatureWFxT = 198,
+  AArch64_FeatureXS = 199,
+  AArch64_FeatureZCRegMove = 200,
+  AArch64_FeatureZCZeroing = 201,
+  AArch64_FeatureZCZeroingFPWorkaround = 202,
+  AArch64_FeatureZCZeroingGP = 203,
+  AArch64_HasV8_0aOps = 204,
+  AArch64_HasV8_0rOps = 205,
+  AArch64_HasV8_1aOps = 206,
+  AArch64_HasV8_2aOps = 207,
+  AArch64_HasV8_3aOps = 208,
+  AArch64_HasV8_4aOps = 209,
+  AArch64_HasV8_5aOps = 210,
+  AArch64_HasV8_6aOps = 211,
+  AArch64_HasV8_7aOps = 212,
+  AArch64_HasV8_8aOps = 213,
+  AArch64_HasV8_9aOps = 214,
+  AArch64_HasV9_0aOps = 215,
+  AArch64_HasV9_1aOps = 216,
+  AArch64_HasV9_2aOps = 217,
+  AArch64_HasV9_3aOps = 218,
+  AArch64_HasV9_4aOps = 219,
+  AArch64_HasV9_5aOps = 220,
+  AArch64_TuneA35 = 221,
+  AArch64_TuneA53 = 222,
+  AArch64_TuneA55 = 223,
+  AArch64_TuneA57 = 224,
+  AArch64_TuneA64FX = 225,
+  AArch64_TuneA65 = 226,
+  AArch64_TuneA72 = 227,
+  AArch64_TuneA73 = 228,
+  AArch64_TuneA75 = 229,
+  AArch64_TuneA76 = 230,
+  AArch64_TuneA77 = 231,
+  AArch64_TuneA78 = 232,
+  AArch64_TuneA78C = 233,
+  AArch64_TuneA510 = 234,
+  AArch64_TuneA520 = 235,
+  AArch64_TuneA710 = 236,
+  AArch64_TuneA715 = 237,
+  AArch64_TuneA720 = 238,
+  AArch64_TuneAmpere1 = 239,
+  AArch64_TuneAmpere1A = 240,
+  AArch64_TuneAmpere1B = 241,
+  AArch64_TuneAppleA7 = 242,
+  AArch64_TuneAppleA10 = 243,
+  AArch64_TuneAppleA11 = 244,
+  AArch64_TuneAppleA12 = 245,
+  AArch64_TuneAppleA13 = 246,
+  AArch64_TuneAppleA14 = 247,
+  AArch64_TuneAppleA15 = 248,
+  AArch64_TuneAppleA16 = 249,
+  AArch64_TuneAppleA17 = 250,
+  AArch64_TuneCarmel = 251,
+  AArch64_TuneExynosM3 = 252,
+  AArch64_TuneExynosM4 = 253,
+  AArch64_TuneFalkor = 254,
+  AArch64_TuneKryo = 255,
+  AArch64_TuneNeoverse512TVB = 256,
+  AArch64_TuneNeoverseE1 = 257,
+  AArch64_TuneNeoverseN1 = 258,
+  AArch64_TuneNeoverseN2 = 259,
+  AArch64_TuneNeoverseV1 = 260,
+  AArch64_TuneNeoverseV2 = 261,
+  AArch64_TuneR82 = 262,
+  AArch64_TuneSaphira = 263,
+  AArch64_TuneTSV110 = 264,
+  AArch64_TuneThunderX = 265,
+  AArch64_TuneThunderX2T99 = 266,
+  AArch64_TuneThunderX3T110 = 267,
+  AArch64_TuneThunderXT81 = 268,
+  AArch64_TuneThunderXT83 = 269,
+  AArch64_TuneThunderXT88 = 270,
+  AArch64_TuneX1 = 271,
+  AArch64_TuneX2 = 272,
+  AArch64_TuneX3 = 273,
+  AArch64_TuneX4 = 274,
+  AArch64_NumSubtargetFeatures = 275
+};
+#endif // GET_SUBTARGETINFO_ENUM
+
+
+

thirdparty/capstone/arch/AArch64/AArch64InstPrinter.h

@@ -0,0 +1,350 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically translated source file from LLVM. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Only small edits allowed. */
+/* For multiple similar edits, please create a Patch for the translator. */
+
+/* Capstone's C++ file translator: */
+/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
+
+//===-- AArch64InstPrinter.h - Convert AArch64 MCInst to assembly syntax --===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This class prints an AArch64 MCInst to a .s file.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64INSTPRINTER_H
+#define LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64INSTPRINTER_H
+
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+#include <capstone/platform.h>
+
+#include "AArch64Mapping.h"
+
+#include "../../MCInst.h"
+#include "../../MCRegisterInfo.h"
+#include "../../MCInstPrinter.h"
+#include "../../SStream.h"
+#include "../../utils.h"
+
+#define CONCAT(a, b) CONCAT_(a, b)
+#define CONCAT_(a, b) a##_##b
+#define CHAR(c) #c[0]
+
+void printInst(MCInst *MI, uint64_t Address, const char *Annot, SStream *O);
+void printRegName(SStream *OS, unsigned Reg);
+void printRegNameAlt(SStream *OS, unsigned Reg, unsigned AltIdx);
+// Autogenerated by tblgen.
+const char *getRegName(unsigned Reg);
+bool printSysAlias(MCInst *MI, SStream *O);
+bool printSyspAlias(MCInst *MI, SStream *O);
+bool printRangePrefetchAlias(MCInst *MI, SStream *O, const char *Annot);
+// Operand printers
+void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
+void printImm(MCInst *MI, unsigned OpNo, SStream *O);
+void printImmHex(MCInst *MI, unsigned OpNo, SStream *O);
+#define DECLARE_printSImm(Size) \
+	void CONCAT(printSImm, Size)(MCInst * MI, unsigned OpNo, SStream *O);
+DECLARE_printSImm(16);
+DECLARE_printSImm(8);
+
+#define DECLARE_printImmSVE(T) void CONCAT(printImmSVE, T)(T Val, SStream * O);
+DECLARE_printImmSVE(int16_t);
+DECLARE_printImmSVE(int8_t);
+DECLARE_printImmSVE(int64_t);
+DECLARE_printImmSVE(int32_t);
+DECLARE_printImmSVE(uint16_t);
+DECLARE_printImmSVE(uint8_t);
+DECLARE_printImmSVE(uint64_t);
+DECLARE_printImmSVE(uint32_t);
+
+void printPostIncOperand(MCInst *MI, unsigned OpNo, unsigned Imm, SStream *O);
+#define DEFINE_printPostIncOperand(Amount) \
+	static inline void CONCAT(printPostIncOperand, Amount)( \
+		MCInst * MI, unsigned OpNo, SStream *O) \
+	{ \
+		add_cs_detail(MI, \
+			      CONCAT(AArch64_OP_GROUP_PostIncOperand, Amount), \
+			      OpNo, Amount); \
+		printPostIncOperand(MI, OpNo, Amount, O); \
+	}
+DEFINE_printPostIncOperand(64);
+DEFINE_printPostIncOperand(32);
+DEFINE_printPostIncOperand(16);
+DEFINE_printPostIncOperand(8);
+DEFINE_printPostIncOperand(1);
+DEFINE_printPostIncOperand(4);
+DEFINE_printPostIncOperand(2);
+DEFINE_printPostIncOperand(48);
+DEFINE_printPostIncOperand(24);
+DEFINE_printPostIncOperand(3);
+DEFINE_printPostIncOperand(12);
+DEFINE_printPostIncOperand(6);
+
+void printVRegOperand(MCInst *MI, unsigned OpNo, SStream *O);
+void printSysCROperand(MCInst *MI, unsigned OpNo, SStream *O);
+void printAddSubImm(MCInst *MI, unsigned OpNum, SStream *O);
+#define DECLARE_printLogicalImm(T) \
+	void CONCAT(printLogicalImm, T)(MCInst * MI, unsigned OpNum, \
+					SStream *O);
+DECLARE_printLogicalImm(int64_t);
+DECLARE_printLogicalImm(int32_t);
+DECLARE_printLogicalImm(int8_t);
+DECLARE_printLogicalImm(int16_t);
+
+void printShifter(MCInst *MI, unsigned OpNum, SStream *O);
+void printShiftedRegister(MCInst *MI, unsigned OpNum, SStream *O);
+void printExtendedRegister(MCInst *MI, unsigned OpNum, SStream *O);
+void printArithExtend(MCInst *MI, unsigned OpNum, SStream *O);
+
+void printMemExtend(MCInst *MI, unsigned OpNum, SStream *O, char SrcRegKind,
+		    unsigned Width);
+void printMemExtend(MCInst *MI, unsigned OpNum, SStream *O, char SrcRegKind,
+		    unsigned Width);
+#define DEFINE_printMemExtend(SrcRegKind, Width) \
+	static inline void CONCAT(printMemExtend, CONCAT(SrcRegKind, Width))( \
+		MCInst * MI, unsigned OpNum, SStream *O) \
+	{ \
+		add_cs_detail( \
+			MI, \
+			CONCAT(CONCAT(AArch64_OP_GROUP_MemExtend, SrcRegKind), \
+			       Width), \
+			OpNum, CHAR(SrcRegKind), Width); \
+		printMemExtend(MI, OpNum, O, CHAR(SrcRegKind), Width); \
+	}
+DEFINE_printMemExtend(w, 8);
+DEFINE_printMemExtend(x, 8);
+DEFINE_printMemExtend(w, 64);
+DEFINE_printMemExtend(x, 64);
+DEFINE_printMemExtend(w, 16);
+DEFINE_printMemExtend(x, 16);
+DEFINE_printMemExtend(w, 128);
+DEFINE_printMemExtend(x, 128);
+DEFINE_printMemExtend(w, 32);
+DEFINE_printMemExtend(x, 32);
+
+#define DECLARE_printRegWithShiftExtend(SignedExtend, ExtWidth, SrcRegKind, \
+					Suffix) \
+	void CONCAT(printRegWithShiftExtend, \
+		    CONCAT(SignedExtend, \
+			   CONCAT(ExtWidth, CONCAT(SrcRegKind, Suffix))))( \
+		MCInst * MI, unsigned OpNum, SStream *O);
+DECLARE_printRegWithShiftExtend(false, 8, x, d);
+DECLARE_printRegWithShiftExtend(true, 8, w, d);
+DECLARE_printRegWithShiftExtend(false, 8, w, d);
+DECLARE_printRegWithShiftExtend(false, 8, x, 0);
+DECLARE_printRegWithShiftExtend(true, 8, w, s);
+DECLARE_printRegWithShiftExtend(false, 8, w, s);
+DECLARE_printRegWithShiftExtend(false, 64, x, d);
+DECLARE_printRegWithShiftExtend(true, 64, w, d);
+DECLARE_printRegWithShiftExtend(false, 64, w, d);
+DECLARE_printRegWithShiftExtend(false, 64, x, 0);
+DECLARE_printRegWithShiftExtend(true, 64, w, s);
+DECLARE_printRegWithShiftExtend(false, 64, w, s);
+DECLARE_printRegWithShiftExtend(false, 16, x, d);
+DECLARE_printRegWithShiftExtend(true, 16, w, d);
+DECLARE_printRegWithShiftExtend(false, 16, w, d);
+DECLARE_printRegWithShiftExtend(false, 16, x, 0);
+DECLARE_printRegWithShiftExtend(true, 16, w, s);
+DECLARE_printRegWithShiftExtend(false, 16, w, s);
+DECLARE_printRegWithShiftExtend(false, 32, x, d);
+DECLARE_printRegWithShiftExtend(true, 32, w, d);
+DECLARE_printRegWithShiftExtend(false, 32, w, d);
+DECLARE_printRegWithShiftExtend(false, 32, x, 0);
+DECLARE_printRegWithShiftExtend(true, 32, w, s);
+DECLARE_printRegWithShiftExtend(false, 32, w, s);
+DECLARE_printRegWithShiftExtend(false, 8, x, s);
+DECLARE_printRegWithShiftExtend(false, 16, x, s);
+DECLARE_printRegWithShiftExtend(false, 32, x, s);
+DECLARE_printRegWithShiftExtend(false, 64, x, s);
+DECLARE_printRegWithShiftExtend(false, 128, x, 0);
+
+void printCondCode(MCInst *MI, unsigned OpNum, SStream *O);
+void printInverseCondCode(MCInst *MI, unsigned OpNum, SStream *O);
+void printAlignedLabel(MCInst *MI, uint64_t Address, unsigned OpNum,
+		       SStream *O);
+void printUImm12Offset(MCInst *MI, unsigned OpNum, unsigned Scale, SStream *O);
+void printAMIndexedWB(MCInst *MI, unsigned OpNum, unsigned Scale, SStream *O);
+#define DEFINE_printUImm12Offset(Scale) \
+	static inline void CONCAT(printUImm12Offset, Scale)( \
+		MCInst * MI, unsigned OpNum, SStream *O) \
+	{ \
+		add_cs_detail(MI, \
+			      CONCAT(AArch64_OP_GROUP_UImm12Offset, Scale), \
+			      OpNum, Scale); \
+		printUImm12Offset(MI, OpNum, Scale, O); \
+	}
+DEFINE_printUImm12Offset(1);
+DEFINE_printUImm12Offset(8);
+DEFINE_printUImm12Offset(2);
+DEFINE_printUImm12Offset(16);
+DEFINE_printUImm12Offset(4);
+
+void printAMNoIndex(MCInst *MI, unsigned OpNum, SStream *O);
+#define DECLARE_printImmScale(Scale) \
+	void CONCAT(printImmScale, Scale)(MCInst * MI, unsigned OpNum, \
+					  SStream *O);
+DECLARE_printImmScale(8);
+DECLARE_printImmScale(2);
+DECLARE_printImmScale(4);
+DECLARE_printImmScale(16);
+DECLARE_printImmScale(32);
+DECLARE_printImmScale(3);
+
+#define DECLARE_printImmRangeScale(Scale, Offset) \
+	void CONCAT(printImmRangeScale, CONCAT(Scale, Offset))( \
+		MCInst * MI, unsigned OpNum, SStream *O);
+DECLARE_printImmRangeScale(2, 1);
+DECLARE_printImmRangeScale(4, 3);
+
+#define DECLARE_printPrefetchOp(IsSVEPrefetch) \
+	void CONCAT(printPrefetchOp, \
+		    IsSVEPrefetch)(MCInst * MI, unsigned OpNum, SStream *O);
+DECLARE_printPrefetchOp(true);
+DECLARE_printPrefetchOp(false);
+
+void printRPRFMOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printPSBHintOp(MCInst *MI, unsigned OpNum, SStream *O);
+void printBTIHintOp(MCInst *MI, unsigned OpNum, SStream *O);
+void printVectorList(MCInst *MI, unsigned OpNum, SStream *O,
+		     const char *LayoutSuffix);
+void printMatrixTileList(MCInst *MI, unsigned OpNum, SStream *O);
+/// (i.e. attached to the instruction rather than the registers).
+/// Print a list of vector registers where the type suffix is implicit
+void printImplicitlyTypedVectorList(MCInst *MI, unsigned OpNum, SStream *O);
+#define DECLARE_printTypedVectorList(NumLanes, LaneKind) \
+	void CONCAT(printTypedVectorList, CONCAT(NumLanes, LaneKind))( \
+		MCInst * MI, unsigned OpNum, SStream *O);
+DECLARE_printTypedVectorList(0, b);
+DECLARE_printTypedVectorList(0, d);
+DECLARE_printTypedVectorList(0, h);
+DECLARE_printTypedVectorList(0, s);
+DECLARE_printTypedVectorList(0, q);
+DECLARE_printTypedVectorList(16, b);
+DECLARE_printTypedVectorList(1, d);
+DECLARE_printTypedVectorList(2, d);
+DECLARE_printTypedVectorList(2, s);
+DECLARE_printTypedVectorList(4, h);
+DECLARE_printTypedVectorList(4, s);
+DECLARE_printTypedVectorList(8, b);
+DECLARE_printTypedVectorList(8, h);
+DECLARE_printTypedVectorList(0, 0);
+
+#define DECLARE_printVectorIndex(Scale) \
+	void CONCAT(printVectorIndex, Scale)(MCInst * MI, unsigned OpNum, \
+					     SStream *O);
+DECLARE_printVectorIndex(1);
+DECLARE_printVectorIndex(8);
+
+void printAdrAdrpLabel(MCInst *MI, uint64_t Address, unsigned OpNum,
+		       SStream *O);
+void printBarrierOption(MCInst *MI, unsigned OpNum, SStream *O);
+void printBarriernXSOption(MCInst *MI, unsigned OpNum, SStream *O);
+void printMSRSystemRegister(MCInst *MI, unsigned OpNum, SStream *O);
+void printMRSSystemRegister(MCInst *MI, unsigned OpNum, SStream *O);
+void printSystemPStateField(MCInst *MI, unsigned OpNum, SStream *O);
+void printSIMDType10Operand(MCInst *MI, unsigned OpNum, SStream *O);
+#define DECLARE_printPredicateAsCounter(EltSize) \
+	void CONCAT(printPredicateAsCounter, \
+		    EltSize)(MCInst * MI, unsigned OpNum, SStream *O);
+DECLARE_printPredicateAsCounter(8);
+DECLARE_printPredicateAsCounter(64);
+DECLARE_printPredicateAsCounter(16);
+DECLARE_printPredicateAsCounter(32);
+DECLARE_printPredicateAsCounter(0);
+
+#define DECLARE_printGPRSeqPairsClassOperand(size) \
+	void CONCAT(printGPRSeqPairsClassOperand, \
+		    size)(MCInst * MI, unsigned OpNum, SStream *O);
+DECLARE_printGPRSeqPairsClassOperand(32);
+DECLARE_printGPRSeqPairsClassOperand(64);
+
+#define DECLARE_printImm8OptLsl(T) \
+	void CONCAT(printImm8OptLsl, T)(MCInst * MI, unsigned OpNum, \
+					SStream *O);
+DECLARE_printImm8OptLsl(int16_t);
+DECLARE_printImm8OptLsl(int8_t);
+DECLARE_printImm8OptLsl(int64_t);
+DECLARE_printImm8OptLsl(int32_t);
+DECLARE_printImm8OptLsl(uint16_t);
+DECLARE_printImm8OptLsl(uint8_t);
+DECLARE_printImm8OptLsl(uint64_t);
+DECLARE_printImm8OptLsl(uint32_t);
+
+#define DECLARE_printSVELogicalImm(T) \
+	void CONCAT(printSVELogicalImm, T)(MCInst * MI, unsigned OpNum, \
+					   SStream *O);
+DECLARE_printSVELogicalImm(int16_t);
+DECLARE_printSVELogicalImm(int32_t);
+DECLARE_printSVELogicalImm(int64_t);
+
+void printSVEPattern(MCInst *MI, unsigned OpNum, SStream *O);
+void printSVEVecLenSpecifier(MCInst *MI, unsigned OpNum, SStream *O);
+#define DECLARE_printMatrixTileVector(IsVertical) \
+	void CONCAT(printMatrixTileVector, \
+		    IsVertical)(MCInst * MI, unsigned OpNum, SStream *O);
+DECLARE_printMatrixTileVector(0);
+DECLARE_printMatrixTileVector(1);
+
+void printMatrixTile(MCInst *MI, unsigned OpNum, SStream *O);
+#define DECLARE_printMatrix(EltSize) \
+	void CONCAT(printMatrix, EltSize)(MCInst * MI, unsigned OpNum, \
+					  SStream *O);
+DECLARE_printMatrix(64);
+DECLARE_printMatrix(32);
+DECLARE_printMatrix(16);
+DECLARE_printMatrix(0);
+
+void printSVCROp(MCInst *MI, unsigned OpNum, SStream *O);
+#define DECLARE_printSVERegOp(char) \
+	void CONCAT(printSVERegOp, char)(MCInst * MI, unsigned OpNum, \
+					 SStream *O);
+DECLARE_printSVERegOp(b);
+DECLARE_printSVERegOp(d);
+DECLARE_printSVERegOp(h);
+DECLARE_printSVERegOp(s);
+DECLARE_printSVERegOp(0);
+DECLARE_printSVERegOp(q);
+
+void printGPR64as32(MCInst *MI, unsigned OpNum, SStream *O);
+void printGPR64x8(MCInst *MI, unsigned OpNum, SStream *O);
+void printSyspXzrPair(MCInst *MI, unsigned OpNum, SStream *O);
+#define DECLARE_printZPRasFPR(Width) \
+	void CONCAT(printZPRasFPR, Width)(MCInst * MI, unsigned OpNum, \
+					  SStream *O);
+DECLARE_printZPRasFPR(8);
+DECLARE_printZPRasFPR(64);
+DECLARE_printZPRasFPR(16);
+DECLARE_printZPRasFPR(32);
+DECLARE_printZPRasFPR(128);
+
+#define DECLARE_printExactFPImm(ImmIs0, ImmIs1) \
+	void CONCAT(printExactFPImm, CONCAT(ImmIs0, ImmIs1))( \
+		MCInst * MI, unsigned OpNum, SStream *O);
+DECLARE_printExactFPImm(AArch64ExactFPImm_half, AArch64ExactFPImm_one);
+DECLARE_printExactFPImm(AArch64ExactFPImm_zero, AArch64ExactFPImm_one);
+DECLARE_printExactFPImm(AArch64ExactFPImm_half, AArch64ExactFPImm_two);
+
+#define DECLARE_printMatrixIndex(Scale) \
+	void CONCAT(printMatrixIndex, Scale)(MCInst * MI, unsigned OpNum, \
+					     SStream *O);
+DECLARE_printMatrixIndex(8);
+DECLARE_printMatrixIndex(0);
+DECLARE_printMatrixIndex(1);
+
+// end namespace llvm
+
+#endif // LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64INSTPRINTER_H

thirdparty/capstone/arch/AArch64/AArch64Linkage.h

@@ -0,0 +1,23 @@
+/* Capstone Disassembly Engine */
+/* By Rot127 <unisono@quyllur.org> 2022-2023 */
+
+#ifndef CS_AARCH64_LINKAGE_H
+#define CS_AARCH64_LINKAGE_H
+
+// Function definitions to call static LLVM functions.
+
+#include "../../MCDisassembler.h"
+#include "../../MCInst.h"
+#include "../../MCRegisterInfo.h"
+#include "../../SStream.h"
+#include "capstone/capstone.h"
+
+DecodeStatus AArch64_LLVM_getInstruction(csh handle, const uint8_t *Bytes,
+					 size_t ByteLen, MCInst *MI,
+					 uint16_t *Size, uint64_t Address,
+					 void *Info);
+const char *AArch64_LLVM_getRegisterName(unsigned RegNo, unsigned AltIdx);
+void AArch64_LLVM_printInstruction(MCInst *MI, SStream *O,
+				   void * /* MCRegisterInfo* */ info);
+
+#endif // CS_AARCH64_LINKAGE_H

thirdparty/capstone/arch/AArch64/AArch64Mapping.h

@@ -0,0 +1,82 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+
+#ifndef CS_AARCH64_MAP_H
+#define CS_AARCH64_MAP_H
+
+#include "capstone/capstone.h"
+#include "../../MCInst.h"
+#include "../../SStream.h"
+
+typedef enum {
+#include "AArch64GenCSOpGroup.inc"
+} aarch64_op_group;
+
+// return name of register in friendly string
+const char *AArch64_reg_name(csh handle, unsigned int reg);
+
+// given internal insn id, return public instruction info
+void AArch64_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
+
+const char *AArch64_insn_name(csh handle, unsigned int id);
+
+const char *AArch64_group_name(csh handle, unsigned int id);
+
+void AArch64_reg_access(const cs_insn *insn, cs_regs regs_read,
+			uint8_t *regs_read_count, cs_regs regs_write,
+			uint8_t *regs_write_count);
+
+void AArch64_add_cs_detail(MCInst *MI, int /* aarch64_op_group */ op_group,
+			   va_list args);
+
+static inline void add_cs_detail(MCInst *MI,
+				 int /* aarch64_op_group */ op_group, ...)
+{
+	if (!MI->flat_insn->detail)
+		return;
+	va_list args;
+	va_start(args, op_group);
+	AArch64_add_cs_detail(MI, op_group, args);
+	va_end(args);
+}
+
+void AArch64_init_mri(MCRegisterInfo *MRI);
+
+void AArch64_init_cs_detail(MCInst *MI);
+
+void AArch64_set_instr_map_data(MCInst *MI);
+
+bool AArch64_getInstruction(csh handle, const uint8_t *code, size_t code_len,
+			    MCInst *instr, uint16_t *size, uint64_t address,
+			    void *info);
+
+void AArch64_printer(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info);
+
+void AArch64_set_detail_op_reg(MCInst *MI, unsigned OpNum, aarch64_reg Reg);
+void AArch64_set_detail_op_imm(MCInst *MI, unsigned OpNum,
+			       aarch64_op_type ImmType, int64_t Imm);
+void AArch64_set_detail_op_imm_range(MCInst *MI, unsigned OpNum,
+				     uint32_t FirstImm, uint32_t offset);
+void AArch64_set_detail_op_mem(MCInst *MI, unsigned OpNum, uint64_t Val);
+void AArch64_set_detail_op_mem_offset(MCInst *MI, unsigned OpNum, uint64_t Val);
+void AArch64_set_detail_shift_ext(MCInst *MI, unsigned OpNum, bool SignExtend,
+				  bool DoShift, unsigned ExtWidth,
+				  char SrcRegKind);
+void AArch64_set_detail_op_float(MCInst *MI, unsigned OpNum, float Val);
+void AArch64_set_detail_op_sys(MCInst *MI, unsigned OpNum, aarch64_sysop sys_op,
+			       aarch64_op_type type);
+void AArch64_set_detail_op_sme(MCInst *MI, unsigned OpNum,
+			       aarch64_sme_op_part part,
+			       AArch64Layout_VectorLayout vas, ...);
+void AArch64_set_detail_op_pred(MCInst *MI, unsigned OpNum);
+void AArch64_insert_detail_op_reg_at(MCInst *MI, unsigned index,
+				     aarch64_reg Reg, cs_ac_type access);
+void AArch64_insert_detail_op_float_at(MCInst *MI, unsigned index, double val,
+				       cs_ac_type access);
+void AArch64_insert_detail_op_imm_at(MCInst *MI, unsigned index, int64_t Imm);
+void AArch64_insert_detail_op_sys(MCInst *MI, unsigned index, aarch64_sysop sys_op,
+			       aarch64_op_type type);
+void AArch64_insert_detail_op_sme(MCInst *MI, unsigned index, aarch64_op_sme sme_op);
+void AArch64_add_vas(MCInst *MI, const SStream *OS);
+
+#endif

thirdparty/capstone/arch/AArch64/AArch64Module.c

@@ -0,0 +1,46 @@
+/* Capstone Disassembly Engine */
+/* By Dang Hoang Vu <danghvu@gmail.com> 2013 */
+
+#ifdef CAPSTONE_HAS_AARCH64
+
+#include "../../utils.h"
+#include "../../MCRegisterInfo.h"
+#include "AArch64InstPrinter.h"
+#include "AArch64Mapping.h"
+#include "AArch64Module.h"
+
+cs_err AArch64_global_init(cs_struct *ud)
+{
+	MCRegisterInfo *mri;
+	mri = cs_mem_malloc(sizeof(*mri));
+
+	AArch64_init_mri(mri);
+	ud->printer = AArch64_printer;
+	ud->printer_info = mri;
+	ud->getinsn_info = mri;
+	ud->disasm = AArch64_getInstruction;
+	ud->reg_name = AArch64_reg_name;
+	ud->insn_id = AArch64_get_insn_id;
+	ud->insn_name = AArch64_insn_name;
+	ud->group_name = AArch64_group_name;
+	ud->post_printer = NULL;
+#ifndef CAPSTONE_DIET
+	ud->reg_access = AArch64_reg_access;
+#endif
+
+	return CS_ERR_OK;
+}
+
+cs_err AArch64_option(cs_struct *handle, cs_opt_type type, size_t value)
+{
+	if (type == CS_OPT_SYNTAX)
+		handle->syntax |= (int)value;
+
+	if (type == CS_OPT_MODE) {
+		handle->mode |= (cs_mode)value;
+	}
+
+	return CS_ERR_OK;
+}
+
+#endif

thirdparty/capstone/arch/AArch64/AArch64Module.h

@@ -0,0 +1,12 @@
+/* Capstone Disassembly Engine */
+/* By Travis Finkenauer <tmfinken@gmail.com>, 2018 */
+
+#ifndef CS_AARCH64_MODULE_H
+#define CS_AARCH64_MODULE_H
+
+#include "../../utils.h"
+
+cs_err AArch64_global_init(cs_struct *ud);
+cs_err AArch64_option(cs_struct *handle, cs_opt_type type, size_t value);
+
+#endif

thirdparty/capstone/arch/Alpha/AlphaDisassembler.c

@@ -0,0 +1,113 @@
+/* Capstone Disassembly Engine */
+/* By Dmitry Sibirtsev  <sibirtsevdl@gmail.com>, 2023 */
+
+#ifdef CAPSTONE_HAS_ALPHA
+
+#include <stdio.h> // DEBUG
+#include <stdlib.h>
+#include <string.h>
+
+#include "../../utils.h"
+
+#include "../../MCFixedLenDisassembler.h"
+#include "../../Mapping.h"
+
+#include "AlphaDisassembler.h"
+#include "AlphaLinkage.h"
+
+static DecodeStatus DecodeGPRCRegisterClass(MCInst *Inst, unsigned RegNo,
+											uint64_t Address,
+											const void *Decoder);
+
+static DecodeStatus DecodeF4RCRegisterClass(MCInst *Inst, unsigned RegNo,
+											uint64_t Address,
+											const void *Decoder);
+
+static DecodeStatus DecodeF8RCRegisterClass(MCInst *Inst, unsigned RegNo,
+											uint64_t Address,
+											const void *Decoder);
+
+#include "AlphaGenDisassemblerTables.inc"
+
+#define GET_REGINFO_ENUM
+#define GET_REGINFO_MC_DESC
+
+#include "AlphaGenRegisterInfo.inc"
+
+static DecodeStatus DecodeGPRCRegisterClass(MCInst *Inst, unsigned RegNo,
+											uint64_t Address,
+											const void *Decoder)
+{
+	if (RegNo > 31)
+		return MCDisassembler_Fail;
+
+	unsigned Register = GPRC[RegNo];
+	MCOperand_CreateReg0(Inst, (Register));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeF4RCRegisterClass(MCInst *Inst, unsigned RegNo,
+											uint64_t Address,
+											const void *Decoder)
+{
+	if (RegNo > 31)
+		return MCDisassembler_Fail;
+
+	unsigned Register = F4RC[RegNo];
+	MCOperand_CreateReg0(Inst, (Register));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeF8RCRegisterClass(MCInst *Inst, unsigned RegNo,
+											uint64_t Address,
+											const void *Decoder)
+{
+	if (RegNo > 31)
+		return MCDisassembler_Fail;
+
+	unsigned Register = F8RC[RegNo];
+	MCOperand_CreateReg0(Inst, (Register));
+	return MCDisassembler_Success;
+}
+
+#define GET_SUBTARGETINFO_ENUM
+
+#include "AlphaGenInstrInfo.inc"
+
+DecodeStatus Alpha_LLVM_getInstruction(csh handle, const uint8_t *Bytes,
+									   size_t ByteLen, MCInst *MI,
+									   uint16_t *Size, uint64_t Address,
+									   void *Info)
+{
+	if (!handle) {
+		return MCDisassembler_Fail;
+	}
+
+	if (ByteLen < 4) {
+		*Size = 0;
+		return MCDisassembler_Fail;
+	}
+
+	uint32_t Insn = readBytes32(MI, Bytes);
+	// Calling the auto-generated decoder function.
+	DecodeStatus Result =
+		decodeInstruction_4(DecoderTable32, MI, Insn, Address, NULL);
+
+	if (Result != MCDisassembler_Fail) {
+		*Size = 4;
+		return Result;
+	}
+
+	*Size = 4;
+	return MCDisassembler_Fail;
+}
+
+void Alpha_init(MCRegisterInfo *MRI)
+{
+	MCRegisterInfo_InitMCRegisterInfo(
+		MRI, AlphaRegDesc, ARR_SIZE(AlphaRegDesc), 0, 0, AlphaMCRegisterClasses,
+		ARR_SIZE(AlphaMCRegisterClasses), 0, 0, AlphaRegDiffLists, 0,
+		AlphaSubRegIdxLists, 1, 0);
+}
+
+#endif

thirdparty/capstone/arch/Alpha/AlphaDisassembler.h

@@ -0,0 +1,18 @@
+/* Capstone Disassembly Engine */
+/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2023 */
+
+#ifndef CS_ALPHADISASSEMBLER_H
+#define CS_ALPHADISASSEMBLER_H
+
+#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
+#include <stdint.h>
+#endif
+
+#include "../../MCDisassembler.h"
+#include "../../MCInst.h"
+#include "../../MCRegisterInfo.h"
+#include <capstone/capstone.h>
+
+void Alpha_init(MCRegisterInfo *MRI);
+
+#endif // CS_ALPHADISASSEMBLER_H

thirdparty/capstone/arch/Alpha/AlphaGenCSMappingInsnName.inc

@@ -0,0 +1,164 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: 083d57d0731afc1746680d828bdfe2fa41f62a61 */
+/* LLVM-tag: llvmorg-3.0.0-2-g083d57d0731a */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+  "invalid", // Alpha_INS_INVALID
+  "addl", // Alpha_INS_ADDL
+  "addq", // Alpha_INS_ADDQ
+  "adds/su", // Alpha_INS_ADDSsSU
+  "addt/su", // Alpha_INS_ADDTsSU
+  "and", // Alpha_INS_AND
+  "beq", // Alpha_INS_BEQ
+  "bge", // Alpha_INS_BGE
+  "bgt", // Alpha_INS_BGT
+  "bic", // Alpha_INS_BIC
+  "bis", // Alpha_INS_BIS
+  "blbc", // Alpha_INS_BLBC
+  "blbs", // Alpha_INS_BLBS
+  "ble", // Alpha_INS_BLE
+  "blt", // Alpha_INS_BLT
+  "bne", // Alpha_INS_BNE
+  "br", // Alpha_INS_BR
+  "bsr", // Alpha_INS_BSR
+  "cmoveq", // Alpha_INS_CMOVEQ
+  "cmovge", // Alpha_INS_CMOVGE
+  "cmovgt", // Alpha_INS_CMOVGT
+  "cmovlbc", // Alpha_INS_CMOVLBC
+  "cmovlbs", // Alpha_INS_CMOVLBS
+  "cmovle", // Alpha_INS_CMOVLE
+  "cmovlt", // Alpha_INS_CMOVLT
+  "cmovne", // Alpha_INS_CMOVNE
+  "cmpbge", // Alpha_INS_CMPBGE
+  "cmpeq", // Alpha_INS_CMPEQ
+  "cmple", // Alpha_INS_CMPLE
+  "cmplt", // Alpha_INS_CMPLT
+  "cmpteq/su", // Alpha_INS_CMPTEQsSU
+  "cmptle/su", // Alpha_INS_CMPTLEsSU
+  "cmptlt/su", // Alpha_INS_CMPTLTsSU
+  "cmptun/su", // Alpha_INS_CMPTUNsSU
+  "cmpule", // Alpha_INS_CMPULE
+  "cmpult", // Alpha_INS_CMPULT
+  "COND_BRANCH", // Alpha_INS_COND_BRANCH
+  "cpyse", // Alpha_INS_CPYSE
+  "cpysn", // Alpha_INS_CPYSN
+  "cpys", // Alpha_INS_CPYS
+  "ctlz", // Alpha_INS_CTLZ
+  "ctpop", // Alpha_INS_CTPOP
+  "cttz", // Alpha_INS_CTTZ
+  "cvtqs/sui", // Alpha_INS_CVTQSsSUI
+  "cvtqt/sui", // Alpha_INS_CVTQTsSUI
+  "cvtst/s", // Alpha_INS_CVTSTsS
+  "cvttq/svc", // Alpha_INS_CVTTQsSVC
+  "cvtts/sui", // Alpha_INS_CVTTSsSUI
+  "divs/su", // Alpha_INS_DIVSsSU
+  "divt/su", // Alpha_INS_DIVTsSU
+  "ecb", // Alpha_INS_ECB
+  "eqv", // Alpha_INS_EQV
+  "excb", // Alpha_INS_EXCB
+  "extbl", // Alpha_INS_EXTBL
+  "extlh", // Alpha_INS_EXTLH
+  "extll", // Alpha_INS_EXTLL
+  "extqh", // Alpha_INS_EXTQH
+  "extql", // Alpha_INS_EXTQL
+  "extwh", // Alpha_INS_EXTWH
+  "extwl", // Alpha_INS_EXTWL
+  "fbeq", // Alpha_INS_FBEQ
+  "fbge", // Alpha_INS_FBGE
+  "fbgt", // Alpha_INS_FBGT
+  "fble", // Alpha_INS_FBLE
+  "fblt", // Alpha_INS_FBLT
+  "fbne", // Alpha_INS_FBNE
+  "fcmoveq", // Alpha_INS_FCMOVEQ
+  "fcmovge", // Alpha_INS_FCMOVGE
+  "fcmovgt", // Alpha_INS_FCMOVGT
+  "fcmovle", // Alpha_INS_FCMOVLE
+  "fcmovlt", // Alpha_INS_FCMOVLT
+  "fcmovne", // Alpha_INS_FCMOVNE
+  "fetch", // Alpha_INS_FETCH
+  "fetch_m", // Alpha_INS_FETCH_M
+  "ftois", // Alpha_INS_FTOIS
+  "ftoit", // Alpha_INS_FTOIT
+  "insbl", // Alpha_INS_INSBL
+  "inslh", // Alpha_INS_INSLH
+  "insll", // Alpha_INS_INSLL
+  "insqh", // Alpha_INS_INSQH
+  "insql", // Alpha_INS_INSQL
+  "inswh", // Alpha_INS_INSWH
+  "inswl", // Alpha_INS_INSWL
+  "itofs", // Alpha_INS_ITOFS
+  "itoft", // Alpha_INS_ITOFT
+  "jmp", // Alpha_INS_JMP
+  "jsr", // Alpha_INS_JSR
+  "jsr_coroutine", // Alpha_INS_JSR_COROUTINE
+  "lda", // Alpha_INS_LDA
+  "ldah", // Alpha_INS_LDAH
+  "ldbu", // Alpha_INS_LDBU
+  "ldl", // Alpha_INS_LDL
+  "ldl_l", // Alpha_INS_LDL_L
+  "ldq", // Alpha_INS_LDQ
+  "ldq_l", // Alpha_INS_LDQ_L
+  "ldq_u", // Alpha_INS_LDQ_U
+  "lds", // Alpha_INS_LDS
+  "ldt", // Alpha_INS_LDT
+  "ldwu", // Alpha_INS_LDWU
+  "mb", // Alpha_INS_MB
+  "mskbl", // Alpha_INS_MSKBL
+  "msklh", // Alpha_INS_MSKLH
+  "mskll", // Alpha_INS_MSKLL
+  "mskqh", // Alpha_INS_MSKQH
+  "mskql", // Alpha_INS_MSKQL
+  "mskwh", // Alpha_INS_MSKWH
+  "mskwl", // Alpha_INS_MSKWL
+  "mull", // Alpha_INS_MULL
+  "mulq", // Alpha_INS_MULQ
+  "muls/su", // Alpha_INS_MULSsSU
+  "mult/su", // Alpha_INS_MULTsSU
+  "ornot", // Alpha_INS_ORNOT
+  "rc", // Alpha_INS_RC
+  "ret", // Alpha_INS_RET
+  "rpcc", // Alpha_INS_RPCC
+  "rs", // Alpha_INS_RS
+  "s4addl", // Alpha_INS_S4ADDL
+  "s4addq", // Alpha_INS_S4ADDQ
+  "s4subl", // Alpha_INS_S4SUBL
+  "s4subq", // Alpha_INS_S4SUBQ
+  "s8addl", // Alpha_INS_S8ADDL
+  "s8addq", // Alpha_INS_S8ADDQ
+  "s8subl", // Alpha_INS_S8SUBL
+  "s8subq", // Alpha_INS_S8SUBQ
+  "sextb", // Alpha_INS_SEXTB
+  "sextw", // Alpha_INS_SEXTW
+  "sll", // Alpha_INS_SLL
+  "sqrts/su", // Alpha_INS_SQRTSsSU
+  "sqrtt/su", // Alpha_INS_SQRTTsSU
+  "sra", // Alpha_INS_SRA
+  "srl", // Alpha_INS_SRL
+  "stb", // Alpha_INS_STB
+  "stl", // Alpha_INS_STL
+  "stl_c", // Alpha_INS_STL_C
+  "stq", // Alpha_INS_STQ
+  "stq_c", // Alpha_INS_STQ_C
+  "stq_u", // Alpha_INS_STQ_U
+  "sts", // Alpha_INS_STS
+  "stt", // Alpha_INS_STT
+  "stw", // Alpha_INS_STW
+  "subl", // Alpha_INS_SUBL
+  "subq", // Alpha_INS_SUBQ
+  "subs/su", // Alpha_INS_SUBSsSU
+  "subt/su", // Alpha_INS_SUBTsSU
+  "trapb", // Alpha_INS_TRAPB
+  "umulh", // Alpha_INS_UMULH
+  "wh64", // Alpha_INS_WH64
+  "wh64en", // Alpha_INS_WH64EN
+  "wmb", // Alpha_INS_WMB
+  "xor", // Alpha_INS_XOR
+  "zapnot", // Alpha_INS_ZAPNOT

thirdparty/capstone/arch/Alpha/AlphaGenCSOpGroup.inc

@@ -0,0 +1,14 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: 083d57d0731afc1746680d828bdfe2fa41f62a61 */
+/* LLVM-tag: llvmorg-3.0.0-2-g083d57d0731a */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+  Alpha_OP_GROUP_Operand = 0,

thirdparty/capstone/arch/Alpha/AlphaGenRegisterInfo.inc

@@ -0,0 +1,280 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: 083d57d0731afc1746680d828bdfe2fa41f62a61 */
+/* LLVM-tag: llvmorg-3.0.0-2-g083d57d0731a */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+#ifdef GET_REGINFO_ENUM
+#undef GET_REGINFO_ENUM
+
+enum {
+  Alpha_NoRegister,
+  Alpha_F0 = 1,
+  Alpha_F1 = 2,
+  Alpha_F2 = 3,
+  Alpha_F3 = 4,
+  Alpha_F4 = 5,
+  Alpha_F5 = 6,
+  Alpha_F6 = 7,
+  Alpha_F7 = 8,
+  Alpha_F8 = 9,
+  Alpha_F9 = 10,
+  Alpha_F10 = 11,
+  Alpha_F11 = 12,
+  Alpha_F12 = 13,
+  Alpha_F13 = 14,
+  Alpha_F14 = 15,
+  Alpha_F15 = 16,
+  Alpha_F16 = 17,
+  Alpha_F17 = 18,
+  Alpha_F18 = 19,
+  Alpha_F19 = 20,
+  Alpha_F20 = 21,
+  Alpha_F21 = 22,
+  Alpha_F22 = 23,
+  Alpha_F23 = 24,
+  Alpha_F24 = 25,
+  Alpha_F25 = 26,
+  Alpha_F26 = 27,
+  Alpha_F27 = 28,
+  Alpha_F28 = 29,
+  Alpha_F29 = 30,
+  Alpha_F30 = 31,
+  Alpha_F31 = 32,
+  Alpha_R0 = 33,
+  Alpha_R1 = 34,
+  Alpha_R2 = 35,
+  Alpha_R3 = 36,
+  Alpha_R4 = 37,
+  Alpha_R5 = 38,
+  Alpha_R6 = 39,
+  Alpha_R7 = 40,
+  Alpha_R8 = 41,
+  Alpha_R9 = 42,
+  Alpha_R10 = 43,
+  Alpha_R11 = 44,
+  Alpha_R12 = 45,
+  Alpha_R13 = 46,
+  Alpha_R14 = 47,
+  Alpha_R15 = 48,
+  Alpha_R16 = 49,
+  Alpha_R17 = 50,
+  Alpha_R18 = 51,
+  Alpha_R19 = 52,
+  Alpha_R20 = 53,
+  Alpha_R21 = 54,
+  Alpha_R22 = 55,
+  Alpha_R23 = 56,
+  Alpha_R24 = 57,
+  Alpha_R25 = 58,
+  Alpha_R26 = 59,
+  Alpha_R27 = 60,
+  Alpha_R28 = 61,
+  Alpha_R29 = 62,
+  Alpha_R30 = 63,
+  Alpha_R31 = 64,
+  NUM_TARGET_REGS // 65
+};
+
+// Register classes
+
+enum {
+  Alpha_F4RCRegClassID = 0,
+  Alpha_F8RCRegClassID = 1,
+  Alpha_GPRCRegClassID = 2,
+
+};
+#endif // GET_REGINFO_ENUM
+
+#ifdef GET_REGINFO_MC_DESC
+#undef GET_REGINFO_MC_DESC
+
+static const MCPhysReg AlphaRegDiffLists[] = {
+  /* 0 */ -1, 0,
+};
+
+static const uint16_t AlphaSubRegIdxLists[] = {
+  /* 0 */ 0,
+};
+
+static const MCRegisterDesc AlphaRegDesc[] = { // Descriptors
+  { 3, 0, 0, 0, 0, 0 },
+  { 24, 1, 1, 0, 1, 0 },
+  { 54, 1, 1, 0, 1, 0 },
+  { 76, 1, 1, 0, 1, 0 },
+  { 98, 1, 1, 0, 1, 0 },
+  { 120, 1, 1, 0, 1, 0 },
+  { 142, 1, 1, 0, 1, 0 },
+  { 164, 1, 1, 0, 1, 0 },
+  { 186, 1, 1, 0, 1, 0 },
+  { 208, 1, 1, 0, 1, 0 },
+  { 230, 1, 1, 0, 1, 0 },
+  { 0, 1, 1, 0, 1, 0 },
+  { 30, 1, 1, 0, 1, 0 },
+  { 60, 1, 1, 0, 1, 0 },
+  { 82, 1, 1, 0, 1, 0 },
+  { 104, 1, 1, 0, 1, 0 },
+  { 126, 1, 1, 0, 1, 0 },
+  { 148, 1, 1, 0, 1, 0 },
+  { 170, 1, 1, 0, 1, 0 },
+  { 192, 1, 1, 0, 1, 0 },
+  { 214, 1, 1, 0, 1, 0 },
+  { 8, 1, 1, 0, 1, 0 },
+  { 38, 1, 1, 0, 1, 0 },
+  { 68, 1, 1, 0, 1, 0 },
+  { 90, 1, 1, 0, 1, 0 },
+  { 112, 1, 1, 0, 1, 0 },
+  { 134, 1, 1, 0, 1, 0 },
+  { 156, 1, 1, 0, 1, 0 },
+  { 178, 1, 1, 0, 1, 0 },
+  { 200, 1, 1, 0, 1, 0 },
+  { 222, 1, 1, 0, 1, 0 },
+  { 16, 1, 1, 0, 1, 0 },
+  { 46, 1, 1, 0, 1, 0 },
+  { 27, 1, 1, 0, 1, 0 },
+  { 57, 1, 1, 0, 1, 0 },
+  { 79, 1, 1, 0, 1, 0 },
+  { 101, 1, 1, 0, 1, 0 },
+  { 123, 1, 1, 0, 1, 0 },
+  { 145, 1, 1, 0, 1, 0 },
+  { 167, 1, 1, 0, 1, 0 },
+  { 189, 1, 1, 0, 1, 0 },
+  { 211, 1, 1, 0, 1, 0 },
+  { 233, 1, 1, 0, 1, 0 },
+  { 4, 1, 1, 0, 1, 0 },
+  { 34, 1, 1, 0, 1, 0 },
+  { 64, 1, 1, 0, 1, 0 },
+  { 86, 1, 1, 0, 1, 0 },
+  { 108, 1, 1, 0, 1, 0 },
+  { 130, 1, 1, 0, 1, 0 },
+  { 152, 1, 1, 0, 1, 0 },
+  { 174, 1, 1, 0, 1, 0 },
+  { 196, 1, 1, 0, 1, 0 },
+  { 218, 1, 1, 0, 1, 0 },
+  { 12, 1, 1, 0, 1, 0 },
+  { 42, 1, 1, 0, 1, 0 },
+  { 72, 1, 1, 0, 1, 0 },
+  { 94, 1, 1, 0, 1, 0 },
+  { 116, 1, 1, 0, 1, 0 },
+  { 138, 1, 1, 0, 1, 0 },
+  { 160, 1, 1, 0, 1, 0 },
+  { 182, 1, 1, 0, 1, 0 },
+  { 204, 1, 1, 0, 1, 0 },
+  { 226, 1, 1, 0, 1, 0 },
+  { 20, 1, 1, 0, 1, 0 },
+  { 50, 1, 1, 0, 1, 0 },
+};
+
+  // F4RC Register Class...
+  static const MCPhysReg F4RC[] = {
+    Alpha_F0, Alpha_F1, Alpha_F10, Alpha_F11, Alpha_F12, Alpha_F13, Alpha_F14, Alpha_F15, Alpha_F16, Alpha_F17, Alpha_F18, Alpha_F19, Alpha_F20, Alpha_F21, Alpha_F22, Alpha_F23, Alpha_F24, Alpha_F25, Alpha_F26, Alpha_F27, Alpha_F28, Alpha_F29, Alpha_F30, Alpha_F2, Alpha_F3, Alpha_F4, Alpha_F5, Alpha_F6, Alpha_F7, Alpha_F8, Alpha_F9, Alpha_F31, 
+  };
+
+  // F4RC Bit set.
+  static const uint8_t F4RCBits[] = {
+    0xfe, 0xff, 0xff, 0xff, 0x01, 
+  };
+
+  // F8RC Register Class...
+  static const MCPhysReg F8RC[] = {
+    Alpha_F0, Alpha_F1, Alpha_F10, Alpha_F11, Alpha_F12, Alpha_F13, Alpha_F14, Alpha_F15, Alpha_F16, Alpha_F17, Alpha_F18, Alpha_F19, Alpha_F20, Alpha_F21, Alpha_F22, Alpha_F23, Alpha_F24, Alpha_F25, Alpha_F26, Alpha_F27, Alpha_F28, Alpha_F29, Alpha_F30, Alpha_F2, Alpha_F3, Alpha_F4, Alpha_F5, Alpha_F6, Alpha_F7, Alpha_F8, Alpha_F9, Alpha_F31, 
+  };
+
+  // F8RC Bit set.
+  static const uint8_t F8RCBits[] = {
+    0xfe, 0xff, 0xff, 0xff, 0x01, 
+  };
+
+  // GPRC Register Class...
+  static const MCPhysReg GPRC[] = {
+    Alpha_R0, Alpha_R1, Alpha_R2, Alpha_R3, Alpha_R4, Alpha_R5, Alpha_R6, Alpha_R7, Alpha_R8, Alpha_R16, Alpha_R17, Alpha_R18, Alpha_R19, Alpha_R20, Alpha_R21, Alpha_R22, Alpha_R23, Alpha_R24, Alpha_R25, Alpha_R28, Alpha_R27, Alpha_R26, Alpha_R29, Alpha_R9, Alpha_R10, Alpha_R11, Alpha_R12, Alpha_R13, Alpha_R14, Alpha_R15, Alpha_R30, Alpha_R31, 
+  };
+
+  // GPRC Bit set.
+  static const uint8_t GPRCBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 
+  };
+
+static const MCRegisterClass AlphaMCRegisterClasses[] = {
+  { F4RC, F4RCBits, sizeof(F4RCBits) },
+  { F8RC, F8RCBits, sizeof(F8RCBits) },
+  { GPRC, GPRCBits, sizeof(GPRCBits) },
+};
+
+static const uint16_t AlphaRegEncodingTable[] = {
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+};
+#endif // GET_REGINFO_MC_DESC
+
+

thirdparty/capstone/arch/Alpha/AlphaGenSubtargetInfo.inc

@@ -0,0 +1,24 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: 083d57d0731afc1746680d828bdfe2fa41f62a61 */
+/* LLVM-tag: llvmorg-3.0.0-2-g083d57d0731a */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+#ifdef GET_SUBTARGETINFO_ENUM
+#undef GET_SUBTARGETINFO_ENUM
+
+enum {
+  Alpha_FeatureCIX = 0,
+  Alpha_NumSubtargetFeatures = 1
+};
+#endif // GET_SUBTARGETINFO_ENUM
+
+
+

thirdparty/capstone/arch/Alpha/AlphaInstPrinter.c

@@ -0,0 +1,90 @@
+/* Capstone Disassembly Engine */
+/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2023 */
+
+#ifdef CAPSTONE_HAS_ALPHA
+
+#include <platform.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "../../utils.h"
+#include "../../Mapping.h"
+#include "../../MCInstPrinter.h"
+
+#include "AlphaLinkage.h"
+#include "AlphaMapping.h"
+
+static const char *getRegisterName(unsigned RegNo);
+
+static void printInstruction(MCInst *, uint64_t, SStream *);
+static void printOperand(MCInst *MI, int OpNum, SStream *O);
+static void printOperandAddr(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O);
+
+#define GET_INSTRINFO_ENUM
+
+#include "AlphaGenInstrInfo.inc"
+
+#define GET_REGINFO_ENUM
+
+#include "AlphaGenRegisterInfo.inc"
+
+static void printOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	if (OpNum >= MI->size)
+		return;
+
+	Alpha_add_cs_detail(MI, OpNum);
+	
+	MCOperand *Op;
+	Op = MCInst_getOperand(MI, OpNum);
+	if (MCOperand_isReg(Op)) {
+		unsigned reg = MCOperand_getReg(Op);
+		SStream_concat(O, "%s", getRegisterName(reg));
+	} else if (MCOperand_isImm(Op)) {
+		int64_t Imm = MCOperand_getImm(Op);
+		if (Imm >= 0) {
+			if (Imm > HEX_THRESHOLD)
+				SStream_concat(O, "0x%" PRIx64, Imm);
+			else
+				SStream_concat(O, "%" PRIu64, Imm);
+		} else {
+			if (Imm < -HEX_THRESHOLD)
+				SStream_concat(O, "-0x%" PRIx64, -Imm);
+			else
+				SStream_concat(O, "-%" PRIu64, -Imm);
+		}
+	}
+}
+
+static void printOperandAddr(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O) 
+{
+	MCOperand *Op = MCInst_getOperand(MI, (OpNum));
+
+	uint64_t Imm = MCOperand_getImm(Op);
+	uint64_t Target = Address + 4 + (int16_t) (Imm << 2);
+
+	Alpha_set_detail_op_imm(MI, OpNum, ALPHA_OP_IMM, Target);
+	printUInt64(O, Target);
+}
+
+#define PRINT_ALIAS_INSTR
+
+#include "AlphaGenAsmWriter.inc"
+
+const char *Alpha_LLVM_getRegisterName(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	return getRegisterName(id);
+#else
+	return NULL;
+#endif
+}
+
+void Alpha_LLVM_printInstruction(MCInst *MI, SStream *O, void *Info)
+{
+	printAliasInstr(MI, MI->address, O);
+	printInstruction(MI, MI->address, O);
+}
+
+#endif

thirdparty/capstone/arch/Alpha/AlphaLinkage.h

@@ -0,0 +1,21 @@
+/* Capstone Disassembly Engine */
+/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2023 */
+
+#ifndef CS_ALPHA_LINKAGE_H
+#define CS_ALPHA_LINKAGE_H
+
+// Function definitions to call static LLVM functions.
+
+#include "../../MCInst.h"
+#include "../../MCRegisterInfo.h"
+#include "../../SStream.h"
+#include "AlphaMapping.h"
+
+const char *Alpha_LLVM_getRegisterName(csh handle, unsigned int id);
+void Alpha_LLVM_printInstruction(MCInst *MI, SStream *O, void *Info);
+DecodeStatus Alpha_LLVM_getInstruction(csh handle, const uint8_t *Bytes,
+									   size_t ByteLen, MCInst *MI,
+									   uint16_t *Size, uint64_t Address,
+									   void *Info);
+
+#endif // CS_ALPHA_LINKAGE_H

thirdparty/capstone/arch/Alpha/AlphaMapping.c

@@ -0,0 +1,182 @@
+/* Capstone Disassembly Engine */
+/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2023 */
+
+#ifdef CAPSTONE_HAS_ALPHA
+
+#include <stdio.h> // debug
+#include <string.h>
+
+#include "../../Mapping.h"
+#include "../../cs_priv.h"
+#include "../../cs_simple_types.h"
+#include "../../utils.h"
+
+#include "AlphaLinkage.h"
+#include "AlphaMapping.h"
+#include "./AlphaDisassembler.h"
+
+#define GET_INSTRINFO_ENUM
+
+#include "AlphaGenInstrInfo.inc"
+
+static const insn_map insns[] = {
+#include "AlphaGenCSMappingInsn.inc"
+};
+
+static const map_insn_ops insn_operands[] = {
+#include "AlphaGenCSMappingInsnOp.inc"
+};
+
+void Alpha_init_cs_detail(MCInst *MI)
+{
+	if (detail_is_set(MI)) {
+		memset(get_detail(MI), 0,
+			   offsetof(cs_detail, alpha) + sizeof(cs_alpha));
+	}
+}
+
+void Alpha_add_cs_detail(MCInst *MI, unsigned OpNum)
+{
+	if (!detail_is_set(MI))
+		return;
+
+	cs_op_type op_type = map_get_op_type(MI, OpNum);
+	if (op_type == CS_OP_IMM)
+		Alpha_set_detail_op_imm(MI, OpNum, ALPHA_OP_IMM,
+								MCInst_getOpVal(MI, OpNum));
+	else if (op_type == CS_OP_REG)
+		Alpha_set_detail_op_reg(MI, OpNum, MCInst_getOpVal(MI, OpNum));
+	else
+		assert(0 && "Op type not handled.");
+}
+
+void Alpha_set_detail_op_imm(MCInst *MI, unsigned OpNum, alpha_op_type ImmType,
+							 int64_t Imm)
+{
+	if (!detail_is_set(MI))
+		return;
+	assert(!(map_get_op_type(MI, OpNum) & CS_OP_MEM));
+	assert(map_get_op_type(MI, OpNum) == CS_OP_IMM);
+	assert(ImmType == ALPHA_OP_IMM);
+
+	Alpha_get_detail_op(MI, 0)->type = ImmType;
+	Alpha_get_detail_op(MI, 0)->imm = Imm;
+	Alpha_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
+	Alpha_inc_op_count(MI);
+}
+
+void Alpha_set_detail_op_reg(MCInst *MI, unsigned OpNum, alpha_op_type Reg)
+{
+	if (!detail_is_set(MI))
+		return;
+	assert(!(map_get_op_type(MI, OpNum) & CS_OP_MEM));
+	assert(map_get_op_type(MI, OpNum) == CS_OP_REG);
+
+	Alpha_get_detail_op(MI, 0)->type = ALPHA_OP_REG;
+	Alpha_get_detail_op(MI, 0)->reg = Reg;
+	Alpha_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
+	Alpha_inc_op_count(MI);
+}
+
+// given internal insn id, return public instruction info
+void Alpha_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
+{
+	unsigned short i;
+
+	i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache);
+	if (i == 0) { return; }
+	insn->id = insns[i].mapid;
+
+	if (insn->detail) {
+#ifndef CAPSTONE_DIET
+		memcpy(insn->detail->regs_read, insns[i].regs_use,
+				sizeof(insns[i].regs_use));
+		insn->detail->regs_read_count =
+			(uint8_t)count_positive(insns[i].regs_use);
+
+		memcpy(insn->detail->regs_write, insns[i].regs_mod,
+				sizeof(insns[i].regs_mod));
+		insn->detail->regs_write_count =
+			(uint8_t)count_positive(insns[i].regs_mod);
+
+		memcpy(insn->detail->groups, insns[i].groups,
+				sizeof(insns[i].groups));
+		insn->detail->groups_count =
+			(uint8_t)count_positive8(insns[i].groups);
+#endif
+	}
+}
+
+#ifndef CAPSTONE_DIET
+
+static const char * const insn_names[] = {
+#include "AlphaGenCSMappingInsnName.inc"
+};
+
+// special alias insn
+// static name_map alias_insn_names[] = {{0, NULL}};
+#endif
+
+const char *Alpha_insn_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	if (id >= ALPHA_INS_ENDING)
+		return NULL;
+
+	if (id < ARR_SIZE(insn_names))
+		return insn_names[id];
+
+	return NULL;
+#else
+	return NULL;
+#endif
+}
+
+#ifndef CAPSTONE_DIET
+static const name_map group_name_maps[] = {
+	{Alpha_GRP_INVALID, NULL},
+	{Alpha_GRP_CALL, "call"},
+	{Alpha_GRP_JUMP, "jump"},
+	{Alpha_GRP_BRANCH_RELATIVE, "branch_relative"},
+};
+#endif
+
+const char *Alpha_group_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
+#else
+	return NULL;
+#endif
+}
+
+const char *Alpha_getRegisterName(csh handle, unsigned int id)
+{
+	return Alpha_LLVM_getRegisterName(handle, id);
+}
+
+void Alpha_printInst(MCInst *MI, SStream *O, void *Info)
+{
+	Alpha_LLVM_printInstruction(MI, O, Info);
+}
+
+void Alpha_set_instr_map_data(MCInst *MI) 
+{
+	map_cs_id(MI, insns, ARR_SIZE(insns));
+	map_implicit_reads(MI, insns);
+	map_implicit_writes(MI, insns);
+	map_groups(MI, insns);
+}
+
+bool Alpha_getInstruction(csh handle, const uint8_t *code,
+								  size_t code_len, MCInst *instr,
+								  uint16_t *size, uint64_t address, void *info)
+{
+	Alpha_init_cs_detail(instr);
+	bool Result = Alpha_LLVM_getInstruction(handle, code, code_len, instr, size,
+									 address, info);
+	Alpha_set_instr_map_data(instr);
+	return Result;
+}
+
+#endif

thirdparty/capstone/arch/Alpha/AlphaMapping.h

@@ -0,0 +1,35 @@
+/* Capstone Disassembly Engine */
+/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2023 */
+
+#ifndef CS_ALPHA_MAP_H
+#define CS_ALPHA_MAP_H
+
+#include "../../MCDisassembler.h"
+#include "../../MCInst.h"
+#include "../../SStream.h"
+#include <capstone/capstone.h>
+
+// unsigned int Alpha_map_insn_id(cs_struct *h, unsigned int id);
+
+// given internal insn id, return public instruction info
+void Alpha_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
+
+const char *Alpha_insn_name(csh handle, unsigned int id);
+
+const char *Alpha_group_name(csh handle, unsigned int id);
+
+void Alpha_printInst(MCInst *MI, SStream *O, void *Info);
+
+const char *Alpha_getRegisterName(csh handle, unsigned int id);
+bool Alpha_getInstruction(csh handle, const uint8_t *code,
+								  size_t code_len, MCInst *instr,
+								  uint16_t *size, uint64_t address, void *info);
+void Alpha_init_cs_detail(MCInst *MI);
+void Alpha_add_cs_detail(MCInst *MI, unsigned OpNum);
+
+void Alpha_set_instr_map_data(MCInst *MI);
+void Alpha_set_detail_op_imm(MCInst *MI, unsigned OpNum, alpha_op_type ImmType,
+							 int64_t Imm);
+void Alpha_set_detail_op_reg(MCInst *MI, unsigned OpNum, alpha_op_type Reg);
+
+#endif

thirdparty/capstone/arch/Alpha/AlphaModule.c

@@ -0,0 +1,44 @@
+/* Capstone Disassembly Engine */
+/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2023 */
+
+#ifdef CAPSTONE_HAS_ALPHA
+
+#include "../../utils.h"
+#include "../../MCRegisterInfo.h"
+#include "AlphaDisassembler.h"
+#include "AlphaMapping.h"
+#include "AlphaModule.h"
+
+cs_err ALPHA_global_init(cs_struct *ud)
+{
+	MCRegisterInfo *mri;
+
+	mri = cs_mem_malloc(sizeof(*mri));
+
+	Alpha_init(mri);
+	ud->printer = Alpha_printInst;
+	ud->printer_info = mri;
+	ud->getinsn_info = mri;
+	ud->disasm = Alpha_getInstruction;
+	ud->post_printer = NULL;
+
+	ud->reg_name = Alpha_getRegisterName;
+	ud->insn_id = Alpha_get_insn_id;
+	ud->insn_name = Alpha_insn_name;
+	ud->group_name = Alpha_group_name;
+
+	return CS_ERR_OK;
+}
+
+cs_err ALPHA_option(cs_struct *handle, cs_opt_type type, size_t value)
+{
+	if (type == CS_OPT_SYNTAX) {
+		handle->syntax = (int)value;
+	} else if (type == CS_OPT_MODE) {
+		handle->mode = (cs_mode)value;
+	}
+
+	return CS_ERR_OK;
+}
+
+#endif

thirdparty/capstone/arch/Alpha/AlphaModule.h

@@ -0,0 +1,12 @@
+/* Capstone Disassembly Engine */
+/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2023 */
+
+#ifndef CAPSTONE_ALPHAMODULE_H
+#define CAPSTONE_ALPHAMODULE_H
+
+#include "../../utils.h"
+
+cs_err ALPHA_global_init(cs_struct *ud);
+cs_err ALPHA_option(cs_struct *handle, cs_opt_type type, size_t value);
+
+#endif // CAPSTONE_ALPHAMODULE_H

thirdparty/capstone/arch/BPF/BPFConstants.h

@@ -0,0 +1,88 @@
+/* Capstone Disassembly Engine */
+/* BPF Backend by david942j <david942j@gmail.com>, 2019 */
+
+/* This file defines constants and macros used for parsing a BPF instruction */
+
+#ifndef CS_BPF_CONSTANTS_H
+#define CS_BPF_CONSTANTS_H
+
+#define BPF_CLASS(code) ((code) & 0x7)
+
+///< Instruction classes
+#define BPF_CLASS_LD	0x00
+#define BPF_CLASS_LDX	0x01
+#define BPF_CLASS_ST	0x02
+#define BPF_CLASS_STX	0x03
+#define BPF_CLASS_ALU	0x04
+#define BPF_CLASS_JMP	0x05
+#define BPF_CLASS_RET	0x06	///< cBPF only
+#define BPF_CLASS_MISC	0x07	///< cBPF only
+#define BPF_CLASS_ALU64	0x07	///< eBPF only
+
+#define BPF_OP(code) ((code) & 0xf0)
+
+///< Types of ALU instruction
+#define BPF_ALU_ADD	0x00
+#define BPF_ALU_SUB	0x10
+#define BPF_ALU_MUL	0x20
+#define BPF_ALU_DIV	0x30
+#define BPF_ALU_OR	0x40
+#define BPF_ALU_AND	0x50
+#define BPF_ALU_LSH	0x60
+#define BPF_ALU_RSH	0x70
+#define BPF_ALU_NEG	0x80
+#define BPF_ALU_MOD	0x90
+#define BPF_ALU_XOR	0xa0
+#define BPF_ALU_MOV	0xb0  ///< eBPF only: mov reg to reg
+#define BPF_ALU_ARSH	0xc0  ///< eBPF only: sign extending shift right
+#define BPF_ALU_END	0xd0  ///< eBPF only: endianness conversion
+
+///< Types of jmp instruction
+#define BPF_JUMP_JA	0x00	///< goto
+#define BPF_JUMP_JEQ	0x10	///< '=='
+#define BPF_JUMP_JGT	0x20	///< unsigned '>'
+#define BPF_JUMP_JGE	0x30	///< unsigned '>='
+#define BPF_JUMP_JSET	0x40	///< '&'
+#define BPF_JUMP_JNE	0x50	///< eBPF only: '!=' */
+#define BPF_JUMP_JSGT	0x60	///< eBPF only: signed '>'
+#define BPF_JUMP_JSGE	0x70	///< eBPF only: signed '>='
+#define BPF_JUMP_CALL	0x80	///< eBPF only: function call
+#define BPF_JUMP_EXIT	0x90	///< eBPF only: exit
+#define BPF_JUMP_JLT	0xa0	///< eBPF only: unsigned '<'
+#define BPF_JUMP_JLE	0xb0	///< eBPF only: unsigned '<='
+#define BPF_JUMP_JSLT	0xc0	///< eBPF only: signed '<'
+#define BPF_JUMP_JSLE	0xd0	///< eBPF only: signed '<='
+
+#define BPF_SRC(code) ((code) & 0x08)
+#define BPF_RVAL(code) ((code) & 0x18) /* cBPF only: for return types */
+///< Source operand
+#define BPF_SRC_K	0x00
+#define BPF_SRC_X	0x08
+#define BPF_SRC_A	0x10 /* cBPF only */
+
+#define BPF_SRC_LITTLE	BPF_SRC_K
+#define BPF_SRC_BIG	BPF_SRC_X
+
+#define BPF_SIZE(code) ((code) & 0x18)
+///< Size modifier
+#define BPF_SIZE_W   0x00	///< word
+#define BPF_SIZE_H   0x08	///< half word
+#define BPF_SIZE_B   0x10	///< byte
+#define BPF_SIZE_DW  0x18	///< eBPF only: double word
+
+#define BPF_MODE(code) ((code) & 0xe0)
+///< Mode modifier
+#define BPF_MODE_IMM	0x00	///< used for 32-bit mov in cBPF and 64-bit in eBPF
+#define BPF_MODE_ABS	0x20
+#define BPF_MODE_IND	0x40
+#define BPF_MODE_MEM	0x60
+#define BPF_MODE_LEN	0x80	///< cBPF only, reserved in eBPF
+#define BPF_MODE_MSH	0xa0	///< cBPF only, reserved in eBPF
+#define BPF_MODE_XADD	0xc0	///< eBPF only: exclusive add
+
+#define BPF_MISCOP(code) ((code) & 0x80)
+///< Operation of misc
+#define BPF_MISCOP_TAX	0x00
+#define BPF_MISCOP_TXA	0x80
+
+#endif

thirdparty/capstone/arch/BPF/BPFDisassembler.c

@@ -0,0 +1,463 @@
+/* Capstone Disassembly Engine */
+/* BPF Backend by david942j <david942j@gmail.com>, 2019 */
+
+#ifdef CAPSTONE_HAS_BPF
+
+#include <string.h>
+#include <stddef.h> // offsetof macro
+
+#include "BPFConstants.h"
+#include "BPFDisassembler.h"
+#include "BPFMapping.h"
+#include "../../cs_priv.h"
+
+static uint16_t read_u16(cs_struct *ud, const uint8_t *code)
+{
+	if (MODE_IS_BIG_ENDIAN(ud->mode))
+		return (((uint16_t)code[0] << 8) | code[1]);
+	else
+		return (((uint16_t)code[1] << 8) | code[0]);
+}
+
+static uint32_t read_u32(cs_struct *ud, const uint8_t *code)
+{
+	if (MODE_IS_BIG_ENDIAN(ud->mode))
+		return ((uint32_t)read_u16(ud, code) << 16) | read_u16(ud, code + 2);
+	else
+		return ((uint32_t)read_u16(ud, code + 2) << 16) | read_u16(ud, code);
+}
+
+///< Malloc bpf_internal, also checks if code_len is large enough.
+static bpf_internal *alloc_bpf_internal(size_t code_len)
+{
+	bpf_internal *bpf;
+
+	if (code_len < 8)
+		return NULL;
+	bpf = cs_mem_malloc(sizeof(bpf_internal));
+	if (bpf == NULL)
+		return NULL;
+	/* default value */
+	bpf->insn_size = 8;
+	return bpf;
+}
+
+///< Fetch a cBPF structure from code
+static bpf_internal* fetch_cbpf(cs_struct *ud, const uint8_t *code,
+		size_t code_len)
+{
+	bpf_internal *bpf;
+
+	bpf = alloc_bpf_internal(code_len);
+	if (bpf == NULL)
+		return NULL;
+
+	bpf->op = read_u16(ud, code);
+	bpf->jt = code[2];
+	bpf->jf = code[3];
+	bpf->k = read_u32(ud, code + 4);
+	return bpf;
+}
+
+///< Fetch an eBPF structure from code
+static bpf_internal* fetch_ebpf(cs_struct *ud, const uint8_t *code,
+		size_t code_len)
+{
+	bpf_internal *bpf;
+
+	bpf = alloc_bpf_internal(code_len);
+	if (bpf == NULL)
+		return NULL;
+
+	bpf->op = (uint16_t)code[0];
+	bpf->dst = code[1] & 0xf;
+	bpf->src = (code[1] & 0xf0) >> 4;
+
+	// eBPF has one 16-byte instruction: BPF_LD | BPF_DW | BPF_IMM,
+	// in this case imm is combined with the next block's imm.
+	if (bpf->op == (BPF_CLASS_LD | BPF_SIZE_DW | BPF_MODE_IMM)) {
+		if (code_len < 16) {
+			cs_mem_free(bpf);
+			return NULL;
+		}
+		bpf->k = read_u32(ud, code + 4) | (((uint64_t)read_u32(ud, code + 12)) << 32);
+		bpf->insn_size = 16;
+	}
+	else {
+		bpf->offset = read_u16(ud, code + 2);
+		bpf->k = read_u32(ud, code + 4);
+	}
+	return bpf;
+}
+
+#define CHECK_READABLE_REG(ud, reg) do { \
+		if (! ((reg) >= BPF_REG_R0 && (reg) <= BPF_REG_R10)) \
+			return false; \
+	} while (0)
+
+#define CHECK_WRITABLE_REG(ud, reg) do { \
+		if (! ((reg) >= BPF_REG_R0 && (reg) < BPF_REG_R10)) \
+			return false; \
+	} while (0)
+
+#define CHECK_READABLE_AND_PUSH(ud, MI, r) do { \
+		CHECK_READABLE_REG(ud, r + BPF_REG_R0); \
+		MCOperand_CreateReg0(MI, r + BPF_REG_R0); \
+	} while (0)
+
+#define CHECK_WRITABLE_AND_PUSH(ud, MI, r) do { \
+		CHECK_WRITABLE_REG(ud, r + BPF_REG_R0); \
+		MCOperand_CreateReg0(MI, r + BPF_REG_R0); \
+	} while (0)
+
+static bool decodeLoad(cs_struct *ud, MCInst *MI, bpf_internal *bpf)
+{
+	if (!EBPF_MODE(ud)) {
+		/*
+		 *  +-----+-----------+--------------------+
+		 *  | ldb |    [k]    |       [x+k]        |
+		 *  | ldh |    [k]    |       [x+k]        |
+		 *  +-----+-----------+--------------------+
+		 */
+		if (BPF_SIZE(bpf->op) == BPF_SIZE_DW)
+			return false;
+		if (BPF_SIZE(bpf->op) == BPF_SIZE_B || BPF_SIZE(bpf->op) == BPF_SIZE_H) {
+			/* no ldx */
+			if (BPF_CLASS(bpf->op) != BPF_CLASS_LD)
+				return false;
+			/* can only be BPF_ABS and BPF_IND */
+			if (BPF_MODE(bpf->op) == BPF_MODE_ABS) {
+				MCOperand_CreateImm0(MI, bpf->k);
+				return true;
+			}
+			else if (BPF_MODE(bpf->op) == BPF_MODE_IND) {
+				MCOperand_CreateReg0(MI, BPF_REG_X);
+				MCOperand_CreateImm0(MI, bpf->k);
+				return true;
+			}
+			return false;
+		}
+		/*
+		 *  +-----+----+------+------+-----+-------+
+		 *  | ld  | #k | #len | M[k] | [k] | [x+k] |
+		 *  +-----+----+------+------+-----+-------+
+		 *  | ldx | #k | #len | M[k] | 4*([k]&0xf) |
+		 *  +-----+----+------+------+-------------+
+		 */
+		switch (BPF_MODE(bpf->op)) {
+		default:
+			break;
+		case BPF_MODE_IMM:
+			MCOperand_CreateImm0(MI, bpf->k);
+			return true;
+		case BPF_MODE_LEN:
+			return true;
+		case BPF_MODE_MEM:
+			MCOperand_CreateImm0(MI, bpf->k);
+			return true;
+		}
+		if (BPF_CLASS(bpf->op) == BPF_CLASS_LD) {
+			if (BPF_MODE(bpf->op) == BPF_MODE_ABS) {
+				MCOperand_CreateImm0(MI, bpf->k);
+				return true;
+			}
+			else if (BPF_MODE(bpf->op) == BPF_MODE_IND) {
+				MCOperand_CreateReg0(MI, BPF_REG_X);
+				MCOperand_CreateImm0(MI, bpf->k);
+				return true;
+			}
+		}
+		else { /* LDX */
+			if (BPF_MODE(bpf->op) == BPF_MODE_MSH) {
+				MCOperand_CreateImm0(MI, bpf->k);
+				return true;
+			}
+		}
+		return false;
+	}
+
+	/* eBPF mode */
+	/*
+	 * - IMM: lddw dst, imm64
+	 * - ABS: ld{w,h,b,dw} [k]
+	 * - IND: ld{w,h,b,dw} [src+k]
+	 * - MEM: ldx{w,h,b,dw} dst, [src+off]
+	 */
+	if (BPF_CLASS(bpf->op) == BPF_CLASS_LD) {
+		switch (BPF_MODE(bpf->op)) {
+		case BPF_MODE_IMM:
+			if (bpf->op != (BPF_CLASS_LD | BPF_SIZE_DW | BPF_MODE_IMM))
+				return false;
+			CHECK_WRITABLE_AND_PUSH(ud, MI, bpf->dst);
+			MCOperand_CreateImm0(MI, bpf->k);
+			return true;
+		case BPF_MODE_ABS:
+			MCOperand_CreateImm0(MI, bpf->k);
+			return true;
+		case BPF_MODE_IND:
+			CHECK_READABLE_AND_PUSH(ud, MI, bpf->src);
+			MCOperand_CreateImm0(MI, bpf->k);
+			return true;
+		}
+		return false;
+
+	}
+	/* LDX */
+	if (BPF_MODE(bpf->op) == BPF_MODE_MEM) {
+		CHECK_WRITABLE_AND_PUSH(ud, MI, bpf->dst);
+		CHECK_READABLE_AND_PUSH(ud, MI, bpf->src);
+		MCOperand_CreateImm0(MI, bpf->offset);
+		return true;
+	}
+	return false;
+}
+
+static bool decodeStore(cs_struct *ud, MCInst *MI, bpf_internal *bpf)
+{
+	/* in cBPF, only BPF_ST* | BPF_MEM | BPF_W is valid
+	 * while in eBPF:
+	 * - BPF_STX | BPF_XADD | BPF_{W,DW}
+	 * - BPF_ST* | BPF_MEM | BPF_{W,H,B,DW}
+	 * are valid
+	 */
+	if (!EBPF_MODE(ud)) {
+		/* can only store to M[] */
+		if (bpf->op != (BPF_CLASS(bpf->op) | BPF_MODE_MEM | BPF_SIZE_W))
+			return false;
+		MCOperand_CreateImm0(MI, bpf->k);
+		return true;
+	}
+
+	/* eBPF */
+
+	if (BPF_MODE(bpf->op) == BPF_MODE_XADD) {
+		if (BPF_CLASS(bpf->op) != BPF_CLASS_STX)
+			return false;
+		if (BPF_SIZE(bpf->op) != BPF_SIZE_W && BPF_SIZE(bpf->op) != BPF_SIZE_DW)
+			return false;
+		/* xadd [dst + off], src */
+		CHECK_READABLE_AND_PUSH(ud, MI, bpf->dst);
+		MCOperand_CreateImm0(MI, bpf->offset);
+		CHECK_READABLE_AND_PUSH(ud, MI, bpf->src);
+		return true;
+	}
+
+	if (BPF_MODE(bpf->op) != BPF_MODE_MEM)
+		return false;
+
+	/* st [dst + off], src */
+	CHECK_READABLE_AND_PUSH(ud, MI, bpf->dst);
+	MCOperand_CreateImm0(MI, bpf->offset);
+	if (BPF_CLASS(bpf->op) == BPF_CLASS_ST)
+		MCOperand_CreateImm0(MI, bpf->k);
+	else
+		CHECK_READABLE_AND_PUSH(ud, MI, bpf->src);
+	return true;
+}
+
+static bool decodeALU(cs_struct *ud, MCInst *MI, bpf_internal *bpf)
+{
+	/* Set MI->Operands */
+
+	/* cBPF */
+	if (!EBPF_MODE(ud)) {
+		if (BPF_OP(bpf->op) > BPF_ALU_XOR)
+			return false;
+		/* cBPF's NEG has no operands */
+		if (BPF_OP(bpf->op) == BPF_ALU_NEG)
+			return true;
+		if (BPF_SRC(bpf->op) == BPF_SRC_K)
+			MCOperand_CreateImm0(MI, bpf->k);
+		else /* BPF_SRC_X */
+			MCOperand_CreateReg0(MI, BPF_REG_X);
+		return true;
+	}
+
+	/* eBPF */
+
+	if (BPF_OP(bpf->op) > BPF_ALU_END)
+		return false;
+	/* ENDian's imm must be one of 16, 32, 64 */
+	if (BPF_OP(bpf->op) == BPF_ALU_END) {
+		if (bpf->k != 16 && bpf->k != 32 && bpf->k != 64)
+			return false;
+		if (BPF_CLASS(bpf->op) == BPF_CLASS_ALU64 && BPF_SRC(bpf->op) != BPF_SRC_LITTLE)
+			return false;
+	}
+
+	/* - op dst, imm
+	 * - op dst, src
+	 * - neg dst
+	 * - le<imm> dst
+	 */
+	/* every ALU instructions have dst op */
+	CHECK_WRITABLE_AND_PUSH(ud, MI, bpf->dst);
+
+	/* special cases */
+	if (BPF_OP(bpf->op) == BPF_ALU_NEG)
+		return true;
+	if (BPF_OP(bpf->op) == BPF_ALU_END) {
+		/* bpf->k must be one of 16, 32, 64 */
+		MCInst_setOpcode(MI, MCInst_getOpcode(MI) | ((uint32_t)bpf->k << 4));
+		return true;
+	}
+
+	/* normal cases */
+	if (BPF_SRC(bpf->op) == BPF_SRC_K) {
+		MCOperand_CreateImm0(MI, bpf->k);
+	}
+	else { /* BPF_SRC_X */
+		CHECK_READABLE_AND_PUSH(ud, MI, bpf->src);
+	}
+	return true;
+}
+
+static bool decodeJump(cs_struct *ud, MCInst *MI, bpf_internal *bpf)
+{
+	/* cBPF and eBPF are very different in class jump */
+	if (!EBPF_MODE(ud)) {
+		if (BPF_OP(bpf->op) > BPF_JUMP_JSET)
+			return false;
+
+		/* ja is a special case of jumps */
+		if (BPF_OP(bpf->op) == BPF_JUMP_JA) {
+			MCOperand_CreateImm0(MI, bpf->k);
+			return true;
+		}
+
+		if (BPF_SRC(bpf->op) == BPF_SRC_K)
+			MCOperand_CreateImm0(MI, bpf->k);
+		else /* BPF_SRC_X */
+			MCOperand_CreateReg0(MI, BPF_REG_X);
+		MCOperand_CreateImm0(MI, bpf->jt);
+		MCOperand_CreateImm0(MI, bpf->jf);
+	}
+	else {
+		if (BPF_OP(bpf->op) > BPF_JUMP_JSLE)
+			return false;
+
+		/* No operands for exit */
+		if (BPF_OP(bpf->op) == BPF_JUMP_EXIT)
+			return bpf->op == (BPF_CLASS_JMP | BPF_JUMP_EXIT);
+		if (BPF_OP(bpf->op) == BPF_JUMP_CALL) {
+			if (bpf->op == (BPF_CLASS_JMP | BPF_JUMP_CALL)) {
+				MCOperand_CreateImm0(MI, bpf->k);
+				return true;
+			}
+			if (bpf->op == (BPF_CLASS_JMP | BPF_JUMP_CALL | BPF_SRC_X)) {
+				CHECK_READABLE_AND_PUSH(ud, MI, bpf->k);
+				return true;
+			}
+			return false;
+		}
+
+		/* ja is a special case of jumps */
+		if (BPF_OP(bpf->op) == BPF_JUMP_JA) {
+			if (BPF_SRC(bpf->op) != BPF_SRC_K)
+				return false;
+			MCOperand_CreateImm0(MI, bpf->offset);
+			return true;
+		}
+
+		/* <j>  dst, src, +off */
+		CHECK_READABLE_AND_PUSH(ud, MI, bpf->dst);
+		if (BPF_SRC(bpf->op) == BPF_SRC_K)
+			MCOperand_CreateImm0(MI, bpf->k);
+		else
+			CHECK_READABLE_AND_PUSH(ud, MI, bpf->src);
+		MCOperand_CreateImm0(MI, bpf->offset);
+	}
+	return true;
+}
+
+static bool decodeReturn(cs_struct *ud, MCInst *MI, bpf_internal *bpf)
+{
+	/* Here only handles the BPF_RET class in cBPF */
+	switch (BPF_RVAL(bpf->op)) {
+	case BPF_SRC_K:
+		MCOperand_CreateImm0(MI, bpf->k);
+		return true;
+	case BPF_SRC_X:
+		MCOperand_CreateReg0(MI, BPF_REG_X);
+		return true;
+	case BPF_SRC_A:
+		MCOperand_CreateReg0(MI, BPF_REG_A);
+		return true;
+	}
+	return false;
+}
+
+static bool decodeMISC(cs_struct *ud, MCInst *MI, bpf_internal *bpf)
+{
+	uint16_t op = bpf->op ^ BPF_CLASS_MISC;
+	return op == BPF_MISCOP_TAX || op == BPF_MISCOP_TXA;
+}
+
+///< 1. Check if the instruction is valid
+///< 2. Set MI->opcode
+///< 3. Set MI->Operands
+static bool getInstruction(cs_struct *ud, MCInst *MI, bpf_internal *bpf)
+{
+	cs_detail *detail;
+
+	detail = MI->flat_insn->detail;
+	// initialize detail
+	if (detail) {
+		memset(detail, 0, offsetof(cs_detail, bpf) + sizeof(cs_bpf));
+	}
+
+	MCInst_clear(MI);
+	MCInst_setOpcode(MI, bpf->op);
+
+	switch (BPF_CLASS(bpf->op)) {
+	default: /* should never happen */
+		return false;
+	case BPF_CLASS_LD:
+	case BPF_CLASS_LDX:
+		return decodeLoad(ud, MI, bpf);
+	case BPF_CLASS_ST:
+	case BPF_CLASS_STX:
+		return decodeStore(ud, MI, bpf);
+	case BPF_CLASS_ALU:
+		return decodeALU(ud, MI, bpf);
+	case BPF_CLASS_JMP:
+		return decodeJump(ud, MI, bpf);
+	case BPF_CLASS_RET:
+		/* eBPF doesn't have this class */
+		if (EBPF_MODE(ud))
+			return false;
+		return decodeReturn(ud, MI, bpf);
+	case BPF_CLASS_MISC:
+	/* case BPF_CLASS_ALU64: */
+		if (EBPF_MODE(ud))
+			return decodeALU(ud, MI, bpf);
+		else
+			return decodeMISC(ud, MI, bpf);
+	}
+}
+
+bool BPF_getInstruction(csh ud, const uint8_t *code, size_t code_len,
+		MCInst *instr, uint16_t *size, uint64_t address, void *info)
+{
+	cs_struct *cs;
+	bpf_internal *bpf;
+
+	cs = (cs_struct*)ud;
+	if (EBPF_MODE(cs))
+		bpf = fetch_ebpf(cs, code, code_len);
+	else
+		bpf = fetch_cbpf(cs, code, code_len);
+	if (bpf == NULL)
+		return false;
+	if (!getInstruction(cs, instr, bpf)) {
+		cs_mem_free(bpf);
+		return false;
+	}
+
+	*size = bpf->insn_size;
+	cs_mem_free(bpf);
+
+	return true;
+}
+
+#endif

thirdparty/capstone/arch/BPF/BPFDisassembler.h

@@ -0,0 +1,27 @@
+/* Capstone Disassembly Engine */
+/* BPF Backend by david942j <david942j@gmail.com>, 2019 */
+
+#ifndef CS_BPF_DISASSEMBLER_H
+#define CS_BPF_DISASSEMBLER_H
+
+#include "../../MCInst.h"
+
+typedef struct bpf_internal {
+	uint16_t op;
+	uint64_t k;
+	/* for cBPF */
+	uint8_t jt;
+	uint8_t jf;
+	/* for eBPF */
+	uint8_t dst;
+	uint8_t src;
+	uint16_t offset;
+
+	/* length of this bpf instruction */
+	uint8_t insn_size;
+} bpf_internal;
+
+bool BPF_getInstruction(csh ud, const uint8_t *code, size_t code_len,
+		MCInst *instr, uint16_t *size, uint64_t address, void *info);
+
+#endif

thirdparty/capstone/arch/BPF/BPFInstPrinter.c

@@ -0,0 +1,285 @@
+/* Capstone Disassembly Engine */
+/* BPF Backend by david942j <david942j@gmail.com>, 2019 */
+
+#include <capstone/platform.h>
+
+#include "BPFConstants.h"
+#include "BPFInstPrinter.h"
+#include "BPFMapping.h"
+
+static cs_bpf_op *expand_bpf_operands(cs_bpf *bpf)
+{
+	/* assert(bpf->op_count < 3); */
+	return &bpf->operands[bpf->op_count++];
+}
+
+static void push_op_reg(cs_bpf *bpf, bpf_op_type val, uint8_t ac_mode)
+{
+	cs_bpf_op *op = expand_bpf_operands(bpf);
+
+	op->type = BPF_OP_REG;
+	op->reg = val;
+	op->access = ac_mode;
+}
+
+static void push_op_imm(cs_bpf *bpf, uint64_t val)
+{
+	cs_bpf_op *op = expand_bpf_operands(bpf);
+
+	op->type = BPF_OP_IMM;
+	op->imm = val;
+}
+
+static void push_op_off(cs_bpf *bpf, uint32_t val)
+{
+	cs_bpf_op *op = expand_bpf_operands(bpf);
+
+	op->type = BPF_OP_OFF;
+	op->off = val;
+}
+
+static void push_op_mem(cs_bpf *bpf, bpf_reg reg, uint32_t val)
+{
+	cs_bpf_op *op = expand_bpf_operands(bpf);
+
+	op->type = BPF_OP_MEM;
+	op->mem.base = reg;
+	op->mem.disp = val;
+}
+
+static void push_op_mmem(cs_bpf *bpf, uint32_t val)
+{
+	cs_bpf_op *op = expand_bpf_operands(bpf);
+
+	op->type = BPF_OP_MMEM;
+	op->mmem = val;
+}
+
+static void push_op_msh(cs_bpf *bpf, uint32_t val)
+{
+	cs_bpf_op *op = expand_bpf_operands(bpf);
+
+	op->type = BPF_OP_MSH;
+	op->msh = val;
+}
+
+static void push_op_ext(cs_bpf *bpf, bpf_ext_type val)
+{
+	cs_bpf_op *op = expand_bpf_operands(bpf);
+
+	op->type = BPF_OP_EXT;
+	op->ext = val;
+}
+
+static void convert_operands(MCInst *MI, cs_bpf *bpf)
+{
+	unsigned opcode = MCInst_getOpcode(MI);
+	unsigned mc_op_count = MCInst_getNumOperands(MI);
+	MCOperand *op;
+	MCOperand *op2;
+	unsigned i;
+
+	bpf->op_count = 0;
+	if (BPF_CLASS(opcode) == BPF_CLASS_LD || BPF_CLASS(opcode) == BPF_CLASS_LDX) {
+		switch (BPF_MODE(opcode)) {
+		case BPF_MODE_IMM:
+			if (EBPF_MODE(MI->csh)) {
+				push_op_reg(bpf, MCOperand_getReg(MCInst_getOperand(MI, 0)), CS_AC_WRITE);
+				push_op_imm(bpf, MCOperand_getImm(MCInst_getOperand(MI, 1)));
+			} else {
+				push_op_imm(bpf, MCOperand_getImm(MCInst_getOperand(MI, 0)));
+			}
+			break;
+		case BPF_MODE_ABS:
+			op = MCInst_getOperand(MI, 0);
+			push_op_mem(bpf, BPF_REG_INVALID, (uint32_t)MCOperand_getImm(op));
+			break;
+		case BPF_MODE_IND:
+			op = MCInst_getOperand(MI, 0);
+			op2 = MCInst_getOperand(MI, 1);
+			push_op_mem(bpf, MCOperand_getReg(op), (uint32_t)MCOperand_getImm(op2));
+			break;
+		case BPF_MODE_MEM:
+			if (EBPF_MODE(MI->csh)) {
+				/* ldx{w,h,b,dw} dst, [src+off] */
+				push_op_reg(bpf, MCOperand_getReg(MCInst_getOperand(MI, 0)), CS_AC_WRITE);
+				op = MCInst_getOperand(MI, 1);
+				op2 = MCInst_getOperand(MI, 2);
+				push_op_mem(bpf, MCOperand_getReg(op), (uint32_t)MCOperand_getImm(op2));
+			}
+			else {
+				push_op_mmem(bpf, (uint32_t)MCOperand_getImm(MCInst_getOperand(MI, 0)));
+			}
+			break;
+		case BPF_MODE_LEN:
+			push_op_ext(bpf, BPF_EXT_LEN);
+			break;
+		case BPF_MODE_MSH:
+			op = MCInst_getOperand(MI, 0);
+			push_op_msh(bpf, (uint32_t)MCOperand_getImm(op));
+			break;
+		/* case BPF_MODE_XADD: // not exists */
+		}
+		return;
+	}
+	if (BPF_CLASS(opcode) == BPF_CLASS_ST || BPF_CLASS(opcode) == BPF_CLASS_STX) {
+		if (!EBPF_MODE(MI->csh)) {
+			// cBPF has only one case - st* M[k]
+			push_op_mmem(bpf, (uint32_t)MCOperand_getImm(MCInst_getOperand(MI, 0)));
+			return;
+		}
+		/* eBPF has two cases:
+		 * - st [dst + off], src
+		 * - xadd [dst + off], src
+		 * they have same form of operands.
+		 */
+		op = MCInst_getOperand(MI, 0);
+		op2 = MCInst_getOperand(MI, 1);
+		push_op_mem(bpf, MCOperand_getReg(op), (uint32_t)MCOperand_getImm(op2));
+		op = MCInst_getOperand(MI, 2);
+		if (MCOperand_isImm(op))
+			push_op_imm(bpf, MCOperand_getImm(op));
+		else if (MCOperand_isReg(op))
+			push_op_reg(bpf, MCOperand_getReg(op), CS_AC_READ);
+		return;
+	}
+
+	if (BPF_CLASS(opcode) == BPF_CLASS_JMP) {
+		for (i = 0; i < mc_op_count; i++) {
+			op = MCInst_getOperand(MI, i);
+			if (MCOperand_isImm(op)) {
+				/* decide the imm is BPF_OP_IMM or BPF_OP_OFF type here */
+				/*
+				 * 1. ja +off
+				 * 2. j {x,k}, +jt, +jf // cBPF
+				 * 3. j dst_reg, {src_reg, k}, +off // eBPF
+				 */
+				if (BPF_OP(opcode) == BPF_JUMP_JA ||
+						(!EBPF_MODE(MI->csh) && i >= 1) ||
+						(EBPF_MODE(MI->csh) && i == 2))
+					push_op_off(bpf, (uint32_t)MCOperand_getImm(op));
+				else
+					push_op_imm(bpf, MCOperand_getImm(op));
+			}
+			else if (MCOperand_isReg(op)) {
+				push_op_reg(bpf, MCOperand_getReg(op), CS_AC_READ);
+			}
+		}
+		return;
+	}
+
+	if (!EBPF_MODE(MI->csh)) {
+		/* In cBPF mode, all registers in operands are accessed as read */
+		for (i = 0; i < mc_op_count; i++) {
+			op = MCInst_getOperand(MI, i);
+			if (MCOperand_isImm(op))
+				push_op_imm(bpf, MCOperand_getImm(op));
+			else if (MCOperand_isReg(op))
+				push_op_reg(bpf, MCOperand_getReg(op), CS_AC_READ);
+		}
+		return;
+	}
+
+	/* remain cases are: eBPF mode && ALU */
+	/* if (BPF_CLASS(opcode) == BPF_CLASS_ALU || BPF_CLASS(opcode) == BPF_CLASS_ALU64) */
+
+	/* We have three types:
+	 * 1. {l,b}e dst               // dst = byteswap(dst)
+	 * 2. neg dst                  // dst = -dst
+	 * 3. <op> dst, {src_reg, imm} // dst = dst <op> src
+	 * so we can simply check the number of operands,
+	 * exactly one operand means we are in case 1. and 2.,
+	 * otherwise in case 3.
+	 */
+	if (mc_op_count == 1) {
+		op = MCInst_getOperand(MI, 0);
+		push_op_reg(bpf, MCOperand_getReg(op), CS_AC_READ | CS_AC_WRITE);
+	}
+	else { // if (mc_op_count == 2)
+		op = MCInst_getOperand(MI, 0);
+		push_op_reg(bpf, MCOperand_getReg(op), CS_AC_READ | CS_AC_WRITE);
+
+		op = MCInst_getOperand(MI, 1);
+		if (MCOperand_isImm(op))
+			push_op_imm(bpf, MCOperand_getImm(op));
+		else if (MCOperand_isReg(op))
+			push_op_reg(bpf, MCOperand_getReg(op), CS_AC_READ);
+	}
+}
+
+static void print_operand(MCInst *MI, struct SStream *O, const cs_bpf_op *op)
+{
+	switch (op->type) {
+	case BPF_OP_INVALID:
+		SStream_concat(O, "invalid");
+		break;
+	case BPF_OP_REG:
+		SStream_concat(O, BPF_reg_name((csh)MI->csh, op->reg));
+		break;
+	case BPF_OP_IMM:
+		SStream_concat(O, "0x%" PRIx64, op->imm);
+		break;
+	case BPF_OP_OFF:
+		SStream_concat(O, "+0x%x", op->off);
+		break;
+	case BPF_OP_MEM:
+		SStream_concat(O, "[");
+		if (op->mem.base != BPF_REG_INVALID)
+			SStream_concat(O, BPF_reg_name((csh)MI->csh, op->mem.base));
+		if (op->mem.disp != 0) {
+			if (op->mem.base != BPF_REG_INVALID)
+				SStream_concat(O, "+");
+			SStream_concat(O, "0x%x", op->mem.disp);
+		}
+		if (op->mem.base == BPF_REG_INVALID && op->mem.disp == 0) // special case
+			SStream_concat(O, "0x0");
+		SStream_concat(O, "]");
+		break;
+	case BPF_OP_MMEM:
+		SStream_concat(O, "m[0x%x]", op->mmem);
+		break;
+	case BPF_OP_MSH:
+		SStream_concat(O, "4*([0x%x]&0xf)", op->msh);
+		break;
+	case BPF_OP_EXT:
+		switch (op->ext) {
+		case BPF_EXT_LEN:
+			SStream_concat(O, "#len");
+			break;
+		}
+		break;
+	}
+}
+
+/*
+ * 1. human readable mnemonic
+ * 2. set pubOpcode (BPF_INSN_*)
+ * 3. set detail->bpf.operands
+ * */
+void BPF_printInst(MCInst *MI, struct SStream *O, void *PrinterInfo)
+{
+	int i;
+	cs_insn insn;
+	cs_bpf bpf;
+
+	insn.detail = NULL;
+	/* set pubOpcode as instruction id */
+	BPF_get_insn_id((cs_struct*)MI->csh, &insn, MCInst_getOpcode(MI));
+	MCInst_setOpcodePub(MI, insn.id);
+
+	SStream_concat(O, BPF_insn_name((csh)MI->csh, insn.id));
+	convert_operands(MI, &bpf);
+	for (i = 0; i < bpf.op_count; i++) {
+		if (i == 0)
+			SStream_concat(O, "\t");
+		else
+			SStream_concat(O, ", ");
+		print_operand(MI, O, &bpf.operands[i]);
+	}
+
+#ifndef CAPSTONE_DIET
+	if (MI->flat_insn->detail) {
+		MI->flat_insn->detail->bpf = bpf;
+	}
+#endif
+}

thirdparty/capstone/arch/BPF/BPFInstPrinter.h

@@ -0,0 +1,16 @@
+/* Capstone Disassembly Engine */
+/* BPF Backend by david942j <david942j@gmail.com>, 2019 */
+
+#ifndef CS_BPFINSTPRINTER_H
+#define CS_BPFINSTPRINTER_H
+
+#include <capstone/capstone.h>
+
+#include "../../MCInst.h"
+#include "../../SStream.h"
+
+struct SStream;
+
+void BPF_printInst(MCInst *MI, struct SStream *O, void *Info);
+
+#endif

thirdparty/capstone/arch/BPF/BPFMapping.c

@@ -0,0 +1,534 @@
+/* Capstone Disassembly Engine */
+/* BPF Backend by david942j <david942j@gmail.com>, 2019 */
+
+#include <string.h>
+
+#include "BPFConstants.h"
+#include "BPFMapping.h"
+#include "../../Mapping.h"
+#include "../../utils.h"
+
+#ifndef CAPSTONE_DIET
+static const name_map group_name_maps[] = {
+	{ BPF_GRP_INVALID, NULL },
+
+	{ BPF_GRP_LOAD, "load" },
+	{ BPF_GRP_STORE, "store" },
+	{ BPF_GRP_ALU, "alu" },
+	{ BPF_GRP_JUMP, "jump" },
+	{ BPF_GRP_CALL, "call" },
+	{ BPF_GRP_RETURN, "return" },
+	{ BPF_GRP_MISC, "misc" },
+};
+#endif
+
+const char *BPF_group_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
+#else
+	return NULL;
+#endif
+}
+
+#ifndef CAPSTONE_DIET
+static const name_map insn_name_maps[BPF_INS_ENDING] = {
+	{ BPF_INS_INVALID, NULL },
+
+	{ BPF_INS_ADD, "add" },
+	{ BPF_INS_SUB, "sub" },
+	{ BPF_INS_MUL, "mul" },
+	{ BPF_INS_DIV, "div" },
+	{ BPF_INS_OR, "or" },
+	{ BPF_INS_AND, "and" },
+	{ BPF_INS_LSH, "lsh" },
+	{ BPF_INS_RSH, "rsh" },
+	{ BPF_INS_NEG, "neg" },
+	{ BPF_INS_MOD, "mod" },
+	{ BPF_INS_XOR, "xor" },
+	{ BPF_INS_MOV, "mov" },
+	{ BPF_INS_ARSH, "arsh" },
+
+	{ BPF_INS_ADD64, "add64" },
+	{ BPF_INS_SUB64, "sub64" },
+	{ BPF_INS_MUL64, "mul64" },
+	{ BPF_INS_DIV64, "div64" },
+	{ BPF_INS_OR64, "or64" },
+	{ BPF_INS_AND64, "and64" },
+	{ BPF_INS_LSH64, "lsh64" },
+	{ BPF_INS_RSH64, "rsh64" },
+	{ BPF_INS_NEG64, "neg64" },
+	{ BPF_INS_MOD64, "mod64" },
+	{ BPF_INS_XOR64, "xor64" },
+	{ BPF_INS_MOV64, "mov64" },
+	{ BPF_INS_ARSH64, "arsh64" },
+
+	{ BPF_INS_LE16, "le16" },
+	{ BPF_INS_LE32, "le32" },
+	{ BPF_INS_LE64, "le64" },
+	{ BPF_INS_BE16, "be16" },
+	{ BPF_INS_BE32, "be32" },
+	{ BPF_INS_BE64, "be64" },
+	{ BPF_INS_BSWAP16, "bswap16" },
+	{ BPF_INS_BSWAP32, "bswap32" },
+	{ BPF_INS_BSWAP64, "bswap64" },
+
+	{ BPF_INS_LDW, "ldw" },
+	{ BPF_INS_LDH, "ldh" },
+	{ BPF_INS_LDB, "ldb" },
+	{ BPF_INS_LDDW,	"lddw" },
+	{ BPF_INS_LDXW, "ldxw" },
+	{ BPF_INS_LDXH, "ldxh" },
+	{ BPF_INS_LDXB, "ldxb" },
+	{ BPF_INS_LDXDW, "ldxdw" },
+
+	{ BPF_INS_STW, "stw" },
+	{ BPF_INS_STH, "sth" },
+	{ BPF_INS_STB, "stb" },
+	{ BPF_INS_STDW,	"stdw" },
+	{ BPF_INS_STXW, "stxw" },
+	{ BPF_INS_STXH, "stxh" },
+	{ BPF_INS_STXB, "stxb" },
+	{ BPF_INS_STXDW, "stxdw" },
+	{ BPF_INS_XADDW, "xaddw" },
+	{ BPF_INS_XADDDW, "xadddw" },
+
+	{ BPF_INS_JMP, "jmp" },
+	{ BPF_INS_JEQ, "jeq" },
+	{ BPF_INS_JGT, "jgt" },
+	{ BPF_INS_JGE, "jge" },
+	{ BPF_INS_JSET, "jset" },
+	{ BPF_INS_JNE, "jne" },
+	{ BPF_INS_JSGT,	"jsgt" },
+	{ BPF_INS_JSGE,	"jsge" },
+	{ BPF_INS_CALL,	"call" },
+	{ BPF_INS_CALLX, "callx" },
+	{ BPF_INS_EXIT,	"exit" },
+	{ BPF_INS_JLT, "jlt" },
+	{ BPF_INS_JLE, "jle" },
+	{ BPF_INS_JSLT, "jslt" },
+	{ BPF_INS_JSLE,	"jsle" },
+
+	{ BPF_INS_RET, "ret" },
+
+	{ BPF_INS_TAX, "tax" },
+	{ BPF_INS_TXA, "txa" },
+};
+#endif
+
+const char *BPF_insn_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	/* We have some special cases because 'ld' in cBPF is equivalent to 'ldw'
+	 * in eBPF, and we don't want to see 'ldw' appears in cBPF mode.
+	 */
+	if (!EBPF_MODE(handle)) {
+		switch (id) {
+		case BPF_INS_LD: return "ld";
+		case BPF_INS_LDX: return "ldx";
+		case BPF_INS_ST: return "st";
+		case BPF_INS_STX: return "stx";
+		}
+	}
+	return id2name(insn_name_maps, ARR_SIZE(insn_name_maps), id);
+#else
+	return NULL;
+#endif
+}
+
+const char *BPF_reg_name(csh handle, unsigned int reg)
+{
+#ifndef CAPSTONE_DIET
+	if (EBPF_MODE(handle)) {
+		if (reg < BPF_REG_R0 || reg > BPF_REG_R10)
+			return NULL;
+		static const char reg_names[11][4] = {
+			"r0", "r1", "r2", "r3", "r4",
+			"r5", "r6", "r7", "r8", "r9",
+			"r10"
+		};
+		return reg_names[reg - BPF_REG_R0];
+	}
+
+	/* cBPF mode */
+	if (reg == BPF_REG_A)
+		return "a";
+	else if (reg == BPF_REG_X)
+		return "x";
+	else
+		return NULL;
+#else
+	return NULL;
+#endif
+}
+
+static bpf_insn op2insn_ld(unsigned opcode)
+{
+#define CASE(c) case BPF_SIZE_##c: \
+		if (BPF_CLASS(opcode) == BPF_CLASS_LD) \
+			return BPF_INS_LD##c; \
+		else \
+			return BPF_INS_LDX##c;
+
+	switch (BPF_SIZE(opcode)) {
+	CASE(W);
+	CASE(H);
+	CASE(B);
+	CASE(DW);
+	}
+#undef CASE
+
+	return BPF_INS_INVALID;
+}
+
+static bpf_insn op2insn_st(unsigned opcode)
+{
+	/*
+	 * - BPF_STX | BPF_XADD | BPF_{W,DW}
+	 * - BPF_ST* | BPF_MEM | BPF_{W,H,B,DW}
+	 */
+
+	if (opcode == (BPF_CLASS_STX | BPF_MODE_XADD | BPF_SIZE_W))
+		return BPF_INS_XADDW;
+	if (opcode == (BPF_CLASS_STX | BPF_MODE_XADD | BPF_SIZE_DW))
+		return BPF_INS_XADDDW;
+
+	/* should be BPF_MEM */
+#define CASE(c) case BPF_SIZE_##c: \
+		if (BPF_CLASS(opcode) == BPF_CLASS_ST) \
+			return BPF_INS_ST##c; \
+		else \
+			return BPF_INS_STX##c;
+	switch (BPF_SIZE(opcode)) {
+	CASE(W);
+	CASE(H);
+	CASE(B);
+	CASE(DW);
+	}
+#undef CASE
+
+	return BPF_INS_INVALID;
+}
+
+static bpf_insn op2insn_alu(unsigned opcode)
+{
+	/* Endian is a special case */
+	if (BPF_OP(opcode) == BPF_ALU_END) {
+		if (BPF_CLASS(opcode) == BPF_CLASS_ALU64) {
+			switch (opcode ^ BPF_CLASS_ALU64 ^ BPF_ALU_END ^ BPF_SRC_LITTLE) {
+			case (16 << 4):
+				return BPF_INS_BSWAP16;
+			case (32 << 4):
+				return BPF_INS_BSWAP32;
+			case (64 << 4):
+				return BPF_INS_BSWAP64;
+			default:
+				return BPF_INS_INVALID;
+			}
+		}
+
+		switch (opcode ^ BPF_CLASS_ALU ^ BPF_ALU_END) {
+		case BPF_SRC_LITTLE | (16 << 4):
+			return BPF_INS_LE16;
+		case BPF_SRC_LITTLE | (32 << 4):
+			return BPF_INS_LE32;
+		case BPF_SRC_LITTLE | (64 << 4):
+			return BPF_INS_LE64;
+		case BPF_SRC_BIG | (16 << 4):
+			return BPF_INS_BE16;
+		case BPF_SRC_BIG | (32 << 4):
+			return BPF_INS_BE32;
+		case BPF_SRC_BIG | (64 << 4):
+			return BPF_INS_BE64;
+		}
+		return BPF_INS_INVALID;
+	}
+
+#define CASE(c) case BPF_ALU_##c: \
+		if (BPF_CLASS(opcode) == BPF_CLASS_ALU) \
+			return BPF_INS_##c; \
+		else \
+			return BPF_INS_##c##64;
+
+	switch (BPF_OP(opcode)) {
+	CASE(ADD);
+	CASE(SUB);
+	CASE(MUL);
+	CASE(DIV);
+	CASE(OR);
+	CASE(AND);
+	CASE(LSH);
+	CASE(RSH);
+	CASE(NEG);
+	CASE(MOD);
+	CASE(XOR);
+	CASE(MOV);
+	CASE(ARSH);
+	}
+#undef CASE
+
+	return BPF_INS_INVALID;
+}
+
+static bpf_insn op2insn_jmp(unsigned opcode)
+{
+	if (opcode == (BPF_CLASS_JMP | BPF_JUMP_CALL | BPF_SRC_X)) {
+		return BPF_INS_CALLX;
+	}
+
+#define CASE(c) case BPF_JUMP_##c: return BPF_INS_##c
+	switch (BPF_OP(opcode)) {
+	case BPF_JUMP_JA:
+		return BPF_INS_JMP;
+	CASE(JEQ);
+	CASE(JGT);
+	CASE(JGE);
+	CASE(JSET);
+	CASE(JNE);
+	CASE(JSGT);
+	CASE(JSGE);
+	CASE(CALL);
+	CASE(EXIT);
+	CASE(JLT);
+	CASE(JLE);
+	CASE(JSLT);
+	CASE(JSLE);
+	}
+#undef CASE
+
+	return BPF_INS_INVALID;
+}
+
+#ifndef CAPSTONE_DIET
+static void update_regs_access(cs_struct *ud, cs_detail *detail,
+		bpf_insn insn_id, unsigned int opcode)
+{
+	if (insn_id == BPF_INS_INVALID)
+		return;
+#define PUSH_READ(r) do { \
+		detail->regs_read[detail->regs_read_count] = r; \
+		detail->regs_read_count++; \
+	} while (0)
+#define PUSH_WRITE(r) do { \
+		detail->regs_write[detail->regs_write_count] = r; \
+		detail->regs_write_count++; \
+	} while (0)
+	/*
+	 * In eBPF mode, only these instructions have implicit registers access:
+	 * - legacy ld{w,h,b,dw} * // w: r0
+	 * - exit // r: r0
+	 */
+	if (EBPF_MODE(ud)) {
+		switch (insn_id) {
+		default:
+			break;
+		case BPF_INS_LDW:
+		case BPF_INS_LDH:
+		case BPF_INS_LDB:
+		case BPF_INS_LDDW:
+			if (BPF_MODE(opcode) == BPF_MODE_ABS || BPF_MODE(opcode) == BPF_MODE_IND) {
+				PUSH_WRITE(BPF_REG_R0);
+			}
+			break;
+		case BPF_INS_EXIT:
+			PUSH_READ(BPF_REG_R0);
+			break;
+		}
+		return;
+	}
+
+	/* cBPF mode */
+	switch (BPF_CLASS(opcode)) {
+	default:
+		break;
+	case BPF_CLASS_LD:
+		PUSH_WRITE(BPF_REG_A);
+		break;
+	case BPF_CLASS_LDX:
+		PUSH_WRITE(BPF_REG_X);
+		break;
+	case BPF_CLASS_ST:
+		PUSH_READ(BPF_REG_A);
+		break;
+	case BPF_CLASS_STX:
+		PUSH_READ(BPF_REG_X);
+		break;
+	case BPF_CLASS_ALU:
+		PUSH_READ(BPF_REG_A);
+		PUSH_WRITE(BPF_REG_A);
+		break;
+	case BPF_CLASS_JMP:
+		if (insn_id != BPF_INS_JMP) // except the unconditional jump
+			PUSH_READ(BPF_REG_A);
+		break;
+	/* case BPF_CLASS_RET: */
+	case BPF_CLASS_MISC:
+		if (insn_id == BPF_INS_TAX) {
+			PUSH_READ(BPF_REG_A);
+			PUSH_WRITE(BPF_REG_X);
+		}
+		else {
+			PUSH_READ(BPF_REG_X);
+			PUSH_WRITE(BPF_REG_A);
+		}
+		break;
+	}
+}
+#endif
+
+/*
+ * 1. Convert opcode(id) to BPF_INS_*
+ * 2. Set regs_read/regs_write/groups
+ */
+void BPF_get_insn_id(cs_struct *ud, cs_insn *insn, unsigned int opcode)
+{
+	// No need to care the mode (cBPF or eBPF) since all checks has be done in
+	// BPF_getInstruction, we can simply map opcode to BPF_INS_*.
+	bpf_insn id = BPF_INS_INVALID;
+#ifndef CAPSTONE_DIET
+	cs_detail *detail;
+	bpf_insn_group grp;
+
+	detail = insn->detail;
+ #define PUSH_GROUP(grp) do { \
+		if (detail) { \
+			detail->groups[detail->groups_count] = grp; \
+			detail->groups_count++; \
+		} \
+	} while(0)
+#else
+ #define PUSH_GROUP(grp) do {} while(0)
+#endif
+
+	switch (BPF_CLASS(opcode)) {
+	default:	// will never happen
+		break;
+	case BPF_CLASS_LD:
+	case BPF_CLASS_LDX:
+		id = op2insn_ld(opcode);
+		PUSH_GROUP(BPF_GRP_LOAD);
+		break;
+	case BPF_CLASS_ST:
+	case BPF_CLASS_STX:
+		id = op2insn_st(opcode);
+		PUSH_GROUP(BPF_GRP_STORE);
+		break;
+	case BPF_CLASS_ALU:
+		id = op2insn_alu(opcode);
+		PUSH_GROUP(BPF_GRP_ALU);
+		break;
+	case BPF_CLASS_JMP:
+		id = op2insn_jmp(opcode);
+#ifndef CAPSTONE_DIET
+		grp = BPF_GRP_JUMP;
+		if (id == BPF_INS_CALL || id == BPF_INS_CALLX)
+			grp = BPF_GRP_CALL;
+		else if (id == BPF_INS_EXIT)
+			grp = BPF_GRP_RETURN;
+		PUSH_GROUP(grp);
+#endif
+		break;
+	case BPF_CLASS_RET:
+		id = BPF_INS_RET;
+		PUSH_GROUP(BPF_GRP_RETURN);
+		break;
+	// BPF_CLASS_MISC and BPF_CLASS_ALU64 have exactly same value
+	case BPF_CLASS_MISC:
+	/* case BPF_CLASS_ALU64: */
+		if (EBPF_MODE(ud)) {
+			// ALU64 in eBPF
+			id = op2insn_alu(opcode);
+			PUSH_GROUP(BPF_GRP_ALU);
+		}
+		else {
+			if (BPF_MISCOP(opcode) == BPF_MISCOP_TXA)
+				id = BPF_INS_TXA;
+			else
+				id = BPF_INS_TAX;
+			PUSH_GROUP(BPF_GRP_MISC);
+		}
+		break;
+	}
+
+	insn->id = id;
+#undef PUSH_GROUP
+
+#ifndef CAPSTONE_DIET
+	if (detail) {
+		update_regs_access(ud, detail, id, opcode);
+	}
+#endif
+}
+
+static void sort_and_uniq(cs_regs arr, uint8_t n, uint8_t *new_n)
+{
+	/* arr is always a tiny (usually n < 3) array,
+	 * a simple O(n^2) sort is efficient enough. */
+	int i;
+	int j;
+	int iMin;
+	int tmp;
+
+	/* a modified selection sort for sorting and making unique */
+	for (j = 0; j < n; j++) {
+		/* arr[iMin] will be min(arr[j .. n-1]) */
+		iMin = j;
+		for (i = j + 1; i < n; i++) {
+			if (arr[i] < arr[iMin])
+				iMin = i;
+		}
+		if (j != 0 && arr[iMin] == arr[j - 1]) { // duplicate ele found
+			arr[iMin] = arr[n - 1];
+			--n;
+		}
+		else {
+			tmp = arr[iMin];
+			arr[iMin] = arr[j];
+			arr[j] = tmp;
+		}
+	}
+
+	*new_n = n;
+}
+void BPF_reg_access(const cs_insn *insn,
+		cs_regs regs_read, uint8_t *regs_read_count,
+		cs_regs regs_write, uint8_t *regs_write_count)
+{
+	unsigned i;
+	uint8_t read_count, write_count;
+	const cs_bpf *bpf = &(insn->detail->bpf);
+
+	read_count = insn->detail->regs_read_count;
+	write_count = insn->detail->regs_write_count;
+
+	// implicit registers
+	memcpy(regs_read, insn->detail->regs_read, read_count * sizeof(insn->detail->regs_read[0]));
+	memcpy(regs_write, insn->detail->regs_write, write_count * sizeof(insn->detail->regs_write[0]));
+
+	for (i = 0; i < bpf->op_count; i++) {
+		const cs_bpf_op *op = &(bpf->operands[i]);
+		switch (op->type) {
+		default:
+			break;
+		case BPF_OP_REG:
+			if (op->access & CS_AC_READ) {
+				regs_read[read_count] = op->reg;
+				read_count++;
+			}
+			if (op->access & CS_AC_WRITE) {
+				regs_write[write_count] = op->reg;
+				write_count++;
+			}
+			break;
+		case BPF_OP_MEM:
+			if (op->mem.base != BPF_REG_INVALID) {
+				regs_read[read_count] = op->mem.base;
+				read_count++;
+			}
+			break;
+		}
+	}
+
+	sort_and_uniq(regs_read, read_count, regs_read_count);
+	sort_and_uniq(regs_write, write_count, regs_write_count);
+}

thirdparty/capstone/arch/BPF/BPFMapping.h

@@ -0,0 +1,21 @@
+/* Capstone Disassembly Engine */
+/* BPF Backend by david942j <david942j@gmail.com>, 2019 */
+
+#ifndef CS_BPFMAPPING_H
+#define CS_BPFMAPPING_H
+
+#include <capstone/capstone.h>
+
+#include "../../cs_priv.h"
+
+#define EBPF_MODE(ud) (((cs_struct*)ud)->mode & CS_MODE_BPF_EXTENDED)
+
+const char *BPF_group_name(csh handle, unsigned int id);
+const char *BPF_insn_name(csh handle, unsigned int id);
+const char *BPF_reg_name(csh handle, unsigned int reg);
+void BPF_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
+void BPF_reg_access(const cs_insn *insn,
+		cs_regs regs_read, uint8_t *regs_read_count,
+		cs_regs regs_write, uint8_t *regs_write_count);
+
+#endif

thirdparty/capstone/arch/BPF/BPFModule.c

@@ -0,0 +1,34 @@
+/* Capstone Disassembly Engine */
+/* BPF Backend by david942j <david942j@gmail.com>, 2019 */
+
+#ifdef CAPSTONE_HAS_BPF
+
+#include "BPFDisassembler.h"
+#include "BPFInstPrinter.h"
+#include "BPFMapping.h"
+#include "BPFModule.h"
+
+cs_err BPF_global_init(cs_struct *ud)
+{
+	ud->printer = BPF_printInst;
+	ud->reg_name = BPF_reg_name;
+	ud->insn_id = BPF_get_insn_id;
+	ud->insn_name = BPF_insn_name;
+	ud->group_name = BPF_group_name;
+#ifndef CAPSTONE_DIET
+	ud->reg_access = BPF_reg_access;
+#endif
+	ud->disasm = BPF_getInstruction;
+
+	return CS_ERR_OK;
+}
+
+cs_err BPF_option(cs_struct *handle, cs_opt_type type, size_t value)
+{
+	if (type == CS_OPT_MODE)
+		handle->mode = (cs_mode)value;
+
+	return CS_ERR_OK;
+}
+
+#endif

thirdparty/capstone/arch/BPF/BPFModule.h

@@ -0,0 +1,12 @@
+/* Capstone Disassembly Engine */
+/* BPF Backend by david942j <david942j@gmail.com>, 2019 */
+
+#ifndef CS_BPF_MODULE_H
+#define CS_BPF_MODULE_H
+
+#include "../../utils.h"
+
+cs_err BPF_global_init(cs_struct *ud);
+cs_err BPF_option(cs_struct *handle, cs_opt_type type, size_t value);
+
+#endif

thirdparty/capstone/arch/EVM/EVMDisassembler.c

@@ -0,0 +1,379 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh, 2018 */
+
+#include <string.h>
+#include <stddef.h> // offsetof macro
+                    // alternatively #include "../../utils.h" like everyone else
+
+#include "EVMDisassembler.h"
+#include "EVMMapping.h"
+
+static const short opcodes[256] = {
+	EVM_INS_STOP,
+	EVM_INS_ADD,
+	EVM_INS_MUL,
+	EVM_INS_SUB,
+	EVM_INS_DIV,
+	EVM_INS_SDIV,
+	EVM_INS_MOD,
+	EVM_INS_SMOD,
+	EVM_INS_ADDMOD,
+	EVM_INS_MULMOD,
+	EVM_INS_EXP,
+	EVM_INS_SIGNEXTEND,
+	-1,
+	-1,
+	-1,
+	-1,
+	EVM_INS_LT,
+	EVM_INS_GT,
+	EVM_INS_SLT,
+	EVM_INS_SGT,
+	EVM_INS_EQ,
+	EVM_INS_ISZERO,
+	EVM_INS_AND,
+	EVM_INS_OR,
+	EVM_INS_XOR,
+	EVM_INS_NOT,
+	EVM_INS_BYTE,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	EVM_INS_SHA3,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	EVM_INS_ADDRESS,
+	EVM_INS_BALANCE,
+	EVM_INS_ORIGIN,
+	EVM_INS_CALLER,
+	EVM_INS_CALLVALUE,
+	EVM_INS_CALLDATALOAD,
+	EVM_INS_CALLDATASIZE,
+	EVM_INS_CALLDATACOPY,
+	EVM_INS_CODESIZE,
+	EVM_INS_CODECOPY,
+	EVM_INS_GASPRICE,
+	EVM_INS_EXTCODESIZE,
+	EVM_INS_EXTCODECOPY,
+	EVM_INS_RETURNDATASIZE,
+	EVM_INS_RETURNDATACOPY,
+	-1,
+	EVM_INS_BLOCKHASH,
+	EVM_INS_COINBASE,
+	EVM_INS_TIMESTAMP,
+	EVM_INS_NUMBER,
+	EVM_INS_DIFFICULTY,
+	EVM_INS_GASLIMIT,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	EVM_INS_POP,
+	EVM_INS_MLOAD,
+	EVM_INS_MSTORE,
+	EVM_INS_MSTORE8,
+	EVM_INS_SLOAD,
+	EVM_INS_SSTORE,
+	EVM_INS_JUMP,
+	EVM_INS_JUMPI,
+	EVM_INS_PC,
+	EVM_INS_MSIZE,
+	EVM_INS_GAS,
+	EVM_INS_JUMPDEST,
+	-1,
+	-1,
+	-1,
+	-1,
+	EVM_INS_PUSH1,
+	EVM_INS_PUSH2,
+	EVM_INS_PUSH3,
+	EVM_INS_PUSH4,
+	EVM_INS_PUSH5,
+	EVM_INS_PUSH6,
+	EVM_INS_PUSH7,
+	EVM_INS_PUSH8,
+	EVM_INS_PUSH9,
+	EVM_INS_PUSH10,
+	EVM_INS_PUSH11,
+	EVM_INS_PUSH12,
+	EVM_INS_PUSH13,
+	EVM_INS_PUSH14,
+	EVM_INS_PUSH15,
+	EVM_INS_PUSH16,
+	EVM_INS_PUSH17,
+	EVM_INS_PUSH18,
+	EVM_INS_PUSH19,
+	EVM_INS_PUSH20,
+	EVM_INS_PUSH21,
+	EVM_INS_PUSH22,
+	EVM_INS_PUSH23,
+	EVM_INS_PUSH24,
+	EVM_INS_PUSH25,
+	EVM_INS_PUSH26,
+	EVM_INS_PUSH27,
+	EVM_INS_PUSH28,
+	EVM_INS_PUSH29,
+	EVM_INS_PUSH30,
+	EVM_INS_PUSH31,
+	EVM_INS_PUSH32,
+	EVM_INS_DUP1,
+	EVM_INS_DUP2,
+	EVM_INS_DUP3,
+	EVM_INS_DUP4,
+	EVM_INS_DUP5,
+	EVM_INS_DUP6,
+	EVM_INS_DUP7,
+	EVM_INS_DUP8,
+	EVM_INS_DUP9,
+	EVM_INS_DUP10,
+	EVM_INS_DUP11,
+	EVM_INS_DUP12,
+	EVM_INS_DUP13,
+	EVM_INS_DUP14,
+	EVM_INS_DUP15,
+	EVM_INS_DUP16,
+	EVM_INS_SWAP1,
+	EVM_INS_SWAP2,
+	EVM_INS_SWAP3,
+	EVM_INS_SWAP4,
+	EVM_INS_SWAP5,
+	EVM_INS_SWAP6,
+	EVM_INS_SWAP7,
+	EVM_INS_SWAP8,
+	EVM_INS_SWAP9,
+	EVM_INS_SWAP10,
+	EVM_INS_SWAP11,
+	EVM_INS_SWAP12,
+	EVM_INS_SWAP13,
+	EVM_INS_SWAP14,
+	EVM_INS_SWAP15,
+	EVM_INS_SWAP16,
+	EVM_INS_LOG0,
+	EVM_INS_LOG1,
+	EVM_INS_LOG2,
+	EVM_INS_LOG3,
+	EVM_INS_LOG4,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	EVM_INS_CREATE,
+	EVM_INS_CALL,
+	EVM_INS_CALLCODE,
+	EVM_INS_RETURN,
+	EVM_INS_DELEGATECALL,
+	EVM_INS_CALLBLACKBOX,
+	-1,
+	-1,
+	-1,
+	-1,
+	EVM_INS_STATICCALL,
+	-1,
+	-1,
+	EVM_INS_REVERT,
+	-1,
+	EVM_INS_SUICIDE,
+};
+
+bool EVM_getInstruction(csh ud, const uint8_t *code, size_t code_len,
+	MCInst *MI, uint16_t *size, uint64_t address, void *inst_info)
+{
+	unsigned char opcode;
+
+	if (code_len == 0)
+		return false;
+
+	opcode = code[0];
+	if (opcodes[opcode] == -1) {
+		// invalid opcode
+		return false;
+	}
+
+	// valid opcode
+	MI->address = address;
+	MI->OpcodePub = MI->Opcode = opcode;
+
+	if (opcode >= EVM_INS_PUSH1 && opcode <= EVM_INS_PUSH32) {
+		unsigned char len = (opcode - EVM_INS_PUSH1 + 1);
+		if (code_len < 1 + len) {
+			// not enough data
+			return false;
+		}
+
+		*size = 1 + len;
+		memcpy(MI->evm_data, code + 1, len);
+	} else
+		*size = 1;
+
+	if (MI->flat_insn->detail) {
+		memset(MI->flat_insn->detail, 0, offsetof(cs_detail, evm)+sizeof(cs_evm));
+		EVM_get_insn_id((cs_struct *)ud, MI->flat_insn, opcode);
+
+		if (MI->flat_insn->detail->evm.pop) {
+			MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_STACK_READ;
+			MI->flat_insn->detail->groups_count++;
+		}
+
+		if (MI->flat_insn->detail->evm.push) {
+			MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_STACK_WRITE;
+			MI->flat_insn->detail->groups_count++;
+		}
+
+		// setup groups
+		switch(opcode) {
+			default:
+				break;
+			case EVM_INS_ADD:
+			case EVM_INS_MUL:
+			case EVM_INS_SUB:
+			case EVM_INS_DIV:
+			case EVM_INS_SDIV:
+			case EVM_INS_MOD:
+			case EVM_INS_SMOD:
+			case EVM_INS_ADDMOD:
+			case EVM_INS_MULMOD:
+			case EVM_INS_EXP:
+			case EVM_INS_SIGNEXTEND:
+				MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_MATH;
+				MI->flat_insn->detail->groups_count++;
+				break;
+
+			case EVM_INS_MSTORE:
+			case EVM_INS_MSTORE8:
+			case EVM_INS_CALLDATACOPY:
+			case EVM_INS_CODECOPY:
+			case EVM_INS_EXTCODECOPY:
+				MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_MEM_WRITE;
+				MI->flat_insn->detail->groups_count++;
+				break;
+
+			case EVM_INS_MLOAD:
+			case EVM_INS_CREATE:
+			case EVM_INS_CALL:
+			case EVM_INS_CALLCODE:
+			case EVM_INS_RETURN:
+			case EVM_INS_DELEGATECALL:
+			case EVM_INS_REVERT:
+				MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_MEM_READ;
+				MI->flat_insn->detail->groups_count++;
+				break;
+
+			case EVM_INS_SSTORE:
+				MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_STORE_WRITE;
+				MI->flat_insn->detail->groups_count++;
+				break;
+
+			case EVM_INS_SLOAD:
+				MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_STORE_READ;
+				MI->flat_insn->detail->groups_count++;
+				break;
+
+			case EVM_INS_JUMP:
+			case EVM_INS_JUMPI:
+				MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_JUMP;
+				MI->flat_insn->detail->groups_count++;
+				break;
+
+			case EVM_INS_STOP:
+			case EVM_INS_SUICIDE:
+				MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_HALT;
+				MI->flat_insn->detail->groups_count++;
+				break;
+
+		}
+	}
+
+	return true;
+}

thirdparty/capstone/arch/EVM/EVMDisassembler.h

@@ -0,0 +1,12 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh, 2018 */
+
+#ifndef CS_EVMDISASSEMBLER_H
+#define CS_EVMDISASSEMBLER_H
+
+#include "../../MCInst.h"
+
+bool EVM_getInstruction(csh ud, const uint8_t *code, size_t code_len,
+		MCInst *instr, uint16_t *size, uint64_t address, void *info);
+
+#endif

thirdparty/capstone/arch/EVM/EVMInstPrinter.c

@@ -0,0 +1,20 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh, 2018 */
+
+#include "EVMInstPrinter.h"
+#include "EVMMapping.h"
+
+
+void EVM_printInst(MCInst *MI, struct SStream *O, void *PrinterInfo)
+{
+	SStream_concat0(O, EVM_insn_name((csh)MI->csh, MI->Opcode));
+
+	if (MI->Opcode >= EVM_INS_PUSH1 && MI->Opcode <= EVM_INS_PUSH32) {
+		unsigned int i;
+
+		SStream_concat0(O, "\t");
+		for (i = 0; i < MI->Opcode - EVM_INS_PUSH1 + 1; i++) {
+			SStream_concat(O, "%02x", MI->evm_data[i]);
+		}
+	}
+}

thirdparty/capstone/arch/EVM/EVMInstPrinter.h

@@ -0,0 +1,17 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh, 2018 */
+
+#ifndef CS_EVMINSTPRINTER_H
+#define CS_EVMINSTPRINTER_H
+
+
+#include "capstone/capstone.h"
+#include "../../MCInst.h"
+#include "../../SStream.h"
+#include "../../cs_priv.h"
+
+struct SStream;
+
+void EVM_printInst(MCInst *MI, struct SStream *O, void *Info);
+
+#endif

thirdparty/capstone/arch/EVM/EVMMapping.c

@@ -0,0 +1,345 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh, 2018 */
+
+#ifdef CAPSTONE_HAS_EVM
+
+#include <string.h>
+
+#include "../../cs_priv.h"
+#include "../../Mapping.h"
+#include "../../utils.h"
+
+#include "EVMMapping.h"
+
+#ifndef CAPSTONE_DIET
+static const cs_evm insns[256] = {
+#include "EVMMappingInsn.inc"
+};
+
+// look for @id in @insns, given its size in @max.
+// return -1 if not found
+static int evm_insn_find(const cs_evm *insns, unsigned int max, unsigned int id)
+{
+	if (id >= max)
+		return -1;
+
+	if (insns[id].fee == 0xffffffff)
+		// unused opcode
+		return -1;
+
+	return (int)id;
+}
+#endif
+
+// fill in details
+void EVM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
+{
+	insn->id = id;
+#ifndef CAPSTONE_DIET
+	if (evm_insn_find(insns, ARR_SIZE(insns), id) > 0) {
+		if (h->detail_opt) {
+			memcpy(&insn->detail->evm, &insns[id], sizeof(insns[id]));
+		}
+	}
+#endif
+}
+
+#ifndef CAPSTONE_DIET
+static const name_map insn_name_maps[256] = {
+	{ EVM_INS_STOP, "stop" },
+	{ EVM_INS_ADD, "add" },
+	{ EVM_INS_MUL, "mul" },
+	{ EVM_INS_SUB, "sub" },
+	{ EVM_INS_DIV, "div" },
+	{ EVM_INS_SDIV, "sdiv" },
+	{ EVM_INS_MOD, "mod" },
+	{ EVM_INS_SMOD, "smod" },
+	{ EVM_INS_ADDMOD, "addmod" },
+	{ EVM_INS_MULMOD, "mulmod" },
+	{ EVM_INS_EXP, "exp" },
+	{ EVM_INS_SIGNEXTEND, "signextend" },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_LT, "lt" },
+	{ EVM_INS_GT, "gt" },
+	{ EVM_INS_SLT, "slt" },
+	{ EVM_INS_SGT, "sgt" },
+	{ EVM_INS_EQ, "eq" },
+	{ EVM_INS_ISZERO, "iszero" },
+	{ EVM_INS_AND, "and" },
+	{ EVM_INS_OR, "or" },
+	{ EVM_INS_XOR, "xor" },
+	{ EVM_INS_NOT, "not" },
+	{ EVM_INS_BYTE, "byte" },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_SHA3, "sha3" },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_ADDRESS, "address" },
+	{ EVM_INS_BALANCE, "balance" },
+	{ EVM_INS_ORIGIN, "origin" },
+	{ EVM_INS_CALLER, "caller" },
+	{ EVM_INS_CALLVALUE, "callvalue" },
+	{ EVM_INS_CALLDATALOAD, "calldataload" },
+	{ EVM_INS_CALLDATASIZE, "calldatasize" },
+	{ EVM_INS_CALLDATACOPY, "calldatacopy" },
+	{ EVM_INS_CODESIZE, "codesize" },
+	{ EVM_INS_CODECOPY, "codecopy" },
+	{ EVM_INS_GASPRICE, "gasprice" },
+	{ EVM_INS_EXTCODESIZE, "extcodesize" },
+	{ EVM_INS_EXTCODECOPY, "extcodecopy" },
+	{ EVM_INS_RETURNDATASIZE, "returndatasize" },
+	{ EVM_INS_RETURNDATACOPY, "returndatacopy" },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_BLOCKHASH, "blockhash" },
+	{ EVM_INS_COINBASE, "coinbase" },
+	{ EVM_INS_TIMESTAMP, "timestamp" },
+	{ EVM_INS_NUMBER, "number" },
+	{ EVM_INS_DIFFICULTY, "difficulty" },
+	{ EVM_INS_GASLIMIT, "gaslimit" },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_POP, "pop" },
+	{ EVM_INS_MLOAD, "mload" },
+	{ EVM_INS_MSTORE, "mstore" },
+	{ EVM_INS_MSTORE8, "mstore8" },
+	{ EVM_INS_SLOAD, "sload" },
+	{ EVM_INS_SSTORE, "sstore" },
+	{ EVM_INS_JUMP, "jump" },
+	{ EVM_INS_JUMPI, "jumpi" },
+	{ EVM_INS_PC, "pc" },
+	{ EVM_INS_MSIZE, "msize" },
+	{ EVM_INS_GAS, "gas" },
+	{ EVM_INS_JUMPDEST, "jumpdest" },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_PUSH1, "push1" },
+	{ EVM_INS_PUSH2, "push2" },
+	{ EVM_INS_PUSH3, "push3" },
+	{ EVM_INS_PUSH4, "push4" },
+	{ EVM_INS_PUSH5, "push5" },
+	{ EVM_INS_PUSH6, "push6" },
+	{ EVM_INS_PUSH7, "push7" },
+	{ EVM_INS_PUSH8, "push8" },
+	{ EVM_INS_PUSH9, "push9" },
+	{ EVM_INS_PUSH10, "push10" },
+	{ EVM_INS_PUSH11, "push11" },
+	{ EVM_INS_PUSH12, "push12" },
+	{ EVM_INS_PUSH13, "push13" },
+	{ EVM_INS_PUSH14, "push14" },
+	{ EVM_INS_PUSH15, "push15" },
+	{ EVM_INS_PUSH16, "push16" },
+	{ EVM_INS_PUSH17, "push17" },
+	{ EVM_INS_PUSH18, "push18" },
+	{ EVM_INS_PUSH19, "push19" },
+	{ EVM_INS_PUSH20, "push20" },
+	{ EVM_INS_PUSH21, "push21" },
+	{ EVM_INS_PUSH22, "push22" },
+	{ EVM_INS_PUSH23, "push23" },
+	{ EVM_INS_PUSH24, "push24" },
+	{ EVM_INS_PUSH25, "push25" },
+	{ EVM_INS_PUSH26, "push26" },
+	{ EVM_INS_PUSH27, "push27" },
+	{ EVM_INS_PUSH28, "push28" },
+	{ EVM_INS_PUSH29, "push29" },
+	{ EVM_INS_PUSH30, "push30" },
+	{ EVM_INS_PUSH31, "push31" },
+	{ EVM_INS_PUSH32, "push32" },
+	{ EVM_INS_DUP1, "dup1" },
+	{ EVM_INS_DUP2, "dup2" },
+	{ EVM_INS_DUP3, "dup3" },
+	{ EVM_INS_DUP4, "dup4" },
+	{ EVM_INS_DUP5, "dup5" },
+	{ EVM_INS_DUP6, "dup6" },
+	{ EVM_INS_DUP7, "dup7" },
+	{ EVM_INS_DUP8, "dup8" },
+	{ EVM_INS_DUP9, "dup9" },
+	{ EVM_INS_DUP10, "dup10" },
+	{ EVM_INS_DUP11, "dup11" },
+	{ EVM_INS_DUP12, "dup12" },
+	{ EVM_INS_DUP13, "dup13" },
+	{ EVM_INS_DUP14, "dup14" },
+	{ EVM_INS_DUP15, "dup15" },
+	{ EVM_INS_DUP16, "dup16" },
+	{ EVM_INS_SWAP1, "swap1" },
+	{ EVM_INS_SWAP2, "swap2" },
+	{ EVM_INS_SWAP3, "swap3" },
+	{ EVM_INS_SWAP4, "swap4" },
+	{ EVM_INS_SWAP5, "swap5" },
+	{ EVM_INS_SWAP6, "swap6" },
+	{ EVM_INS_SWAP7, "swap7" },
+	{ EVM_INS_SWAP8, "swap8" },
+	{ EVM_INS_SWAP9, "swap9" },
+	{ EVM_INS_SWAP10, "swap10" },
+	{ EVM_INS_SWAP11, "swap11" },
+	{ EVM_INS_SWAP12, "swap12" },
+	{ EVM_INS_SWAP13, "swap13" },
+	{ EVM_INS_SWAP14, "swap14" },
+	{ EVM_INS_SWAP15, "swap15" },
+	{ EVM_INS_SWAP16, "swap16" },
+	{ EVM_INS_LOG0, "log0" },
+	{ EVM_INS_LOG1, "log1" },
+	{ EVM_INS_LOG2, "log2" },
+	{ EVM_INS_LOG3, "log3" },
+	{ EVM_INS_LOG4, "log4" },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_CREATE, "create" },
+	{ EVM_INS_CALL, "call" },
+	{ EVM_INS_CALLCODE, "callcode" },
+	{ EVM_INS_RETURN, "return" },
+	{ EVM_INS_DELEGATECALL, "delegatecall" },
+	{ EVM_INS_CALLBLACKBOX, "callblackbox" },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_STATICCALL, "staticcall" },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_REVERT, "revert" },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_SUICIDE, "suicide" },
+};
+#endif
+
+const char *EVM_insn_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	if (id >= ARR_SIZE(insn_name_maps))
+		return NULL;
+	else
+		return insn_name_maps[id].name;
+#else
+	return NULL;
+#endif
+}
+
+#ifndef CAPSTONE_DIET
+static const name_map group_name_maps[] = {
+	// generic groups
+	{ EVM_GRP_INVALID, NULL },
+	{ EVM_GRP_JUMP,	"jump" },
+	// special groups
+	{ EVM_GRP_MATH,	"math" },
+	{ EVM_GRP_STACK_WRITE, "stack_write" },
+	{ EVM_GRP_STACK_READ, "stack_read" },
+	{ EVM_GRP_MEM_WRITE, "mem_write" },
+	{ EVM_GRP_MEM_READ, "mem_read" },
+	{ EVM_GRP_STORE_WRITE, "store_write" },
+	{ EVM_GRP_STORE_READ, "store_read" },
+	{ EVM_GRP_HALT, "halt" },
+};
+#endif
+
+const char *EVM_group_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
+#else
+	return NULL;
+#endif
+}
+#endif

thirdparty/capstone/arch/EVM/EVMMapping.h

@@ -0,0 +1,8 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh, 2018 */
+
+#include <capstone/capstone.h>
+
+void EVM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
+const char *EVM_insn_name(csh handle, unsigned int id);
+const char *EVM_group_name(csh handle, unsigned int id);

thirdparty/capstone/arch/EVM/EVMMappingInsn.inc

@@ -0,0 +1,259 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh, 2018 */
+
+{ 0, 0, 0 }, // STOP
+{ 2, 1, 3 }, // ADD
+{ 2, 1, 5 }, // MUL
+{ 2, 1, 3 }, // SUB
+{ 2, 1, 5 }, // DIV
+{ 2, 1, 5 }, // SDIV
+{ 2, 1, 5 }, // MOD
+{ 2, 1, 5 }, // SMOD
+{ 3, 1, 8 }, // ADDMOD
+{ 3, 1, 8 }, // MULMOD
+{ 2, 1, 10 }, // EXP
+{ 2, 1, 5 }, // SIGNEXTEND
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 2, 1, 3 }, // LT
+{ 2, 1, 3 }, // GT
+{ 2, 1, 3 }, // SLT
+{ 2, 1, 3 }, // SGT
+{ 2, 1, 3 }, // EQ
+{ 1, 1, 3 }, // ISZERO
+{ 2, 1, 3 }, // AND
+{ 2, 1, 3 }, // OR
+{ 2, 1, 3 }, // XOR
+{ 1, 1, 3 }, // NOT
+{ 2, 1, 3 }, // BYTE
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 2, 1, 30 }, // SHA3
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 1, 2 }, // ADDRESS
+{ 1, 1, 20 }, // BALANCE
+{ 0, 1, 2 }, // ORIGIN
+{ 0, 1, 2 }, // CALLER
+{ 0, 1, 2 }, // CALLVALUE
+{ 1, 1, 3 }, // CALLDATALOAD
+{ 0, 1, 2 }, // CALLDATASIZE
+{ 3, 0, 3 }, // CALLDATACOPY
+{ 0, 1, 2 }, // CODESIZE
+{ 3, 0, 3 }, // CODECOPY
+{ 0, 1, 2 }, // GASPRICE
+{ 1, 1, 20 }, // EXTCODESIZE
+{ 4, 0, 20 }, // EXTCODECOPY
+{ 0, 1, 2 }, // RETURNDATASIZE
+{ 3, 0, 3 }, // RETURNDATACOPY
+{ 0, 0, 0xffffffff }, // unused
+{ 1, 1, 20 }, // BLOCKHASH
+{ 0, 1, 2 }, // COINBASE
+{ 0, 1, 2 }, // TIMESTAMP
+{ 0, 1, 2 }, // NUMBER
+{ 0, 1, 2 }, // DIFFICULTY
+{ 0, 1, 2 }, // GASLIMIT
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 1, 0, 2 }, // POP
+{ 1, 1, 3 }, // MLOAD
+{ 2, 0, 3 }, // MSTORE
+{ 2, 0, 3 }, // MSTORE8
+{ 1, 1, 50 }, // SLOAD
+{ 2, 0, 0 }, // SSTORE
+{ 1, 0, 8 }, // JUMP
+{ 2, 0, 10 }, // JUMPI
+{ 0, 1, 2 }, // GETPC
+{ 0, 1, 2 }, // MSIZE
+{ 0, 1, 2 }, // GAS
+{ 0, 0, 1 }, // JUMPDEST
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 1, 3 }, // PUSH1
+{ 0, 1, 3 }, // PUSH2
+{ 0, 1, 3 }, // PUSH3
+{ 0, 1, 3 }, // PUSH4
+{ 0, 1, 3 }, // PUSH5
+{ 0, 1, 3 }, // PUSH6
+{ 0, 1, 3 }, // PUSH7
+{ 0, 1, 3 }, // PUSH8
+{ 0, 1, 3 }, // PUSH9
+{ 0, 1, 3 }, // PUSH10
+{ 0, 1, 3 }, // PUSH11
+{ 0, 1, 3 }, // PUSH12
+{ 0, 1, 3 }, // PUSH13
+{ 0, 1, 3 }, // PUSH14
+{ 0, 1, 3 }, // PUSH15
+{ 0, 1, 3 }, // PUSH16
+{ 0, 1, 3 }, // PUSH17
+{ 0, 1, 3 }, // PUSH18
+{ 0, 1, 3 }, // PUSH19
+{ 0, 1, 3 }, // PUSH20
+{ 0, 1, 3 }, // PUSH21
+{ 0, 1, 3 }, // PUSH22
+{ 0, 1, 3 }, // PUSH23
+{ 0, 1, 3 }, // PUSH24
+{ 0, 1, 3 }, // PUSH25
+{ 0, 1, 3 }, // PUSH26
+{ 0, 1, 3 }, // PUSH27
+{ 0, 1, 3 }, // PUSH28
+{ 0, 1, 3 }, // PUSH29
+{ 0, 1, 3 }, // PUSH30
+{ 0, 1, 3 }, // PUSH31
+{ 0, 1, 3 }, // PUSH32
+{ 1, 2, 3 }, // DUP1
+{ 2, 3, 3 }, // DUP2
+{ 3, 4, 3 }, // DUP3
+{ 4, 5, 3 }, // DUP4
+{ 5, 6, 3 }, // DUP5
+{ 6, 7, 3 }, // DUP6
+{ 7, 8, 3 }, // DUP7
+{ 8, 9, 3 }, // DUP8
+{ 9, 10, 3 }, // DUP9
+{ 10, 11, 3 }, // DUP10
+{ 11, 12, 3 }, // DUP11
+{ 12, 13, 3 }, // DUP12
+{ 13, 14, 3 }, // DUP13
+{ 14, 15, 3 }, // DUP14
+{ 15, 16, 3 }, // DUP15
+{ 16, 17, 3 }, // DUP16
+{ 2, 2, 3 }, // SWAP1
+{ 3, 3, 3 }, // SWAP2
+{ 4, 4, 3 }, // SWAP3
+{ 5, 5, 3 }, // SWAP4
+{ 6, 6, 3 }, // SWAP5
+{ 7, 7, 3 }, // SWAP6
+{ 8, 8, 3 }, // SWAP7
+{ 9, 9, 3 }, // SWAP8
+{ 10, 10, 3 }, // SWAP9
+{ 11, 11, 3 }, // SWAP10
+{ 12, 12, 3 }, // SWAP11
+{ 13, 13, 3 }, // SWAP12
+{ 14, 14, 3 }, // SWAP13
+{ 15, 15, 3 }, // SWAP14
+{ 16, 16, 3 }, // SWAP15
+{ 17, 17, 3 }, // SWAP16
+{ 2, 0, 375 }, // LOG0
+{ 3, 0, 750 }, // LOG1
+{ 4, 0, 1125 }, // LOG2
+{ 5, 0, 1500 }, // LOG3
+{ 6, 0, 1875 }, // LOG4
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 3, 1, 32000 }, // CREATE
+{ 7, 1, 40 }, // CALL
+{ 7, 1, 40 }, // CALLCODE
+{ 2, 0, 0 }, // RETURN
+{ 6, 1, 40 }, // DELEGATECALL
+{ 7, 1, 40 }, // CALLBLACKBOX
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 6, 1, 40 }, // STATICCALL
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 2, 0, 0 }, // REVERT
+{ 0, 0, 0xffffffff }, // unused
+{ 1, 0, 0 }, // SUICIDE

thirdparty/capstone/arch/EVM/EVMModule.c

@@ -0,0 +1,33 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh, 2018 */
+
+#ifdef CAPSTONE_HAS_EVM
+
+#include "../../cs_priv.h"
+#include "EVMDisassembler.h"
+#include "EVMInstPrinter.h"
+#include "EVMMapping.h"
+#include "EVMModule.h"
+
+cs_err EVM_global_init(cs_struct *ud)
+{
+	// verify if requested mode is valid
+	if (ud->mode)
+		return CS_ERR_MODE;
+
+	ud->printer = EVM_printInst;
+	ud->printer_info = NULL;
+	ud->insn_id = EVM_get_insn_id;
+	ud->insn_name = EVM_insn_name;
+	ud->group_name = EVM_group_name;
+	ud->disasm = EVM_getInstruction;
+
+	return CS_ERR_OK;
+}
+
+cs_err EVM_option(cs_struct *handle, cs_opt_type type, size_t value)
+{
+	return CS_ERR_OK;
+}
+
+#endif

thirdparty/capstone/arch/EVM/EVMModule.h

@@ -0,0 +1,12 @@
+/* Capstone Disassembly Engine */
+/* By Travis Finkenauer <tmfinken@gmail.com>, 2018 */
+
+#ifndef CS_EVM_MODULE_H
+#define CS_EVM_MODULE_H
+
+#include "../../utils.h"
+
+cs_err EVM_global_init(cs_struct *ud);
+cs_err EVM_option(cs_struct *handle, cs_opt_type type, size_t value);
+
+#endif

thirdparty/capstone/arch/HPPA/HPPAConstants.h

@@ -0,0 +1,74 @@
+/* Capstone Disassembly Engine */
+/* By Dmitry Sibirtsev  <sibirtsevdl@gmail.com>, 2023 */
+
+/* This file defines constants and macros used for parsing a HPPA instruction */
+
+#ifndef CS_HPPA_CONSTANTS_H
+#define CS_HPPA_CONSTANTS_H
+
+#define HPPA_OP_TYPE(byte) (byte) >> 2
+#define MODE_IS_HPPA_20(mode) (((mode)&CS_MODE_HPPA_20) != 0)
+#define MODE_IS_HPPA_20W(mode) (((mode) & (1 << 3)) != 0)
+
+///> HPPA opcode types
+#define HPPA_OP_TYPE_SYSOP 0x00
+#define HPPA_OP_TYPE_MEMMGMT 0x01
+#define HPPA_OP_TYPE_ALU 0x02
+#define HPPA_OP_TYPE_IDXMEM 0x03
+#define HPPA_OP_TYPE_SPOP 0x04
+#define HPPA_OP_TYPE_DIAG 0x05
+#define HPPA_OP_TYPE_FMPYADD 0x06
+#define HPPA_OP_TYPE_LDIL 0x08
+#define HPPA_OP_TYPE_COPRW 0x09
+#define HPPA_OP_TYPE_ADDIL 0x0a
+#define HPPA_OP_TYPE_COPRDW 0x0b
+#define HPPA_OP_TYPE_COPR 0x0c
+#define HPPA_OP_TYPE_LDO 0x0d
+#define HPPA_OP_TYPE_FLOAT 0x0e
+#define HPPA_OP_TYPE_PRDSPEC 0x0f
+#define HPPA_OP_TYPE_LDB 0x10
+#define HPPA_OP_TYPE_LDH 0x11
+#define HPPA_OP_TYPE_LDW 0x12
+#define HPPA_OP_TYPE_LDWM 0x13
+#define HPPA_OP_TYPE_LOADDW 0x14
+#define HPPA_OP_TYPE_FLDW 0x16
+#define HPPA_OP_TYPE_LOADW 0x17
+#define HPPA_OP_TYPE_STB 0x18
+#define HPPA_OP_TYPE_STH 0x19
+#define HPPA_OP_TYPE_STW 0x1a
+#define HPPA_OP_TYPE_STWM 0x1b
+#define HPPA_OP_TYPE_STOREDW 0x1c
+#define HPPA_OP_TYPE_FSTW 0x1e
+#define HPPA_OP_TYPE_STOREW 0x1f
+#define HPPA_OP_TYPE_CMPBT 0x20
+#define HPPA_OP_TYPE_CMPIBT 0x21
+#define HPPA_OP_TYPE_CMPBF 0x22
+#define HPPA_OP_TYPE_CMPIBF 0x23
+#define HPPA_OP_TYPE_CMPICLR 0x24
+#define HPPA_OP_TYPE_SUBI 0x25
+#define HPPA_OP_TYPE_FMPYSUB 0x26
+#define HPPA_OP_TYPE_CMPBDWT 0x27
+#define HPPA_OP_TYPE_ADDBT 0x28
+#define HPPA_OP_TYPE_ADDIBT 0x29
+#define HPPA_OP_TYPE_ADDBF 0x2a
+#define HPPA_OP_TYPE_ADDIBF 0x2b
+#define HPPA_OP_TYPE_ADDIT 0x2c
+#define HPPA_OP_TYPE_ADDI 0x2d
+#define HPPA_OP_TYPE_FPFUSED 0x2e
+#define HPPA_OP_TYPE_CMPBDWF 0x2f
+#define HPPA_OP_TYPE_BBS 0x30
+#define HPPA_OP_TYPE_BB 0x31
+#define HPPA_OP_TYPE_MOVB 0x32
+#define HPPA_OP_TYPE_MOVIB 0x33
+#define HPPA_OP_TYPE_SHEXDEP0 0x34
+#define HPPA_OP_TYPE_SHEXDEP1 0x35
+#define HPPA_OP_TYPE_SHEXDEP2 0x36
+#define HPPA_OP_TYPE_BE 0x38
+#define HPPA_OP_TYPE_BLE 0x39
+#define HPPA_OP_TYPE_BRANCH 0x3a
+#define HPPA_OP_TYPE_CMPIBDW 0x3b
+#define HPPA_OP_TYPE_SHEXDEP3 0x3c
+#define HPPA_OP_TYPE_SHEXDEP4 0x3d
+#define HPPA_OP_TYPE_MULTMED 0x3e
+
+#endif // CS_HPPA_CONSTANTS_H

thirdparty/capstone/arch/HPPA/HPPADisassembler.h

@@ -0,0 +1,13 @@
+/* Capstone Disassembly Engine */
+/* By Dmitry Sibirtsev  <sibirtsevdl@gmail.com>, 2023 */
+
+#ifndef CS_HPPA_DISASSEMBLER_H
+#define CS_HPPA_DISASSEMBLER_H
+
+#include "../../MCInst.h"
+
+bool HPPA_getInstruction(csh ud, const uint8_t *code, size_t code_len,
+			 MCInst *instr, uint16_t *size, uint64_t address,
+			 void *info);
+
+#endif

thirdparty/capstone/arch/HPPA/HPPAInstPrinter.c

@@ -0,0 +1,839 @@
+/* Capstone Disassembly Engine */
+/* By Dmitry Sibirtsev  <sibirtsevdl@gmail.com>, 2023 */
+
+#ifdef CAPSTONE_HAS_HPPA
+
+#include <capstone/platform.h>
+#include "../../Mapping.h"
+#include "../../utils.h"
+
+#include "HPPAInstPrinter.h"
+#include "HPPAMapping.h"
+
+static const struct pa_insn pa_insns[] = {
+	{ HPPA_INS_LDI, HPPA_GRP_LONG_IMM },
+	{ HPPA_INS_CMPIB, HPPA_GRP_BRANCH },
+	{ HPPA_INS_COMIB, HPPA_GRP_BRANCH },
+	{ HPPA_INS_CMPB, HPPA_GRP_BRANCH },
+	{ HPPA_INS_COMB, HPPA_GRP_BRANCH },
+	{ HPPA_INS_ADDB, HPPA_GRP_BRANCH },
+	{ HPPA_INS_ADDIB, HPPA_GRP_BRANCH },
+	{ HPPA_INS_NOP, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_COPY, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_MTSAR, HPPA_GRP_SYSCTRL },
+	{ HPPA_INS_LDD, HPPA_GRP_MEM_REF },
+	{ HPPA_INS_LDW, HPPA_GRP_MEM_REF },
+	{ HPPA_INS_LDH, HPPA_GRP_MEM_REF },
+	{ HPPA_INS_LDB, HPPA_GRP_MEM_REF },
+	{ HPPA_INS_STD, HPPA_GRP_MEM_REF },
+	{ HPPA_INS_STW, HPPA_GRP_MEM_REF },
+	{ HPPA_INS_STH, HPPA_GRP_MEM_REF },
+	{ HPPA_INS_STB, HPPA_GRP_MEM_REF },
+	{ HPPA_INS_LDWM, HPPA_GRP_MEM_REF },
+	{ HPPA_INS_STWM, HPPA_GRP_MEM_REF },
+	{ HPPA_INS_LDWX, HPPA_GRP_MEM_REF },
+	{ HPPA_INS_LDHX, HPPA_GRP_MEM_REF },
+	{ HPPA_INS_LDBX, HPPA_GRP_MEM_REF },
+	{ HPPA_INS_LDWA, HPPA_GRP_MEM_REF },
+	{ HPPA_INS_LDCW, HPPA_GRP_MEM_REF },
+	{ HPPA_INS_STWA, HPPA_GRP_MEM_REF },
+	{ HPPA_INS_STBY, HPPA_GRP_MEM_REF },
+	{ HPPA_INS_LDDA, HPPA_GRP_MEM_REF },
+	{ HPPA_INS_LDCD, HPPA_GRP_MEM_REF },
+	{ HPPA_INS_STDA, HPPA_GRP_MEM_REF },
+	{ HPPA_INS_LDWAX, HPPA_GRP_MEM_REF },
+	{ HPPA_INS_LDCWX, HPPA_GRP_MEM_REF },
+	{ HPPA_INS_LDWS, HPPA_GRP_MEM_REF },
+	{ HPPA_INS_LDHS, HPPA_GRP_MEM_REF },
+	{ HPPA_INS_LDBS, HPPA_GRP_MEM_REF },
+	{ HPPA_INS_LDWAS, HPPA_GRP_MEM_REF },
+	{ HPPA_INS_LDCWS, HPPA_GRP_MEM_REF },
+	{ HPPA_INS_STWS, HPPA_GRP_MEM_REF },
+	{ HPPA_INS_STHS, HPPA_GRP_MEM_REF },
+	{ HPPA_INS_STBS, HPPA_GRP_MEM_REF },
+	{ HPPA_INS_STWAS, HPPA_GRP_MEM_REF },
+	{ HPPA_INS_STDBY, HPPA_GRP_MEM_REF },
+	{ HPPA_INS_STBYS, HPPA_GRP_MEM_REF },
+	{ HPPA_INS_LDO, HPPA_GRP_LONG_IMM },
+	{ HPPA_INS_LDIL, HPPA_GRP_LONG_IMM },
+	{ HPPA_INS_ADDIL, HPPA_GRP_LONG_IMM },
+	{ HPPA_INS_B, HPPA_GRP_BRANCH },
+	{ HPPA_INS_BL, HPPA_GRP_BRANCH },
+	{ HPPA_INS_GATE, HPPA_GRP_BRANCH },
+	{ HPPA_INS_BLR, HPPA_GRP_BRANCH },
+	{ HPPA_INS_BV, HPPA_GRP_BRANCH },
+	{ HPPA_INS_BVE, HPPA_GRP_BRANCH },
+	{ HPPA_INS_BE, HPPA_GRP_BRANCH },
+	{ HPPA_INS_BLE, HPPA_GRP_BRANCH },
+	{ HPPA_INS_MOVB, HPPA_GRP_BRANCH },
+	{ HPPA_INS_MOVIB, HPPA_GRP_BRANCH },
+	{ HPPA_INS_COMBT, HPPA_GRP_BRANCH },
+	{ HPPA_INS_COMBF, HPPA_GRP_BRANCH },
+	{ HPPA_INS_COMIBT, HPPA_GRP_BRANCH },
+	{ HPPA_INS_COMIBF, HPPA_GRP_BRANCH },
+	{ HPPA_INS_ADDBT, HPPA_GRP_BRANCH },
+	{ HPPA_INS_ADDBF, HPPA_GRP_BRANCH },
+	{ HPPA_INS_ADDIBT, HPPA_GRP_BRANCH },
+	{ HPPA_INS_ADDIBF, HPPA_GRP_BRANCH },
+	{ HPPA_INS_BB, HPPA_GRP_BRANCH },
+	{ HPPA_INS_BVB, HPPA_GRP_BRANCH },
+	{ HPPA_INS_CLRBTS, HPPA_GRP_BRANCH },
+	{ HPPA_INS_POPBTS, HPPA_GRP_BRANCH },
+	{ HPPA_INS_PUSHNOM, HPPA_GRP_BRANCH },
+	{ HPPA_INS_PUSHBTS, HPPA_GRP_BRANCH },
+	{ HPPA_INS_CMPCLR, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_COMCLR, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_OR, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_XOR, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_AND, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_ANDCM, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_UXOR, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_UADDCM, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_UADDCMT, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_DCOR, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_IDCOR, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_ADDI, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_ADDIO, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_ADDIT, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_ADDITO, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_ADD, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_ADDL, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_ADDO, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_ADDC, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_ADDCO, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_SUB, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_SUBO, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_SUBB, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_SUBBO, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_SUBT, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_SUBTO, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_DS, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_SUBI, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_SUBIO, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_CMPICLR, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_COMICLR, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_SHLADD, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_SH1ADD, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_SH1ADDL, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_SH1ADDO, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_SH2ADD, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_SH2ADDL, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_SH2ADDO, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_SH3ADD, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_SH3ADDL, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_SH3ADDO, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_HADD, HPPA_GRP_MULTIMEDIA },
+	{ HPPA_INS_HAVG, HPPA_GRP_MULTIMEDIA },
+	{ HPPA_INS_HSHL, HPPA_GRP_MULTIMEDIA },
+	{ HPPA_INS_HSHLADD, HPPA_GRP_MULTIMEDIA },
+	{ HPPA_INS_HSHR, HPPA_GRP_MULTIMEDIA },
+	{ HPPA_INS_HSHRADD, HPPA_GRP_MULTIMEDIA },
+	{ HPPA_INS_HSUB, HPPA_GRP_MULTIMEDIA },
+	{ HPPA_INS_MIXH, HPPA_GRP_MULTIMEDIA },
+	{ HPPA_INS_MIXW, HPPA_GRP_MULTIMEDIA },
+	{ HPPA_INS_PERMH, HPPA_GRP_MULTIMEDIA },
+	{ HPPA_INS_SHRPD, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_SHRPW, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_VSHD, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_SHD, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_EXTRD, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_EXTRW, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_VEXTRU, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_VEXTRS, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_EXTRU, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_EXTRS, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_DEPD, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_DEPDI, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_DEPW, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_DEPWI, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_ZVDEP, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_VDEP, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_ZDEP, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_DEP, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_ZVDEPI, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_VDEPI, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_ZDEPI, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_DEPI, HPPA_GRP_COMPUTATION },
+	{ HPPA_INS_BREAK, HPPA_GRP_SYSCTRL },
+	{ HPPA_INS_RFI, HPPA_GRP_SYSCTRL },
+	{ HPPA_INS_RFIR, HPPA_GRP_SYSCTRL },
+	{ HPPA_INS_SSM, HPPA_GRP_SYSCTRL },
+	{ HPPA_INS_RSM, HPPA_GRP_SYSCTRL },
+	{ HPPA_INS_MTSM, HPPA_GRP_SYSCTRL },
+	{ HPPA_INS_LDSID, HPPA_GRP_SYSCTRL },
+	{ HPPA_INS_MTSP, HPPA_GRP_SYSCTRL },
+	{ HPPA_INS_MTCTL, HPPA_GRP_SYSCTRL },
+	{ HPPA_INS_MTSARCM, HPPA_GRP_SYSCTRL },
+	{ HPPA_INS_MFIA, HPPA_GRP_SYSCTRL },
+	{ HPPA_INS_MFSP, HPPA_GRP_SYSCTRL },
+	{ HPPA_INS_MFCTL, HPPA_GRP_SYSCTRL },
+	{ HPPA_INS_SYNC, HPPA_GRP_SYSCTRL },
+	{ HPPA_INS_SYNCDMA, HPPA_GRP_SYSCTRL },
+	{ HPPA_INS_PROBE, HPPA_GRP_SYSCTRL },
+	{ HPPA_INS_PROBEI, HPPA_GRP_SYSCTRL },
+	{ HPPA_INS_PROBER, HPPA_GRP_SYSCTRL },
+	{ HPPA_INS_PROBERI, HPPA_GRP_SYSCTRL },
+	{ HPPA_INS_PROBEW, HPPA_GRP_SYSCTRL },
+	{ HPPA_INS_PROBEWI, HPPA_GRP_SYSCTRL },
+	{ HPPA_INS_LPA, HPPA_GRP_SYSCTRL },
+	{ HPPA_INS_LCI, HPPA_GRP_SYSCTRL },
+	{ HPPA_INS_PDTLB, HPPA_GRP_SYSCTRL },
+	{ HPPA_INS_PITLB, HPPA_GRP_SYSCTRL },
+	{ HPPA_INS_PDTLBE, HPPA_GRP_SYSCTRL },
+	{ HPPA_INS_PITLBE, HPPA_GRP_SYSCTRL },
+	{ HPPA_INS_IDTLBA, HPPA_GRP_SYSCTRL },
+	{ HPPA_INS_IITLBA, HPPA_GRP_SYSCTRL },
+	{ HPPA_INS_IDTLBP, HPPA_GRP_SYSCTRL },
+	{ HPPA_INS_IITLBP, HPPA_GRP_SYSCTRL },
+	{ HPPA_INS_PDC, HPPA_GRP_SYSCTRL },
+	{ HPPA_INS_FDC, HPPA_GRP_SYSCTRL },
+	{ HPPA_INS_FIC, HPPA_GRP_SYSCTRL },
+	{ HPPA_INS_FDCE, HPPA_GRP_SYSCTRL },
+	{ HPPA_INS_FICE, HPPA_GRP_SYSCTRL },
+	{ HPPA_INS_DIAG, HPPA_GRP_SYSCTRL },
+	{ HPPA_INS_IDTLBT, HPPA_GRP_SYSCTRL },
+	{ HPPA_INS_IITLBT, HPPA_GRP_SYSCTRL },
+	{ HPPA_INS_MTCPU, HPPA_GRP_SYSCTRL },
+	{ HPPA_INS_MFCPU, HPPA_GRP_SYSCTRL },
+	{ HPPA_INS_TOCEN, HPPA_GRP_SYSCTRL },
+	{ HPPA_INS_TOCDIS, HPPA_GRP_SYSCTRL },
+	{ HPPA_INS_SHDWGR, HPPA_GRP_SYSCTRL },
+	{ HPPA_INS_GRSHDW, HPPA_GRP_SYSCTRL },
+	{ HPPA_INS_GFW, HPPA_GRP_SYSCTRL },
+	{ HPPA_INS_GFR, HPPA_GRP_SYSCTRL },
+	{ HPPA_INS_FLDW, HPPA_GRP_FLOAT },
+	{ HPPA_INS_FLDD, HPPA_GRP_FLOAT },
+	{ HPPA_INS_FSTW, HPPA_GRP_FLOAT },
+	{ HPPA_INS_FSTD, HPPA_GRP_FLOAT },
+	{ HPPA_INS_FLDWX, HPPA_GRP_FLOAT },
+	{ HPPA_INS_FLDDX, HPPA_GRP_FLOAT },
+	{ HPPA_INS_FSTWX, HPPA_GRP_FLOAT },
+	{ HPPA_INS_FSTDX, HPPA_GRP_FLOAT },
+	{ HPPA_INS_FSTQX, HPPA_GRP_FLOAT },
+	{ HPPA_INS_FLDWS, HPPA_GRP_FLOAT },
+	{ HPPA_INS_FLDDS, HPPA_GRP_FLOAT },
+	{ HPPA_INS_FSTWS, HPPA_GRP_FLOAT },
+	{ HPPA_INS_FSTDS, HPPA_GRP_FLOAT },
+	{ HPPA_INS_FSTQS, HPPA_GRP_FLOAT },
+	{ HPPA_INS_FADD, HPPA_GRP_FLOAT },
+	{ HPPA_INS_FSUB, HPPA_GRP_FLOAT },
+	{ HPPA_INS_FMPY, HPPA_GRP_FLOAT },
+	{ HPPA_INS_FDIV, HPPA_GRP_FLOAT },
+	{ HPPA_INS_FSQRT, HPPA_GRP_FLOAT },
+	{ HPPA_INS_FABS, HPPA_GRP_FLOAT },
+	{ HPPA_INS_FREM, HPPA_GRP_FLOAT },
+	{ HPPA_INS_FRND, HPPA_GRP_FLOAT },
+	{ HPPA_INS_FCPY, HPPA_GRP_FLOAT },
+	{ HPPA_INS_FCNVFF, HPPA_GRP_FLOAT },
+	{ HPPA_INS_FCNVXF, HPPA_GRP_FLOAT },
+	{ HPPA_INS_FCNVFX, HPPA_GRP_FLOAT },
+	{ HPPA_INS_FCNVFXT, HPPA_GRP_FLOAT },
+	{ HPPA_INS_FMPYFADD, HPPA_GRP_FLOAT },
+	{ HPPA_INS_FMPYNFADD, HPPA_GRP_FLOAT },
+	{ HPPA_INS_FNEG, HPPA_GRP_FLOAT },
+	{ HPPA_INS_FNEGABS, HPPA_GRP_FLOAT },
+	{ HPPA_INS_FCNV, HPPA_GRP_FLOAT },
+	{ HPPA_INS_FCMP, HPPA_GRP_FLOAT },
+	{ HPPA_INS_XMPYU, HPPA_GRP_FLOAT },
+	{ HPPA_INS_FMPYADD, HPPA_GRP_FLOAT },
+	{ HPPA_INS_FMPYSUB, HPPA_GRP_FLOAT },
+	{ HPPA_INS_FTEST, HPPA_GRP_FLOAT },
+	{ HPPA_INS_FID, HPPA_GRP_FLOAT },
+	{ HPPA_INS_PMDIS, HPPA_GRP_PERFMON },
+	{ HPPA_INS_PMENB, HPPA_GRP_PERFMON },
+	{ HPPA_INS_SPOP0, HPPA_GRP_ASSIST },
+	{ HPPA_INS_SPOP1, HPPA_GRP_ASSIST },
+	{ HPPA_INS_SPOP2, HPPA_GRP_ASSIST },
+	{ HPPA_INS_SPOP3, HPPA_GRP_ASSIST },
+	{ HPPA_INS_COPR, HPPA_GRP_ASSIST },
+	{ HPPA_INS_CLDW, HPPA_GRP_ASSIST },
+	{ HPPA_INS_CLDD, HPPA_GRP_ASSIST },
+	{ HPPA_INS_CSTW, HPPA_GRP_ASSIST },
+	{ HPPA_INS_CSTD, HPPA_GRP_ASSIST },
+	{ HPPA_INS_CLDWX, HPPA_GRP_ASSIST },
+	{ HPPA_INS_CLDDX, HPPA_GRP_ASSIST },
+	{ HPPA_INS_CSTWX, HPPA_GRP_ASSIST },
+	{ HPPA_INS_CSTDX, HPPA_GRP_ASSIST },
+	{ HPPA_INS_CLDWS, HPPA_GRP_ASSIST },
+	{ HPPA_INS_CLDDS, HPPA_GRP_ASSIST },
+	{ HPPA_INS_CSTWS, HPPA_GRP_ASSIST },
+	{ HPPA_INS_CSTDS, HPPA_GRP_ASSIST },
+	{ HPPA_INS_CALL, HPPA_GRP_INVALID },
+	{ HPPA_INS_RET, HPPA_GRP_INVALID },
+};
+
+static void set_op_imm(cs_hppa *hppa, uint64_t val)
+{
+	cs_hppa_op *op = &hppa->operands[hppa->op_count++];
+	op->type = HPPA_OP_IMM;
+	op->imm = val;
+}
+
+static void set_op_reg(cs_hppa *hppa, uint64_t val, cs_ac_type access)
+{
+	cs_hppa_op *op = &hppa->operands[hppa->op_count++];
+	op->type = HPPA_OP_REG;
+	op->reg = val;
+	op->access = access;
+}
+
+static void set_op_idx_reg(cs_hppa *hppa, uint64_t reg)
+{
+	cs_hppa_op *op = &hppa->operands[hppa->op_count++];
+	op->type = HPPA_OP_IDX_REG;
+	op->reg = reg;
+	op->access = CS_AC_READ;
+}
+
+static void set_op_disp(cs_hppa *hppa, uint64_t val)
+{
+	cs_hppa_op *op = &hppa->operands[hppa->op_count++];
+	op->type = HPPA_OP_DISP;
+	op->imm = val;
+}
+
+static void set_op_target(cs_hppa *hppa, uint64_t val)
+{
+	cs_hppa_op *op = &hppa->operands[hppa->op_count++];
+	op->type = HPPA_OP_TARGET;
+	op->imm = val;
+}
+
+static void set_op_mem(cs_hppa *hppa, uint32_t base, uint32_t space,
+		       cs_ac_type base_access)
+{
+	cs_hppa_op *op = &hppa->operands[hppa->op_count++];
+	op->type = HPPA_OP_MEM;
+	op->mem.base = base;
+	op->mem.space = space;
+	op->mem.base_access = base_access;
+}
+/* HPPA instruction formats (access)
+   i - imm arguments
+   R - read access register
+   W - write access register
+   w - read + write access register
+   r - index register (read only)
+   T - offset (pc relative)
+   o - displacement (imm)
+   x - [r] or [o] defined by the operand kind
+   b - base register (may be writable in some cases)
+*/
+static const struct pa_insn_fmt pa_formats[] = {
+	{ HPPA_INS_LDI, "iW", false },
+
+	{ HPPA_INS_CMPIB, "iRT", false },
+	{ HPPA_INS_COMIB, "iRT", false },
+
+	{ HPPA_INS_CMPB, "RRT", false },
+	{ HPPA_INS_COMB, "RRT", false },
+
+	{ HPPA_INS_ADDB, "RwT", false },
+
+	{ HPPA_INS_ADDIB, "iwT", false },
+
+	{ HPPA_INS_NOP, "", false },
+	{ HPPA_INS_COPY, "RW", false },
+	{ HPPA_INS_MTSAR, "R", false },
+
+	{ HPPA_INS_LDD, "x(Rb)W", false },
+	{ HPPA_INS_LDW, "x(Rb)W", false },
+	{ HPPA_INS_LDH, "x(Rb)W", false },
+	{ HPPA_INS_LDB, "x(Rb)W", false },
+	{ HPPA_INS_STD, "Ro(Rb)", false },
+	{ HPPA_INS_STW, "Ro(Rb)", false },
+	{ HPPA_INS_STH, "Ro(Rb)", false },
+	{ HPPA_INS_STB, "Ro(Rb)", false },
+	{ HPPA_INS_LDWM, "o(Rw)W", false },
+	{ HPPA_INS_STWM, "Ro(Rw)", false },
+	{ HPPA_INS_LDWX, "r(Rb)W", false },
+	{ HPPA_INS_LDHX, "r(Rb)W", false },
+	{ HPPA_INS_LDBX, "r(Rb)W", false },
+	{ HPPA_INS_LDWA, "x(R)W", false },
+	{ HPPA_INS_LDCW, "x(Rb)W", false },
+	{ HPPA_INS_STWA, "Ro(b)", false },
+	{ HPPA_INS_STBY, "Ro(Rb)", false },
+	{ HPPA_INS_LDDA, "x(b)W", false },
+	{ HPPA_INS_LDCD, "x(Rb)W", false },
+	{ HPPA_INS_STDA, "Ro(b)", false },
+	{ HPPA_INS_LDWAX, "r(b)W", false },
+	{ HPPA_INS_LDCWX, "r(Rb)W", false },
+	{ HPPA_INS_LDWS, "o(Rb)W", false },
+	{ HPPA_INS_LDHS, "o(Rb)W", false },
+	{ HPPA_INS_LDBS, "o(Rb)W", false },
+	{ HPPA_INS_LDWAS, "o(b)W", false },
+	{ HPPA_INS_LDCWS, "o(Rb)W", false },
+	{ HPPA_INS_STWS, "Ro(Rb)", false },
+	{ HPPA_INS_STHS, "Ro(Rb)", false },
+	{ HPPA_INS_STBS, "Ro(Rb)", false },
+	{ HPPA_INS_STWAS, "Ro(b)", false },
+	{ HPPA_INS_STDBY, "Ro(Rb)", false },
+	{ HPPA_INS_STBYS, "Ro(Rb)", false },
+
+	{ HPPA_INS_LDO, "o(R)W", false },
+	{ HPPA_INS_LDIL, "iW", false },
+	{ HPPA_INS_ADDIL, "iR", false },
+
+	{ HPPA_INS_B, "TW", false },
+	{ HPPA_INS_BL, "TW", false },
+	{ HPPA_INS_GATE, "TW", false },
+	{ HPPA_INS_BLR, "RW", false },
+	{ HPPA_INS_BV, "x(R)", false },
+	{ HPPA_INS_BVE, "(b)", false },
+	{ HPPA_INS_BVE, "(b)W", true },
+	{ HPPA_INS_BE, "o(RR)", false },
+	{ HPPA_INS_BE, "o(RR)WW", true },
+	{ HPPA_INS_BLE, "o(RR)", false },
+	{ HPPA_INS_MOVB, "RWT", false },
+	{ HPPA_INS_MOVIB, "iWT", false },
+	{ HPPA_INS_COMBT, "RRT", false },
+	{ HPPA_INS_COMBF, "RRT", false },
+	{ HPPA_INS_COMIBT, "iRT", false },
+	{ HPPA_INS_COMIBF, "iRT", false },
+	{ HPPA_INS_ADDBT, "RwT", false },
+	{ HPPA_INS_ADDBF, "RwT", false },
+	{ HPPA_INS_ADDIBT, "iwT", false },
+	{ HPPA_INS_ADDIBF, "iwT", false },
+	{ HPPA_INS_BB, "RiT", false },
+	{ HPPA_INS_BVB, "RT", false },
+	{ HPPA_INS_CLRBTS, "", false },
+	{ HPPA_INS_POPBTS, "i", false },
+	{ HPPA_INS_PUSHNOM, "", false },
+	{ HPPA_INS_PUSHBTS, "R", false },
+
+	{ HPPA_INS_CMPCLR, "RRW", false },
+	{ HPPA_INS_COMCLR, "RRW", false },
+	{ HPPA_INS_OR, "RRW", false },
+	{ HPPA_INS_XOR, "RRW", false },
+	{ HPPA_INS_AND, "RRW", false },
+	{ HPPA_INS_ANDCM, "RRW", false },
+	{ HPPA_INS_UXOR, "RRW", false },
+	{ HPPA_INS_UADDCM, "RRW", false },
+	{ HPPA_INS_UADDCMT, "RRW", false },
+	{ HPPA_INS_DCOR, "RW", false },
+	{ HPPA_INS_IDCOR, "RW", false },
+	{ HPPA_INS_ADDI, "iRW", false },
+	{ HPPA_INS_ADDIO, "iRW", false },
+	{ HPPA_INS_ADDIT, "iRW", false },
+	{ HPPA_INS_ADDITO, "iRW", false },
+	{ HPPA_INS_ADD, "RRW", false },
+	{ HPPA_INS_ADDL, "RRW", false },
+	{ HPPA_INS_ADDO, "RRW", false },
+	{ HPPA_INS_ADDC, "RRW", false },
+	{ HPPA_INS_ADDCO, "RRW", false },
+	{ HPPA_INS_SUB, "RRW", false },
+	{ HPPA_INS_SUBO, "RRW", false },
+	{ HPPA_INS_SUBB, "RRW", false },
+	{ HPPA_INS_SUBBO, "RRW", false },
+	{ HPPA_INS_SUBT, "RRW", false },
+	{ HPPA_INS_SUBTO, "RRW", false },
+	{ HPPA_INS_DS, "RRW", false },
+	{ HPPA_INS_SUBI, "iRW", false },
+	{ HPPA_INS_SUBIO, "iRW", false },
+	{ HPPA_INS_CMPICLR, "iRW", false },
+	{ HPPA_INS_COMICLR, "iRW", false },
+	{ HPPA_INS_SHLADD, "RiRW", false },
+	{ HPPA_INS_SH1ADD, "RRW", false },
+	{ HPPA_INS_SH1ADDL, "RRW", false },
+	{ HPPA_INS_SH1ADDO, "RRW", false },
+	{ HPPA_INS_SH2ADD, "RRW", false },
+	{ HPPA_INS_SH2ADDL, "RRW", false },
+	{ HPPA_INS_SH2ADDO, "RRW", false },
+	{ HPPA_INS_SH3ADD, "RRW", false },
+	{ HPPA_INS_SH3ADDL, "RRW", false },
+	{ HPPA_INS_SH3ADDO, "RRW", false },
+
+	{ HPPA_INS_HADD, "RRW", false },
+	{ HPPA_INS_HAVG, "RRW", false },
+	{ HPPA_INS_HSHL, "RiW", false },
+	{ HPPA_INS_HSHLADD, "RiRW", false },
+	{ HPPA_INS_HSHR, "RiW", false },
+	{ HPPA_INS_HSHRADD, "RiRW", false },
+	{ HPPA_INS_HSUB, "RRW", false },
+	{ HPPA_INS_MIXH, "RRW", false },
+	{ HPPA_INS_MIXW, "RRW", false },
+	{ HPPA_INS_PERMH, "RW", false },
+
+	{ HPPA_INS_SHRPD, "RRiW", false },
+	{ HPPA_INS_SHRPD, "RRRW", true },
+	{ HPPA_INS_SHRPW, "RRiW", false },
+	{ HPPA_INS_SHRPW, "RRRW", true },
+	{ HPPA_INS_VSHD, "RRW", false },
+	{ HPPA_INS_SHD, "RRiW", false },
+	{ HPPA_INS_EXTRD, "RiiW", false },
+	{ HPPA_INS_EXTRD, "RRiW", true },
+	{ HPPA_INS_EXTRW, "RiiW", false },
+	{ HPPA_INS_EXTRW, "RRiW", true },
+	{ HPPA_INS_VEXTRU, "RiW", false },
+	{ HPPA_INS_VEXTRS, "RiW", false },
+	{ HPPA_INS_EXTRU, "RiiW", false },
+	{ HPPA_INS_EXTRS, "RiiW", false },
+	{ HPPA_INS_DEPD, "RiiW", false },
+	{ HPPA_INS_DEPDI, "iiiW", false },
+	{ HPPA_INS_DEPW, "RiiW", false },
+	{ HPPA_INS_DEPW, "RRiW", true },
+	{ HPPA_INS_DEPWI, "iiiW", false },
+	{ HPPA_INS_DEPWI, "iRiW", true },
+	{ HPPA_INS_ZVDEP, "RiW", false },
+	{ HPPA_INS_VDEP, "RiW", false },
+	{ HPPA_INS_ZDEP, "RiiW", false },
+	{ HPPA_INS_DEP, "RiiW", false },
+	{ HPPA_INS_ZVDEPI, "iiW", false },
+	{ HPPA_INS_VDEPI, "iiW", false },
+	{ HPPA_INS_ZDEPI, "iiiW", false },
+	{ HPPA_INS_DEPI, "iiiW", false },
+
+	{ HPPA_INS_BREAK, "ii", false },
+	{ HPPA_INS_RFI, "", false },
+	{ HPPA_INS_RFIR, "", false },
+	{ HPPA_INS_SSM, "iW", false },
+	{ HPPA_INS_RSM, "iW", false },
+	{ HPPA_INS_MTSM, "R", false },
+	{ HPPA_INS_LDSID, "(RR)W", false },
+	{ HPPA_INS_MTSP, "RW", false },
+	{ HPPA_INS_MTCTL, "RW", false },
+	{ HPPA_INS_MTSARCM, "R", false },
+	{ HPPA_INS_MFIA, "W", false },
+	{ HPPA_INS_MFSP, "RW", false },
+	{ HPPA_INS_MFCTL, "RW", false },
+	{ HPPA_INS_SYNC, "", false },
+	{ HPPA_INS_SYNCDMA, "", false },
+	{ HPPA_INS_PROBE, "(RR)RW", false },
+	{ HPPA_INS_PROBEI, "(RR)iW", false },
+	{ HPPA_INS_PROBER, "(RR)RW", false },
+	{ HPPA_INS_PROBERI, "(RR)iW", false },
+	{ HPPA_INS_PROBEW, "(RR)RW", false },
+	{ HPPA_INS_PROBEWI, "(RR)iW", false },
+	{ HPPA_INS_LPA, "r(Rb)W", false },
+	{ HPPA_INS_LCI, "r(RR)W", false },
+	{ HPPA_INS_PDTLB, "r(Rb)", false },
+	{ HPPA_INS_PITLB, "r(Rb)", false },
+	{ HPPA_INS_PDTLBE, "r(Rb)", false },
+	{ HPPA_INS_PITLBE, "r(Rb)", false },
+	{ HPPA_INS_IDTLBA, "R(RR)", false },
+	{ HPPA_INS_IITLBA, "R(RR)", false },
+	{ HPPA_INS_IDTLBP, "R(RR)", false },
+	{ HPPA_INS_IITLBP, "R(RR)", false },
+	{ HPPA_INS_PDC, "r(Rb)", false },
+	{ HPPA_INS_FDC, "x(Rb)", false },
+	{ HPPA_INS_FIC, "r(Rb)", false },
+	{ HPPA_INS_FDCE, "r(Rb)", false },
+	{ HPPA_INS_FICE, "r(Rb)", false },
+	{ HPPA_INS_DIAG, "i", false },
+	{ HPPA_INS_IDTLBT, "RR", false },
+	{ HPPA_INS_IITLBT, "RR", false },
+
+	{ HPPA_INS_FLDW, "x(Rb)W", false },
+	{ HPPA_INS_FLDD, "x(Rb)W", false },
+	{ HPPA_INS_FSTW, "Rx(Rb)", false },
+	{ HPPA_INS_FSTD, "Rx(Rb)", false },
+	{ HPPA_INS_FLDWX, "r(Rb)W", false },
+	{ HPPA_INS_FLDDX, "r(Rb)W", false },
+	{ HPPA_INS_FSTWX, "Rr(Rb)", false },
+	{ HPPA_INS_FSTDX, "Rr(Rb)", false },
+	{ HPPA_INS_FSTQX, "", false },
+	{ HPPA_INS_FLDWS, "o(Rb)W", false },
+	{ HPPA_INS_FLDDS, "o(Rb)W", false },
+	{ HPPA_INS_FSTWS, "Ro(Rb)", false },
+	{ HPPA_INS_FSTDS, "Ro(Rb)", false },
+	{ HPPA_INS_FSTQS, "Ro(Rb)", false },
+	{ HPPA_INS_FADD, "RRW", false },
+	{ HPPA_INS_FSUB, "RRW", false },
+	{ HPPA_INS_FMPY, "RRW", false },
+	{ HPPA_INS_FDIV, "RRW", false },
+	{ HPPA_INS_FSQRT, "RW", false },
+	{ HPPA_INS_FABS, "RW", false },
+	{ HPPA_INS_FREM, "", false },
+	{ HPPA_INS_FRND, "RW", false },
+	{ HPPA_INS_FCPY, "RW", false },
+	{ HPPA_INS_FCNVFF, "RW", false },
+	{ HPPA_INS_FCNVXF, "RW", false },
+	{ HPPA_INS_FCNVFX, "RW", false },
+	{ HPPA_INS_FCNVFXT, "RW", false },
+	{ HPPA_INS_FMPYFADD, "RRRW", false },
+	{ HPPA_INS_FMPYNFADD, "RRRW", false },
+	{ HPPA_INS_FNEG, "RW", false },
+	{ HPPA_INS_FNEGABS, "RW", false },
+	{ HPPA_INS_FCNV, "RW", false },
+	{ HPPA_INS_FCMP, "RR", false },
+	{ HPPA_INS_FCMP, "RRi", true },
+	{ HPPA_INS_XMPYU, "RRW", false },
+	{ HPPA_INS_FMPYADD, "RRWRw", false },
+	{ HPPA_INS_FMPYSUB, "RRWRw", false },
+	{ HPPA_INS_FTEST, "", false },
+	{ HPPA_INS_FTEST, "i", true },
+	{ HPPA_INS_FID, "", false },
+
+	{ HPPA_INS_PMDIS, "", false },
+	{ HPPA_INS_PMENB, "", false },
+
+	{ HPPA_INS_SPOP0, "", false },
+	{ HPPA_INS_SPOP1, "W", false },
+	{ HPPA_INS_SPOP2, "R", false },
+	{ HPPA_INS_SPOP3, "RR", false },
+	{ HPPA_INS_COPR, "", false },
+	{ HPPA_INS_CLDW, "x(Rb)W", false },
+	{ HPPA_INS_CLDD, "o(Rb)W", false },
+	{ HPPA_INS_CSTW, "Rx(Rb)", false },
+	{ HPPA_INS_CSTD, "Rx(Rb)", false },
+	{ HPPA_INS_CLDWX, "r(Rb)W", false },
+	{ HPPA_INS_CLDDX, "r(Rb)W", false },
+	{ HPPA_INS_CSTWX, "Rr(Rb)", false },
+	{ HPPA_INS_CSTDX, "Rr(Rb)", false },
+	{ HPPA_INS_CLDWS, "o(Rb)W", false },
+	{ HPPA_INS_CLDDS, "o(Rb)W", false },
+	{ HPPA_INS_CSTWS, "Ro(Rb)", false },
+	{ HPPA_INS_CSTDS, "Ro(Rb)", false },
+
+	{ HPPA_INS_CALL, "", false },
+	{ HPPA_INS_RET, "", false },
+};
+
+static void print_operand(MCInst *MI, SStream *O, const cs_hppa_op *op)
+{
+	switch (op->type) {
+	case HPPA_OP_INVALID:
+		SStream_concat(O, "invalid");
+		break;
+	case HPPA_OP_REG:
+		SStream_concat(O, HPPA_reg_name((csh)MI->csh, op->reg));
+		break;
+	case HPPA_OP_IMM:
+		printInt32(O, op->imm);
+		break;
+	case HPPA_OP_DISP:
+		printInt32(O, op->imm);
+		break;
+	case HPPA_OP_IDX_REG:
+		SStream_concat(O, HPPA_reg_name((csh)MI->csh, op->reg));
+		break;
+	case HPPA_OP_MEM:
+		SStream_concat(O, "(");
+		if (op->mem.space != HPPA_REG_INVALID &&
+		    op->mem.space != HPPA_REG_SR0) {
+			SStream_concat(O, HPPA_reg_name((csh)MI->csh,
+							op->mem.space));
+			SStream_concat(O, ",");
+		}
+		SStream_concat(O, HPPA_reg_name((csh)MI->csh, op->mem.base));
+		SStream_concat(O, ")");
+		break;
+	case HPPA_OP_TARGET:
+		printUInt64(O, MI->address + op->imm);
+		break;
+	}
+}
+
+#define NUMFMTS ARR_SIZE(pa_formats)
+
+static void fill_operands(MCInst *MI, cs_hppa *hppa)
+{
+	hppa->op_count = 0;
+	unsigned mc_op_count = MCInst_getNumOperands(MI);
+	if (mc_op_count == 0)
+		return;
+
+	hppa_ext *hppa_ext = &MI->hppa_ext;
+	uint32_t opcode = MCInst_getOpcode(MI);
+
+	for (int i = 0; i < NUMFMTS; ++i) {
+		const struct pa_insn_fmt *pa_fmt = &pa_formats[i];
+		if (opcode != pa_fmt->insn_id ||
+		    hppa_ext->is_alternative != pa_fmt->is_alternative) {
+			continue;
+		}
+		const char *fmt = pa_fmt->format;
+		uint8_t idx = 0;
+		uint32_t space_regs[2] = { HPPA_REG_INVALID, HPPA_REG_INVALID };
+		uint8_t space_reg_idx = 0;
+		cs_ac_type base_access = CS_AC_INVALID;
+		MCOperand *op = NULL;
+		while (*fmt) {
+			op = MCInst_getOperand(MI, idx++);
+			switch (*fmt++) {
+			case 'i':
+				if (MCOperand_isReg(op)) {
+					set_op_reg(hppa, MCOperand_getReg(op),
+						   CS_AC_READ);
+				} else {
+					set_op_imm(hppa, MCOperand_getImm(op));
+				}
+				break;
+			case 'o':
+				set_op_disp(hppa, MCOperand_getImm(op));
+				break;
+
+			case 'R':
+				set_op_reg(hppa, MCOperand_getReg(op),
+					   CS_AC_READ);
+				break;
+
+			case 'W':
+				set_op_reg(hppa, MCOperand_getReg(op),
+					   CS_AC_WRITE);
+				break;
+
+			case 'w':
+				set_op_reg(hppa, MCOperand_getReg(op),
+					   CS_AC_READ_WRITE);
+				break;
+
+			case 'r':
+				set_op_idx_reg(hppa, MCOperand_getReg(op));
+				break;
+
+			case 'T':
+				set_op_target(hppa, MCOperand_getImm(op) + 8);
+				break;
+
+			case 'x':
+				if (MCOperand_isReg(op)) {
+					set_op_idx_reg(hppa,
+						       MCOperand_getReg(op));
+				} else {
+					set_op_disp(hppa, MCOperand_getImm(op));
+				}
+				break;
+
+			case '(':
+				while (*fmt != ')') {
+					if (space_reg_idx > 0) {
+						op = MCInst_getOperand(MI,
+								       idx++);
+					}
+					assert(space_reg_idx <
+					       ARR_SIZE(space_regs));
+					space_regs[space_reg_idx] =
+						MCOperand_getReg(op);
+					if (*fmt == 'R') {
+						base_access = CS_AC_READ;
+					} else if (*fmt == 'W') {
+						base_access = CS_AC_WRITE;
+					} else if (*fmt == 'b') {
+						base_access = CS_AC_READ;
+						if (hppa_ext->b_writeble)
+							base_access |=
+								CS_AC_WRITE;
+					}
+					fmt++;
+					space_reg_idx++;
+				}
+
+				if (space_regs[1] == HPPA_REG_INVALID)
+					set_op_mem(hppa, space_regs[0],
+						   space_regs[1], base_access);
+				else
+					set_op_mem(hppa, space_regs[1],
+						   space_regs[0], base_access);
+				fmt++;
+				break;
+
+			default:
+				printf("Unknown: %c\n", *(fmt - 1));
+				break;
+			}
+		}
+		break;
+	}
+}
+
+static void print_modifiers(MCInst *MI, SStream *O)
+{
+	hppa_ext *hppa_ext = &MI->hppa_ext;
+	for (uint8_t i = 0; i < hppa_ext->mod_num; ++i) {
+		SStream_concat(O, ",");
+		if (hppa_ext->modifiers[i].type == HPPA_MOD_STR)
+			SStream_concat(O, hppa_ext->modifiers[i].str_mod);
+		else
+			SStream_concat(O, "%d", hppa_ext->modifiers[i].int_mod);
+	}
+}
+
+static void add_groups(MCInst *MI)
+{
+	unsigned int opcode = MCInst_getOpcode(MI);
+	for (unsigned i = 0; i < ARR_SIZE(pa_insns); ++i) {
+		if (pa_insns[i].insn != opcode) {
+			continue;
+		}
+		add_group(MI, pa_insns[i].grp);
+	}
+}
+
+#ifndef CAPSTONE_DIET
+static void update_regs_access(MCInst *MI, unsigned int opcode)
+{
+	if (opcode == HPPA_INS_INVALID)
+		return;
+
+	hppa_ext *hppa_ext = &MI->hppa_ext;
+	switch (opcode) {
+	default:
+		break;
+	case HPPA_INS_BLE:
+		map_add_implicit_write(MI, HPPA_REG_GR31);
+		map_add_implicit_write(MI, HPPA_REG_SR0);
+		break;
+	case HPPA_INS_BVB:
+		map_add_implicit_read(MI, HPPA_REG_CR11);
+		break;
+	case HPPA_INS_RFI:
+		if (hppa_ext->mod_num == 0) {
+			break;
+		}
+		// fallthrough
+	case HPPA_INS_RFIR:
+		map_add_implicit_write(MI, HPPA_REG_GR1);
+		map_add_implicit_write(MI, HPPA_REG_GR8);
+		map_add_implicit_write(MI, HPPA_REG_GR9);
+		map_add_implicit_write(MI, HPPA_REG_GR16);
+		map_add_implicit_write(MI, HPPA_REG_GR17);
+		map_add_implicit_write(MI, HPPA_REG_GR24);
+		map_add_implicit_write(MI, HPPA_REG_GR25);
+		break;
+	case HPPA_INS_VDEP:
+	case HPPA_INS_VDEPI:
+	case HPPA_INS_VEXTRS:
+	case HPPA_INS_VEXTRU:
+	case HPPA_INS_VSHD:
+	case HPPA_INS_ZVDEPI:
+		map_add_implicit_read(MI, HPPA_REG_CR11);
+		break;
+	case HPPA_INS_ADDIL:
+		map_add_implicit_write(MI, HPPA_REG_GR1);
+		break;
+	}
+}
+#endif
+
+void HPPA_printInst(MCInst *MI, SStream *O, void *Info)
+{
+	cs_hppa hppa;
+
+	/* set pubOpcode as instruction id */
+	MCInst_setOpcodePub(MI, MCInst_getOpcode(MI));
+
+	SStream_concat(O, HPPA_insn_name((csh)MI->csh, MCInst_getOpcode(MI)));
+	print_modifiers(MI, O);
+	SStream_concat(O, " ");
+	fill_operands(MI, &hppa);
+	for (int i = 0; i < hppa.op_count; i++) {
+		cs_hppa_op *op = &hppa.operands[i];
+		print_operand(MI, O, op);
+		if (op->type != HPPA_OP_IDX_REG && op->type != HPPA_OP_DISP &&
+		    i != hppa.op_count - 1) {
+			SStream_concat(O, ",");
+		}
+	}
+
+	if (detail_is_set(MI)) {
+		cs_hppa *hppa_detail = HPPA_get_detail(MI);
+		*hppa_detail = hppa;
+		add_groups(MI);
+#ifndef CAPSTONE_DIET
+		update_regs_access(MI, MCInst_getOpcode(MI));
+#endif
+	}
+}
+
+#endif

thirdparty/capstone/arch/HPPA/HPPAInstPrinter.h

@@ -0,0 +1,25 @@
+/* Capstone Disassembly Engine */
+/* By Dmitry Sibirtsev  <sibirtsevdl@gmail.com>, 2023 */
+
+#ifndef CS_HPPAINSTPRINTER_H
+#define CS_HPPAINSTPRINTER_H
+
+#include <capstone/capstone.h>
+
+#include "../../MCInst.h"
+#include "../../SStream.h"
+
+struct pa_insn {
+	hppa_insn insn;
+	hppa_insn_group grp;
+};
+
+struct pa_insn_fmt {
+	hppa_insn insn_id;
+	const char *format;
+	bool is_alternative; ///< true if some completer affects the instruction format
+};
+
+void HPPA_printInst(MCInst *MI, SStream *O, void *Info);
+
+#endif

thirdparty/capstone/arch/HPPA/HPPAMapping.c

@@ -0,0 +1,442 @@
+/* Capstone Disassembly Engine */
+/* By Dmitry Sibirtsev  <sibirtsevdl@gmail.com>, 2023 */
+
+#ifdef CAPSTONE_HAS_HPPA
+
+#include <string.h>
+#include <stdlib.h>
+
+#include "HPPAMapping.h"
+#include "HPPAConstants.h"
+#include "../../Mapping.h"
+#include "../../utils.h"
+
+#ifndef CAPSTONE_DIET
+static const name_map group_name_maps[] = {
+	{ HPPA_GRP_INVALID, NULL },
+
+	{ HPPA_GRP_COMPUTATION, "computation" },
+	{ HPPA_GRP_MULTIMEDIA, "multimedia" },
+	{ HPPA_GRP_MEM_REF, "memory_reference" },
+	{ HPPA_GRP_LONG_IMM, "long_imm" },
+	{ HPPA_GRP_BRANCH, "branch" },
+	{ HPPA_GRP_SYSCTRL, "system_control" },
+	{ HPPA_GRP_ASSIST, "assist" },
+	{ HPPA_GRP_FLOAT, "float" },
+};
+#endif
+
+const char *HPPA_group_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
+#else
+	return NULL;
+#endif
+}
+
+#ifndef CAPSTONE_DIET
+static const name_map insn_name_maps[HPPA_INS_ENDING] = {
+	{ HPPA_INS_INVALID, NULL },
+
+	{ HPPA_INS_ADD, "add" },
+	{ HPPA_INS_ADDI, "addi" },
+	{ HPPA_INS_ADDIO, "addio" },
+	{ HPPA_INS_ADDIT, "addit" },
+	{ HPPA_INS_ADDITO, "addito" },
+	{ HPPA_INS_ADDB, "addb" },
+	{ HPPA_INS_ADDBT, "addbt" },
+	{ HPPA_INS_ADDBF, "addbf" },
+	{ HPPA_INS_ADDIB, "addib" },
+	{ HPPA_INS_ADDIBT, "addibt" },
+	{ HPPA_INS_ADDIBF, "addibf" },
+	{ HPPA_INS_ADDIL, "addil" },
+	{ HPPA_INS_ADDC, "addc" },
+	{ HPPA_INS_ADDCO, "addco" },
+	{ HPPA_INS_ADDL, "addl" },
+	{ HPPA_INS_ADDO, "addo" },
+	{ HPPA_INS_AND, "and" },
+	{ HPPA_INS_ANDCM, "andcm" },
+	{ HPPA_INS_B, "b" },
+	{ HPPA_INS_BB, "bb" },
+	{ HPPA_INS_BE, "be" },
+	{ HPPA_INS_BL, "bl" },
+	{ HPPA_INS_BLE, "ble" },
+	{ HPPA_INS_BLR, "blr" },
+	{ HPPA_INS_BREAK, "break" },
+	{ HPPA_INS_BV, "bv" },
+	{ HPPA_INS_BVB, "bvb" },
+	{ HPPA_INS_BVE, "bve" },
+	{ HPPA_INS_CALL, "call" },
+	{ HPPA_INS_CLDD, "cldd" },
+	{ HPPA_INS_CLDDS, "cldds" },
+	{ HPPA_INS_CLDDX, "clddx" },
+	{ HPPA_INS_CLDW, "cldw" },
+	{ HPPA_INS_CLDWS, "cldws" },
+	{ HPPA_INS_CLDWX, "cldwx" },
+	{ HPPA_INS_CLRBTS, "clrbts" },
+	{ HPPA_INS_CMPB, "cmpb" },
+	{ HPPA_INS_CMPCLR, "cmpclr" },
+	{ HPPA_INS_CMPIB, "cmpib" },
+	{ HPPA_INS_CMPICLR, "cmpiclr" },
+	{ HPPA_INS_COMB, "comb" },
+	{ HPPA_INS_COMBT, "combt" },
+	{ HPPA_INS_COMBF, "combf" },
+	{ HPPA_INS_COMCLR, "comclr" },
+	{ HPPA_INS_COMIB, "comib" },
+	{ HPPA_INS_COMIBT, "comibt" },
+	{ HPPA_INS_COMIBF, "comibf" },
+	{ HPPA_INS_COMICLR, "comiclr" },
+	{ HPPA_INS_COPR, "copr" },
+	{ HPPA_INS_COPY, "copy" },
+	{ HPPA_INS_CSTD, "cstd" },
+	{ HPPA_INS_CSTDS, "cstds" },
+	{ HPPA_INS_CSTDX, "cstdx" },
+	{ HPPA_INS_CSTW, "cstw" },
+	{ HPPA_INS_CSTWS, "cstws" },
+	{ HPPA_INS_CSTWX, "cstwx" },
+	{ HPPA_INS_DCOR, "dcor" },
+	{ HPPA_INS_DEP, "dep" },
+	{ HPPA_INS_DEPI, "depi" },
+	{ HPPA_INS_DEPD, "depd" },
+	{ HPPA_INS_DEPDI, "depdi" },
+	{ HPPA_INS_DEPW, "depw" },
+	{ HPPA_INS_DEPWI, "depwi" },
+	{ HPPA_INS_DIAG, "diag" },
+	{ HPPA_INS_DS, "ds" },
+	{ HPPA_INS_EXTRD, "extrd" },
+	{ HPPA_INS_EXTRS, "extrs" },
+	{ HPPA_INS_EXTRU, "extru" },
+	{ HPPA_INS_EXTRW, "extrw" },
+	{ HPPA_INS_FABS, "fabs" },
+	{ HPPA_INS_FADD, "fadd" },
+	{ HPPA_INS_FCMP, "fcmp" },
+	{ HPPA_INS_FCNV, "fcnv" },
+	{ HPPA_INS_FCNVFF, "fcnvff" },
+	{ HPPA_INS_FCNVFX, "fcnvfx" },
+	{ HPPA_INS_FCNVFXT, "fcnvfxt" },
+	{ HPPA_INS_FCNVXF, "fcnvxf" },
+	{ HPPA_INS_FCPY, "fcpy" },
+	{ HPPA_INS_FDC, "fdc" },
+	{ HPPA_INS_FDCE, "fdce" },
+	{ HPPA_INS_FDIV, "fdiv" },
+	{ HPPA_INS_FIC, "fic" },
+	{ HPPA_INS_FICE, "fice" },
+	{ HPPA_INS_FID, "fid" },
+	{ HPPA_INS_FLDD, "fldd" },
+	{ HPPA_INS_FLDDS, "fldds" },
+	{ HPPA_INS_FLDDX, "flddx" },
+	{ HPPA_INS_FLDW, "fldw" },
+	{ HPPA_INS_FLDWS, "fldws" },
+	{ HPPA_INS_FLDWX, "fldwx" },
+	{ HPPA_INS_FMPY, "fmpy" },
+	{ HPPA_INS_FMPYADD, "fmpyadd" },
+	{ HPPA_INS_FMPYFADD, "fmpyfadd" },
+	{ HPPA_INS_FMPYNFADD, "fmpynfadd" },
+	{ HPPA_INS_FMPYSUB, "fmpysub" },
+	{ HPPA_INS_FNEG, "fneg" },
+	{ HPPA_INS_FNEGABS, "fnegabs" },
+	{ HPPA_INS_FREM, "frem" },
+	{ HPPA_INS_FRND, "frnd" },
+	{ HPPA_INS_FSQRT, "fsqrt" },
+	{ HPPA_INS_FSTD, "fstd" },
+	{ HPPA_INS_FSTDS, "fstds" },
+	{ HPPA_INS_FSTDX, "fstdx" },
+	{ HPPA_INS_FSTW, "fstw" },
+	{ HPPA_INS_FSTWS, "fstws" },
+	{ HPPA_INS_FSTWX, "fstwx" },
+	{ HPPA_INS_FSTQS, "fstqs" },
+	{ HPPA_INS_FSTQX, "fstqx" },
+	{ HPPA_INS_FSUB, "fsub" },
+	{ HPPA_INS_FTEST, "ftest" },
+	{ HPPA_INS_GATE, "gate" },
+	{ HPPA_INS_GFR, "gfr" },
+	{ HPPA_INS_GFW, "gfw" },
+	{ HPPA_INS_GRSHDW, "grshdw" },
+	{ HPPA_INS_HADD, "hadd" },
+	{ HPPA_INS_HAVG, "havg" },
+	{ HPPA_INS_HSHL, "hshl" },
+	{ HPPA_INS_HSHLADD, "hshladd" },
+	{ HPPA_INS_HSHR, "hshr" },
+	{ HPPA_INS_HSHRADD, "hshradd" },
+	{ HPPA_INS_HSUB, "hsub" },
+	{ HPPA_INS_IDTLBA, "idtlba" },
+	{ HPPA_INS_IDTLBP, "idtlbp" },
+	{ HPPA_INS_IDTLBT, "idtlbt" },
+	{ HPPA_INS_IDCOR, "idcor" },
+	{ HPPA_INS_IITLBA, "iitlba" },
+	{ HPPA_INS_IITLBP, "iitlbp" },
+	{ HPPA_INS_IITLBT, "iitlbt" },
+	{ HPPA_INS_LCI, "lci" },
+	{ HPPA_INS_LDB, "ldb" },
+	{ HPPA_INS_LDBS, "ldbs" },
+	{ HPPA_INS_LDBX, "ldbx" },
+	{ HPPA_INS_LDCD, "ldcd" },
+	{ HPPA_INS_LDCW, "ldcw" },
+	{ HPPA_INS_LDCWS, "ldcws" },
+	{ HPPA_INS_LDCWX, "ldcwx" },
+	{ HPPA_INS_LDD, "ldd" },
+	{ HPPA_INS_LDDA, "ldda" },
+	{ HPPA_INS_LDH, "ldh" },
+	{ HPPA_INS_LDHS, "ldhs" },
+	{ HPPA_INS_LDHX, "ldhx" },
+	{ HPPA_INS_LDI, "ldi" },
+	{ HPPA_INS_LDIL, "ldil" },
+	{ HPPA_INS_LDO, "ldo" },
+	{ HPPA_INS_LDSID, "ldsid" },
+	{ HPPA_INS_LDW, "ldw" },
+	{ HPPA_INS_LDWA, "ldwa" },
+	{ HPPA_INS_LDWAS, "ldwas" },
+	{ HPPA_INS_LDWAX, "ldwax" },
+	{ HPPA_INS_LDWM, "ldwm" },
+	{ HPPA_INS_LDWS, "ldws" },
+	{ HPPA_INS_LDWX, "ldwx" },
+	{ HPPA_INS_LPA, "lpa" },
+	{ HPPA_INS_MFCPU, "mfcpu" },
+	{ HPPA_INS_MFCTL, "mfctl" },
+	{ HPPA_INS_MFIA, "mfia" },
+	{ HPPA_INS_MFSP, "mfsp" },
+	{ HPPA_INS_MIXH, "mixh" },
+	{ HPPA_INS_MIXW, "mixw" },
+	{ HPPA_INS_MOVB, "movb" },
+	{ HPPA_INS_MOVIB, "movib" },
+	{ HPPA_INS_MTCPU, "mtcpu" },
+	{ HPPA_INS_MTCTL, "mtctl" },
+	{ HPPA_INS_MTSAR, "mtsar" },
+	{ HPPA_INS_MTSARCM, "mtsarcm" },
+	{ HPPA_INS_MTSM, "mtsm" },
+	{ HPPA_INS_MTSP, "mtsp" },
+	{ HPPA_INS_NOP, "nop" },
+	{ HPPA_INS_OR, "or" },
+	{ HPPA_INS_PDC, "pdc" },
+	{ HPPA_INS_PDTLB, "pdtlb" },
+	{ HPPA_INS_PDTLBE, "pdtlbe" },
+	{ HPPA_INS_PERMH, "permh" },
+	{ HPPA_INS_PITLB, "pitlb" },
+	{ HPPA_INS_PITLBE, "pitlbe" },
+	{ HPPA_INS_PMDIS, "pmdis" },
+	{ HPPA_INS_PMENB, "pmenb" },
+	{ HPPA_INS_POPBTS, "popbts" },
+	{ HPPA_INS_PROBE, "probe" },
+	{ HPPA_INS_PROBEI, "probei" },
+	{ HPPA_INS_PROBER, "prober" },
+	{ HPPA_INS_PROBERI, "proberi" },
+	{ HPPA_INS_PROBEW, "probew" },
+	{ HPPA_INS_PROBEWI, "probewi" },
+	{ HPPA_INS_PUSHBTS, "pushbts" },
+	{ HPPA_INS_PUSHNOM, "pushnom" },
+	{ HPPA_INS_RET, "ret" },
+	{ HPPA_INS_RFI, "rfi" },
+	{ HPPA_INS_RFIR, "rfir" },
+	{ HPPA_INS_RSM, "rsm" },
+	{ HPPA_INS_SHDWGR, "shdwgr" },
+	{ HPPA_INS_SHLADD, "shladd" },
+	{ HPPA_INS_SH1ADD, "sh1add" },
+	{ HPPA_INS_SH1ADDL, "sh1addl" },
+	{ HPPA_INS_SH1ADDO, "sh1addo" },
+	{ HPPA_INS_SH2ADD, "sh2add" },
+	{ HPPA_INS_SH2ADDL, "sh2addl" },
+	{ HPPA_INS_SH2ADDO, "sh2addo" },
+	{ HPPA_INS_SH3ADD, "sh3add" },
+	{ HPPA_INS_SH3ADDL, "sh3addl" },
+	{ HPPA_INS_SH3ADDO, "sh3addo" },
+	{ HPPA_INS_SHD, "shd" },
+	{ HPPA_INS_SHRPD, "shrpd" },
+	{ HPPA_INS_SHRPW, "shrpw" },
+	{ HPPA_INS_SPOP0, "spop0" },
+	{ HPPA_INS_SPOP1, "spop1" },
+	{ HPPA_INS_SPOP2, "spop2" },
+	{ HPPA_INS_SPOP3, "spop3" },
+	{ HPPA_INS_SSM, "ssm" },
+	{ HPPA_INS_STB, "stb" },
+	{ HPPA_INS_STBS, "stbs" },
+	{ HPPA_INS_STBY, "stby" },
+	{ HPPA_INS_STBYS, "stbys" },
+	{ HPPA_INS_STD, "std" },
+	{ HPPA_INS_STDA, "stda" },
+	{ HPPA_INS_STDBY, "stdby" },
+	{ HPPA_INS_STH, "sth" },
+	{ HPPA_INS_STHS, "sths" },
+	{ HPPA_INS_STW, "stw" },
+	{ HPPA_INS_STWA, "stwa" },
+	{ HPPA_INS_STWAS, "stwas" },
+	{ HPPA_INS_STWS, "stws" },
+	{ HPPA_INS_STWM, "stwm" },
+	{ HPPA_INS_SUB, "sub" },
+	{ HPPA_INS_SUBB, "subb" },
+	{ HPPA_INS_SUBBO, "subbo" },
+	{ HPPA_INS_SUBI, "subi" },
+	{ HPPA_INS_SUBIO, "subio" },
+	{ HPPA_INS_SUBO, "subo" },
+	{ HPPA_INS_SUBT, "subt" },
+	{ HPPA_INS_SUBTO, "subto" },
+	{ HPPA_INS_SYNC, "sync" },
+	{ HPPA_INS_SYNCDMA, "syncdma" },
+	{ HPPA_INS_TOCDIS, "tocdis" },
+	{ HPPA_INS_TOCEN, "tocen" },
+	{ HPPA_INS_UADDCM, "uaddcm" },
+	{ HPPA_INS_UADDCMT, "uaddcmt" },
+	{ HPPA_INS_UXOR, "uxor" },
+	{ HPPA_INS_VDEP, "vdep" },
+	{ HPPA_INS_VDEPI, "vdepi" },
+	{ HPPA_INS_VEXTRS, "vextrs" },
+	{ HPPA_INS_VEXTRU, "vextru" },
+	{ HPPA_INS_VSHD, "vshd" },
+	{ HPPA_INS_XMPYU, "xmpyu" },
+	{ HPPA_INS_XOR, "xor" },
+	{ HPPA_INS_ZDEP, "zdep" },
+	{ HPPA_INS_ZDEPI, "zdepi" },
+	{ HPPA_INS_ZVDEP, "zvdep" },
+	{ HPPA_INS_ZVDEPI, "zvdepi" },
+};
+#endif
+
+const char *HPPA_insn_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	return id2name(insn_name_maps, ARR_SIZE(insn_name_maps), id);
+#else
+	return NULL;
+#endif
+}
+
+#ifndef CAPSTONE_DIET
+/* Integer register names, indexed by the numbers which appear in the
+   opcodes.  */
+static const char *const reg_names[] = {
+	"flags", "r1",	"rp",  "r3",  "r4",   "r5",   "r6",  "r7",
+	"r8",	 "r9",	"r10", "r11", "r12",  "r13",  "r14", "r15",
+	"r16",	 "r17", "r18", "r19", "r20",  "r21",  "r22", "r23",
+	"r24",	 "r25", "r26", "dp",  "ret0", "ret1", "sp",  "r31"
+};
+
+/* Floating point register names, indexed by the numbers which appear in the
+   opcodes.  */
+static const char *const fp_reg_names[] = {
+	"fpsr", "fpe2", "fpe4", "fpe6", "fr4",	"fr5",	"fr6",	"fr7",
+	"fr8",	"fr9",	"fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
+	"fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
+	"fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31"
+};
+
+static const char *const control_reg[] = {
+	"rctr",	 "cr1",	  "cr2",  "cr3", "cr4",	  "cr5",   "cr6",  "cr7",
+	"pidr1", "pidr2", "ccr",  "sar", "pidr3", "pidr4", "iva",  "eiem",
+	"itmr",	 "pcsq",  "pcoq", "iir", "isr",	  "ior",   "ipsw", "eirr",
+	"tr0",	 "tr1",	  "tr2",  "tr3", "tr4",	  "tr5",   "tr6",  "tr7"
+};
+
+static const char *const space_reg[] = { "sr0", "sr1", "sr2", "sr3",
+					 "sr4", "sr5", "sr6", "sr7" };
+
+static const char *const fpe_reg[] = {
+	"fpe1",	 "fpe3",  "fpe5",  "fpe7",  "fr4R",  "fr5R",  "fr6R",  "fr7R",
+	"fr8R",	 "fr9R",  "fr10R", "fr11R", "fr12R", "fr13R", "fr14R", "fr15R",
+	"fr16R", "fr17R", "fr18R", "fr19R", "fr20R", "fr21R", "fr22R", "fr23R",
+	"fr24R", "fr25R", "fr26R", "fr27R", "fr28R", "fr29R", "fr30R", "fr31R"
+};
+
+static const char *const sp_fp_reg[] = {
+	"fr16L", "fr17L", "fr18L", "fr19L", "fr20L", "fr21L", "fr22L", "fr23L",
+	"fr24L", "fr25L", "fr26L", "fr27L", "fr28L", "fr29L", "fr30L", "fr31L",
+	"fr16R", "fr17R", "fr18R", "fr19R", "fr20R", "fr21R", "fr22R", "fr23R",
+	"fr24R", "fr25R", "fr26R", "fr27R", "fr28R", "fr29R", "fr30R", "fr31R"
+};
+#endif
+
+const char *HPPA_reg_name(csh handle, unsigned int reg)
+{
+#ifndef CAPSTONE_DIET
+	if (reg >= HPPA_REG_GR0 && reg <= HPPA_REG_GR31)
+		return reg_names[reg - HPPA_REG_GR0];
+	else if (reg >= HPPA_REG_FPR0 && reg <= HPPA_REG_FPR31)
+		return fp_reg_names[reg - HPPA_REG_FPR0];
+	else if (reg >= HPPA_REG_SR0 && reg <= HPPA_REG_SR7)
+		return space_reg[reg - HPPA_REG_SR0];
+	else if (reg >= HPPA_REG_CR0 && reg <= HPPA_REG_CR31)
+		return control_reg[reg - HPPA_REG_CR0];
+	else if (reg >= HPPA_REG_FPE0 && reg <= HPPA_REG_FPE31)
+		return fpe_reg[reg - HPPA_REG_FPE0];
+	else if (reg >= HPPA_REG_SP_FPR0 && reg <= HPPA_REG_SP_FPR31)
+		return sp_fp_reg[reg - HPPA_REG_SP_FPR0];
+	return NULL;
+#else
+	return NULL;
+#endif
+}
+
+void HPPA_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int opcode)
+{
+	insn->id = opcode;
+}
+
+static void sort_and_uniq(cs_regs arr, uint8_t n, uint8_t *new_n)
+{
+	/* arr is always a tiny (usually n < 3) array,
+	 * a simple O(n^2) sort is efficient enough. */
+	int i;
+	int j;
+	int iMin;
+	int tmp;
+
+	/* a modified selection sort for sorting and making unique */
+	for (j = 0; j < n; j++) {
+		/* arr[iMin] will be min(arr[j .. n-1]) */
+		iMin = j;
+		for (i = j + 1; i < n; i++) {
+			if (arr[i] < arr[iMin])
+				iMin = i;
+		}
+		if (j != 0 && arr[iMin] == arr[j - 1]) { // duplicate ele found
+			arr[iMin] = arr[n - 1];
+			--n;
+		} else {
+			tmp = arr[iMin];
+			arr[iMin] = arr[j];
+			arr[j] = tmp;
+		}
+	}
+
+	*new_n = n;
+}
+
+void HPPA_reg_access(const cs_insn *insn, cs_regs regs_read,
+		     uint8_t *regs_read_count, cs_regs regs_write,
+		     uint8_t *regs_write_count)
+{
+	uint8_t read_count = 0;
+	uint8_t write_count = 0;
+	const cs_hppa *hppa = &(insn->detail->hppa);
+
+	for (unsigned i = 0; i < hppa->op_count; ++i) {
+		const cs_hppa_op *op = &(hppa->operands[i]);
+		switch (op->type) {
+		case HPPA_OP_REG:
+		case HPPA_OP_IDX_REG:
+			if (op->access & CS_AC_READ) {
+				regs_read[read_count++] = op->reg;
+			}
+			if (op->access & CS_AC_WRITE) {
+				regs_write[write_count++] = op->reg;
+			}
+			break;
+		case HPPA_OP_MEM:
+			if (op->mem.space != HPPA_REG_INVALID)
+				regs_read[read_count++] = op->mem.space;
+			if (op->mem.base_access & CS_AC_READ) {
+				regs_read[read_count++] = op->mem.base;
+			}
+			if (op->mem.base_access & CS_AC_WRITE) {
+				regs_write[write_count++] = op->mem.base;
+			}
+			break;
+		default:
+			break;
+		}
+	}
+
+	sort_and_uniq(regs_read, read_count, regs_read_count);
+	sort_and_uniq(regs_write, write_count, regs_write_count);
+}
+
+#endif

thirdparty/capstone/arch/HPPA/HPPAMapping.h

@@ -0,0 +1,19 @@
+/* Capstone Disassembly Engine */
+/* By Dmitry Sibirtsev  <sibirtsevdl@gmail.com>, 2023 */
+
+#ifndef CS_HPPAMAPPING_H
+#define CS_HPPAMAPPING_H
+
+#include <capstone/capstone.h>
+
+#include "../../cs_priv.h"
+
+const char *HPPA_group_name(csh handle, unsigned int id);
+const char *HPPA_insn_name(csh handle, unsigned int id);
+const char *HPPA_reg_name(csh handle, unsigned int reg);
+void HPPA_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
+void HPPA_reg_access(const cs_insn *insn, cs_regs regs_read,
+		     uint8_t *regs_read_count, cs_regs regs_write,
+		     uint8_t *regs_write_count);
+
+#endif

thirdparty/capstone/arch/HPPA/HPPAModule.c

@@ -0,0 +1,34 @@
+/* Capstone Disassembly Engine */
+/* By Dmitry Sibirtsev  <sibirtsevdl@gmail.com>, 2023 */
+
+#ifdef CAPSTONE_HAS_HPPA
+
+#include "HPPADisassembler.h"
+#include "HPPAInstPrinter.h"
+#include "HPPAMapping.h"
+#include "HPPAModule.h"
+
+cs_err HPPA_global_init(cs_struct *ud)
+{
+	ud->printer = HPPA_printInst;
+	ud->reg_name = HPPA_reg_name;
+	ud->insn_id = HPPA_get_insn_id;
+	ud->insn_name = HPPA_insn_name;
+	ud->group_name = HPPA_group_name;
+#ifndef CAPSTONE_DIET
+	ud->reg_access = HPPA_reg_access;
+#endif
+	ud->disasm = HPPA_getInstruction;
+
+	return CS_ERR_OK;
+}
+
+cs_err HPPA_option(cs_struct *handle, cs_opt_type type, size_t value)
+{
+	if (type == CS_OPT_MODE)
+		handle->mode = (cs_mode)value;
+
+	return CS_ERR_OK;
+}
+
+#endif

thirdparty/capstone/arch/HPPA/HPPAModule.h

@@ -0,0 +1,12 @@
+/* Capstone Disassembly Engine */
+/* By Dmitry Sibirtsev  <sibirtsevdl@gmail.com>, 2023 */
+
+#ifndef CS_HPPA_MODULE_H
+#define CS_HPPA_MODULE_H
+
+#include "../../utils.h"
+
+cs_err HPPA_global_init(cs_struct *ud);
+cs_err HPPA_option(cs_struct *handle, cs_opt_type type, size_t value);
+
+#endif

thirdparty/capstone/arch/LoongArch/LoongArchDisassembler.c

@@ -0,0 +1,199 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically translated source file from LLVM. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Only small edits allowed. */
+/* For multiple similar edits, please create a Patch for the translator. */
+
+/* Capstone's C++ file translator: */
+/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
+
+//===-- LoongArchDisassembler.cpp - Disassembler for LoongArch ------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the LoongArchDisassembler class.
+//
+//===----------------------------------------------------------------------===//
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+#include <capstone/platform.h>
+
+#include "../../MCInst.h"
+#include "../../MathExtras.h"
+#include "../../MCInstPrinter.h"
+#include "../../MCDisassembler.h"
+#include "../../MCFixedLenDisassembler.h"
+#include "../../cs_priv.h"
+#include "../../utils.h"
+#include "LoongArchDisassemblerExtension.h"
+#define GET_SUBTARGETINFO_ENUM
+#include "LoongArchGenSubtargetInfo.inc"
+
+#define GET_INSTRINFO_ENUM
+#include "LoongArchGenInstrInfo.inc"
+
+#define GET_REGINFO_ENUM
+#include "LoongArchGenRegisterInfo.inc"
+
+#define CONCAT(a, b) CONCAT_(a, b)
+#define CONCAT_(a, b) a##_##b
+
+#define DEBUG_TYPE "loongarch-disassembler"
+
+static DecodeStatus DecodeGPRRegisterClass(MCInst *Inst, uint64_t RegNo,
+					   uint64_t Address,
+					   const void *Decoder)
+{
+	if (RegNo >= 32)
+		return MCDisassembler_Fail;
+	MCOperand_CreateReg0(Inst, (LoongArch_R0 + RegNo));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeFPR32RegisterClass(MCInst *Inst, uint64_t RegNo,
+					     uint64_t Address,
+					     const void *Decoder)
+{
+	if (RegNo >= 32)
+		return MCDisassembler_Fail;
+	MCOperand_CreateReg0(Inst, (LoongArch_F0 + RegNo));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeFPR64RegisterClass(MCInst *Inst, uint64_t RegNo,
+					     uint64_t Address,
+					     const void *Decoder)
+{
+	if (RegNo >= 32)
+		return MCDisassembler_Fail;
+	MCOperand_CreateReg0(Inst, (LoongArch_F0_64 + RegNo));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeCFRRegisterClass(MCInst *Inst, uint64_t RegNo,
+					   uint64_t Address,
+					   const void *Decoder)
+{
+	if (RegNo >= 8)
+		return MCDisassembler_Fail;
+	MCOperand_CreateReg0(Inst, (LoongArch_FCC0 + RegNo));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeFCSRRegisterClass(MCInst *Inst, uint64_t RegNo,
+					    uint64_t Address,
+					    const void *Decoder)
+{
+	if (RegNo >= 4)
+		return MCDisassembler_Fail;
+	MCOperand_CreateReg0(Inst, (LoongArch_FCSR0 + RegNo));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeLSX128RegisterClass(MCInst *Inst, uint64_t RegNo,
+					      uint64_t Address,
+					      const void *Decoder)
+{
+	if (RegNo >= 32)
+		return MCDisassembler_Fail;
+	MCOperand_CreateReg0(Inst, (LoongArch_VR0 + RegNo));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeLASX256RegisterClass(MCInst *Inst, uint64_t RegNo,
+					       uint64_t Address,
+					       const void *Decoder)
+{
+	if (RegNo >= 32)
+		return MCDisassembler_Fail;
+	MCOperand_CreateReg0(Inst, (LoongArch_XR0 + RegNo));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeSCRRegisterClass(MCInst *Inst, uint64_t RegNo,
+					   uint64_t Address,
+					   const void *Decoder)
+{
+	if (RegNo >= 4)
+		return MCDisassembler_Fail;
+	MCOperand_CreateReg0(Inst, (LoongArch_SCR0 + RegNo));
+	return MCDisassembler_Success;
+}
+
+#define DEFINE_decodeUImmOperand(N, P) \
+	static DecodeStatus CONCAT(decodeUImmOperand, CONCAT(N, P))( \
+		MCInst * Inst, uint64_t Imm, int64_t Address, \
+		const void *Decoder) \
+	{ \
+		MCOperand_CreateImm0(Inst, (Imm + P)); \
+		return MCDisassembler_Success; \
+	}
+DEFINE_decodeUImmOperand(2, 1);
+DEFINE_decodeUImmOperand(12, 0);
+
+#define DEFINE_decodeSImmOperand(N, S) \
+	static DecodeStatus CONCAT(decodeSImmOperand, CONCAT(N, S))( \
+		MCInst * Inst, uint64_t Imm, int64_t Address, \
+		const void *Decoder) \
+	{ \
+		MCOperand_CreateImm0(Inst, (SignExtend64((Imm << S), N + S))); \
+		return MCDisassembler_Success; \
+	}
+DEFINE_decodeSImmOperand(5, 0);
+DEFINE_decodeSImmOperand(12, 0);
+DEFINE_decodeSImmOperand(16, 0);
+DEFINE_decodeSImmOperand(20, 0);
+DEFINE_decodeSImmOperand(14, 2);
+DEFINE_decodeSImmOperand(9, 3);
+DEFINE_decodeSImmOperand(10, 2);
+DEFINE_decodeSImmOperand(11, 1);
+DEFINE_decodeSImmOperand(8, 3);
+DEFINE_decodeSImmOperand(8, 2);
+DEFINE_decodeSImmOperand(8, 1);
+DEFINE_decodeSImmOperand(8, 0);
+DEFINE_decodeSImmOperand(21, 2);
+DEFINE_decodeSImmOperand(16, 2);
+DEFINE_decodeSImmOperand(26, 2);
+DEFINE_decodeSImmOperand(13, 0);
+
+#include "LoongArchGenDisassemblerTables.inc"
+
+static DecodeStatus getInstruction(MCInst *MI, uint64_t *Size,
+				   const uint8_t *Bytes, size_t BytesLen,
+				   uint64_t Address, SStream *CS)
+{
+	uint32_t Insn;
+	DecodeStatus Result;
+
+	// We want to read exactly 4 bytes of data because all LoongArch instructions
+	// are fixed 32 bits.
+	if (BytesLen < 4) {
+		*Size = 0;
+		return MCDisassembler_Fail;
+	}
+
+	Insn = readBytes32(MI, Bytes);
+	// Calling the auto-generated decoder function.
+	Result = decodeInstruction_4(DecoderTable32, MI, Insn, Address, NULL);
+	*Size = 4;
+
+	return Result;
+}
+
+DecodeStatus LoongArch_LLVM_getInstruction(MCInst *MI, uint64_t *Size,
+					   const uint8_t *Bytes,
+					   size_t BytesLen, uint64_t Address,
+					   SStream *CS)
+{
+	return getInstruction(MI, Size, Bytes, BytesLen, Address, CS);
+}

thirdparty/capstone/arch/LoongArch/LoongArchDisassemblerExtension.c

@@ -0,0 +1,25 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+/*    Rot127 <unisono@quyllur.org>, 2022-2023 */
+/*    Jiajie Chen <c@jia.je>, 2024 */
+/*    Yanglin Xun <1109673069@qq.com>, 2024 */
+
+#include <capstone/loongarch.h>
+
+#include "LoongArchDisassemblerExtension.h"
+
+#define GET_SUBTARGETINFO_ENUM
+#include "LoongArchGenSubtargetInfo.inc"
+
+bool LoongArch_getFeatureBits(unsigned int mode, unsigned int feature)
+{
+	// handle loongarch32/64
+	if (feature == LoongArch_Feature64Bit) {
+		if (mode & CS_MODE_LOONGARCH64)
+			return true;
+		return false;
+	}
+
+	// otherwise we support everything
+	return true;
+}

thirdparty/capstone/arch/LoongArch/LoongArchDisassemblerExtension.h

@@ -0,0 +1,14 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+/*    Rot127 <unisono@quyllur.org>, 2022-2023 */
+/*    Jiajie Chen <c@jia.je>, 2024 */
+/*    Yanglin Xun <1109673069@qq.com>, 2024 */
+
+#ifndef CS_LOONGARCH_DISASSEMBLER_EXTENSION_H
+#define CS_LOONGARCH_DISASSEMBLER_EXTENSION_H
+
+#include "capstone/capstone.h"
+
+bool LoongArch_getFeatureBits(unsigned int mode, unsigned int feature);
+
+#endif // CS_LOONGARCH_DISASSEMBLER_EXTENSION_H

thirdparty/capstone/arch/LoongArch/LoongArchGenCSAliasEnum.inc

@@ -0,0 +1,20 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+	LOONGARCH_INS_ALIAS_LA, // Real instr.: LOONGARCH_PseudoLA_GOT
+	LOONGARCH_INS_ALIAS_LA_GLOBAL, // Real instr.: LOONGARCH_PseudoLA_GOT
+	LOONGARCH_INS_ALIAS_LA_LOCAL, // Real instr.: LOONGARCH_PseudoLA_PCREL
+	LOONGARCH_INS_ALIAS_NOP, // Real instr.: LOONGARCH_ANDI
+	LOONGARCH_INS_ALIAS_MOVE, // Real instr.: LOONGARCH_OR
+	LOONGARCH_INS_ALIAS_RET, // Real instr.: LOONGARCH_JIRL
+	LOONGARCH_INS_ALIAS_JR, // Real instr.: LOONGARCH_JIRL

thirdparty/capstone/arch/LoongArch/LoongArchGenCSAliasMnemMap.inc

@@ -0,0 +1,20 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+	{ LOONGARCH_INS_ALIAS_LA, "la" },
+	{ LOONGARCH_INS_ALIAS_LA_GLOBAL, "la_global" },
+	{ LOONGARCH_INS_ALIAS_LA_LOCAL, "la_local" },
+	{ LOONGARCH_INS_ALIAS_NOP, "nop" },
+	{ LOONGARCH_INS_ALIAS_MOVE, "move" },
+	{ LOONGARCH_INS_ALIAS_RET, "ret" },
+	{ LOONGARCH_INS_ALIAS_JR, "jr" },

thirdparty/capstone/arch/LoongArch/LoongArchGenCSFeatureName.inc

@@ -0,0 +1,18 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+{ LOONGARCH_FEATURE_ISLA64, "IsLA64" },
+{ LOONGARCH_FEATURE_ISLA32, "IsLA32" },
+{ LOONGARCH_FEATURE_HASLAGLOBALWITHPCREL, "HasLaGlobalWithPcrel" },
+{ LOONGARCH_FEATURE_HASLAGLOBALWITHABS, "HasLaGlobalWithAbs" },
+{ LOONGARCH_FEATURE_HASLALOCALWITHABS, "HasLaLocalWithAbs" },

thirdparty/capstone/arch/LoongArch/LoongArchGenCSOpGroup.inc

@@ -0,0 +1,15 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+  LOONGARCH_OP_GROUP_OPERAND = 0,
+  LOONGARCH_OP_GROUP_ATOMICMEMOP = 1,

thirdparty/capstone/arch/LoongArch/LoongArchGenRegisterInfo.inc

@@ -0,0 +1,708 @@
+#ifdef GET_REGINFO_ENUM
+#undef GET_REGINFO_ENUM
+
+enum {
+  LoongArch_NoRegister,
+  LoongArch_F0 = 1,
+  LoongArch_F1 = 2,
+  LoongArch_F2 = 3,
+  LoongArch_F3 = 4,
+  LoongArch_F4 = 5,
+  LoongArch_F5 = 6,
+  LoongArch_F6 = 7,
+  LoongArch_F7 = 8,
+  LoongArch_F8 = 9,
+  LoongArch_F9 = 10,
+  LoongArch_F10 = 11,
+  LoongArch_F11 = 12,
+  LoongArch_F12 = 13,
+  LoongArch_F13 = 14,
+  LoongArch_F14 = 15,
+  LoongArch_F15 = 16,
+  LoongArch_F16 = 17,
+  LoongArch_F17 = 18,
+  LoongArch_F18 = 19,
+  LoongArch_F19 = 20,
+  LoongArch_F20 = 21,
+  LoongArch_F21 = 22,
+  LoongArch_F22 = 23,
+  LoongArch_F23 = 24,
+  LoongArch_F24 = 25,
+  LoongArch_F25 = 26,
+  LoongArch_F26 = 27,
+  LoongArch_F27 = 28,
+  LoongArch_F28 = 29,
+  LoongArch_F29 = 30,
+  LoongArch_F30 = 31,
+  LoongArch_F31 = 32,
+  LoongArch_FCC0 = 33,
+  LoongArch_FCC1 = 34,
+  LoongArch_FCC2 = 35,
+  LoongArch_FCC3 = 36,
+  LoongArch_FCC4 = 37,
+  LoongArch_FCC5 = 38,
+  LoongArch_FCC6 = 39,
+  LoongArch_FCC7 = 40,
+  LoongArch_FCSR0 = 41,
+  LoongArch_FCSR1 = 42,
+  LoongArch_FCSR2 = 43,
+  LoongArch_FCSR3 = 44,
+  LoongArch_R0 = 45,
+  LoongArch_R1 = 46,
+  LoongArch_R2 = 47,
+  LoongArch_R3 = 48,
+  LoongArch_R4 = 49,
+  LoongArch_R5 = 50,
+  LoongArch_R6 = 51,
+  LoongArch_R7 = 52,
+  LoongArch_R8 = 53,
+  LoongArch_R9 = 54,
+  LoongArch_R10 = 55,
+  LoongArch_R11 = 56,
+  LoongArch_R12 = 57,
+  LoongArch_R13 = 58,
+  LoongArch_R14 = 59,
+  LoongArch_R15 = 60,
+  LoongArch_R16 = 61,
+  LoongArch_R17 = 62,
+  LoongArch_R18 = 63,
+  LoongArch_R19 = 64,
+  LoongArch_R20 = 65,
+  LoongArch_R21 = 66,
+  LoongArch_R22 = 67,
+  LoongArch_R23 = 68,
+  LoongArch_R24 = 69,
+  LoongArch_R25 = 70,
+  LoongArch_R26 = 71,
+  LoongArch_R27 = 72,
+  LoongArch_R28 = 73,
+  LoongArch_R29 = 74,
+  LoongArch_R30 = 75,
+  LoongArch_R31 = 76,
+  LoongArch_SCR0 = 77,
+  LoongArch_SCR1 = 78,
+  LoongArch_SCR2 = 79,
+  LoongArch_SCR3 = 80,
+  LoongArch_VR0 = 81,
+  LoongArch_VR1 = 82,
+  LoongArch_VR2 = 83,
+  LoongArch_VR3 = 84,
+  LoongArch_VR4 = 85,
+  LoongArch_VR5 = 86,
+  LoongArch_VR6 = 87,
+  LoongArch_VR7 = 88,
+  LoongArch_VR8 = 89,
+  LoongArch_VR9 = 90,
+  LoongArch_VR10 = 91,
+  LoongArch_VR11 = 92,
+  LoongArch_VR12 = 93,
+  LoongArch_VR13 = 94,
+  LoongArch_VR14 = 95,
+  LoongArch_VR15 = 96,
+  LoongArch_VR16 = 97,
+  LoongArch_VR17 = 98,
+  LoongArch_VR18 = 99,
+  LoongArch_VR19 = 100,
+  LoongArch_VR20 = 101,
+  LoongArch_VR21 = 102,
+  LoongArch_VR22 = 103,
+  LoongArch_VR23 = 104,
+  LoongArch_VR24 = 105,
+  LoongArch_VR25 = 106,
+  LoongArch_VR26 = 107,
+  LoongArch_VR27 = 108,
+  LoongArch_VR28 = 109,
+  LoongArch_VR29 = 110,
+  LoongArch_VR30 = 111,
+  LoongArch_VR31 = 112,
+  LoongArch_XR0 = 113,
+  LoongArch_XR1 = 114,
+  LoongArch_XR2 = 115,
+  LoongArch_XR3 = 116,
+  LoongArch_XR4 = 117,
+  LoongArch_XR5 = 118,
+  LoongArch_XR6 = 119,
+  LoongArch_XR7 = 120,
+  LoongArch_XR8 = 121,
+  LoongArch_XR9 = 122,
+  LoongArch_XR10 = 123,
+  LoongArch_XR11 = 124,
+  LoongArch_XR12 = 125,
+  LoongArch_XR13 = 126,
+  LoongArch_XR14 = 127,
+  LoongArch_XR15 = 128,
+  LoongArch_XR16 = 129,
+  LoongArch_XR17 = 130,
+  LoongArch_XR18 = 131,
+  LoongArch_XR19 = 132,
+  LoongArch_XR20 = 133,
+  LoongArch_XR21 = 134,
+  LoongArch_XR22 = 135,
+  LoongArch_XR23 = 136,
+  LoongArch_XR24 = 137,
+  LoongArch_XR25 = 138,
+  LoongArch_XR26 = 139,
+  LoongArch_XR27 = 140,
+  LoongArch_XR28 = 141,
+  LoongArch_XR29 = 142,
+  LoongArch_XR30 = 143,
+  LoongArch_XR31 = 144,
+  LoongArch_F0_64 = 145,
+  LoongArch_F1_64 = 146,
+  LoongArch_F2_64 = 147,
+  LoongArch_F3_64 = 148,
+  LoongArch_F4_64 = 149,
+  LoongArch_F5_64 = 150,
+  LoongArch_F6_64 = 151,
+  LoongArch_F7_64 = 152,
+  LoongArch_F8_64 = 153,
+  LoongArch_F9_64 = 154,
+  LoongArch_F10_64 = 155,
+  LoongArch_F11_64 = 156,
+  LoongArch_F12_64 = 157,
+  LoongArch_F13_64 = 158,
+  LoongArch_F14_64 = 159,
+  LoongArch_F15_64 = 160,
+  LoongArch_F16_64 = 161,
+  LoongArch_F17_64 = 162,
+  LoongArch_F18_64 = 163,
+  LoongArch_F19_64 = 164,
+  LoongArch_F20_64 = 165,
+  LoongArch_F21_64 = 166,
+  LoongArch_F22_64 = 167,
+  LoongArch_F23_64 = 168,
+  LoongArch_F24_64 = 169,
+  LoongArch_F25_64 = 170,
+  LoongArch_F26_64 = 171,
+  LoongArch_F27_64 = 172,
+  LoongArch_F28_64 = 173,
+  LoongArch_F29_64 = 174,
+  LoongArch_F30_64 = 175,
+  LoongArch_F31_64 = 176,
+  NUM_TARGET_REGS // 177
+};
+
+// Register classes
+
+enum {
+  LoongArch_FPR32RegClassID = 0,
+  LoongArch_GPRRegClassID = 1,
+  LoongArch_GPRTRegClassID = 2,
+  LoongArch_CFRRegClassID = 3,
+  LoongArch_FCSRRegClassID = 4,
+  LoongArch_SCRRegClassID = 5,
+  LoongArch_FPR64RegClassID = 6,
+  LoongArch_LSX128RegClassID = 7,
+  LoongArch_LASX256RegClassID = 8,
+
+};
+
+// Register alternate name indices
+
+enum {
+  LoongArch_NoRegAltName,	// 0
+  LoongArch_RegAliasName,	// 1
+  NUM_TARGET_REG_ALT_NAMES = 2
+};
+
+// Subregister indices
+
+enum {
+  LoongArch_NoSubRegister,
+  LoongArch_sub_32,	// 1
+  LoongArch_sub_64,	// 2
+  LoongArch_sub_128,	// 3
+  LoongArch_NUM_TARGET_SUBREGS
+};
+#endif // GET_REGINFO_ENUM
+
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+#ifdef GET_REGINFO_MC_DESC
+#undef GET_REGINFO_MC_DESC
+
+static const MCPhysReg LoongArchRegDiffLists[] = {
+  /* 0 */ -32, 64, -144, 0,
+  /* 4 */ 144, -64, 32, 0,
+};
+
+static const uint16_t LoongArchSubRegIdxLists[] = {
+  /* 0 */ 3, 2, 1, 0,
+};
+
+static const MCRegisterDesc LoongArchRegDesc[] = { // Descriptors
+  { 3, 0, 0, 0, 0, 0 },
+  { 47, 3, 4, 3, 12288, 2 },
+  { 116, 3, 4, 3, 12289, 2 },
+  { 171, 3, 4, 3, 12290, 2 },
+  { 226, 3, 4, 3, 12291, 2 },
+  { 495, 3, 4, 3, 12292, 2 },
+  { 539, 3, 4, 3, 12293, 2 },
+  { 583, 3, 4, 3, 12294, 2 },
+  { 627, 3, 4, 3, 12295, 2 },
+  { 666, 3, 4, 3, 12296, 2 },
+  { 705, 3, 4, 3, 12297, 2 },
+  { 0, 3, 4, 3, 12298, 2 },
+  { 69, 3, 4, 3, 12299, 2 },
+  { 138, 3, 4, 3, 12300, 2 },
+  { 193, 3, 4, 3, 12301, 2 },
+  { 248, 3, 4, 3, 12302, 2 },
+  { 506, 3, 4, 3, 12303, 2 },
+  { 550, 3, 4, 3, 12304, 2 },
+  { 594, 3, 4, 3, 12305, 2 },
+  { 638, 3, 4, 3, 12306, 2 },
+  { 677, 3, 4, 3, 12307, 2 },
+  { 14, 3, 4, 3, 12308, 2 },
+  { 83, 3, 4, 3, 12309, 2 },
+  { 152, 3, 4, 3, 12310, 2 },
+  { 207, 3, 4, 3, 12311, 2 },
+  { 262, 3, 4, 3, 12312, 2 },
+  { 520, 3, 4, 3, 12313, 2 },
+  { 564, 3, 4, 3, 12314, 2 },
+  { 608, 3, 4, 3, 12315, 2 },
+  { 652, 3, 4, 3, 12316, 2 },
+  { 691, 3, 4, 3, 12317, 2 },
+  { 28, 3, 4, 3, 12318, 2 },
+  { 97, 3, 4, 3, 12319, 2 },
+  { 42, 3, 3, 3, 12320, 2 },
+  { 111, 3, 3, 3, 12321, 2 },
+  { 166, 3, 3, 3, 12322, 2 },
+  { 221, 3, 3, 3, 12323, 2 },
+  { 490, 3, 3, 3, 12324, 2 },
+  { 534, 3, 3, 3, 12325, 2 },
+  { 578, 3, 3, 3, 12326, 2 },
+  { 622, 3, 3, 3, 12327, 2 },
+  { 55, 3, 3, 3, 12328, 2 },
+  { 124, 3, 3, 3, 12329, 2 },
+  { 179, 3, 3, 3, 12330, 2 },
+  { 234, 3, 3, 3, 12331, 2 },
+  { 52, 3, 3, 3, 12332, 2 },
+  { 121, 3, 3, 3, 12333, 2 },
+  { 176, 3, 3, 3, 12334, 2 },
+  { 231, 3, 3, 3, 12335, 2 },
+  { 499, 3, 3, 3, 12336, 2 },
+  { 543, 3, 3, 3, 12337, 2 },
+  { 587, 3, 3, 3, 12338, 2 },
+  { 631, 3, 3, 3, 12339, 2 },
+  { 670, 3, 3, 3, 12340, 2 },
+  { 709, 3, 3, 3, 12341, 2 },
+  { 5, 3, 3, 3, 12342, 2 },
+  { 74, 3, 3, 3, 12343, 2 },
+  { 143, 3, 3, 3, 12344, 2 },
+  { 198, 3, 3, 3, 12345, 2 },
+  { 253, 3, 3, 3, 12346, 2 },
+  { 511, 3, 3, 3, 12347, 2 },
+  { 555, 3, 3, 3, 12348, 2 },
+  { 599, 3, 3, 3, 12349, 2 },
+  { 643, 3, 3, 3, 12350, 2 },
+  { 682, 3, 3, 3, 12351, 2 },
+  { 19, 3, 3, 3, 12352, 2 },
+  { 88, 3, 3, 3, 12353, 2 },
+  { 157, 3, 3, 3, 12354, 2 },
+  { 212, 3, 3, 3, 12355, 2 },
+  { 267, 3, 3, 3, 12356, 2 },
+  { 525, 3, 3, 3, 12357, 2 },
+  { 569, 3, 3, 3, 12358, 2 },
+  { 613, 3, 3, 3, 12359, 2 },
+  { 657, 3, 3, 3, 12360, 2 },
+  { 696, 3, 3, 3, 12361, 2 },
+  { 33, 3, 3, 3, 12362, 2 },
+  { 102, 3, 3, 3, 12363, 2 },
+  { 50, 3, 3, 3, 12364, 2 },
+  { 119, 3, 3, 3, 12365, 2 },
+  { 174, 3, 3, 3, 12366, 2 },
+  { 229, 3, 3, 3, 12367, 2 },
+  { 61, 1, 6, 1, 12288, 0 },
+  { 130, 1, 6, 1, 12289, 0 },
+  { 185, 1, 6, 1, 12290, 0 },
+  { 240, 1, 6, 1, 12291, 0 },
+  { 498, 1, 6, 1, 12292, 0 },
+  { 542, 1, 6, 1, 12293, 0 },
+  { 586, 1, 6, 1, 12294, 0 },
+  { 630, 1, 6, 1, 12295, 0 },
+  { 669, 1, 6, 1, 12296, 0 },
+  { 708, 1, 6, 1, 12297, 0 },
+  { 4, 1, 6, 1, 12298, 0 },
+  { 73, 1, 6, 1, 12299, 0 },
+  { 142, 1, 6, 1, 12300, 0 },
+  { 197, 1, 6, 1, 12301, 0 },
+  { 252, 1, 6, 1, 12302, 0 },
+  { 510, 1, 6, 1, 12303, 0 },
+  { 554, 1, 6, 1, 12304, 0 },
+  { 598, 1, 6, 1, 12305, 0 },
+  { 642, 1, 6, 1, 12306, 0 },
+  { 681, 1, 6, 1, 12307, 0 },
+  { 18, 1, 6, 1, 12308, 0 },
+  { 87, 1, 6, 1, 12309, 0 },
+  { 156, 1, 6, 1, 12310, 0 },
+  { 211, 1, 6, 1, 12311, 0 },
+  { 266, 1, 6, 1, 12312, 0 },
+  { 524, 1, 6, 1, 12313, 0 },
+  { 568, 1, 6, 1, 12314, 0 },
+  { 612, 1, 6, 1, 12315, 0 },
+  { 656, 1, 6, 1, 12316, 0 },
+  { 695, 1, 6, 1, 12317, 0 },
+  { 32, 1, 6, 1, 12318, 0 },
+  { 101, 1, 6, 1, 12319, 0 },
+  { 65, 0, 3, 0, 12288, 0 },
+  { 134, 0, 3, 0, 12289, 0 },
+  { 189, 0, 3, 0, 12290, 0 },
+  { 244, 0, 3, 0, 12291, 0 },
+  { 502, 0, 3, 0, 12292, 0 },
+  { 546, 0, 3, 0, 12293, 0 },
+  { 590, 0, 3, 0, 12294, 0 },
+  { 634, 0, 3, 0, 12295, 0 },
+  { 673, 0, 3, 0, 12296, 0 },
+  { 712, 0, 3, 0, 12297, 0 },
+  { 9, 0, 3, 0, 12298, 0 },
+  { 78, 0, 3, 0, 12299, 0 },
+  { 147, 0, 3, 0, 12300, 0 },
+  { 202, 0, 3, 0, 12301, 0 },
+  { 257, 0, 3, 0, 12302, 0 },
+  { 515, 0, 3, 0, 12303, 0 },
+  { 559, 0, 3, 0, 12304, 0 },
+  { 603, 0, 3, 0, 12305, 0 },
+  { 647, 0, 3, 0, 12306, 0 },
+  { 686, 0, 3, 0, 12307, 0 },
+  { 23, 0, 3, 0, 12308, 0 },
+  { 92, 0, 3, 0, 12309, 0 },
+  { 161, 0, 3, 0, 12310, 0 },
+  { 216, 0, 3, 0, 12311, 0 },
+  { 271, 0, 3, 0, 12312, 0 },
+  { 529, 0, 3, 0, 12313, 0 },
+  { 573, 0, 3, 0, 12314, 0 },
+  { 617, 0, 3, 0, 12315, 0 },
+  { 661, 0, 3, 0, 12316, 0 },
+  { 700, 0, 3, 0, 12317, 0 },
+  { 37, 0, 3, 0, 12318, 0 },
+  { 106, 0, 3, 0, 12319, 0 },
+  { 297, 2, 5, 2, 12288, 0 },
+  { 324, 2, 5, 2, 12289, 0 },
+  { 344, 2, 5, 2, 12290, 0 },
+  { 364, 2, 5, 2, 12291, 0 },
+  { 384, 2, 5, 2, 12292, 0 },
+  { 404, 2, 5, 2, 12293, 0 },
+  { 424, 2, 5, 2, 12294, 0 },
+  { 444, 2, 5, 2, 12295, 0 },
+  { 464, 2, 5, 2, 12296, 0 },
+  { 484, 2, 5, 2, 12297, 0 },
+  { 276, 2, 5, 2, 12298, 0 },
+  { 303, 2, 5, 2, 12299, 0 },
+  { 330, 2, 5, 2, 12300, 0 },
+  { 350, 2, 5, 2, 12301, 0 },
+  { 370, 2, 5, 2, 12302, 0 },
+  { 390, 2, 5, 2, 12303, 0 },
+  { 410, 2, 5, 2, 12304, 0 },
+  { 430, 2, 5, 2, 12305, 0 },
+  { 450, 2, 5, 2, 12306, 0 },
+  { 470, 2, 5, 2, 12307, 0 },
+  { 283, 2, 5, 2, 12308, 0 },
+  { 310, 2, 5, 2, 12309, 0 },
+  { 337, 2, 5, 2, 12310, 0 },
+  { 357, 2, 5, 2, 12311, 0 },
+  { 377, 2, 5, 2, 12312, 0 },
+  { 397, 2, 5, 2, 12313, 0 },
+  { 417, 2, 5, 2, 12314, 0 },
+  { 437, 2, 5, 2, 12315, 0 },
+  { 457, 2, 5, 2, 12316, 0 },
+  { 477, 2, 5, 2, 12317, 0 },
+  { 290, 2, 5, 2, 12318, 0 },
+  { 317, 2, 5, 2, 12319, 0 },
+};
+
+  // FPR32 Register Class...
+  static const MCPhysReg FPR32[] = {
+    LoongArch_F0, LoongArch_F1, LoongArch_F2, LoongArch_F3, LoongArch_F4, LoongArch_F5, LoongArch_F6, LoongArch_F7, LoongArch_F8, LoongArch_F9, LoongArch_F10, LoongArch_F11, LoongArch_F12, LoongArch_F13, LoongArch_F14, LoongArch_F15, LoongArch_F16, LoongArch_F17, LoongArch_F18, LoongArch_F19, LoongArch_F20, LoongArch_F21, LoongArch_F22, LoongArch_F23, LoongArch_F24, LoongArch_F25, LoongArch_F26, LoongArch_F27, LoongArch_F28, LoongArch_F29, LoongArch_F30, LoongArch_F31, 
+  };
+
+  // FPR32 Bit set.
+  static const uint8_t FPR32Bits[] = {
+    0xfe, 0xff, 0xff, 0xff, 0x01, 
+  };
+
+  // GPR Register Class...
+  static const MCPhysReg GPR[] = {
+    LoongArch_R4, LoongArch_R5, LoongArch_R6, LoongArch_R7, LoongArch_R8, LoongArch_R9, LoongArch_R10, LoongArch_R11, LoongArch_R12, LoongArch_R13, LoongArch_R14, LoongArch_R15, LoongArch_R16, LoongArch_R17, LoongArch_R18, LoongArch_R19, LoongArch_R20, LoongArch_R22, LoongArch_R23, LoongArch_R24, LoongArch_R25, LoongArch_R26, LoongArch_R27, LoongArch_R28, LoongArch_R29, LoongArch_R30, LoongArch_R31, LoongArch_R0, LoongArch_R1, LoongArch_R2, LoongArch_R3, LoongArch_R21, 
+  };
+
+  // GPR Bit set.
+  static const uint8_t GPRBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
+  };
+
+  // GPRT Register Class...
+  static const MCPhysReg GPRT[] = {
+    LoongArch_R4, LoongArch_R5, LoongArch_R6, LoongArch_R7, LoongArch_R8, LoongArch_R9, LoongArch_R10, LoongArch_R11, LoongArch_R12, LoongArch_R13, LoongArch_R14, LoongArch_R15, LoongArch_R16, LoongArch_R17, LoongArch_R18, LoongArch_R19, LoongArch_R20, 
+  };
+
+  // GPRT Bit set.
+  static const uint8_t GPRTBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x03, 
+  };
+
+  // CFR Register Class...
+  static const MCPhysReg CFR[] = {
+    LoongArch_FCC0, LoongArch_FCC1, LoongArch_FCC2, LoongArch_FCC3, LoongArch_FCC4, LoongArch_FCC5, LoongArch_FCC6, LoongArch_FCC7, 
+  };
+
+  // CFR Bit set.
+  static const uint8_t CFRBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, 
+  };
+
+  // FCSR Register Class...
+  static const MCPhysReg FCSR[] = {
+    LoongArch_FCSR0, LoongArch_FCSR1, LoongArch_FCSR2, LoongArch_FCSR3, 
+  };
+
+  // FCSR Bit set.
+  static const uint8_t FCSRBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 
+  };
+
+  // SCR Register Class...
+  static const MCPhysReg SCR[] = {
+    LoongArch_SCR0, LoongArch_SCR1, LoongArch_SCR2, LoongArch_SCR3, 
+  };
+
+  // SCR Bit set.
+  static const uint8_t SCRBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 
+  };
+
+  // FPR64 Register Class...
+  static const MCPhysReg FPR64[] = {
+    LoongArch_F0_64, LoongArch_F1_64, LoongArch_F2_64, LoongArch_F3_64, LoongArch_F4_64, LoongArch_F5_64, LoongArch_F6_64, LoongArch_F7_64, LoongArch_F8_64, LoongArch_F9_64, LoongArch_F10_64, LoongArch_F11_64, LoongArch_F12_64, LoongArch_F13_64, LoongArch_F14_64, LoongArch_F15_64, LoongArch_F16_64, LoongArch_F17_64, LoongArch_F18_64, LoongArch_F19_64, LoongArch_F20_64, LoongArch_F21_64, LoongArch_F22_64, LoongArch_F23_64, LoongArch_F24_64, LoongArch_F25_64, LoongArch_F26_64, LoongArch_F27_64, LoongArch_F28_64, LoongArch_F29_64, LoongArch_F30_64, LoongArch_F31_64, 
+  };
+
+  // FPR64 Bit set.
+  static const uint8_t FPR64Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 
+  };
+
+  // LSX128 Register Class...
+  static const MCPhysReg LSX128[] = {
+    LoongArch_VR0, LoongArch_VR1, LoongArch_VR2, LoongArch_VR3, LoongArch_VR4, LoongArch_VR5, LoongArch_VR6, LoongArch_VR7, LoongArch_VR8, LoongArch_VR9, LoongArch_VR10, LoongArch_VR11, LoongArch_VR12, LoongArch_VR13, LoongArch_VR14, LoongArch_VR15, LoongArch_VR16, LoongArch_VR17, LoongArch_VR18, LoongArch_VR19, LoongArch_VR20, LoongArch_VR21, LoongArch_VR22, LoongArch_VR23, LoongArch_VR24, LoongArch_VR25, LoongArch_VR26, LoongArch_VR27, LoongArch_VR28, LoongArch_VR29, LoongArch_VR30, LoongArch_VR31, 
+  };
+
+  // LSX128 Bit set.
+  static const uint8_t LSX128Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 
+  };
+
+  // LASX256 Register Class...
+  static const MCPhysReg LASX256[] = {
+    LoongArch_XR0, LoongArch_XR1, LoongArch_XR2, LoongArch_XR3, LoongArch_XR4, LoongArch_XR5, LoongArch_XR6, LoongArch_XR7, LoongArch_XR8, LoongArch_XR9, LoongArch_XR10, LoongArch_XR11, LoongArch_XR12, LoongArch_XR13, LoongArch_XR14, LoongArch_XR15, LoongArch_XR16, LoongArch_XR17, LoongArch_XR18, LoongArch_XR19, LoongArch_XR20, LoongArch_XR21, LoongArch_XR22, LoongArch_XR23, LoongArch_XR24, LoongArch_XR25, LoongArch_XR26, LoongArch_XR27, LoongArch_XR28, LoongArch_XR29, LoongArch_XR30, LoongArch_XR31, 
+  };
+
+  // LASX256 Bit set.
+  static const uint8_t LASX256Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 
+  };
+
+static const MCRegisterClass LoongArchMCRegisterClasses[] = {
+  { FPR32, FPR32Bits, sizeof(FPR32Bits) },
+  { GPR, GPRBits, sizeof(GPRBits) },
+  { GPRT, GPRTBits, sizeof(GPRTBits) },
+  { CFR, CFRBits, sizeof(CFRBits) },
+  { FCSR, FCSRBits, sizeof(FCSRBits) },
+  { SCR, SCRBits, sizeof(SCRBits) },
+  { FPR64, FPR64Bits, sizeof(FPR64Bits) },
+  { LSX128, LSX128Bits, sizeof(LSX128Bits) },
+  { LASX256, LASX256Bits, sizeof(LASX256Bits) },
+};
+
+static const uint16_t LoongArchRegEncodingTable[] = {
+  0,
+  0,
+  1,
+  2,
+  3,
+  4,
+  5,
+  6,
+  7,
+  8,
+  9,
+  10,
+  11,
+  12,
+  13,
+  14,
+  15,
+  16,
+  17,
+  18,
+  19,
+  20,
+  21,
+  22,
+  23,
+  24,
+  25,
+  26,
+  27,
+  28,
+  29,
+  30,
+  31,
+  0,
+  1,
+  2,
+  3,
+  4,
+  5,
+  6,
+  7,
+  0,
+  1,
+  2,
+  3,
+  0,
+  1,
+  2,
+  3,
+  4,
+  5,
+  6,
+  7,
+  8,
+  9,
+  10,
+  11,
+  12,
+  13,
+  14,
+  15,
+  16,
+  17,
+  18,
+  19,
+  20,
+  21,
+  22,
+  23,
+  24,
+  25,
+  26,
+  27,
+  28,
+  29,
+  30,
+  31,
+  0,
+  1,
+  2,
+  3,
+  0,
+  1,
+  2,
+  3,
+  4,
+  5,
+  6,
+  7,
+  8,
+  9,
+  10,
+  11,
+  12,
+  13,
+  14,
+  15,
+  16,
+  17,
+  18,
+  19,
+  20,
+  21,
+  22,
+  23,
+  24,
+  25,
+  26,
+  27,
+  28,
+  29,
+  30,
+  31,
+  0,
+  1,
+  2,
+  3,
+  4,
+  5,
+  6,
+  7,
+  8,
+  9,
+  10,
+  11,
+  12,
+  13,
+  14,
+  15,
+  16,
+  17,
+  18,
+  19,
+  20,
+  21,
+  22,
+  23,
+  24,
+  25,
+  26,
+  27,
+  28,
+  29,
+  30,
+  31,
+  0,
+  1,
+  2,
+  3,
+  4,
+  5,
+  6,
+  7,
+  8,
+  9,
+  10,
+  11,
+  12,
+  13,
+  14,
+  15,
+  16,
+  17,
+  18,
+  19,
+  20,
+  21,
+  22,
+  23,
+  24,
+  25,
+  26,
+  27,
+  28,
+  29,
+  30,
+  31,
+};
+#endif // GET_REGINFO_MC_DESC
+
+
+

thirdparty/capstone/arch/LoongArch/LoongArchGenSubtargetInfo.inc

@@ -0,0 +1,38 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+#ifdef GET_SUBTARGETINFO_ENUM
+#undef GET_SUBTARGETINFO_ENUM
+
+enum {
+  LoongArch_Feature32Bit = 0,
+  LoongArch_Feature64Bit = 1,
+  LoongArch_FeatureAutoVec = 2,
+  LoongArch_FeatureBasicD = 3,
+  LoongArch_FeatureBasicF = 4,
+  LoongArch_FeatureExtLASX = 5,
+  LoongArch_FeatureExtLBT = 6,
+  LoongArch_FeatureExtLSX = 7,
+  LoongArch_FeatureExtLVZ = 8,
+  LoongArch_FeatureFrecipe = 9,
+  LoongArch_FeatureRelax = 10,
+  LoongArch_FeatureUAL = 11,
+  LoongArch_LaGlobalWithAbs = 12,
+  LoongArch_LaGlobalWithPcrel = 13,
+  LoongArch_LaLocalWithAbs = 14,
+  LoongArch_NumSubtargetFeatures = 15
+};
+#endif // GET_SUBTARGETINFO_ENUM
+
+
+

thirdparty/capstone/arch/LoongArch/LoongArchInstPrinter.c

@@ -0,0 +1,102 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically translated source file from LLVM. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Only small edits allowed. */
+/* For multiple similar edits, please create a Patch for the translator. */
+
+/* Capstone's C++ file translator: */
+/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
+
+//===- LoongArchInstPrinter.cpp - Convert LoongArch MCInst to asm syntax --===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This class prints an LoongArch MCInst to a .s file.
+//
+//===----------------------------------------------------------------------===//
+
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+#include <capstone/platform.h>
+
+#include "LoongArchMapping.h"
+#include "LoongArchInstPrinter.h"
+
+#define GET_SUBTARGETINFO_ENUM
+#include "LoongArchGenSubtargetInfo.inc"
+
+#define GET_INSTRINFO_ENUM
+#include "LoongArchGenInstrInfo.inc"
+
+#define GET_REGINFO_ENUM
+#include "LoongArchGenRegisterInfo.inc"
+
+#define CONCAT(a, b) CONCAT_(a, b)
+#define CONCAT_(a, b) a##_##b
+
+#define DEBUG_TYPE "loongarch-asm-printer"
+
+// Include the auto-generated portion of the assembly writer.
+#define PRINT_ALIAS_INSTR
+#include "LoongArchGenAsmWriter.inc"
+
+static void printInst(MCInst *MI, uint64_t Address, const char *Annot,
+		      SStream *O)
+{
+	if (!printAliasInstr(MI, Address, O))
+		printInstruction(MI, Address, O);
+	;
+}
+
+void LoongArch_LLVM_printInst(MCInst *MI, uint64_t Address, const char *Annot,
+			      SStream *O)
+{
+	printInst(MI, Address, Annot, O);
+}
+
+const char *LoongArch_LLVM_getRegisterName(unsigned RegNo, unsigned AltIdx)
+{
+	return getRegisterName(RegNo, AltIdx);
+}
+
+static void printRegName(SStream *O, MCRegister Reg)
+{
+	SStream_concat1(O, '$');
+	SStream_concat0(O, getRegisterName(Reg, LoongArch_RegAliasName));
+}
+
+static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
+{
+	add_cs_detail(MI, LOONGARCH_OP_GROUP_OPERAND, OpNo);
+	MCOperand *MO = MCInst_getOperand(MI, (OpNo));
+
+	if (MCOperand_isReg(MO)) {
+		printRegName(O, MCOperand_getReg(MO));
+		return;
+	}
+
+	if (MCOperand_isImm(MO)) {
+		printInt64(O, MCOperand_getImm(MO));
+		return;
+	}
+
+	assert(0 && "Expressions are not supported.");
+}
+
+static void printAtomicMemOp(MCInst *MI, unsigned OpNo, SStream *O)
+{
+	add_cs_detail(MI, LOONGARCH_OP_GROUP_ATOMICMEMOP, OpNo);
+	MCOperand *MO = MCInst_getOperand(MI, (OpNo));
+
+	printRegName(O, MCOperand_getReg(MO));
+}

thirdparty/capstone/arch/LoongArch/LoongArchInstPrinter.h

@@ -0,0 +1,54 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically translated source file from LLVM. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Only small edits allowed. */
+/* For multiple similar edits, please create a Patch for the translator. */
+
+/* Capstone's C++ file translator: */
+/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
+
+//===-- LoongArchInstPrinter.h - Convert LoongArch MCInst to asm syntax ---===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This class prints a LoongArch MCInst to a .s file.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_LOONGARCH_MCTARGETDESC_LOONGARCHINSTPRINTER_H
+#define LLVM_LIB_TARGET_LOONGARCH_MCTARGETDESC_LOONGARCHINSTPRINTER_H
+
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+#include <capstone/platform.h>
+
+#include "../../MCInstPrinter.h"
+#include "../../cs_priv.h"
+#define CONCAT(a, b) CONCAT_(a, b)
+#define CONCAT_(a, b) a##_##b
+
+static void printInst(MCInst *MI, uint64_t Address, const char *Annot,
+		      SStream *O);
+static void printRegName(SStream *O, MCRegister Reg);
+static void printAtomicMemOp(MCInst *MI, unsigned OpNo, SStream *O);
+// Autogenerated by tblgen.
+static void printInstruction(MCInst *MI, uint64_t Address, SStream *O);
+static bool printAliasInstr(MCInst *MI, uint64_t Address, SStream *O);
+static void printCustomAliasOperand(MCInst *MI, uint64_t Address,
+				    unsigned OpIdx, unsigned PrintMethodIdx,
+				    SStream *O);
+static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
+;
+// end namespace llvm
+
+#endif // LLVM_LIB_TARGET_LOONGARCH_MCTARGETDESC_LOONGARCHINSTPRINTER_H

thirdparty/capstone/arch/LoongArch/LoongArchLinkage.h

@@ -0,0 +1,24 @@
+/* Capstone Disassembly Engine */
+/* By Jiajie Chen <c@jia.je>, 2024 */
+/*    Yanglin Xun <1109673069@qq.com>, 2024 */
+
+#ifndef CS_LOONGARCH_LINKAGE_H
+#define CS_LOONGARCH_LINKAGE_H
+
+// Function definitions to call static LLVM functions.
+
+#include "../../MCDisassembler.h"
+#include "../../MCInst.h"
+#include "../../MCRegisterInfo.h"
+#include "../../SStream.h"
+#include "capstone/capstone.h"
+
+const char *LoongArch_LLVM_getRegisterName(unsigned RegNo, unsigned AltIdx);
+void LoongArch_LLVM_printInst(MCInst *MI, uint64_t Address, const char *Annot,
+			      SStream *O);
+DecodeStatus LoongArch_LLVM_getInstruction(MCInst *MI, uint64_t *Size,
+					   const uint8_t *Bytes,
+					   size_t BytesLen, uint64_t Address,
+					   SStream *CS);
+
+#endif // CS_LOONGARCH_LINKAGE_H

thirdparty/capstone/arch/LoongArch/LoongArchMapping.c

@@ -0,0 +1,499 @@
+/* Capstone Disassembly Engine */
+/* By Jiajie Chen <c@jia.je>, 2024 */
+/*    Yanglin Xun <1109673069@qq.com>, 2024 */
+
+#ifdef CAPSTONE_HAS_LOONGARCH
+
+#include <stdio.h>
+#include <string.h>
+
+#include <capstone/capstone.h>
+#include <capstone/loongarch.h>
+
+#include "../../Mapping.h"
+#include "../../MCDisassembler.h"
+#include "../../cs_priv.h"
+#include "../../cs_simple_types.h"
+
+#include "LoongArchMapping.h"
+#include "LoongArchLinkage.h"
+
+#define GET_REGINFO_ENUM
+#define GET_REGINFO_MC_DESC
+#include "LoongArchGenRegisterInfo.inc"
+
+#define GET_INSTRINFO_ENUM
+#include "LoongArchGenInstrInfo.inc"
+
+void LoongArch_init_mri(MCRegisterInfo *MRI)
+{
+	MCRegisterInfo_InitMCRegisterInfo(MRI, LoongArchRegDesc,
+					  sizeof(LoongArchRegDesc), 0, 0,
+					  LoongArchMCRegisterClasses,
+					  ARR_SIZE(LoongArchMCRegisterClasses),
+					  0, 0, LoongArchRegDiffLists, 0,
+					  LoongArchSubRegIdxLists,
+					  ARR_SIZE(LoongArchSubRegIdxLists), 0);
+}
+
+const char *LoongArch_reg_name(csh handle, unsigned int reg)
+{
+	int syntax_opt = ((cs_struct *)(uintptr_t)handle)->syntax;
+
+	if (syntax_opt & CS_OPT_SYNTAX_NOREGNAME) {
+		return LoongArch_LLVM_getRegisterName(reg,
+						      LoongArch_NoRegAltName);
+	}
+	return LoongArch_LLVM_getRegisterName(reg, LoongArch_RegAliasName);
+}
+
+void LoongArch_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
+{
+	// Not used by LoongArch. Information is set after disassembly.
+}
+
+static const char *const insn_name_maps[] = {
+#include "LoongArchGenCSMappingInsnName.inc"
+};
+
+const char *LoongArch_insn_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	if (id < ARR_SIZE(insn_name_maps))
+		return insn_name_maps[id];
+	// not found
+	return NULL;
+#else
+	return NULL;
+#endif
+}
+
+#ifndef CAPSTONE_DIET
+static const name_map group_name_maps[] = {
+	{ LOONGARCH_GRP_INVALID, NULL },
+
+	{ LOONGARCH_GRP_JUMP, "jump" },
+	{ LOONGARCH_GRP_CALL, "call" },
+	{ LOONGARCH_GRP_RET, "return" },
+	{ LOONGARCH_GRP_INT, "int" },
+	{ LOONGARCH_GRP_IRET, "iret" },
+	{ LOONGARCH_GRP_PRIVILEGE, "privilege" },
+	{ LOONGARCH_GRP_BRANCH_RELATIVE, "branch_relative" },
+
+// architecture-specific groups
+#include "LoongArchGenCSFeatureName.inc"
+};
+#endif
+
+const char *LoongArch_group_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
+#else
+	return NULL;
+#endif
+}
+
+void LoongArch_reg_access(const cs_insn *insn, cs_regs regs_read,
+			  uint8_t *regs_read_count, cs_regs regs_write,
+			  uint8_t *regs_write_count)
+{
+	uint8_t i;
+	uint8_t read_count, write_count;
+	cs_loongarch *loongarch = &(insn->detail->loongarch);
+
+	read_count = insn->detail->regs_read_count;
+	write_count = insn->detail->regs_write_count;
+
+	// implicit registers
+	memcpy(regs_read, insn->detail->regs_read,
+	       read_count * sizeof(insn->detail->regs_read[0]));
+	memcpy(regs_write, insn->detail->regs_write,
+	       write_count * sizeof(insn->detail->regs_write[0]));
+
+	// explicit registers
+	for (i = 0; i < loongarch->op_count; i++) {
+		cs_loongarch_op *op = &(loongarch->operands[i]);
+		switch ((int)op->type) {
+		case LOONGARCH_OP_REG:
+			if ((op->access & CS_AC_READ) &&
+			    !arr_exist(regs_read, read_count, op->reg)) {
+				regs_read[read_count] = (uint16_t)op->reg;
+				read_count++;
+			}
+			if ((op->access & CS_AC_WRITE) &&
+			    !arr_exist(regs_write, write_count, op->reg)) {
+				regs_write[write_count] = (uint16_t)op->reg;
+				write_count++;
+			}
+			break;
+		case LOONGARCH_OP_MEM:
+			// registers appeared in memory references always being read
+			if ((op->mem.base != LOONGARCH_REG_INVALID) &&
+			    !arr_exist(regs_read, read_count, op->mem.base)) {
+				regs_read[read_count] = (uint16_t)op->mem.base;
+				read_count++;
+			}
+			if ((insn->detail->writeback) &&
+			    (op->mem.base != LOONGARCH_REG_INVALID) &&
+			    !arr_exist(regs_write, write_count, op->mem.base)) {
+				regs_write[write_count] =
+					(uint16_t)op->mem.base;
+				write_count++;
+			}
+		default:
+			break;
+		}
+	}
+
+	*regs_read_count = read_count;
+	*regs_write_count = write_count;
+}
+
+const insn_map loongarch_insns[] = {
+#include "LoongArchGenCSMappingInsn.inc"
+};
+
+void LoongArch_rewrite_memory_operand(MCInst *MI)
+{
+	// rewrite base + disp operands to memory operands in memory instructions
+	// convert e.g.
+	// ld.d   $t3, $t2, 0x410
+	// op_count: 3
+	//         operands[0].type: REG = t3
+	//         operands[0].access: WRITE
+	//         operands[1].type: REG = t2
+	//         operands[1].access: READ
+	//         operands[2].type: IMM = 0x410
+	//         operands[2].access: READ
+	// to:
+	// op_count: 3
+	//         operands[0].type: REG = t3
+	//         operands[0].access: WRITE
+	//         operands[1].type: MEM
+	//                 operands[1].mem.base: REG = t2
+	//                 operands[1].mem.disp: 0x410
+	//        operands[1].access: READ
+
+	if (!detail_is_set(MI))
+		return;
+
+	const loongarch_suppl_info *suppl_info =
+		map_get_suppl_info(MI, loongarch_insns);
+	if (suppl_info->memory_access == CS_AC_INVALID) {
+		// not memory instruction
+		return;
+	}
+
+	// handle special cases
+	unsigned int base;
+	switch (MI->flat_insn->id) {
+	case LOONGARCH_INS_SC_Q:
+	case LOONGARCH_INS_LLACQ_W:
+	case LOONGARCH_INS_LLACQ_D:
+	case LOONGARCH_INS_SCREL_W:
+	case LOONGARCH_INS_SCREL_D:
+		// last register rj is memory operand
+		LoongArch_get_detail_op(MI, -1)->type = LOONGARCH_OP_MEM;
+		base = LoongArch_get_detail_op(MI, -1)->reg;
+		LoongArch_get_detail_op(MI, -1)->mem.base = base;
+		LoongArch_get_detail_op(MI, -1)->access =
+			suppl_info->memory_access;
+		return;
+
+	case LOONGARCH_INS_LDGT_B:
+	case LOONGARCH_INS_LDGT_H:
+	case LOONGARCH_INS_LDGT_W:
+	case LOONGARCH_INS_LDGT_D:
+	case LOONGARCH_INS_LDLE_B:
+	case LOONGARCH_INS_LDLE_H:
+	case LOONGARCH_INS_LDLE_W:
+	case LOONGARCH_INS_LDLE_D:
+	case LOONGARCH_INS_STGT_B:
+	case LOONGARCH_INS_STGT_H:
+	case LOONGARCH_INS_STGT_W:
+	case LOONGARCH_INS_STGT_D:
+	case LOONGARCH_INS_STLE_B:
+	case LOONGARCH_INS_STLE_H:
+	case LOONGARCH_INS_STLE_W:
+	case LOONGARCH_INS_STLE_D:
+	case LOONGARCH_INS_FLDLE_S:
+	case LOONGARCH_INS_FLDLE_D:
+	case LOONGARCH_INS_FLDGT_S:
+	case LOONGARCH_INS_FLDGT_D:
+	case LOONGARCH_INS_FSTLE_S:
+	case LOONGARCH_INS_FSTLE_D:
+	case LOONGARCH_INS_FSTGT_S:
+	case LOONGARCH_INS_FSTGT_D:
+		// second register rj is memory operand
+		LoongArch_get_detail_op(MI, -2)->type = LOONGARCH_OP_MEM;
+		base = LoongArch_get_detail_op(MI, -2)->reg;
+		LoongArch_get_detail_op(MI, -2)->mem.base = base;
+		LoongArch_get_detail_op(MI, -2)->access =
+			suppl_info->memory_access;
+		return;
+	default:
+		break;
+	}
+
+	switch (suppl_info->form) {
+	case LOONGARCH_INSN_FORM_FMT2RI12:	 // ld, ldl, ldr, st, stl, str
+	case LOONGARCH_INSN_FORM_FMT2RI14:	 // ll, sc, ldptr, stptr
+	case LOONGARCH_INSN_FORM_FMT2RI9_VRI:	 // vldrepl.d
+	case LOONGARCH_INSN_FORM_FMT2RI10_VRI:	 // vldrepl.w
+	case LOONGARCH_INSN_FORM_FMT2RI11_VRI:	 // vldrepl.h
+	case LOONGARCH_INSN_FORM_FMT2RI12_VRI:	 // vld, vldrepl, vst
+	case LOONGARCH_INSN_FORM_FMT2RI8I1_VRII: // vstelm.d
+	case LOONGARCH_INSN_FORM_FMT2RI8I2_VRII: // vstelm.w
+	case LOONGARCH_INSN_FORM_FMT2RI8I3_VRII: // vstelm.h
+	case LOONGARCH_INSN_FORM_FMT2RI8I4_VRII: // vstelm.b
+	case LOONGARCH_INSN_FORM_FMT2RI9_XRI:	 // xvldrepl.d
+	case LOONGARCH_INSN_FORM_FMT2RI10_XRI:	 // xvldrepl.w
+	case LOONGARCH_INSN_FORM_FMT2RI11_XRI:	 // xvldrepl.h
+	case LOONGARCH_INSN_FORM_FMT2RI12_XRI:	 // xvld, xvldrepl, xvst
+	case LOONGARCH_INSN_FORM_FMT2RI8I2_XRII: // xvstelm.d
+	case LOONGARCH_INSN_FORM_FMT2RI8I3_XRII: // xvstelm.w
+	case LOONGARCH_INSN_FORM_FMT2RI8I4_XRII: // xvstelm.h
+	case LOONGARCH_INSN_FORM_FMT2RI8I5_XRII: // xvstelm.b
+	case LOONGARCH_INSN_FORM_FMTPRELD:	 // preld
+	case LOONGARCH_INSN_FORM_FPFMT2RI12:	 // fld, fst
+		// immediate offset
+		LoongArch_get_detail_op(MI, -2)->type = LOONGARCH_OP_MEM;
+		base = LoongArch_get_detail_op(MI, -2)->reg;
+		LoongArch_get_detail_op(MI, -2)->mem.base = base;
+		LoongArch_get_detail_op(MI, -2)->mem.disp =
+			LoongArch_get_detail_op(MI, -1)->imm;
+		LoongArch_get_detail_op(MI, -2)->access =
+			suppl_info->memory_access;
+		LoongArch_dec_op_count(MI);
+		break;
+
+	case LOONGARCH_INSN_FORM_FMT3R: // ldx, stx, amo
+		if (suppl_info->memory_access == CS_AC_READ_WRITE) {
+			// amo: read + write
+			// last register rj is memory operand
+			LoongArch_get_detail_op(MI, -1)->type =
+				LOONGARCH_OP_MEM;
+			base = LoongArch_get_detail_op(MI, -1)->reg;
+			LoongArch_get_detail_op(MI, -1)->mem.base = base;
+			LoongArch_get_detail_op(MI, -1)->access =
+				suppl_info->memory_access;
+			break;
+		}
+		// fallthrough
+
+	case LOONGARCH_INSN_FORM_FPFMTMEM:  // fldx, fstx
+	case LOONGARCH_INSN_FORM_FMT3R_VRR: // vldx, vstx
+	case LOONGARCH_INSN_FORM_FMT3R_XRR: // xvldx, xvstx
+	case LOONGARCH_INSN_FORM_FMTPRELDX: // preldx
+		// register offset
+		LoongArch_get_detail_op(MI, -2)->type = LOONGARCH_OP_MEM;
+		base = LoongArch_get_detail_op(MI, -2)->reg;
+		LoongArch_get_detail_op(MI, -2)->mem.base = base;
+		LoongArch_get_detail_op(MI, -2)->mem.index =
+			LoongArch_get_detail_op(MI, -1)->reg;
+		LoongArch_get_detail_op(MI, -2)->access =
+			suppl_info->memory_access;
+		LoongArch_dec_op_count(MI);
+		break;
+
+	default:
+		assert(0 && "Unknown LoongArch memory instruction");
+		break;
+	}
+}
+
+void LoongArch_set_instr_map_data(MCInst *MI)
+{
+	map_cs_id(MI, loongarch_insns, ARR_SIZE(loongarch_insns));
+	map_implicit_reads(MI, loongarch_insns);
+	map_implicit_writes(MI, loongarch_insns);
+	map_groups(MI, loongarch_insns);
+	const loongarch_suppl_info *suppl_info =
+		map_get_suppl_info(MI, loongarch_insns);
+	if (suppl_info) {
+		LoongArch_get_detail(MI)->format = suppl_info->form;
+	}
+}
+
+bool LoongArch_getInstruction(csh handle, const uint8_t *code, size_t code_len,
+			      MCInst *instr, uint16_t *size, uint64_t address,
+			      void *info)
+{
+	uint64_t temp_size;
+	LoongArch_init_cs_detail(instr);
+	bool Result = LoongArch_LLVM_getInstruction(instr, &temp_size, code,
+						    code_len, address, info) !=
+		      MCDisassembler_Fail;
+	LoongArch_set_instr_map_data(instr);
+	*size = temp_size;
+	return Result;
+}
+
+/// Adds group to the instruction which are not defined in LLVM.
+static void LoongArch_add_cs_groups(MCInst *MI)
+{
+	if (!MI->flat_insn->detail)
+		return;
+	unsigned Opcode = MI->flat_insn->id;
+	cs_loongarch *loongarch = &(MI->flat_insn->detail->loongarch);
+	switch (Opcode) {
+	default:
+		return;
+	case LOONGARCH_INS_BL:
+		add_group(MI, LOONGARCH_GRP_CALL);
+		break;
+	case LOONGARCH_INS_JIRL:
+		if (loongarch->op_count == 3 &&
+		    loongarch->operands[0].reg == LOONGARCH_REG_RA) {
+			// call: jirl ra, rj, offs16
+			add_group(MI, LOONGARCH_GRP_CALL);
+		} else if (loongarch->op_count == 0) {
+			// ret
+			add_group(MI, LOONGARCH_GRP_RET);
+		} else if (loongarch->op_count == 1) {
+			// jr rj
+			add_group(MI, LOONGARCH_GRP_JUMP);
+		}
+		break;
+	case LOONGARCH_INS_B:
+	case LOONGARCH_INS_BCEQZ:
+	case LOONGARCH_INS_BEQ:
+	case LOONGARCH_INS_BEQZ:
+	case LOONGARCH_INS_BGE:
+	case LOONGARCH_INS_BGEU:
+	case LOONGARCH_INS_BLT:
+	case LOONGARCH_INS_BLTU:
+	case LOONGARCH_INS_BNE:
+	case LOONGARCH_INS_BNEZ:
+		add_group(MI, LOONGARCH_GRP_JUMP);
+		add_group(MI, LOONGARCH_GRP_BRANCH_RELATIVE);
+		break;
+	case LOONGARCH_INS_SYSCALL:
+		add_group(MI, LOONGARCH_GRP_INT);
+		break;
+	case LOONGARCH_INS_ERTN:
+		add_group(MI, LOONGARCH_GRP_IRET);
+		add_group(MI, LOONGARCH_GRP_PRIVILEGE);
+		break;
+	case LOONGARCH_INS_CSRXCHG:
+	case LOONGARCH_INS_CACOP:
+	case LOONGARCH_INS_LDDIR:
+	case LOONGARCH_INS_LDPTE:
+	case LOONGARCH_INS_IOCSRRD_B:
+	case LOONGARCH_INS_IOCSRRD_H:
+	case LOONGARCH_INS_IOCSRRD_W:
+	case LOONGARCH_INS_IOCSRRD_D:
+	case LOONGARCH_INS_IOCSRWR_B:
+	case LOONGARCH_INS_IOCSRWR_H:
+	case LOONGARCH_INS_IOCSRWR_W:
+	case LOONGARCH_INS_IOCSRWR_D:
+	case LOONGARCH_INS_TLBCLR:
+	case LOONGARCH_INS_TLBFLUSH:
+	case LOONGARCH_INS_TLBSRCH:
+	case LOONGARCH_INS_TLBRD:
+	case LOONGARCH_INS_TLBWR:
+	case LOONGARCH_INS_INVTLB:
+		add_group(MI, LOONGARCH_GRP_PRIVILEGE);
+		break;
+	}
+}
+
+void LoongArch_printer(MCInst *MI, SStream *O,
+		       void * /* MCRegisterInfo* */ info)
+{
+	MCRegisterInfo *MRI = (MCRegisterInfo *)info;
+	MI->MRI = MRI;
+
+	LoongArch_LLVM_printInst(MI, MI->address, "", O);
+
+	LoongArch_rewrite_memory_operand(MI);
+	LoongArch_add_cs_groups(MI);
+}
+
+void LoongArch_setup_op(cs_loongarch_op *op)
+{
+	memset(op, 0, sizeof(cs_loongarch_op));
+	op->type = LOONGARCH_OP_INVALID;
+}
+
+void LoongArch_init_cs_detail(MCInst *MI)
+{
+	if (detail_is_set(MI)) {
+		unsigned int i;
+
+		memset(get_detail(MI), 0,
+		       offsetof(cs_detail, loongarch) + sizeof(cs_loongarch));
+
+		for (i = 0; i < ARR_SIZE(LoongArch_get_detail(MI)->operands);
+		     i++)
+			LoongArch_setup_op(
+				&LoongArch_get_detail(MI)->operands[i]);
+	}
+}
+
+static const map_insn_ops insn_operands[] = {
+#include "LoongArchGenCSMappingInsnOp.inc"
+};
+
+void LoongArch_set_detail_op_imm(MCInst *MI, unsigned OpNum,
+				 loongarch_op_type ImmType, int64_t Imm)
+{
+	if (!detail_is_set(MI))
+		return;
+	assert((map_get_op_type(MI, OpNum) & ~CS_OP_MEM) == CS_OP_IMM);
+	assert(ImmType == LOONGARCH_OP_IMM);
+
+	LoongArch_get_detail_op(MI, 0)->type = ImmType;
+	LoongArch_get_detail_op(MI, 0)->imm = Imm;
+	LoongArch_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
+	LoongArch_inc_op_count(MI);
+}
+
+void LoongArch_set_detail_op_reg(MCInst *MI, unsigned OpNum, loongarch_reg Reg)
+{
+	if (!detail_is_set(MI))
+		return;
+	assert((map_get_op_type(MI, OpNum) & ~CS_OP_MEM) == CS_OP_REG);
+
+	LoongArch_get_detail_op(MI, 0)->type = LOONGARCH_OP_REG;
+	LoongArch_get_detail_op(MI, 0)->reg = Reg;
+	LoongArch_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
+	LoongArch_inc_op_count(MI);
+}
+
+void LoongArch_add_cs_detail(MCInst *MI, int /* loongarch_op_group */ op_group,
+			     va_list args)
+{
+	if (!detail_is_set(MI))
+		return;
+
+	unsigned OpNum = va_arg(args, unsigned);
+	// Handle memory operands later
+	cs_op_type op_type = map_get_op_type(MI, OpNum) & ~CS_OP_MEM;
+
+	// Fill cs_detail
+	switch (op_group) {
+	default:
+		printf("ERROR: Operand group %d not handled!\n", op_group);
+		assert(0);
+	case LOONGARCH_OP_GROUP_OPERAND:
+		if (op_type == CS_OP_IMM) {
+			LoongArch_set_detail_op_imm(MI, OpNum, LOONGARCH_OP_IMM,
+						    MCInst_getOpVal(MI, OpNum));
+		} else if (op_type == CS_OP_REG) {
+			LoongArch_set_detail_op_reg(MI, OpNum,
+						    MCInst_getOpVal(MI, OpNum));
+		} else
+			assert(0 && "Op type not handled.");
+		break;
+	case LOONGARCH_OP_GROUP_ATOMICMEMOP:
+		assert(op_type == CS_OP_REG);
+		// converted to MEM operand later in LoongArch_rewrite_memory_operand
+		LoongArch_set_detail_op_reg(MI, OpNum,
+					    MCInst_getOpVal(MI, OpNum));
+		break;
+	}
+}
+
+#endif

thirdparty/capstone/arch/LoongArch/LoongArchMapping.h

@@ -0,0 +1,53 @@
+/* Capstone Disassembly Engine */
+/* By Jiajie Chen <c@jia.je>, 2024 */
+/*    Yanglin Xun <1109673069@qq.com>, 2024 */
+
+#ifndef CS_LOONGARCH_MAPPING_H
+#define CS_LOONGARCH_MAPPING_H
+
+#include "../../include/capstone/capstone.h"
+#include "../../utils.h"
+
+typedef enum {
+#include "LoongArchGenCSOpGroup.inc"
+} loongarch_op_group;
+
+void LoongArch_init_mri(MCRegisterInfo *MRI);
+
+// return name of register in friendly string
+const char *LoongArch_reg_name(csh handle, unsigned int reg);
+
+void LoongArch_printer(MCInst *MI, SStream *O,
+		       void * /* MCRegisterInfo* */ info);
+
+// given internal insn id, return public instruction ID
+void LoongArch_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
+
+const char *LoongArch_insn_name(csh handle, unsigned int id);
+
+const char *LoongArch_group_name(csh handle, unsigned int id);
+
+void LoongArch_reg_access(const cs_insn *insn, cs_regs regs_read,
+			  uint8_t *regs_read_count, cs_regs regs_write,
+			  uint8_t *regs_write_count);
+
+bool LoongArch_getInstruction(csh handle, const uint8_t *code, size_t code_len,
+			      MCInst *instr, uint16_t *size, uint64_t address,
+			      void *info);
+
+// cs_detail related functions
+void LoongArch_init_cs_detail(MCInst *MI);
+void LoongArch_add_cs_detail(MCInst *MI, int /* loongarch_op_group */ op_group,
+			     va_list args);
+static inline void add_cs_detail(MCInst *MI,
+				 int /* loongarch_op_group */ op_group, ...)
+{
+	if (!MI->flat_insn->detail)
+		return;
+	va_list args;
+	va_start(args, op_group);
+	LoongArch_add_cs_detail(MI, op_group, args);
+	va_end(args);
+}
+
+#endif // CS_LOONGARCH_MAPPING_H

thirdparty/capstone/arch/LoongArch/LoongArchModule.c

@@ -0,0 +1,53 @@
+/* Capstone Disassembly Engine */
+/* By Jiajie Chen <c@jia.je> 2024 */
+/*    Yanglin Xun <1109673069@qq.com>, 2024 */
+
+#ifdef CAPSTONE_HAS_LOONGARCH
+
+#include <capstone/capstone.h>
+
+#include "LoongArchModule.h"
+#include "../../MCRegisterInfo.h"
+#include "../../cs_priv.h"
+#include "LoongArchMapping.h"
+
+cs_err LoongArch_global_init(cs_struct *ud)
+{
+	MCRegisterInfo *mri;
+	mri = cs_mem_malloc(sizeof(*mri));
+
+	LoongArch_init_mri(mri);
+
+	ud->printer = LoongArch_printer;
+	ud->printer_info = mri;
+	ud->reg_name = LoongArch_reg_name;
+	ud->insn_id = LoongArch_get_insn_id;
+	ud->insn_name = LoongArch_insn_name;
+	ud->group_name = LoongArch_group_name;
+	ud->post_printer = NULL;
+#ifndef CAPSTONE_DIET
+	ud->reg_access = LoongArch_reg_access;
+#endif
+
+	ud->disasm = LoongArch_getInstruction;
+
+	return CS_ERR_OK;
+}
+
+cs_err LoongArch_option(cs_struct *handle, cs_opt_type type, size_t value)
+{
+	switch (type) {
+	case CS_OPT_MODE:
+		handle->mode = (cs_mode)value;
+		break;
+	case CS_OPT_SYNTAX:
+		handle->syntax |= (int)value;
+		break;
+	default:
+		break;
+	}
+
+	return CS_ERR_OK;
+}
+
+#endif

thirdparty/capstone/arch/LoongArch/LoongArchModule.h

@@ -0,0 +1,13 @@
+/* Capstone Disassembly Engine */
+/* By Jiajie Chen <c@jia.je>, 2024 */
+/*    Yanglin Xun <1109673069@qq.com>, 2024 */
+
+#ifndef CS_LOONGARCH_MODULE_H
+#define CS_LOONGARCH_MODULE_H
+
+#include "../../utils.h"
+
+cs_err LoongArch_global_init(cs_struct *ud);
+cs_err LoongArch_option(cs_struct *handle, cs_opt_type type, size_t value);
+
+#endif // CS_LOONGARCH_MODULE_H

thirdparty/capstone/arch/M680X/M680XDisassembler.h

@@ -0,0 +1,17 @@
+/* Capstone Disassembly Engine */
+/* M680X Backend by Wolfgang Schwotzer <wolfgang.schwotzer@gmx.net> 2017 */
+
+#ifndef CS_M680XDISASSEMBLER_H
+#define CS_M680XDISASSEMBLER_H
+
+#include "../../MCInst.h"
+
+bool M680X_getInstruction(csh ud, const uint8_t *code, size_t code_len,
+	MCInst *instr, uint16_t *size, uint64_t address, void *info);
+void M680X_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
+void M680X_reg_access(const cs_insn *insn,
+	cs_regs regs_read, uint8_t *regs_read_count,
+	cs_regs regs_write, uint8_t *regs_write_count);
+
+#endif
+

thirdparty/capstone/arch/M680X/M680XDisassemblerInternals.h

@@ -0,0 +1,57 @@
+/* Capstone Disassembly Engine */
+/* M680X Backend by Wolfgang Schwotzer <wolfgang.schwotzer@gmx.net> 2017 */
+
+#ifndef CS_M680XDISASSEMBLERINTERNALS_H
+#define CS_M680XDISASSEMBLERINTERNALS_H
+
+#include "../../MCInst.h"
+#include "../../include/capstone/m680x.h"
+
+typedef enum e_cpu_type {
+	M680X_CPU_TYPE_INVALID,
+	M680X_CPU_TYPE_6301,	// M680X Hitachi HD6301,HD6303 mode
+	M680X_CPU_TYPE_6309,	// M680X Hitachi HD6309 mode
+	M680X_CPU_TYPE_6800,	// M680X Motorola 6800,6802 mode
+	M680X_CPU_TYPE_6801,	// M680X Motorola 6801,6803 mode
+	M680X_CPU_TYPE_6805,	// M680X Motorola/Freescale M68HC05 mode
+	M680X_CPU_TYPE_6808,	// M680X Motorola/Freescale M68HC08 mode
+	M680X_CPU_TYPE_6809,	// M680X Motorola 6809 mode
+	M680X_CPU_TYPE_6811,	// M680X Motorola/Freescale M68HC11 mode
+	M680X_CPU_TYPE_CPU12,	// M680X Motorola/Freescale CPU12 mode
+	// used on M68HC12/HCS12
+	M680X_CPU_TYPE_HCS08,	// M680X Freescale HCS08 mode
+	M680X_CPU_TYPE_ENDING,
+} e_cpu_type;
+
+struct inst_page1;
+struct inst_pageX;
+
+typedef struct {
+	const struct inst_page1 *inst_page1_table;
+	const struct inst_pageX *inst_overlay_table[2];
+	size_t overlay_table_size[2];
+	uint8_t pageX_prefix[3];
+	const struct inst_pageX *inst_pageX_table[3];
+	size_t pageX_table_size[3];
+	const uint8_t *reg_byte_size;
+	const bool *tfr_reg_valid;
+	m680x_insn insn_cc_not_modified[2];
+} cpu_tables;
+
+/* Private, For internal use only */
+typedef struct m680x_info {
+	const uint8_t *code;	// code buffer
+	uint32_t size;		// byte size of code
+	uint16_t offset;	// address offset of first byte in code buffer
+	e_cpu_type cpu_type;	// The CPU type to be used for disassembling
+	cs_m680x m680x;		// M680X specific properties
+	const cpu_tables *cpu;
+	m680x_insn insn;	// Instruction ID
+	uint8_t insn_size;	// byte size of instruction
+} m680x_info;
+
+extern cs_err M680X_disassembler_init(cs_struct *ud);
+extern cs_err M680X_instprinter_init(cs_struct *ud);
+
+#endif
+

thirdparty/capstone/arch/M680X/M680XInstPrinter.c

@@ -0,0 +1,362 @@
+/* Capstone Disassembly Engine */
+/* M680X Backend by Wolfgang Schwotzer <wolfgang.schwotzer@gmx.net> 2017 */
+
+#ifdef CAPSTONE_HAS_M680X
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <capstone/platform.h>
+
+#include "../../cs_priv.h"
+#include "../../MCInst.h"
+#include "../../SStream.h"
+#include "../../MCRegisterInfo.h"
+#include "../../Mapping.h"
+#include "../../MCInstPrinter.h"
+#include "../../utils.h"
+#include "M680XInstPrinter.h"
+#include "M680XDisassembler.h"
+#include "M680XDisassemblerInternals.h"
+
+#ifndef CAPSTONE_DIET
+static const char s_reg_names[][10] = {
+	"<invalid>", "a", "b", "e", "f", "0", "d", "w", "cc", "dp", "md",
+	"hx", "h", "x", "y", "s", "u", "v", "q", "pc", "tmp2", "tmp3",
+};
+
+static const char s_instruction_names[][6] = {
+	"invld", "aba", "abx", "aby", "adc", "adca", "adcb", "adcd", "adcr",
+	"add", "adda", "addb", "addd", "adde", "addf", "addr", "addw",
+	"aim", "ais", "aix", "and", "anda", "andb", "andcc", "andd", "andr",
+	"asl", "asla", "aslb", "asld",
+	"asr", "asra", "asrb", "asrd", "asrx",
+	"band",
+	"bcc", "bclr", "bcs", "beor", "beq", "bge", "bgnd", "bgt", "bhcc",
+	"bhcs", "bhi",
+	"biand", "bieor", "bih", "bil",
+	"bior", "bit", "bita", "bitb", "bitd", "bitmd", "ble", "bls", "blt",
+	"bmc",
+	"bmi", "bms",
+	"bne", "bor", "bpl", "brclr", "brset", "bra", "brn", "bset", "bsr",
+	"bvc", "bvs",
+	"call", "cba", "cbeq", "cbeqa", "cbeqx", "clc", "cli",
+	"clr", "clra", "clrb", "clrd", "clre", "clrf", "clrh", "clrw", "clrx",
+	"clv", "cmp",
+	"cmpa", "cmpb", "cmpd", "cmpe", "cmpf", "cmpr", "cmps", "cmpu", "cmpw",
+	"cmpx", "cmpy",
+	"com", "coma", "comb", "comd", "come", "comf", "comw", "comx", "cpd",
+	"cphx", "cps", "cpx", "cpy",
+	"cwai", "daa", "dbeq", "dbne", "dbnz", "dbnza", "dbnzx",
+	"dec", "deca", "decb", "decd", "dece", "decf", "decw",
+	"decx", "des", "dex", "dey",
+	"div", "divd", "divq", "ediv", "edivs", "eim", "emacs", "emaxd",
+	"emaxm", "emind", "eminm", "emul", "emuls",
+	"eor", "eora", "eorb", "eord", "eorr", "etbl",
+	"exg", "fdiv", "ibeq", "ibne", "idiv", "idivs", "illgl",
+	"inc", "inca", "incb", "incd", "ince", "incf", "incw", "incx",
+	"ins", "inx", "iny",
+	"jmp", "jsr",
+	"lbcc", "lbcs", "lbeq", "lbge", "lbgt", "lbhi", "lble", "lbls", "lblt",
+	"lbmi", "lbne", "lbpl", "lbra", "lbrn", "lbsr", "lbvc", "lbvs",
+	"lda", "ldaa", "ldab", "ldb", "ldbt", "ldd", "lde", "ldf", "ldhx",
+	"ldmd",
+	"ldq", "lds", "ldu", "ldw", "ldx", "ldy",
+	"leas", "leau", "leax", "leay",
+	"lsl", "lsla", "lslb", "lsld", "lslx",
+	"lsr", "lsra", "lsrb", "lsrd", "lsrw", "lsrx",
+	"maxa", "maxm", "mem", "mina", "minm", "mov", "movb", "movw", "mul",
+	"muld",
+	"neg", "nega", "negb", "negd", "negx",
+	"nop", "nsa", "oim", "ora", "oraa", "orab", "orb", "orcc", "ord", "orr",
+	"psha", "pshb", "pshc", "pshd", "pshh", "pshs", "pshsw", "pshu",
+	"pshuw", "pshx", "pshy",
+	"pula", "pulb", "pulc", "puld", "pulh", "puls", "pulsw", "pulu",
+	"puluw", "pulx", "puly", "rev", "revw",
+	"rol", "rola", "rolb", "rold", "rolw", "rolx",
+	"ror", "rora", "rorb", "rord", "rorw", "rorx",
+	"rsp", "rtc", "rti", "rts", "sba", "sbc", "sbca", "sbcb", "sbcd",
+	"sbcr",
+	"sec", "sei", "sev", "sex", "sexw", "slp", "sta", "staa", "stab", "stb",
+	"stbt", "std", "ste", "stf", "stop", "sthx",
+	"stq", "sts", "stu", "stw", "stx", "sty",
+	"sub", "suba", "subb", "subd", "sube", "subf", "subr", "subw",
+	"swi", "swi2", "swi3",
+	"sync", "tab", "tap", "tax", "tba", "tbeq", "tbl", "tbne", "test",
+	"tfm", "tfr",
+	"tim", "tpa",
+	"tst", "tsta", "tstb", "tstd", "tste", "tstf", "tstw", "tstx",
+	"tsx", "tsy", "txa", "txs", "tys", "wai", "wait", "wav", "wavr",
+	"xgdx", "xgdy",
+};
+
+static const name_map s_group_names[] = {
+	{ M680X_GRP_INVALID, "<invalid>" },
+	{ M680X_GRP_JUMP,  "jump" },
+	{ M680X_GRP_CALL,  "call" },
+	{ M680X_GRP_RET, "return" },
+	{ M680X_GRP_INT, "interrupt" },
+	{ M680X_GRP_IRET,  "interrupt_return" },
+	{ M680X_GRP_PRIV,  "privileged" },
+	{ M680X_GRP_BRAREL,  "branch_relative" },
+};
+#endif
+
+static void printRegName(cs_struct *handle, SStream *OS, unsigned int reg)
+{
+#ifndef CAPSTONE_DIET
+	SStream_concat0(OS, handle->reg_name((csh)handle, reg));
+#endif
+}
+
+static void printInstructionName(cs_struct *handle, SStream *OS,
+	unsigned int insn)
+{
+#ifndef CAPSTONE_DIET
+	SStream_concat0(OS, handle->insn_name((csh)handle, insn));
+#endif
+}
+
+static uint32_t get_unsigned(int32_t value, int byte_size)
+{
+	switch (byte_size) {
+	case 1:
+		return (uint32_t)(value & 0xff);
+
+	case 2:
+		return (uint32_t)(value & 0xffff);
+
+	default:
+	case 4:
+		return (uint32_t)value;
+	}
+}
+
+static void printIncDec(bool isPost, SStream *O, m680x_info *info,
+	cs_m680x_op *op)
+{
+	static const char s_inc_dec[][3] = { "--", "-", "", "+", "++" };
+
+	if (!op->idx.inc_dec)
+		return;
+
+	if ((!isPost && !(op->idx.flags & M680X_IDX_POST_INC_DEC)) ||
+		(isPost && (op->idx.flags & M680X_IDX_POST_INC_DEC))) {
+		const char *prePostfix = "";
+
+		if (info->cpu_type == M680X_CPU_TYPE_CPU12)
+			prePostfix = (op->idx.inc_dec < 0) ? "-" : "+";
+		else if (op->idx.inc_dec >= -2 && (op->idx.inc_dec <= 2)) {
+			prePostfix = (char *)s_inc_dec[op->idx.inc_dec + 2];
+		}
+
+		SStream_concat0(O, prePostfix);
+	}
+}
+
+static void printOperand(MCInst *MI, SStream *O, m680x_info *info,
+	cs_m680x_op *op)
+{
+	switch (op->type) {
+	case M680X_OP_REGISTER:
+		printRegName(MI->csh, O, op->reg);
+		break;
+
+	case M680X_OP_CONSTANT:
+		SStream_concat(O, "%u", op->const_val);
+		break;
+
+	case M680X_OP_IMMEDIATE:
+		if (MI->csh->imm_unsigned)
+			SStream_concat(O, "#%u",
+				get_unsigned(op->imm, op->size));
+		else
+			SStream_concat(O, "#%d", op->imm);
+
+		break;
+
+	case M680X_OP_INDEXED:
+		if (op->idx.flags & M680X_IDX_INDIRECT)
+			SStream_concat0(O, "[");
+
+		if (op->idx.offset_reg != M680X_REG_INVALID)
+			printRegName(MI->csh, O, op->idx.offset_reg);
+		else if (op->idx.offset_bits > 0) {
+			if (op->idx.base_reg == M680X_REG_PC)
+				SStream_concat(O, "$%04x", op->idx.offset_addr);
+			else
+				SStream_concat(O, "%d", op->idx.offset);
+		}
+		else if (op->idx.inc_dec != 0 &&
+			info->cpu_type == M680X_CPU_TYPE_CPU12)
+			SStream_concat(O, "%d", abs(op->idx.inc_dec));
+
+		if (!(op->idx.flags & M680X_IDX_NO_COMMA))
+			SStream_concat(O, ", ");
+
+		printIncDec(false, O, info, op);
+
+		printRegName(MI->csh, O, op->idx.base_reg);
+
+		if (op->idx.base_reg == M680X_REG_PC &&
+			(op->idx.offset_bits > 0))
+			SStream_concat(O, "r");
+
+		printIncDec(true, O, info, op);
+
+		if (op->idx.flags & M680X_IDX_INDIRECT)
+			SStream_concat(O, "]");
+
+		break;
+
+	case M680X_OP_RELATIVE:
+		SStream_concat(O, "$%04x", op->rel.address);
+		break;
+
+	case M680X_OP_DIRECT:
+		SStream_concat(O, "$%02x", op->direct_addr);
+		break;
+
+	case M680X_OP_EXTENDED:
+		if (op->ext.indirect)
+			SStream_concat(O, "[$%04x]", op->ext.address);
+		else {
+			if (op->ext.address < 256) {
+				SStream_concat(O, ">$%04x", op->ext.address);
+			}
+			else {
+				SStream_concat(O, "$%04x", op->ext.address);
+			}
+		}
+
+		break;
+
+	default:
+		SStream_concat0(O, "<invalid_operand>");
+		break;
+	}
+}
+
+static const char *getDelimiter(m680x_info *info, cs_m680x *m680x)
+{
+	bool indexed = false;
+	int count = 0;
+	int i;
+
+	if (info->insn == M680X_INS_TFM)
+		return ", ";
+
+	if (m680x->op_count > 1) {
+		for (i  = 0; i < m680x->op_count; ++i) {
+			if (m680x->operands[i].type == M680X_OP_INDEXED)
+				indexed = true;
+
+			if (m680x->operands[i].type != M680X_OP_REGISTER)
+				count++;
+		}
+	}
+
+	return (indexed && (count >= 1)) ? "; " : ", ";
+};
+
+void M680X_printInst(MCInst *MI, SStream *O, void *PrinterInfo)
+{
+	m680x_info *info = (m680x_info *)PrinterInfo;
+	cs_m680x *m680x = &info->m680x;
+	cs_detail *detail = MI->flat_insn->detail;
+	int suppress_operands = 0;
+	const char *delimiter = getDelimiter(info, m680x);
+	int i;
+
+	if (detail != NULL)
+		memcpy(&detail->m680x, m680x, sizeof(cs_m680x));
+
+	if (info->insn == M680X_INS_INVLD || info->insn == M680X_INS_ILLGL) {
+		if (m680x->op_count)
+			SStream_concat(O, "fcb $%02x", m680x->operands[0].imm);
+		else
+			SStream_concat0(O, "fcb $<unknown>");
+
+		return;
+	}
+
+	printInstructionName(MI->csh, O, info->insn);
+	SStream_concat0(O, " ");
+
+	if ((m680x->flags & M680X_FIRST_OP_IN_MNEM) != 0)
+		suppress_operands++;
+
+	if ((m680x->flags & M680X_SECOND_OP_IN_MNEM) != 0)
+		suppress_operands++;
+
+	for (i  = 0; i < m680x->op_count; ++i) {
+		if (i >= suppress_operands) {
+			printOperand(MI, O, info, &m680x->operands[i]);
+
+			if ((i + 1) != m680x->op_count)
+				SStream_concat0(O, delimiter);
+		}
+	}
+}
+
+const char *M680X_reg_name(csh handle, unsigned int reg)
+{
+#ifndef CAPSTONE_DIET
+
+	if (reg >= ARR_SIZE(s_reg_names))
+		return NULL;
+
+	return s_reg_names[(int)reg];
+#else
+	return NULL;
+#endif
+}
+
+const char *M680X_insn_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+
+	if (id >= ARR_SIZE(s_instruction_names))
+		return NULL;
+	else
+		return s_instruction_names[(int)id];
+
+#else
+	return NULL;
+#endif
+}
+
+const char *M680X_group_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	return id2name(s_group_names, ARR_SIZE(s_group_names), id);
+#else
+	return NULL;
+#endif
+}
+
+cs_err M680X_instprinter_init(cs_struct *ud)
+{
+#ifndef CAPSTONE_DIET
+
+	if (M680X_REG_ENDING != ARR_SIZE(s_reg_names)) {
+		CS_ASSERT(M680X_REG_ENDING == ARR_SIZE(s_reg_names));
+		return CS_ERR_MODE;
+	}
+
+	if (M680X_INS_ENDING != ARR_SIZE(s_instruction_names)) {
+		CS_ASSERT(M680X_INS_ENDING == ARR_SIZE(s_instruction_names));
+		return CS_ERR_MODE;
+	}
+
+	if (M680X_GRP_ENDING != ARR_SIZE(s_group_names)) {
+		CS_ASSERT(M680X_GRP_ENDING == ARR_SIZE(s_group_names));
+		return CS_ERR_MODE;
+	}
+
+#endif
+
+	return CS_ERR_OK;
+}
+
+#endif
+

thirdparty/capstone/arch/M680X/M680XInstPrinter.h

@@ -0,0 +1,25 @@
+/* Capstone Disassembly Engine */
+/* M680X Backend by Wolfgang Schwotzer <wolfgang.schwotzer@gmx.net> 2017 */
+
+#ifndef CS_M680XINSTPRINTER_H
+#define CS_M680XINSTPRINTER_H
+
+
+#include "capstone/capstone.h"
+#include "../../MCRegisterInfo.h"
+#include "../../MCInst.h"
+
+struct SStream;
+
+void M680X_init(MCRegisterInfo *MRI);
+
+void M680X_printInst(MCInst *MI, struct SStream *O, void *Info);
+const char *M680X_reg_name(csh handle, unsigned int reg);
+const char *M680X_insn_name(csh handle, unsigned int id);
+const char *M680X_group_name(csh handle, unsigned int id);
+void M680X_post_printer(csh handle, cs_insn *flat_insn, char *insn_asm,
+	MCInst *mci);
+
+#endif
+
+

thirdparty/capstone/arch/M680X/M680XModule.c

@@ -0,0 +1,77 @@
+/* Capstone Disassembly Engine */
+/* M680X Backend by Wolfgang Schwotzer <wolfgang.schwotzer@gmx.net> 2017 */
+
+#ifdef CAPSTONE_HAS_M680X
+
+#include "../../utils.h"
+#include "../../MCRegisterInfo.h"
+#include "M680XDisassembler.h"
+#include "M680XDisassemblerInternals.h"
+#include "M680XInstPrinter.h"
+#include "M680XModule.h"
+
+cs_err M680X_global_init(cs_struct *ud)
+{
+	m680x_info *info;
+	cs_err errcode;
+
+	/* Do some validation checks */
+	errcode = M680X_disassembler_init(ud);
+
+	if (errcode != CS_ERR_OK)
+		return errcode;
+
+	errcode =  M680X_instprinter_init(ud);
+
+	if (errcode != CS_ERR_OK)
+		return errcode;
+
+	// verify if requested mode is valid
+	if (ud->mode & ~(CS_MODE_M680X_6800 | CS_MODE_M680X_6801 |
+			CS_MODE_M680X_6805 | CS_MODE_M680X_6808 |
+			CS_MODE_M680X_6809 | CS_MODE_M680X_6811 |
+			CS_MODE_M680X_6301 | CS_MODE_M680X_6309 |
+			CS_MODE_M680X_CPU12 | CS_MODE_M680X_HCS08)) {
+		// At least one mode is not supported by M680X
+		return CS_ERR_MODE;
+	}
+
+	if (!(ud->mode & (CS_MODE_M680X_6800 | CS_MODE_M680X_6801 |
+				CS_MODE_M680X_6805 | CS_MODE_M680X_6808 |
+				CS_MODE_M680X_6809 | CS_MODE_M680X_6811 |
+				CS_MODE_M680X_6301 | CS_MODE_M680X_6309 |
+				CS_MODE_M680X_CPU12 | CS_MODE_M680X_HCS08))) {
+		// At least the cpu type has to be selected. No default.
+		return CS_ERR_MODE;
+	}
+
+	info = cs_mem_malloc(sizeof(m680x_info));
+
+	if (!info)
+		return CS_ERR_MEM;
+
+	ud->printer = M680X_printInst;
+	ud->printer_info = info;
+	ud->getinsn_info = NULL;
+	ud->disasm = M680X_getInstruction;
+	ud->reg_name = M680X_reg_name;
+	ud->insn_id = M680X_get_insn_id;
+	ud->insn_name = M680X_insn_name;
+	ud->group_name = M680X_group_name;
+	ud->skipdata_size = 1;
+	ud->post_printer = NULL;
+#ifndef CAPSTONE_DIET
+	ud->reg_access = M680X_reg_access;
+#endif
+
+	return CS_ERR_OK;
+}
+
+cs_err M680X_option(cs_struct *handle, cs_opt_type type, size_t value)
+{
+	//TODO
+	return CS_ERR_OK;
+}
+
+#endif
+

thirdparty/capstone/arch/M680X/M680XModule.h

@@ -0,0 +1,12 @@
+/* Capstone Disassembly Engine */
+/* By Travis Finkenauer <tmfinken@gmail.com>, 2018 */
+
+#ifndef CS_M680X_MODULE_H
+#define CS_M680X_MODULE_H
+
+#include "../../utils.h"
+
+cs_err M680X_global_init(cs_struct *ud);
+cs_err M680X_option(cs_struct *handle, cs_opt_type type, size_t value);
+
+#endif

thirdparty/capstone/arch/M680X/cpu12.inc

@@ -0,0 +1,335 @@
+
+// CPU12 instructions on PAGE1
+static const inst_page1 g_cpu12_inst_page1_table[256] = {
+	// 0x0x
+	{ M680X_INS_BGND, inh_hid, inh_hid },
+	{ M680X_INS_MEM, inh_hid, inh_hid },
+	{ M680X_INS_INY, inh_hid, inh_hid },
+	{ M680X_INS_DEY, inh_hid, inh_hid },
+	{ M680X_INS_DBEQ, loop_hid, inh_hid }, // or DBNE/IBEQ/IBNE/TBEQ/TBNE
+	{ M680X_INS_JMP, idx12_hid, inh_hid },
+	{ M680X_INS_JMP, ext_hid, inh_hid },
+	{ M680X_INS_BSR, rel8_hid, inh_hid },
+	{ M680X_INS_INX, inh_hid, inh_hid },
+	{ M680X_INS_DEX, inh_hid, inh_hid },
+	{ M680X_INS_RTC, inh_hid, inh_hid },
+	{ M680X_INS_RTI, inh_hid, inh_hid },
+	{ M680X_INS_BSET, idx12_hid, imm8_hid },
+	{ M680X_INS_BCLR, idx12_hid, imm8_hid },
+	{ M680X_INS_BRSET, idx12_hid, imm8rel_hid },
+	{ M680X_INS_BRCLR, idx12_hid, imm8rel_hid },
+	// 0x1x
+	{ M680X_INS_ANDCC, imm8_hid, inh_hid },
+	{ M680X_INS_EDIV, inh_hid, inh_hid },
+	{ M680X_INS_MUL, inh_hid, inh_hid },
+	{ M680X_INS_EMUL, inh_hid, inh_hid },
+	{ M680X_INS_ORCC, imm8_hid, inh_hid },
+	{ M680X_INS_JSR, idx12_hid, inh_hid },
+	{ M680X_INS_JSR, ext_hid, inh_hid },
+	{ M680X_INS_JSR, dir_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_LEAY, idx12_hid, inh_hid },
+	{ M680X_INS_LEAX, idx12_hid, inh_hid },
+	{ M680X_INS_LEAS, idx12_hid, inh_hid },
+	{ M680X_INS_BSET, ext_hid, imm8_hid },
+	{ M680X_INS_BCLR, ext_hid, imm8_hid },
+	{ M680X_INS_BRSET, ext_hid, imm8rel_hid },
+	{ M680X_INS_BRCLR, ext_hid, imm8rel_hid },
+	// 0x2x, relative branch instructions
+	{ M680X_INS_BRA, rel8_hid, inh_hid },
+	{ M680X_INS_BRN, rel8_hid, inh_hid },
+	{ M680X_INS_BHI, rel8_hid, inh_hid },
+	{ M680X_INS_BLS, rel8_hid, inh_hid },
+	{ M680X_INS_BCC, rel8_hid, inh_hid },
+	{ M680X_INS_BCS, rel8_hid, inh_hid },
+	{ M680X_INS_BNE, rel8_hid, inh_hid },
+	{ M680X_INS_BEQ, rel8_hid, inh_hid },
+	{ M680X_INS_BVC, rel8_hid, inh_hid },
+	{ M680X_INS_BVS, rel8_hid, inh_hid },
+	{ M680X_INS_BPL, rel8_hid, inh_hid },
+	{ M680X_INS_BMI, rel8_hid, inh_hid },
+	{ M680X_INS_BGE, rel8_hid, inh_hid },
+	{ M680X_INS_BLT, rel8_hid, inh_hid },
+	{ M680X_INS_BGT, rel8_hid, inh_hid },
+	{ M680X_INS_BLE, rel8_hid, inh_hid },
+	// 0x3x
+	{ M680X_INS_PULX, inh_hid, inh_hid },
+	{ M680X_INS_PULY, inh_hid, inh_hid },
+	{ M680X_INS_PULA, inh_hid, inh_hid },
+	{ M680X_INS_PULB, inh_hid, inh_hid },
+	{ M680X_INS_PSHX, inh_hid, inh_hid },
+	{ M680X_INS_PSHY, inh_hid, inh_hid },
+	{ M680X_INS_PSHA, inh_hid, inh_hid },
+	{ M680X_INS_PSHB, inh_hid, inh_hid },
+	{ M680X_INS_PULC, inh_hid, inh_hid },
+	{ M680X_INS_PSHC, inh_hid, inh_hid },
+	{ M680X_INS_PULD, inh_hid, inh_hid },
+	{ M680X_INS_PSHD, inh_hid, inh_hid },
+	{ M680X_INS_WAVR, inh_hid, inh_hid },
+	{ M680X_INS_RTS, inh_hid, inh_hid },
+	{ M680X_INS_WAI, inh_hid, inh_hid },
+	{ M680X_INS_SWI, inh_hid, inh_hid },
+	// 0x4x
+	{ M680X_INS_NEGA, inh_hid, inh_hid },
+	{ M680X_INS_COMA, inh_hid, inh_hid },
+	{ M680X_INS_INCA, inh_hid, inh_hid },
+	{ M680X_INS_DECA, inh_hid, inh_hid },
+	{ M680X_INS_LSRA, inh_hid, inh_hid },
+	{ M680X_INS_ROLA, inh_hid, inh_hid },
+	{ M680X_INS_RORA, inh_hid, inh_hid },
+	{ M680X_INS_ASRA, inh_hid, inh_hid },
+	{ M680X_INS_ASLA, inh_hid, inh_hid },
+	{ M680X_INS_LSRD, inh_hid, inh_hid },
+	{ M680X_INS_CALL, ext_hid, index_hid },
+	{ M680X_INS_CALL, idx12_hid, index_hid },
+	{ M680X_INS_BSET, dir_hid, imm8_hid },
+	{ M680X_INS_BCLR, dir_hid, imm8_hid },
+	{ M680X_INS_BRSET, dir_hid, imm8rel_hid },
+	{ M680X_INS_BRCLR, dir_hid, imm8rel_hid },
+	// 0x5x
+	{ M680X_INS_NEGB, inh_hid, inh_hid },
+	{ M680X_INS_COMB, inh_hid, inh_hid },
+	{ M680X_INS_INCB, inh_hid, inh_hid },
+	{ M680X_INS_DECB, inh_hid, inh_hid },
+	{ M680X_INS_LSRB, inh_hid, inh_hid },
+	{ M680X_INS_ROLB, inh_hid, inh_hid },
+	{ M680X_INS_RORB, inh_hid, inh_hid },
+	{ M680X_INS_ASRB, inh_hid, inh_hid },
+	{ M680X_INS_ASLB, inh_hid, inh_hid },
+	{ M680X_INS_ASLD, inh_hid, inh_hid },
+	{ M680X_INS_STAA, dir_hid, inh_hid },
+	{ M680X_INS_STAB, dir_hid, inh_hid },
+	{ M680X_INS_STD, dir_hid, inh_hid },
+	{ M680X_INS_STY, dir_hid, inh_hid },
+	{ M680X_INS_STX, dir_hid, inh_hid },
+	{ M680X_INS_STS, dir_hid, inh_hid },
+	// 0x6x
+	{ M680X_INS_NEG, idx12_hid, inh_hid },
+	{ M680X_INS_COM, idx12_hid, inh_hid },
+	{ M680X_INS_INC, idx12_hid, inh_hid },
+	{ M680X_INS_DEC, idx12_hid, inh_hid },
+	{ M680X_INS_LSR, idx12_hid, inh_hid },
+	{ M680X_INS_ROL, idx12_hid, inh_hid },
+	{ M680X_INS_ROR, idx12_hid, inh_hid },
+	{ M680X_INS_ASR, idx12_hid, inh_hid },
+	{ M680X_INS_ASL, idx12_hid, inh_hid },
+	{ M680X_INS_CLR, idx12_hid, inh_hid },
+	{ M680X_INS_STAA, idx12_hid, inh_hid },
+	{ M680X_INS_STAB, idx12_hid, inh_hid },
+	{ M680X_INS_STD, idx12_hid, inh_hid },
+	{ M680X_INS_STY, idx12_hid, inh_hid },
+	{ M680X_INS_STX, idx12_hid, inh_hid },
+	{ M680X_INS_STS, idx12_hid, inh_hid },
+	// 0x7x
+	{ M680X_INS_NEG, ext_hid, inh_hid },
+	{ M680X_INS_COM, ext_hid, inh_hid },
+	{ M680X_INS_INC, ext_hid, inh_hid },
+	{ M680X_INS_DEC, ext_hid, inh_hid },
+	{ M680X_INS_LSR, ext_hid, inh_hid },
+	{ M680X_INS_ROL, ext_hid, inh_hid },
+	{ M680X_INS_ROR, ext_hid, inh_hid },
+	{ M680X_INS_ASR, ext_hid, inh_hid },
+	{ M680X_INS_ASL, ext_hid, inh_hid },
+	{ M680X_INS_CLR, ext_hid, inh_hid },
+	{ M680X_INS_STAA, ext_hid, inh_hid },
+	{ M680X_INS_STAB, ext_hid, inh_hid },
+	{ M680X_INS_STD, ext_hid, inh_hid },
+	{ M680X_INS_STY, ext_hid, inh_hid },
+	{ M680X_INS_STX, ext_hid, inh_hid },
+	{ M680X_INS_STS, ext_hid, inh_hid },
+	// 0x8x
+	{ M680X_INS_SUBA, imm8_hid, inh_hid },
+	{ M680X_INS_CMPA, imm8_hid, inh_hid },
+	{ M680X_INS_SBCA, imm8_hid, inh_hid },
+	{ M680X_INS_SUBD, imm16_hid, inh_hid },
+	{ M680X_INS_ANDA, imm8_hid, inh_hid },
+	{ M680X_INS_BITA, imm8_hid, inh_hid },
+	{ M680X_INS_LDAA, imm8_hid, inh_hid },
+	{ M680X_INS_CLRA, inh_hid, inh_hid },
+	{ M680X_INS_EORA, imm8_hid, inh_hid },
+	{ M680X_INS_ADCA, imm8_hid, inh_hid },
+	{ M680X_INS_ORAA, imm8_hid, inh_hid },
+	{ M680X_INS_ADDA, imm8_hid, inh_hid },
+	{ M680X_INS_CPD, imm16_hid, inh_hid },
+	{ M680X_INS_CPY, imm16_hid, inh_hid },
+	{ M680X_INS_CPX, imm16_hid, inh_hid },
+	{ M680X_INS_CPS, imm16_hid, inh_hid },
+	// 0x9x
+	{ M680X_INS_SUBA, dir_hid, inh_hid },
+	{ M680X_INS_CMPA, dir_hid, inh_hid },
+	{ M680X_INS_SBCA, dir_hid, inh_hid },
+	{ M680X_INS_SUBD, dir_hid, inh_hid },
+	{ M680X_INS_ANDA, dir_hid, inh_hid },
+	{ M680X_INS_BITA, dir_hid, inh_hid },
+	{ M680X_INS_LDAA, dir_hid, inh_hid },
+	{ M680X_INS_TSTA, inh_hid, inh_hid },
+	{ M680X_INS_EORA, dir_hid, inh_hid },
+	{ M680X_INS_ADCA, dir_hid, inh_hid },
+	{ M680X_INS_ORAA, dir_hid, inh_hid },
+	{ M680X_INS_ADDA, dir_hid, inh_hid },
+	{ M680X_INS_CPD, dir_hid, inh_hid },
+	{ M680X_INS_CPY, dir_hid, inh_hid },
+	{ M680X_INS_CPX, dir_hid, inh_hid },
+	{ M680X_INS_CPS, dir_hid, inh_hid },
+	// 0xAx
+	{ M680X_INS_SUBA, idx12_hid, inh_hid },
+	{ M680X_INS_CMPA, idx12_hid, inh_hid },
+	{ M680X_INS_SBCA, idx12_hid, inh_hid },
+	{ M680X_INS_SUBD, idx12_hid, inh_hid },
+	{ M680X_INS_ANDA, idx12_hid, inh_hid },
+	{ M680X_INS_BITA, idx12_hid, inh_hid },
+	{ M680X_INS_LDAA, idx12_hid, inh_hid },
+	{ M680X_INS_NOP, inh_hid, inh_hid },
+	{ M680X_INS_EORA, idx12_hid, inh_hid },
+	{ M680X_INS_ADCA, idx12_hid, inh_hid },
+	{ M680X_INS_ORAA, idx12_hid, inh_hid },
+	{ M680X_INS_ADDA, idx12_hid, inh_hid },
+	{ M680X_INS_CPD, idx12_hid, inh_hid },
+	{ M680X_INS_CPY, idx12_hid, inh_hid },
+	{ M680X_INS_CPX, idx12_hid, inh_hid },
+	{ M680X_INS_CPS, idx12_hid, inh_hid },
+	// 0xBx
+	{ M680X_INS_SUBA, ext_hid, inh_hid },
+	{ M680X_INS_CMPA, ext_hid, inh_hid },
+	{ M680X_INS_SBCA, ext_hid, inh_hid },
+	{ M680X_INS_SUBD, ext_hid, inh_hid },
+	{ M680X_INS_ANDA, ext_hid, inh_hid },
+	{ M680X_INS_BITA, ext_hid, inh_hid },
+	{ M680X_INS_LDAA, ext_hid, inh_hid },
+	{ M680X_INS_TFR, rr12_hid, inh_hid }, // or EXG
+	{ M680X_INS_EORA, ext_hid, inh_hid },
+	{ M680X_INS_ADCA, ext_hid, inh_hid },
+	{ M680X_INS_ORAA, ext_hid, inh_hid },
+	{ M680X_INS_ADDA, ext_hid, inh_hid },
+	{ M680X_INS_CPD, ext_hid, inh_hid },
+	{ M680X_INS_CPY, ext_hid, inh_hid },
+	{ M680X_INS_CPX, ext_hid, inh_hid },
+	{ M680X_INS_CPS, ext_hid, inh_hid },
+	// 0xCx
+	{ M680X_INS_SUBB, imm8_hid, inh_hid },
+	{ M680X_INS_CMPB, imm8_hid, inh_hid },
+	{ M680X_INS_SBCB, imm8_hid, inh_hid },
+	{ M680X_INS_ADDD, imm16_hid, inh_hid },
+	{ M680X_INS_ANDB, imm8_hid, inh_hid },
+	{ M680X_INS_BITB, imm8_hid, inh_hid },
+	{ M680X_INS_LDAB, imm8_hid, inh_hid },
+	{ M680X_INS_CLRB, inh_hid, inh_hid },
+	{ M680X_INS_EORB, imm8_hid, inh_hid },
+	{ M680X_INS_ADCB, imm8_hid, inh_hid },
+	{ M680X_INS_ORAB, imm8_hid, inh_hid },
+	{ M680X_INS_ADDB, imm8_hid, inh_hid },
+	{ M680X_INS_LDD, imm16_hid, inh_hid },
+	{ M680X_INS_LDY, imm16_hid, inh_hid },
+	{ M680X_INS_LDX, imm16_hid, inh_hid },
+	{ M680X_INS_LDS, imm16_hid, inh_hid },
+	// 0xDx
+	{ M680X_INS_SUBB, dir_hid, inh_hid },
+	{ M680X_INS_CMPB, dir_hid, inh_hid },
+	{ M680X_INS_SBCB, dir_hid, inh_hid },
+	{ M680X_INS_ADDD, dir_hid, inh_hid },
+	{ M680X_INS_ANDB, dir_hid, inh_hid },
+	{ M680X_INS_BITB, dir_hid, inh_hid },
+	{ M680X_INS_LDAB, dir_hid, inh_hid },
+	{ M680X_INS_TSTB, inh_hid, inh_hid },
+	{ M680X_INS_EORB, dir_hid, inh_hid },
+	{ M680X_INS_ADCB, dir_hid, inh_hid },
+	{ M680X_INS_ORAB, dir_hid, inh_hid },
+	{ M680X_INS_ADDB, dir_hid, inh_hid },
+	{ M680X_INS_LDD, dir_hid, inh_hid },
+	{ M680X_INS_LDY, dir_hid, inh_hid },
+	{ M680X_INS_LDX, dir_hid, inh_hid },
+	{ M680X_INS_LDS, dir_hid, inh_hid },
+	// 0xEx
+	{ M680X_INS_SUBB, idx12_hid, inh_hid },
+	{ M680X_INS_CMPB, idx12_hid, inh_hid },
+	{ M680X_INS_SBCB, idx12_hid, inh_hid },
+	{ M680X_INS_ADDD, idx12_hid, inh_hid },
+	{ M680X_INS_ANDB, idx12_hid, inh_hid },
+	{ M680X_INS_BITB, idx12_hid, inh_hid },
+	{ M680X_INS_LDAB, idx12_hid, inh_hid },
+	{ M680X_INS_TST, idx12_hid, inh_hid },
+	{ M680X_INS_EORB, idx12_hid, inh_hid },
+	{ M680X_INS_ADCB, idx12_hid, inh_hid },
+	{ M680X_INS_ORAB, idx12_hid, inh_hid },
+	{ M680X_INS_ADDB, idx12_hid, inh_hid },
+	{ M680X_INS_LDD, idx12_hid, inh_hid },
+	{ M680X_INS_LDY, idx12_hid, inh_hid },
+	{ M680X_INS_LDX, idx12_hid, inh_hid },
+	{ M680X_INS_LDS, idx12_hid, inh_hid },
+	// 0xFx
+	{ M680X_INS_SUBA, ext_hid, inh_hid },
+	{ M680X_INS_CMPA, ext_hid, inh_hid },
+	{ M680X_INS_SBCA, ext_hid, inh_hid },
+	{ M680X_INS_ADDD, ext_hid, inh_hid },
+	{ M680X_INS_ANDA, ext_hid, inh_hid },
+	{ M680X_INS_BITA, ext_hid, inh_hid },
+	{ M680X_INS_LDAA, ext_hid, inh_hid },
+	{ M680X_INS_TST, ext_hid, inh_hid },
+	{ M680X_INS_EORA, ext_hid, inh_hid },
+	{ M680X_INS_ADCA, ext_hid, inh_hid },
+	{ M680X_INS_ORAA, ext_hid, inh_hid },
+	{ M680X_INS_ADDA, ext_hid, inh_hid },
+	{ M680X_INS_LDD, ext_hid, inh_hid },
+	{ M680X_INS_LDY, ext_hid, inh_hid },
+	{ M680X_INS_LDX, ext_hid, inh_hid },
+	{ M680X_INS_LDS, ext_hid, inh_hid },
+};
+
+// CPU12 instructions on PAGE2
+static const inst_pageX g_cpu12_inst_page2_table[] = {
+	{ 0x00, M680X_INS_MOVW, imm16i12x_hid, inh_hid },
+	{ 0x01, M680X_INS_MOVW, exti12x_hid, inh_hid },
+	{ 0x02, M680X_INS_MOVW, idx12_hid, idx12_hid },
+	{ 0x03, M680X_INS_MOVW, imm16_hid,  ext_hid },
+	{ 0x04, M680X_INS_MOVW, ext_hid, ext_hid },
+	{ 0x05, M680X_INS_MOVW, idx12_hid, ext_hid },
+	{ 0x06, M680X_INS_ABA, inh_hid, inh_hid },
+	{ 0x07, M680X_INS_DAA, inh_hid, inh_hid },
+	{ 0x08, M680X_INS_MOVB, imm8i12x_hid, inh_hid },
+	{ 0x09, M680X_INS_MOVB, exti12x_hid, inh_hid },
+	{ 0x0a, M680X_INS_MOVB, idx12_hid, idx12_hid },
+	{ 0x0b, M680X_INS_MOVB, imm8_hid, ext_hid },
+	{ 0x0c, M680X_INS_MOVB, ext_hid, ext_hid },
+	{ 0x0d, M680X_INS_MOVB, idx12_hid, ext_hid },
+	{ 0x0e, M680X_INS_TAB, inh_hid, inh_hid },
+	{ 0x0f, M680X_INS_TBA, inh_hid, inh_hid },
+	{ 0x10, M680X_INS_IDIV, inh_hid, inh_hid },
+	{ 0x11, M680X_INS_FDIV, inh_hid, inh_hid },
+	{ 0x12, M680X_INS_EMACS, ext_hid, inh_hid },
+	{ 0x13, M680X_INS_EMULS, inh_hid, inh_hid },
+	{ 0x14, M680X_INS_EDIVS, inh_hid, inh_hid },
+	{ 0x15, M680X_INS_IDIVS, inh_hid, inh_hid },
+	{ 0x16, M680X_INS_SBA, inh_hid, inh_hid },
+	{ 0x17, M680X_INS_CBA, inh_hid, inh_hid },
+	{ 0x18, M680X_INS_MAXA, idx12_hid, inh_hid },
+	{ 0x19, M680X_INS_MINA, idx12_hid, inh_hid },
+	{ 0x1a, M680X_INS_EMAXD, idx12_hid, inh_hid },
+	{ 0x1b, M680X_INS_EMIND, idx12_hid, inh_hid },
+	{ 0x1c, M680X_INS_MAXM, idx12_hid, inh_hid },
+	{ 0x1d, M680X_INS_MINM, idx12_hid, inh_hid },
+	{ 0x1e, M680X_INS_EMAXM, idx12_hid, inh_hid },
+	{ 0x1f, M680X_INS_EMINM, idx12_hid, inh_hid },
+	{ 0x20, M680X_INS_LBRA, rel16_hid, inh_hid },
+	{ 0x21, M680X_INS_LBRN, rel16_hid, inh_hid },
+	{ 0x22, M680X_INS_LBHI, rel16_hid, inh_hid },
+	{ 0x23, M680X_INS_LBLS, rel16_hid, inh_hid },
+	{ 0x24, M680X_INS_LBCC, rel16_hid, inh_hid },
+	{ 0x25, M680X_INS_LBCS, rel16_hid, inh_hid },
+	{ 0x26, M680X_INS_LBNE, rel16_hid, inh_hid },
+	{ 0x27, M680X_INS_LBEQ, rel16_hid, inh_hid },
+	{ 0x28, M680X_INS_LBVC, rel16_hid, inh_hid },
+	{ 0x29, M680X_INS_LBVS, rel16_hid, inh_hid },
+	{ 0x2a, M680X_INS_LBPL, rel16_hid, inh_hid },
+	{ 0x2b, M680X_INS_LBMI, rel16_hid, inh_hid },
+	{ 0x2c, M680X_INS_LBGE, rel16_hid, inh_hid },
+	{ 0x2d, M680X_INS_LBLT, rel16_hid, inh_hid },
+	{ 0x2e, M680X_INS_LBGT, rel16_hid, inh_hid },
+	{ 0x2f, M680X_INS_LBLE, rel16_hid, inh_hid },
+	{ 0x3a, M680X_INS_REV, inh_hid, inh_hid },
+	{ 0x3b, M680X_INS_REVW, inh_hid, inh_hid },
+	{ 0x3c, M680X_INS_WAV, inh_hid, inh_hid },
+	{ 0x3d, M680X_INS_TBL, idx12s_hid, inh_hid },
+	{ 0x3e, M680X_INS_STOP, inh_hid, inh_hid },
+	{ 0x3f, M680X_INS_ETBL, idx12s_hid, inh_hid },
+};
+