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Sajid
2024-09-07 18:00:09 +06:00
commit 0f9a53f75a
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113
thirdparty/capstone/arch/Alpha/AlphaDisassembler.c vendored Normal file
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/* Capstone Disassembly Engine */
/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2023 */
#ifdef CAPSTONE_HAS_ALPHA
#include <stdio.h> // DEBUG
#include <stdlib.h>
#include <string.h>
#include "../../utils.h"
#include "../../MCFixedLenDisassembler.h"
#include "../../Mapping.h"
#include "AlphaDisassembler.h"
#include "AlphaLinkage.h"
static DecodeStatus DecodeGPRCRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeF4RCRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeF8RCRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder);
#include "AlphaGenDisassemblerTables.inc"
#define GET_REGINFO_ENUM
#define GET_REGINFO_MC_DESC
#include "AlphaGenRegisterInfo.inc"
static DecodeStatus DecodeGPRCRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder)
{
if (RegNo > 31)
return MCDisassembler_Fail;
unsigned Register = GPRC[RegNo];
MCOperand_CreateReg0(Inst, (Register));
return MCDisassembler_Success;
}
static DecodeStatus DecodeF4RCRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder)
{
if (RegNo > 31)
return MCDisassembler_Fail;
unsigned Register = F4RC[RegNo];
MCOperand_CreateReg0(Inst, (Register));
return MCDisassembler_Success;
}
static DecodeStatus DecodeF8RCRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder)
{
if (RegNo > 31)
return MCDisassembler_Fail;
unsigned Register = F8RC[RegNo];
MCOperand_CreateReg0(Inst, (Register));
return MCDisassembler_Success;
}
#define GET_SUBTARGETINFO_ENUM
#include "AlphaGenInstrInfo.inc"
DecodeStatus Alpha_LLVM_getInstruction(csh handle, const uint8_t *Bytes,
size_t ByteLen, MCInst *MI,
uint16_t *Size, uint64_t Address,
void *Info)
{
if (!handle) {
return MCDisassembler_Fail;
}
if (ByteLen < 4) {
*Size = 0;
return MCDisassembler_Fail;
}
uint32_t Insn = readBytes32(MI, Bytes);
// Calling the auto-generated decoder function.
DecodeStatus Result =
decodeInstruction_4(DecoderTable32, MI, Insn, Address, NULL);
if (Result != MCDisassembler_Fail) {
*Size = 4;
return Result;
}
*Size = 4;
return MCDisassembler_Fail;
}
void Alpha_init(MCRegisterInfo *MRI)
{
MCRegisterInfo_InitMCRegisterInfo(
MRI, AlphaRegDesc, ARR_SIZE(AlphaRegDesc), 0, 0, AlphaMCRegisterClasses,
ARR_SIZE(AlphaMCRegisterClasses), 0, 0, AlphaRegDiffLists, 0,
AlphaSubRegIdxLists, 1, 0);
}
#endif

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/* Capstone Disassembly Engine */
/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2023 */
#ifndef CS_ALPHADISASSEMBLER_H
#define CS_ALPHADISASSEMBLER_H
#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
#include <stdint.h>
#endif
#include "../../MCDisassembler.h"
#include "../../MCInst.h"
#include "../../MCRegisterInfo.h"
#include <capstone/capstone.h>
void Alpha_init(MCRegisterInfo *MRI);
#endif // CS_ALPHADISASSEMBLER_H

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164
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/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: 083d57d0731afc1746680d828bdfe2fa41f62a61 */
/* LLVM-tag: llvmorg-3.0.0-2-g083d57d0731a */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
"invalid", // Alpha_INS_INVALID
"addl", // Alpha_INS_ADDL
"addq", // Alpha_INS_ADDQ
"adds/su", // Alpha_INS_ADDSsSU
"addt/su", // Alpha_INS_ADDTsSU
"and", // Alpha_INS_AND
"beq", // Alpha_INS_BEQ
"bge", // Alpha_INS_BGE
"bgt", // Alpha_INS_BGT
"bic", // Alpha_INS_BIC
"bis", // Alpha_INS_BIS
"blbc", // Alpha_INS_BLBC
"blbs", // Alpha_INS_BLBS
"ble", // Alpha_INS_BLE
"blt", // Alpha_INS_BLT
"bne", // Alpha_INS_BNE
"br", // Alpha_INS_BR
"bsr", // Alpha_INS_BSR
"cmoveq", // Alpha_INS_CMOVEQ
"cmovge", // Alpha_INS_CMOVGE
"cmovgt", // Alpha_INS_CMOVGT
"cmovlbc", // Alpha_INS_CMOVLBC
"cmovlbs", // Alpha_INS_CMOVLBS
"cmovle", // Alpha_INS_CMOVLE
"cmovlt", // Alpha_INS_CMOVLT
"cmovne", // Alpha_INS_CMOVNE
"cmpbge", // Alpha_INS_CMPBGE
"cmpeq", // Alpha_INS_CMPEQ
"cmple", // Alpha_INS_CMPLE
"cmplt", // Alpha_INS_CMPLT
"cmpteq/su", // Alpha_INS_CMPTEQsSU
"cmptle/su", // Alpha_INS_CMPTLEsSU
"cmptlt/su", // Alpha_INS_CMPTLTsSU
"cmptun/su", // Alpha_INS_CMPTUNsSU
"cmpule", // Alpha_INS_CMPULE
"cmpult", // Alpha_INS_CMPULT
"COND_BRANCH", // Alpha_INS_COND_BRANCH
"cpyse", // Alpha_INS_CPYSE
"cpysn", // Alpha_INS_CPYSN
"cpys", // Alpha_INS_CPYS
"ctlz", // Alpha_INS_CTLZ
"ctpop", // Alpha_INS_CTPOP
"cttz", // Alpha_INS_CTTZ
"cvtqs/sui", // Alpha_INS_CVTQSsSUI
"cvtqt/sui", // Alpha_INS_CVTQTsSUI
"cvtst/s", // Alpha_INS_CVTSTsS
"cvttq/svc", // Alpha_INS_CVTTQsSVC
"cvtts/sui", // Alpha_INS_CVTTSsSUI
"divs/su", // Alpha_INS_DIVSsSU
"divt/su", // Alpha_INS_DIVTsSU
"ecb", // Alpha_INS_ECB
"eqv", // Alpha_INS_EQV
"excb", // Alpha_INS_EXCB
"extbl", // Alpha_INS_EXTBL
"extlh", // Alpha_INS_EXTLH
"extll", // Alpha_INS_EXTLL
"extqh", // Alpha_INS_EXTQH
"extql", // Alpha_INS_EXTQL
"extwh", // Alpha_INS_EXTWH
"extwl", // Alpha_INS_EXTWL
"fbeq", // Alpha_INS_FBEQ
"fbge", // Alpha_INS_FBGE
"fbgt", // Alpha_INS_FBGT
"fble", // Alpha_INS_FBLE
"fblt", // Alpha_INS_FBLT
"fbne", // Alpha_INS_FBNE
"fcmoveq", // Alpha_INS_FCMOVEQ
"fcmovge", // Alpha_INS_FCMOVGE
"fcmovgt", // Alpha_INS_FCMOVGT
"fcmovle", // Alpha_INS_FCMOVLE
"fcmovlt", // Alpha_INS_FCMOVLT
"fcmovne", // Alpha_INS_FCMOVNE
"fetch", // Alpha_INS_FETCH
"fetch_m", // Alpha_INS_FETCH_M
"ftois", // Alpha_INS_FTOIS
"ftoit", // Alpha_INS_FTOIT
"insbl", // Alpha_INS_INSBL
"inslh", // Alpha_INS_INSLH
"insll", // Alpha_INS_INSLL
"insqh", // Alpha_INS_INSQH
"insql", // Alpha_INS_INSQL
"inswh", // Alpha_INS_INSWH
"inswl", // Alpha_INS_INSWL
"itofs", // Alpha_INS_ITOFS
"itoft", // Alpha_INS_ITOFT
"jmp", // Alpha_INS_JMP
"jsr", // Alpha_INS_JSR
"jsr_coroutine", // Alpha_INS_JSR_COROUTINE
"lda", // Alpha_INS_LDA
"ldah", // Alpha_INS_LDAH
"ldbu", // Alpha_INS_LDBU
"ldl", // Alpha_INS_LDL
"ldl_l", // Alpha_INS_LDL_L
"ldq", // Alpha_INS_LDQ
"ldq_l", // Alpha_INS_LDQ_L
"ldq_u", // Alpha_INS_LDQ_U
"lds", // Alpha_INS_LDS
"ldt", // Alpha_INS_LDT
"ldwu", // Alpha_INS_LDWU
"mb", // Alpha_INS_MB
"mskbl", // Alpha_INS_MSKBL
"msklh", // Alpha_INS_MSKLH
"mskll", // Alpha_INS_MSKLL
"mskqh", // Alpha_INS_MSKQH
"mskql", // Alpha_INS_MSKQL
"mskwh", // Alpha_INS_MSKWH
"mskwl", // Alpha_INS_MSKWL
"mull", // Alpha_INS_MULL
"mulq", // Alpha_INS_MULQ
"muls/su", // Alpha_INS_MULSsSU
"mult/su", // Alpha_INS_MULTsSU
"ornot", // Alpha_INS_ORNOT
"rc", // Alpha_INS_RC
"ret", // Alpha_INS_RET
"rpcc", // Alpha_INS_RPCC
"rs", // Alpha_INS_RS
"s4addl", // Alpha_INS_S4ADDL
"s4addq", // Alpha_INS_S4ADDQ
"s4subl", // Alpha_INS_S4SUBL
"s4subq", // Alpha_INS_S4SUBQ
"s8addl", // Alpha_INS_S8ADDL
"s8addq", // Alpha_INS_S8ADDQ
"s8subl", // Alpha_INS_S8SUBL
"s8subq", // Alpha_INS_S8SUBQ
"sextb", // Alpha_INS_SEXTB
"sextw", // Alpha_INS_SEXTW
"sll", // Alpha_INS_SLL
"sqrts/su", // Alpha_INS_SQRTSsSU
"sqrtt/su", // Alpha_INS_SQRTTsSU
"sra", // Alpha_INS_SRA
"srl", // Alpha_INS_SRL
"stb", // Alpha_INS_STB
"stl", // Alpha_INS_STL
"stl_c", // Alpha_INS_STL_C
"stq", // Alpha_INS_STQ
"stq_c", // Alpha_INS_STQ_C
"stq_u", // Alpha_INS_STQ_U
"sts", // Alpha_INS_STS
"stt", // Alpha_INS_STT
"stw", // Alpha_INS_STW
"subl", // Alpha_INS_SUBL
"subq", // Alpha_INS_SUBQ
"subs/su", // Alpha_INS_SUBSsSU
"subt/su", // Alpha_INS_SUBTsSU
"trapb", // Alpha_INS_TRAPB
"umulh", // Alpha_INS_UMULH
"wh64", // Alpha_INS_WH64
"wh64en", // Alpha_INS_WH64EN
"wmb", // Alpha_INS_WMB
"xor", // Alpha_INS_XOR
"zapnot", // Alpha_INS_ZAPNOT

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/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: 083d57d0731afc1746680d828bdfe2fa41f62a61 */
/* LLVM-tag: llvmorg-3.0.0-2-g083d57d0731a */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
Alpha_OP_GROUP_Operand = 0,

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/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: 083d57d0731afc1746680d828bdfe2fa41f62a61 */
/* LLVM-tag: llvmorg-3.0.0-2-g083d57d0731a */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
#ifdef GET_REGINFO_ENUM
#undef GET_REGINFO_ENUM
enum {
Alpha_NoRegister,
Alpha_F0 = 1,
Alpha_F1 = 2,
Alpha_F2 = 3,
Alpha_F3 = 4,
Alpha_F4 = 5,
Alpha_F5 = 6,
Alpha_F6 = 7,
Alpha_F7 = 8,
Alpha_F8 = 9,
Alpha_F9 = 10,
Alpha_F10 = 11,
Alpha_F11 = 12,
Alpha_F12 = 13,
Alpha_F13 = 14,
Alpha_F14 = 15,
Alpha_F15 = 16,
Alpha_F16 = 17,
Alpha_F17 = 18,
Alpha_F18 = 19,
Alpha_F19 = 20,
Alpha_F20 = 21,
Alpha_F21 = 22,
Alpha_F22 = 23,
Alpha_F23 = 24,
Alpha_F24 = 25,
Alpha_F25 = 26,
Alpha_F26 = 27,
Alpha_F27 = 28,
Alpha_F28 = 29,
Alpha_F29 = 30,
Alpha_F30 = 31,
Alpha_F31 = 32,
Alpha_R0 = 33,
Alpha_R1 = 34,
Alpha_R2 = 35,
Alpha_R3 = 36,
Alpha_R4 = 37,
Alpha_R5 = 38,
Alpha_R6 = 39,
Alpha_R7 = 40,
Alpha_R8 = 41,
Alpha_R9 = 42,
Alpha_R10 = 43,
Alpha_R11 = 44,
Alpha_R12 = 45,
Alpha_R13 = 46,
Alpha_R14 = 47,
Alpha_R15 = 48,
Alpha_R16 = 49,
Alpha_R17 = 50,
Alpha_R18 = 51,
Alpha_R19 = 52,
Alpha_R20 = 53,
Alpha_R21 = 54,
Alpha_R22 = 55,
Alpha_R23 = 56,
Alpha_R24 = 57,
Alpha_R25 = 58,
Alpha_R26 = 59,
Alpha_R27 = 60,
Alpha_R28 = 61,
Alpha_R29 = 62,
Alpha_R30 = 63,
Alpha_R31 = 64,
NUM_TARGET_REGS // 65
};
// Register classes
enum {
Alpha_F4RCRegClassID = 0,
Alpha_F8RCRegClassID = 1,
Alpha_GPRCRegClassID = 2,
};
#endif // GET_REGINFO_ENUM
#ifdef GET_REGINFO_MC_DESC
#undef GET_REGINFO_MC_DESC
static const MCPhysReg AlphaRegDiffLists[] = {
/* 0 */ -1, 0,
};
static const uint16_t AlphaSubRegIdxLists[] = {
/* 0 */ 0,
};
static const MCRegisterDesc AlphaRegDesc[] = { // Descriptors
{ 3, 0, 0, 0, 0, 0 },
{ 24, 1, 1, 0, 1, 0 },
{ 54, 1, 1, 0, 1, 0 },
{ 76, 1, 1, 0, 1, 0 },
{ 98, 1, 1, 0, 1, 0 },
{ 120, 1, 1, 0, 1, 0 },
{ 142, 1, 1, 0, 1, 0 },
{ 164, 1, 1, 0, 1, 0 },
{ 186, 1, 1, 0, 1, 0 },
{ 208, 1, 1, 0, 1, 0 },
{ 230, 1, 1, 0, 1, 0 },
{ 0, 1, 1, 0, 1, 0 },
{ 30, 1, 1, 0, 1, 0 },
{ 60, 1, 1, 0, 1, 0 },
{ 82, 1, 1, 0, 1, 0 },
{ 104, 1, 1, 0, 1, 0 },
{ 126, 1, 1, 0, 1, 0 },
{ 148, 1, 1, 0, 1, 0 },
{ 170, 1, 1, 0, 1, 0 },
{ 192, 1, 1, 0, 1, 0 },
{ 214, 1, 1, 0, 1, 0 },
{ 8, 1, 1, 0, 1, 0 },
{ 38, 1, 1, 0, 1, 0 },
{ 68, 1, 1, 0, 1, 0 },
{ 90, 1, 1, 0, 1, 0 },
{ 112, 1, 1, 0, 1, 0 },
{ 134, 1, 1, 0, 1, 0 },
{ 156, 1, 1, 0, 1, 0 },
{ 178, 1, 1, 0, 1, 0 },
{ 200, 1, 1, 0, 1, 0 },
{ 222, 1, 1, 0, 1, 0 },
{ 16, 1, 1, 0, 1, 0 },
{ 46, 1, 1, 0, 1, 0 },
{ 27, 1, 1, 0, 1, 0 },
{ 57, 1, 1, 0, 1, 0 },
{ 79, 1, 1, 0, 1, 0 },
{ 101, 1, 1, 0, 1, 0 },
{ 123, 1, 1, 0, 1, 0 },
{ 145, 1, 1, 0, 1, 0 },
{ 167, 1, 1, 0, 1, 0 },
{ 189, 1, 1, 0, 1, 0 },
{ 211, 1, 1, 0, 1, 0 },
{ 233, 1, 1, 0, 1, 0 },
{ 4, 1, 1, 0, 1, 0 },
{ 34, 1, 1, 0, 1, 0 },
{ 64, 1, 1, 0, 1, 0 },
{ 86, 1, 1, 0, 1, 0 },
{ 108, 1, 1, 0, 1, 0 },
{ 130, 1, 1, 0, 1, 0 },
{ 152, 1, 1, 0, 1, 0 },
{ 174, 1, 1, 0, 1, 0 },
{ 196, 1, 1, 0, 1, 0 },
{ 218, 1, 1, 0, 1, 0 },
{ 12, 1, 1, 0, 1, 0 },
{ 42, 1, 1, 0, 1, 0 },
{ 72, 1, 1, 0, 1, 0 },
{ 94, 1, 1, 0, 1, 0 },
{ 116, 1, 1, 0, 1, 0 },
{ 138, 1, 1, 0, 1, 0 },
{ 160, 1, 1, 0, 1, 0 },
{ 182, 1, 1, 0, 1, 0 },
{ 204, 1, 1, 0, 1, 0 },
{ 226, 1, 1, 0, 1, 0 },
{ 20, 1, 1, 0, 1, 0 },
{ 50, 1, 1, 0, 1, 0 },
};
// F4RC Register Class...
static const MCPhysReg F4RC[] = {
Alpha_F0, Alpha_F1, Alpha_F10, Alpha_F11, Alpha_F12, Alpha_F13, Alpha_F14, Alpha_F15, Alpha_F16, Alpha_F17, Alpha_F18, Alpha_F19, Alpha_F20, Alpha_F21, Alpha_F22, Alpha_F23, Alpha_F24, Alpha_F25, Alpha_F26, Alpha_F27, Alpha_F28, Alpha_F29, Alpha_F30, Alpha_F2, Alpha_F3, Alpha_F4, Alpha_F5, Alpha_F6, Alpha_F7, Alpha_F8, Alpha_F9, Alpha_F31,
};
// F4RC Bit set.
static const uint8_t F4RCBits[] = {
0xfe, 0xff, 0xff, 0xff, 0x01,
};
// F8RC Register Class...
static const MCPhysReg F8RC[] = {
Alpha_F0, Alpha_F1, Alpha_F10, Alpha_F11, Alpha_F12, Alpha_F13, Alpha_F14, Alpha_F15, Alpha_F16, Alpha_F17, Alpha_F18, Alpha_F19, Alpha_F20, Alpha_F21, Alpha_F22, Alpha_F23, Alpha_F24, Alpha_F25, Alpha_F26, Alpha_F27, Alpha_F28, Alpha_F29, Alpha_F30, Alpha_F2, Alpha_F3, Alpha_F4, Alpha_F5, Alpha_F6, Alpha_F7, Alpha_F8, Alpha_F9, Alpha_F31,
};
// F8RC Bit set.
static const uint8_t F8RCBits[] = {
0xfe, 0xff, 0xff, 0xff, 0x01,
};
// GPRC Register Class...
static const MCPhysReg GPRC[] = {
Alpha_R0, Alpha_R1, Alpha_R2, Alpha_R3, Alpha_R4, Alpha_R5, Alpha_R6, Alpha_R7, Alpha_R8, Alpha_R16, Alpha_R17, Alpha_R18, Alpha_R19, Alpha_R20, Alpha_R21, Alpha_R22, Alpha_R23, Alpha_R24, Alpha_R25, Alpha_R28, Alpha_R27, Alpha_R26, Alpha_R29, Alpha_R9, Alpha_R10, Alpha_R11, Alpha_R12, Alpha_R13, Alpha_R14, Alpha_R15, Alpha_R30, Alpha_R31,
};
// GPRC Bit set.
static const uint8_t GPRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
};
static const MCRegisterClass AlphaMCRegisterClasses[] = {
{ F4RC, F4RCBits, sizeof(F4RCBits) },
{ F8RC, F8RCBits, sizeof(F8RCBits) },
{ GPRC, GPRCBits, sizeof(GPRCBits) },
};
static const uint16_t AlphaRegEncodingTable[] = {
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
};
#endif // GET_REGINFO_MC_DESC

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/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: 083d57d0731afc1746680d828bdfe2fa41f62a61 */
/* LLVM-tag: llvmorg-3.0.0-2-g083d57d0731a */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
#ifdef GET_SUBTARGETINFO_ENUM
#undef GET_SUBTARGETINFO_ENUM
enum {
Alpha_FeatureCIX = 0,
Alpha_NumSubtargetFeatures = 1
};
#endif // GET_SUBTARGETINFO_ENUM

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/* Capstone Disassembly Engine */
/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2023 */
#ifdef CAPSTONE_HAS_ALPHA
#include <platform.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "../../utils.h"
#include "../../Mapping.h"
#include "../../MCInstPrinter.h"
#include "AlphaLinkage.h"
#include "AlphaMapping.h"
static const char *getRegisterName(unsigned RegNo);
static void printInstruction(MCInst *, uint64_t, SStream *);
static void printOperand(MCInst *MI, int OpNum, SStream *O);
static void printOperandAddr(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O);
#define GET_INSTRINFO_ENUM
#include "AlphaGenInstrInfo.inc"
#define GET_REGINFO_ENUM
#include "AlphaGenRegisterInfo.inc"
static void printOperand(MCInst *MI, int OpNum, SStream *O)
{
if (OpNum >= MI->size)
return;
Alpha_add_cs_detail(MI, OpNum);
MCOperand *Op;
Op = MCInst_getOperand(MI, OpNum);
if (MCOperand_isReg(Op)) {
unsigned reg = MCOperand_getReg(Op);
SStream_concat(O, "%s", getRegisterName(reg));
} else if (MCOperand_isImm(Op)) {
int64_t Imm = MCOperand_getImm(Op);
if (Imm >= 0) {
if (Imm > HEX_THRESHOLD)
SStream_concat(O, "0x%" PRIx64, Imm);
else
SStream_concat(O, "%" PRIu64, Imm);
} else {
if (Imm < -HEX_THRESHOLD)
SStream_concat(O, "-0x%" PRIx64, -Imm);
else
SStream_concat(O, "-%" PRIu64, -Imm);
}
}
}
static void printOperandAddr(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O)
{
MCOperand *Op = MCInst_getOperand(MI, (OpNum));
uint64_t Imm = MCOperand_getImm(Op);
uint64_t Target = Address + 4 + (int16_t) (Imm << 2);
Alpha_set_detail_op_imm(MI, OpNum, ALPHA_OP_IMM, Target);
printUInt64(O, Target);
}
#define PRINT_ALIAS_INSTR
#include "AlphaGenAsmWriter.inc"
const char *Alpha_LLVM_getRegisterName(csh handle, unsigned int id)
{
#ifndef CAPSTONE_DIET
return getRegisterName(id);
#else
return NULL;
#endif
}
void Alpha_LLVM_printInstruction(MCInst *MI, SStream *O, void *Info)
{
printAliasInstr(MI, MI->address, O);
printInstruction(MI, MI->address, O);
}
#endif

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/* Capstone Disassembly Engine */
/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2023 */
#ifndef CS_ALPHA_LINKAGE_H
#define CS_ALPHA_LINKAGE_H
// Function definitions to call static LLVM functions.
#include "../../MCInst.h"
#include "../../MCRegisterInfo.h"
#include "../../SStream.h"
#include "AlphaMapping.h"
const char *Alpha_LLVM_getRegisterName(csh handle, unsigned int id);
void Alpha_LLVM_printInstruction(MCInst *MI, SStream *O, void *Info);
DecodeStatus Alpha_LLVM_getInstruction(csh handle, const uint8_t *Bytes,
size_t ByteLen, MCInst *MI,
uint16_t *Size, uint64_t Address,
void *Info);
#endif // CS_ALPHA_LINKAGE_H

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/* Capstone Disassembly Engine */
/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2023 */
#ifdef CAPSTONE_HAS_ALPHA
#include <stdio.h> // debug
#include <string.h>
#include "../../Mapping.h"
#include "../../cs_priv.h"
#include "../../cs_simple_types.h"
#include "../../utils.h"
#include "AlphaLinkage.h"
#include "AlphaMapping.h"
#include "./AlphaDisassembler.h"
#define GET_INSTRINFO_ENUM
#include "AlphaGenInstrInfo.inc"
static const insn_map insns[] = {
#include "AlphaGenCSMappingInsn.inc"
};
static const map_insn_ops insn_operands[] = {
#include "AlphaGenCSMappingInsnOp.inc"
};
void Alpha_init_cs_detail(MCInst *MI)
{
if (detail_is_set(MI)) {
memset(get_detail(MI), 0,
offsetof(cs_detail, alpha) + sizeof(cs_alpha));
}
}
void Alpha_add_cs_detail(MCInst *MI, unsigned OpNum)
{
if (!detail_is_set(MI))
return;
cs_op_type op_type = map_get_op_type(MI, OpNum);
if (op_type == CS_OP_IMM)
Alpha_set_detail_op_imm(MI, OpNum, ALPHA_OP_IMM,
MCInst_getOpVal(MI, OpNum));
else if (op_type == CS_OP_REG)
Alpha_set_detail_op_reg(MI, OpNum, MCInst_getOpVal(MI, OpNum));
else
assert(0 && "Op type not handled.");
}
void Alpha_set_detail_op_imm(MCInst *MI, unsigned OpNum, alpha_op_type ImmType,
int64_t Imm)
{
if (!detail_is_set(MI))
return;
assert(!(map_get_op_type(MI, OpNum) & CS_OP_MEM));
assert(map_get_op_type(MI, OpNum) == CS_OP_IMM);
assert(ImmType == ALPHA_OP_IMM);
Alpha_get_detail_op(MI, 0)->type = ImmType;
Alpha_get_detail_op(MI, 0)->imm = Imm;
Alpha_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
Alpha_inc_op_count(MI);
}
void Alpha_set_detail_op_reg(MCInst *MI, unsigned OpNum, alpha_op_type Reg)
{
if (!detail_is_set(MI))
return;
assert(!(map_get_op_type(MI, OpNum) & CS_OP_MEM));
assert(map_get_op_type(MI, OpNum) == CS_OP_REG);
Alpha_get_detail_op(MI, 0)->type = ALPHA_OP_REG;
Alpha_get_detail_op(MI, 0)->reg = Reg;
Alpha_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
Alpha_inc_op_count(MI);
}
// given internal insn id, return public instruction info
void Alpha_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
{
unsigned short i;
i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache);
if (i == 0) { return; }
insn->id = insns[i].mapid;
if (insn->detail) {
#ifndef CAPSTONE_DIET
memcpy(insn->detail->regs_read, insns[i].regs_use,
sizeof(insns[i].regs_use));
insn->detail->regs_read_count =
(uint8_t)count_positive(insns[i].regs_use);
memcpy(insn->detail->regs_write, insns[i].regs_mod,
sizeof(insns[i].regs_mod));
insn->detail->regs_write_count =
(uint8_t)count_positive(insns[i].regs_mod);
memcpy(insn->detail->groups, insns[i].groups,
sizeof(insns[i].groups));
insn->detail->groups_count =
(uint8_t)count_positive8(insns[i].groups);
#endif
}
}
#ifndef CAPSTONE_DIET
static const char * const insn_names[] = {
#include "AlphaGenCSMappingInsnName.inc"
};
// special alias insn
// static name_map alias_insn_names[] = {{0, NULL}};
#endif
const char *Alpha_insn_name(csh handle, unsigned int id)
{
#ifndef CAPSTONE_DIET
if (id >= ALPHA_INS_ENDING)
return NULL;
if (id < ARR_SIZE(insn_names))
return insn_names[id];
return NULL;
#else
return NULL;
#endif
}
#ifndef CAPSTONE_DIET
static const name_map group_name_maps[] = {
{Alpha_GRP_INVALID, NULL},
{Alpha_GRP_CALL, "call"},
{Alpha_GRP_JUMP, "jump"},
{Alpha_GRP_BRANCH_RELATIVE, "branch_relative"},
};
#endif
const char *Alpha_group_name(csh handle, unsigned int id)
{
#ifndef CAPSTONE_DIET
return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
#else
return NULL;
#endif
}
const char *Alpha_getRegisterName(csh handle, unsigned int id)
{
return Alpha_LLVM_getRegisterName(handle, id);
}
void Alpha_printInst(MCInst *MI, SStream *O, void *Info)
{
Alpha_LLVM_printInstruction(MI, O, Info);
}
void Alpha_set_instr_map_data(MCInst *MI)
{
map_cs_id(MI, insns, ARR_SIZE(insns));
map_implicit_reads(MI, insns);
map_implicit_writes(MI, insns);
map_groups(MI, insns);
}
bool Alpha_getInstruction(csh handle, const uint8_t *code,
size_t code_len, MCInst *instr,
uint16_t *size, uint64_t address, void *info)
{
Alpha_init_cs_detail(instr);
bool Result = Alpha_LLVM_getInstruction(handle, code, code_len, instr, size,
address, info);
Alpha_set_instr_map_data(instr);
return Result;
}
#endif

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/* Capstone Disassembly Engine */
/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2023 */
#ifndef CS_ALPHA_MAP_H
#define CS_ALPHA_MAP_H
#include "../../MCDisassembler.h"
#include "../../MCInst.h"
#include "../../SStream.h"
#include <capstone/capstone.h>
// unsigned int Alpha_map_insn_id(cs_struct *h, unsigned int id);
// given internal insn id, return public instruction info
void Alpha_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
const char *Alpha_insn_name(csh handle, unsigned int id);
const char *Alpha_group_name(csh handle, unsigned int id);
void Alpha_printInst(MCInst *MI, SStream *O, void *Info);
const char *Alpha_getRegisterName(csh handle, unsigned int id);
bool Alpha_getInstruction(csh handle, const uint8_t *code,
size_t code_len, MCInst *instr,
uint16_t *size, uint64_t address, void *info);
void Alpha_init_cs_detail(MCInst *MI);
void Alpha_add_cs_detail(MCInst *MI, unsigned OpNum);
void Alpha_set_instr_map_data(MCInst *MI);
void Alpha_set_detail_op_imm(MCInst *MI, unsigned OpNum, alpha_op_type ImmType,
int64_t Imm);
void Alpha_set_detail_op_reg(MCInst *MI, unsigned OpNum, alpha_op_type Reg);
#endif

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/* Capstone Disassembly Engine */
/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2023 */
#ifdef CAPSTONE_HAS_ALPHA
#include "../../utils.h"
#include "../../MCRegisterInfo.h"
#include "AlphaDisassembler.h"
#include "AlphaMapping.h"
#include "AlphaModule.h"
cs_err ALPHA_global_init(cs_struct *ud)
{
MCRegisterInfo *mri;
mri = cs_mem_malloc(sizeof(*mri));
Alpha_init(mri);
ud->printer = Alpha_printInst;
ud->printer_info = mri;
ud->getinsn_info = mri;
ud->disasm = Alpha_getInstruction;
ud->post_printer = NULL;
ud->reg_name = Alpha_getRegisterName;
ud->insn_id = Alpha_get_insn_id;
ud->insn_name = Alpha_insn_name;
ud->group_name = Alpha_group_name;
return CS_ERR_OK;
}
cs_err ALPHA_option(cs_struct *handle, cs_opt_type type, size_t value)
{
if (type == CS_OPT_SYNTAX) {
handle->syntax = (int)value;
} else if (type == CS_OPT_MODE) {
handle->mode = (cs_mode)value;
}
return CS_ERR_OK;
}
#endif

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/* Capstone Disassembly Engine */
/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2023 */
#ifndef CAPSTONE_ALPHAMODULE_H
#define CAPSTONE_ALPHAMODULE_H
#include "../../utils.h"
cs_err ALPHA_global_init(cs_struct *ud);
cs_err ALPHA_option(cs_struct *handle, cs_opt_type type, size_t value);
#endif // CAPSTONE_ALPHAMODULE_H