Initial Commit

thirdparty/capstone/arch/Sparc/Sparc.h

@@ -0,0 +1,63 @@
+//===-- Sparc.h - Top-level interface for Sparc representation --*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the entry points for global functions defined in the LLVM
+// Sparc back-end.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifndef CS_SPARC_TARGET_SPARC_H
+#define CS_SPARC_TARGET_SPARC_H
+
+#include "capstone/sparc.h"
+
+inline static const char *SPARCCondCodeToString(sparc_cc CC)
+{
+	switch (CC) {
+		default:	return NULL;	// unreachable
+		case SPARC_CC_ICC_A:  return "a";
+		case SPARC_CC_ICC_N:   return "n";
+		case SPARC_CC_ICC_NE:  return "ne";
+		case SPARC_CC_ICC_E:   return "e";
+		case SPARC_CC_ICC_G:   return "g";
+		case SPARC_CC_ICC_LE:  return "le";
+		case SPARC_CC_ICC_GE:  return "ge";
+		case SPARC_CC_ICC_L:   return "l";
+		case SPARC_CC_ICC_GU:  return "gu";
+		case SPARC_CC_ICC_LEU: return "leu";
+		case SPARC_CC_ICC_CC:  return "cc";
+		case SPARC_CC_ICC_CS:  return "cs";
+		case SPARC_CC_ICC_POS: return "pos";
+		case SPARC_CC_ICC_NEG: return "neg";
+		case SPARC_CC_ICC_VC:  return "vc";
+		case SPARC_CC_ICC_VS:  return "vs";
+
+		case SPARC_CC_FCC_A:   return "a";
+		case SPARC_CC_FCC_N:   return "n";
+		case SPARC_CC_FCC_U:   return "u";
+		case SPARC_CC_FCC_G:   return "g";
+		case SPARC_CC_FCC_UG:  return "ug";
+		case SPARC_CC_FCC_L:   return "l";
+		case SPARC_CC_FCC_UL:  return "ul";
+		case SPARC_CC_FCC_LG:  return "lg";
+		case SPARC_CC_FCC_NE:  return "ne";
+		case SPARC_CC_FCC_E:   return "e";
+		case SPARC_CC_FCC_UE:  return "ue";
+		case SPARC_CC_FCC_GE:  return "ge";
+		case SPARC_CC_FCC_UGE: return "uge";
+		case SPARC_CC_FCC_LE:  return "le";
+		case SPARC_CC_FCC_ULE: return "ule";
+		case SPARC_CC_FCC_O:   return "o";
+	}
+}
+
+#endif

thirdparty/capstone/arch/Sparc/SparcDisassembler.c

@@ -0,0 +1,500 @@
+//===------ SparcDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifdef CAPSTONE_HAS_SPARC
+
+#include <stdio.h>	// DEBUG
+#include <stdlib.h>
+#include <string.h>
+
+#include "../../cs_priv.h"
+#include "../../utils.h"
+
+#include "SparcDisassembler.h"
+
+#include "../../MCInst.h"
+#include "../../MCInstrDesc.h"
+#include "../../MCFixedLenDisassembler.h"
+#include "../../MCRegisterInfo.h"
+#include "../../MCDisassembler.h"
+#include "../../MathExtras.h"
+
+
+#define GET_REGINFO_MC_DESC
+#define GET_REGINFO_ENUM
+#include "SparcGenRegisterInfo.inc"
+static const unsigned IntRegDecoderTable[] = {
+	SP_G0,  SP_G1,  SP_G2,  SP_G3,
+	SP_G4,  SP_G5,  SP_G6,  SP_G7,
+	SP_O0,  SP_O1,  SP_O2,  SP_O3,
+	SP_O4,  SP_O5,  SP_O6,  SP_O7,
+	SP_L0,  SP_L1,  SP_L2,  SP_L3,
+	SP_L4,  SP_L5,  SP_L6,  SP_L7,
+	SP_I0,  SP_I1,  SP_I2,  SP_I3,
+	SP_I4,  SP_I5,  SP_I6,  SP_I7
+};
+
+static const unsigned FPRegDecoderTable[] = {
+	SP_F0,   SP_F1,   SP_F2,   SP_F3,
+	SP_F4,   SP_F5,   SP_F6,   SP_F7,
+	SP_F8,   SP_F9,   SP_F10,  SP_F11,
+	SP_F12,  SP_F13,  SP_F14,  SP_F15,
+	SP_F16,  SP_F17,  SP_F18,  SP_F19,
+	SP_F20,  SP_F21,  SP_F22,  SP_F23,
+	SP_F24,  SP_F25,  SP_F26,  SP_F27,
+	SP_F28,  SP_F29,  SP_F30,  SP_F31
+};
+
+static const unsigned DFPRegDecoderTable[] = {
+	SP_D0,   SP_D16,  SP_D1,   SP_D17,
+	SP_D2,   SP_D18,  SP_D3,   SP_D19,
+	SP_D4,   SP_D20,  SP_D5,   SP_D21,
+	SP_D6,   SP_D22,  SP_D7,   SP_D23,
+	SP_D8,   SP_D24,  SP_D9,   SP_D25,
+	SP_D10,  SP_D26,  SP_D11,  SP_D27,
+	SP_D12,  SP_D28,  SP_D13,  SP_D29,
+	SP_D14,  SP_D30,  SP_D15,  SP_D31
+};
+
+static const unsigned QFPRegDecoderTable[] = {
+	SP_Q0,  SP_Q8,   ~0U,  ~0U,
+	SP_Q1,  SP_Q9,   ~0U,  ~0U,
+	SP_Q2,  SP_Q10,  ~0U,  ~0U,
+	SP_Q3,  SP_Q11,  ~0U,  ~0U,
+	SP_Q4,  SP_Q12,  ~0U,  ~0U,
+	SP_Q5,  SP_Q13,  ~0U,  ~0U,
+	SP_Q6,  SP_Q14,  ~0U,  ~0U,
+	SP_Q7,  SP_Q15,  ~0U,  ~0U
+};
+
+static const unsigned FCCRegDecoderTable[] = {
+	SP_FCC0, SP_FCC1, SP_FCC2, SP_FCC3
+};
+
+static uint64_t getFeatureBits(int mode)
+{
+	// support everything
+	return (uint64_t)-1;
+}
+
+static DecodeStatus DecodeIntRegsRegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Address, const void *Decoder)
+{
+	unsigned Reg;
+
+	if (RegNo > 31)
+		return MCDisassembler_Fail;
+
+	Reg = IntRegDecoderTable[RegNo];
+	MCOperand_CreateReg0(Inst, Reg);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeI64RegsRegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Address, const void *Decoder)
+{
+	unsigned Reg;
+
+	if (RegNo > 31)
+		return MCDisassembler_Fail;
+
+	Reg = IntRegDecoderTable[RegNo];
+	MCOperand_CreateReg0(Inst, Reg);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeFPRegsRegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Address, const void *Decoder)
+{
+	unsigned Reg;
+
+	if (RegNo > 31)
+		return MCDisassembler_Fail;
+
+	Reg = FPRegDecoderTable[RegNo];
+	MCOperand_CreateReg0(Inst, Reg);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeDFPRegsRegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Address, const void *Decoder)
+{
+	unsigned Reg;
+
+	if (RegNo > 31)
+		return MCDisassembler_Fail;
+
+	Reg = DFPRegDecoderTable[RegNo];
+	MCOperand_CreateReg0(Inst, Reg);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeQFPRegsRegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Address, const void *Decoder)
+{
+	unsigned Reg;
+
+	if (RegNo > 31)
+		return MCDisassembler_Fail;
+
+	Reg = QFPRegDecoderTable[RegNo];
+	if (Reg == ~0U)
+		return MCDisassembler_Fail;
+
+	MCOperand_CreateReg0(Inst, Reg);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeFCCRegsRegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Address, const void *Decoder)
+{
+	if (RegNo > 3)
+		return MCDisassembler_Fail;
+
+	MCOperand_CreateReg0(Inst, FCCRegDecoderTable[RegNo]);
+
+	return MCDisassembler_Success;
+}
+
+
+static DecodeStatus DecodeLoadInt(MCInst *Inst, unsigned insn, uint64_t Address,
+		const void *Decoder);
+static DecodeStatus DecodeLoadFP(MCInst *Inst, unsigned insn, uint64_t Address,
+		const void *Decoder);
+static DecodeStatus DecodeLoadDFP(MCInst *Inst, unsigned insn, uint64_t Address,
+		const void *Decoder);
+static DecodeStatus DecodeLoadQFP(MCInst *Inst, unsigned insn, uint64_t Address,
+		const void *Decoder);
+static DecodeStatus DecodeStoreInt(MCInst *Inst, unsigned insn,
+		uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeStoreFP(MCInst *Inst, unsigned insn,
+		uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeStoreDFP(MCInst *Inst, unsigned insn,
+		uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeStoreQFP(MCInst *Inst, unsigned insn,
+		uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeCall(MCInst *Inst, unsigned insn,
+		uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeSIMM13(MCInst *Inst, unsigned insn,
+		uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeJMPL(MCInst *Inst, unsigned insn, uint64_t Address,
+		const void *Decoder);
+static DecodeStatus DecodeReturn(MCInst *MI, unsigned insn, uint64_t Address,
+		const void *Decoder);
+static DecodeStatus DecodeSWAP(MCInst *Inst, unsigned insn, uint64_t Address,
+		const void *Decoder);
+
+
+#define GET_SUBTARGETINFO_ENUM
+#include "SparcGenSubtargetInfo.inc"
+#include "SparcGenDisassemblerTables.inc"
+
+/// readInstruction - read four bytes and return 32 bit word.
+static DecodeStatus readInstruction32(const uint8_t *code, size_t len, uint32_t *Insn)
+{
+	if (len < 4)
+		// not enough data
+		return MCDisassembler_Fail;
+
+	// Encoded as a big-endian 32-bit word in the stream.
+	*Insn = (code[3] <<  0) |
+		(code[2] <<  8) |
+		(code[1] << 16) |
+		((uint32_t) code[0] << 24);
+
+	return MCDisassembler_Success;
+}
+
+bool Sparc_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *MI,
+		uint16_t *size, uint64_t address, void *info)
+{
+	uint32_t Insn;
+	DecodeStatus Result;
+	
+	Result = readInstruction32(code, code_len, &Insn);
+	if (Result == MCDisassembler_Fail)
+		return false;
+
+	if (MI->flat_insn->detail) {
+		memset(MI->flat_insn->detail, 0, offsetof(cs_detail, sparc)+sizeof(cs_sparc));
+	}
+
+	Result = decodeInstruction_4(DecoderTableSparc32, MI, Insn, address,
+			(MCRegisterInfo *)info, 0);
+	if (Result != MCDisassembler_Fail) {
+		*size = 4;
+		return true;
+	}
+
+	return false;
+}
+
+typedef DecodeStatus (*DecodeFunc)(MCInst *MI, unsigned insn, uint64_t Address,
+		const void *Decoder);
+
+static DecodeStatus DecodeMem(MCInst *MI, unsigned insn, uint64_t Address,
+		const void *Decoder,
+		bool isLoad, DecodeFunc DecodeRD)
+{
+	DecodeStatus status;
+	unsigned rd = fieldFromInstruction_4(insn, 25, 5);
+	unsigned rs1 = fieldFromInstruction_4(insn, 14, 5);
+	bool isImm = fieldFromInstruction_4(insn, 13, 1) != 0;
+	unsigned rs2 = 0;
+	unsigned simm13 = 0;
+
+	if (isImm)
+		simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13);
+	else
+		rs2 = fieldFromInstruction_4(insn, 0, 5);
+
+	if (isLoad) {
+		status = DecodeRD(MI, rd, Address, Decoder);
+		if (status != MCDisassembler_Success)
+			return status;
+	}
+
+	// Decode rs1.
+	status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode imm|rs2.
+	if (isImm)
+		MCOperand_CreateImm0(MI, simm13);
+	else {
+		status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
+		if (status != MCDisassembler_Success)
+			return status;
+	}
+
+	if (!isLoad) {
+		status = DecodeRD(MI, rd, Address, Decoder);
+		if (status != MCDisassembler_Success)
+			return status;
+	}
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeLoadInt(MCInst *Inst, unsigned insn, uint64_t Address,
+		const void *Decoder)
+{
+	return DecodeMem(Inst, insn, Address, Decoder, true,
+			DecodeIntRegsRegisterClass);
+}
+
+static DecodeStatus DecodeLoadFP(MCInst *Inst, unsigned insn, uint64_t Address,
+		const void *Decoder)
+{
+	return DecodeMem(Inst, insn, Address, Decoder, true,
+			DecodeFPRegsRegisterClass);
+}
+
+static DecodeStatus DecodeLoadDFP(MCInst *Inst, unsigned insn, uint64_t Address,
+		const void *Decoder)
+{
+	return DecodeMem(Inst, insn, Address, Decoder, true,
+			DecodeDFPRegsRegisterClass);
+}
+
+static DecodeStatus DecodeLoadQFP(MCInst *Inst, unsigned insn, uint64_t Address,
+		const void *Decoder)
+{
+	return DecodeMem(Inst, insn, Address, Decoder, true,
+			DecodeQFPRegsRegisterClass);
+}
+
+static DecodeStatus DecodeStoreInt(MCInst *Inst, unsigned insn,
+		uint64_t Address, const void *Decoder)
+{
+	return DecodeMem(Inst, insn, Address, Decoder, false,
+			DecodeIntRegsRegisterClass);
+}
+
+static DecodeStatus DecodeStoreFP(MCInst *Inst, unsigned insn, uint64_t Address,
+		const void *Decoder)
+{
+	return DecodeMem(Inst, insn, Address, Decoder, false,
+			DecodeFPRegsRegisterClass);
+}
+
+static DecodeStatus DecodeStoreDFP(MCInst *Inst, unsigned insn,
+		uint64_t Address, const void *Decoder)
+{
+	return DecodeMem(Inst, insn, Address, Decoder, false,
+			DecodeDFPRegsRegisterClass);
+}
+
+static DecodeStatus DecodeStoreQFP(MCInst *Inst, unsigned insn,
+		uint64_t Address, const void *Decoder)
+{
+	return DecodeMem(Inst, insn, Address, Decoder, false,
+			DecodeQFPRegsRegisterClass);
+}
+
+static DecodeStatus DecodeCall(MCInst *MI, unsigned insn,
+		uint64_t Address, const void *Decoder)
+{
+	unsigned tgt = fieldFromInstruction_4(insn, 0, 30);
+	tgt <<= 2;
+
+	MCOperand_CreateImm0(MI, tgt);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeSIMM13(MCInst *MI, unsigned insn,
+		uint64_t Address, const void *Decoder)
+{
+	unsigned tgt = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13);
+
+	MCOperand_CreateImm0(MI, tgt);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeJMPL(MCInst *MI, unsigned insn, uint64_t Address,
+		const void *Decoder)
+{
+	DecodeStatus status;
+	unsigned rd = fieldFromInstruction_4(insn, 25, 5);
+	unsigned rs1 = fieldFromInstruction_4(insn, 14, 5);
+	unsigned isImm = fieldFromInstruction_4(insn, 13, 1);
+	unsigned rs2 = 0;
+	unsigned simm13 = 0;
+
+	if (isImm)
+		simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13);
+	else
+		rs2 = fieldFromInstruction_4(insn, 0, 5);
+
+	// Decode RD.
+	status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode RS1.
+	status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode RS1 | SIMM13.
+	if (isImm)
+		MCOperand_CreateImm0(MI, simm13);
+	else {
+		status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
+		if (status != MCDisassembler_Success)
+			return status;
+	}
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeReturn(MCInst *MI, unsigned insn, uint64_t Address,
+		const void *Decoder)
+{
+	DecodeStatus status;
+	unsigned rs1 = fieldFromInstruction_4(insn, 14, 5);
+	unsigned isImm = fieldFromInstruction_4(insn, 13, 1);
+	unsigned rs2 = 0;
+	unsigned simm13 = 0;
+	if (isImm)
+		simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13);
+	else
+		rs2 = fieldFromInstruction_4(insn, 0, 5);
+
+	// Decode RS1.
+	status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode RS2 | SIMM13.
+	if (isImm)
+		MCOperand_CreateImm0(MI, simm13);
+	else {
+		status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
+		if (status != MCDisassembler_Success)
+			return status;
+	}
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeSWAP(MCInst *MI, unsigned insn, uint64_t Address,
+		const void *Decoder)
+{
+	DecodeStatus status;
+	unsigned rd = fieldFromInstruction_4(insn, 25, 5);
+	unsigned rs1 = fieldFromInstruction_4(insn, 14, 5);
+	unsigned isImm = fieldFromInstruction_4(insn, 13, 1);
+	unsigned rs2 = 0;
+	unsigned simm13 = 0;
+
+	if (isImm)
+		simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13);
+	else
+		rs2 = fieldFromInstruction_4(insn, 0, 5);
+
+	// Decode RD.
+	status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode RS1.
+	status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
+	if (status != MCDisassembler_Success)
+		return status;
+
+	// Decode RS1 | SIMM13.
+	if (isImm)
+		MCOperand_CreateImm0(MI, simm13);
+	else {
+		status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
+		if (status != MCDisassembler_Success)
+			return status;
+	}
+
+	return MCDisassembler_Success;
+}
+
+void Sparc_init(MCRegisterInfo *MRI)
+{
+	/*
+	InitMCRegisterInfo(SparcRegDesc, 119, RA, PC,
+			SparcMCRegisterClasses, 8,
+			SparcRegUnitRoots,
+			86,
+			SparcRegDiffLists,
+			SparcRegStrings,
+			SparcSubRegIdxLists,
+			7,
+			SparcSubRegIdxRanges,
+			SparcRegEncodingTable);
+	*/
+
+	MCRegisterInfo_InitMCRegisterInfo(MRI, SparcRegDesc, 119,
+			0, 0,
+			SparcMCRegisterClasses, 8,
+			0, 0,
+			SparcRegDiffLists,
+			0,
+			SparcSubRegIdxLists, 7,
+			0);
+}
+
+#endif

thirdparty/capstone/arch/Sparc/SparcDisassembler.h

@@ -0,0 +1,17 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifndef CS_SPARCDISASSEMBLER_H
+#define CS_SPARCDISASSEMBLER_H
+
+#include "capstone/capstone.h"
+#include "../../MCRegisterInfo.h"
+#include "../../MCInst.h"
+
+void Sparc_init(MCRegisterInfo *MRI);
+
+bool Sparc_getInstruction(csh ud, const uint8_t *code, size_t code_len,
+		MCInst *instr, uint16_t *size, uint64_t address, void *info);
+
+#endif
+

thirdparty/capstone/arch/Sparc/SparcGenInstrInfo.inc

@@ -0,0 +1,514 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|*Target Instruction Enum Values                                              *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+
+#ifdef GET_INSTRINFO_ENUM
+#undef GET_INSTRINFO_ENUM
+
+enum {
+    SP_PHI	= 0,
+    SP_INLINEASM	= 1,
+    SP_CFI_INSTRUCTION	= 2,
+    SP_EH_LABEL	= 3,
+    SP_GC_LABEL	= 4,
+    SP_KILL	= 5,
+    SP_EXTRACT_SUBREG	= 6,
+    SP_INSERT_SUBREG	= 7,
+    SP_IMPLICIT_DEF	= 8,
+    SP_SUBREG_TO_REG	= 9,
+    SP_COPY_TO_REGCLASS	= 10,
+    SP_DBG_VALUE	= 11,
+    SP_REG_SEQUENCE	= 12,
+    SP_COPY	= 13,
+    SP_BUNDLE	= 14,
+    SP_LIFETIME_START	= 15,
+    SP_LIFETIME_END	= 16,
+    SP_STACKMAP	= 17,
+    SP_PATCHPOINT	= 18,
+    SP_LOAD_STACK_GUARD	= 19,
+    SP_STATEPOINT	= 20,
+    SP_FRAME_ALLOC	= 21,
+    SP_ADDCCri	= 22,
+    SP_ADDCCrr	= 23,
+    SP_ADDCri	= 24,
+    SP_ADDCrr	= 25,
+    SP_ADDEri	= 26,
+    SP_ADDErr	= 27,
+    SP_ADDXC	= 28,
+    SP_ADDXCCC	= 29,
+    SP_ADDXri	= 30,
+    SP_ADDXrr	= 31,
+    SP_ADDri	= 32,
+    SP_ADDrr	= 33,
+    SP_ADJCALLSTACKDOWN	= 34,
+    SP_ADJCALLSTACKUP	= 35,
+    SP_ALIGNADDR	= 36,
+    SP_ALIGNADDRL	= 37,
+    SP_ANDCCri	= 38,
+    SP_ANDCCrr	= 39,
+    SP_ANDNCCri	= 40,
+    SP_ANDNCCrr	= 41,
+    SP_ANDNri	= 42,
+    SP_ANDNrr	= 43,
+    SP_ANDXNrr	= 44,
+    SP_ANDXri	= 45,
+    SP_ANDXrr	= 46,
+    SP_ANDri	= 47,
+    SP_ANDrr	= 48,
+    SP_ARRAY16	= 49,
+    SP_ARRAY32	= 50,
+    SP_ARRAY8	= 51,
+    SP_ATOMIC_LOAD_ADD_32	= 52,
+    SP_ATOMIC_LOAD_ADD_64	= 53,
+    SP_ATOMIC_LOAD_AND_32	= 54,
+    SP_ATOMIC_LOAD_AND_64	= 55,
+    SP_ATOMIC_LOAD_MAX_32	= 56,
+    SP_ATOMIC_LOAD_MAX_64	= 57,
+    SP_ATOMIC_LOAD_MIN_32	= 58,
+    SP_ATOMIC_LOAD_MIN_64	= 59,
+    SP_ATOMIC_LOAD_NAND_32	= 60,
+    SP_ATOMIC_LOAD_NAND_64	= 61,
+    SP_ATOMIC_LOAD_OR_32	= 62,
+    SP_ATOMIC_LOAD_OR_64	= 63,
+    SP_ATOMIC_LOAD_SUB_32	= 64,
+    SP_ATOMIC_LOAD_SUB_64	= 65,
+    SP_ATOMIC_LOAD_UMAX_32	= 66,
+    SP_ATOMIC_LOAD_UMAX_64	= 67,
+    SP_ATOMIC_LOAD_UMIN_32	= 68,
+    SP_ATOMIC_LOAD_UMIN_64	= 69,
+    SP_ATOMIC_LOAD_XOR_32	= 70,
+    SP_ATOMIC_LOAD_XOR_64	= 71,
+    SP_ATOMIC_SWAP_64	= 72,
+    SP_BA	= 73,
+    SP_BCOND	= 74,
+    SP_BCONDA	= 75,
+    SP_BINDri	= 76,
+    SP_BINDrr	= 77,
+    SP_BMASK	= 78,
+    SP_BPFCC	= 79,
+    SP_BPFCCA	= 80,
+    SP_BPFCCANT	= 81,
+    SP_BPFCCNT	= 82,
+    SP_BPGEZapn	= 83,
+    SP_BPGEZapt	= 84,
+    SP_BPGEZnapn	= 85,
+    SP_BPGEZnapt	= 86,
+    SP_BPGZapn	= 87,
+    SP_BPGZapt	= 88,
+    SP_BPGZnapn	= 89,
+    SP_BPGZnapt	= 90,
+    SP_BPICC	= 91,
+    SP_BPICCA	= 92,
+    SP_BPICCANT	= 93,
+    SP_BPICCNT	= 94,
+    SP_BPLEZapn	= 95,
+    SP_BPLEZapt	= 96,
+    SP_BPLEZnapn	= 97,
+    SP_BPLEZnapt	= 98,
+    SP_BPLZapn	= 99,
+    SP_BPLZapt	= 100,
+    SP_BPLZnapn	= 101,
+    SP_BPLZnapt	= 102,
+    SP_BPNZapn	= 103,
+    SP_BPNZapt	= 104,
+    SP_BPNZnapn	= 105,
+    SP_BPNZnapt	= 106,
+    SP_BPXCC	= 107,
+    SP_BPXCCA	= 108,
+    SP_BPXCCANT	= 109,
+    SP_BPXCCNT	= 110,
+    SP_BPZapn	= 111,
+    SP_BPZapt	= 112,
+    SP_BPZnapn	= 113,
+    SP_BPZnapt	= 114,
+    SP_BSHUFFLE	= 115,
+    SP_CALL	= 116,
+    SP_CALLri	= 117,
+    SP_CALLrr	= 118,
+    SP_CASXrr	= 119,
+    SP_CASrr	= 120,
+    SP_CMASK16	= 121,
+    SP_CMASK32	= 122,
+    SP_CMASK8	= 123,
+    SP_CMPri	= 124,
+    SP_CMPrr	= 125,
+    SP_EDGE16	= 126,
+    SP_EDGE16L	= 127,
+    SP_EDGE16LN	= 128,
+    SP_EDGE16N	= 129,
+    SP_EDGE32	= 130,
+    SP_EDGE32L	= 131,
+    SP_EDGE32LN	= 132,
+    SP_EDGE32N	= 133,
+    SP_EDGE8	= 134,
+    SP_EDGE8L	= 135,
+    SP_EDGE8LN	= 136,
+    SP_EDGE8N	= 137,
+    SP_FABSD	= 138,
+    SP_FABSQ	= 139,
+    SP_FABSS	= 140,
+    SP_FADDD	= 141,
+    SP_FADDQ	= 142,
+    SP_FADDS	= 143,
+    SP_FALIGNADATA	= 144,
+    SP_FAND	= 145,
+    SP_FANDNOT1	= 146,
+    SP_FANDNOT1S	= 147,
+    SP_FANDNOT2	= 148,
+    SP_FANDNOT2S	= 149,
+    SP_FANDS	= 150,
+    SP_FBCOND	= 151,
+    SP_FBCONDA	= 152,
+    SP_FCHKSM16	= 153,
+    SP_FCMPD	= 154,
+    SP_FCMPEQ16	= 155,
+    SP_FCMPEQ32	= 156,
+    SP_FCMPGT16	= 157,
+    SP_FCMPGT32	= 158,
+    SP_FCMPLE16	= 159,
+    SP_FCMPLE32	= 160,
+    SP_FCMPNE16	= 161,
+    SP_FCMPNE32	= 162,
+    SP_FCMPQ	= 163,
+    SP_FCMPS	= 164,
+    SP_FDIVD	= 165,
+    SP_FDIVQ	= 166,
+    SP_FDIVS	= 167,
+    SP_FDMULQ	= 168,
+    SP_FDTOI	= 169,
+    SP_FDTOQ	= 170,
+    SP_FDTOS	= 171,
+    SP_FDTOX	= 172,
+    SP_FEXPAND	= 173,
+    SP_FHADDD	= 174,
+    SP_FHADDS	= 175,
+    SP_FHSUBD	= 176,
+    SP_FHSUBS	= 177,
+    SP_FITOD	= 178,
+    SP_FITOQ	= 179,
+    SP_FITOS	= 180,
+    SP_FLCMPD	= 181,
+    SP_FLCMPS	= 182,
+    SP_FLUSHW	= 183,
+    SP_FMEAN16	= 184,
+    SP_FMOVD	= 185,
+    SP_FMOVD_FCC	= 186,
+    SP_FMOVD_ICC	= 187,
+    SP_FMOVD_XCC	= 188,
+    SP_FMOVQ	= 189,
+    SP_FMOVQ_FCC	= 190,
+    SP_FMOVQ_ICC	= 191,
+    SP_FMOVQ_XCC	= 192,
+    SP_FMOVRGEZD	= 193,
+    SP_FMOVRGEZQ	= 194,
+    SP_FMOVRGEZS	= 195,
+    SP_FMOVRGZD	= 196,
+    SP_FMOVRGZQ	= 197,
+    SP_FMOVRGZS	= 198,
+    SP_FMOVRLEZD	= 199,
+    SP_FMOVRLEZQ	= 200,
+    SP_FMOVRLEZS	= 201,
+    SP_FMOVRLZD	= 202,
+    SP_FMOVRLZQ	= 203,
+    SP_FMOVRLZS	= 204,
+    SP_FMOVRNZD	= 205,
+    SP_FMOVRNZQ	= 206,
+    SP_FMOVRNZS	= 207,
+    SP_FMOVRZD	= 208,
+    SP_FMOVRZQ	= 209,
+    SP_FMOVRZS	= 210,
+    SP_FMOVS	= 211,
+    SP_FMOVS_FCC	= 212,
+    SP_FMOVS_ICC	= 213,
+    SP_FMOVS_XCC	= 214,
+    SP_FMUL8SUX16	= 215,
+    SP_FMUL8ULX16	= 216,
+    SP_FMUL8X16	= 217,
+    SP_FMUL8X16AL	= 218,
+    SP_FMUL8X16AU	= 219,
+    SP_FMULD	= 220,
+    SP_FMULD8SUX16	= 221,
+    SP_FMULD8ULX16	= 222,
+    SP_FMULQ	= 223,
+    SP_FMULS	= 224,
+    SP_FNADDD	= 225,
+    SP_FNADDS	= 226,
+    SP_FNAND	= 227,
+    SP_FNANDS	= 228,
+    SP_FNEGD	= 229,
+    SP_FNEGQ	= 230,
+    SP_FNEGS	= 231,
+    SP_FNHADDD	= 232,
+    SP_FNHADDS	= 233,
+    SP_FNMULD	= 234,
+    SP_FNMULS	= 235,
+    SP_FNOR	= 236,
+    SP_FNORS	= 237,
+    SP_FNOT1	= 238,
+    SP_FNOT1S	= 239,
+    SP_FNOT2	= 240,
+    SP_FNOT2S	= 241,
+    SP_FNSMULD	= 242,
+    SP_FONE	= 243,
+    SP_FONES	= 244,
+    SP_FOR	= 245,
+    SP_FORNOT1	= 246,
+    SP_FORNOT1S	= 247,
+    SP_FORNOT2	= 248,
+    SP_FORNOT2S	= 249,
+    SP_FORS	= 250,
+    SP_FPACK16	= 251,
+    SP_FPACK32	= 252,
+    SP_FPACKFIX	= 253,
+    SP_FPADD16	= 254,
+    SP_FPADD16S	= 255,
+    SP_FPADD32	= 256,
+    SP_FPADD32S	= 257,
+    SP_FPADD64	= 258,
+    SP_FPMERGE	= 259,
+    SP_FPSUB16	= 260,
+    SP_FPSUB16S	= 261,
+    SP_FPSUB32	= 262,
+    SP_FPSUB32S	= 263,
+    SP_FQTOD	= 264,
+    SP_FQTOI	= 265,
+    SP_FQTOS	= 266,
+    SP_FQTOX	= 267,
+    SP_FSLAS16	= 268,
+    SP_FSLAS32	= 269,
+    SP_FSLL16	= 270,
+    SP_FSLL32	= 271,
+    SP_FSMULD	= 272,
+    SP_FSQRTD	= 273,
+    SP_FSQRTQ	= 274,
+    SP_FSQRTS	= 275,
+    SP_FSRA16	= 276,
+    SP_FSRA32	= 277,
+    SP_FSRC1	= 278,
+    SP_FSRC1S	= 279,
+    SP_FSRC2	= 280,
+    SP_FSRC2S	= 281,
+    SP_FSRL16	= 282,
+    SP_FSRL32	= 283,
+    SP_FSTOD	= 284,
+    SP_FSTOI	= 285,
+    SP_FSTOQ	= 286,
+    SP_FSTOX	= 287,
+    SP_FSUBD	= 288,
+    SP_FSUBQ	= 289,
+    SP_FSUBS	= 290,
+    SP_FXNOR	= 291,
+    SP_FXNORS	= 292,
+    SP_FXOR	= 293,
+    SP_FXORS	= 294,
+    SP_FXTOD	= 295,
+    SP_FXTOQ	= 296,
+    SP_FXTOS	= 297,
+    SP_FZERO	= 298,
+    SP_FZEROS	= 299,
+    SP_GETPCX	= 300,
+    SP_JMPLri	= 301,
+    SP_JMPLrr	= 302,
+    SP_LDDFri	= 303,
+    SP_LDDFrr	= 304,
+    SP_LDFri	= 305,
+    SP_LDFrr	= 306,
+    SP_LDQFri	= 307,
+    SP_LDQFrr	= 308,
+    SP_LDSBri	= 309,
+    SP_LDSBrr	= 310,
+    SP_LDSHri	= 311,
+    SP_LDSHrr	= 312,
+    SP_LDSWri	= 313,
+    SP_LDSWrr	= 314,
+    SP_LDUBri	= 315,
+    SP_LDUBrr	= 316,
+    SP_LDUHri	= 317,
+    SP_LDUHrr	= 318,
+    SP_LDXri	= 319,
+    SP_LDXrr	= 320,
+    SP_LDri	= 321,
+    SP_LDrr	= 322,
+    SP_LEAX_ADDri	= 323,
+    SP_LEA_ADDri	= 324,
+    SP_LZCNT	= 325,
+    SP_MEMBARi	= 326,
+    SP_MOVDTOX	= 327,
+    SP_MOVFCCri	= 328,
+    SP_MOVFCCrr	= 329,
+    SP_MOVICCri	= 330,
+    SP_MOVICCrr	= 331,
+    SP_MOVRGEZri	= 332,
+    SP_MOVRGEZrr	= 333,
+    SP_MOVRGZri	= 334,
+    SP_MOVRGZrr	= 335,
+    SP_MOVRLEZri	= 336,
+    SP_MOVRLEZrr	= 337,
+    SP_MOVRLZri	= 338,
+    SP_MOVRLZrr	= 339,
+    SP_MOVRNZri	= 340,
+    SP_MOVRNZrr	= 341,
+    SP_MOVRRZri	= 342,
+    SP_MOVRRZrr	= 343,
+    SP_MOVSTOSW	= 344,
+    SP_MOVSTOUW	= 345,
+    SP_MOVWTOS	= 346,
+    SP_MOVXCCri	= 347,
+    SP_MOVXCCrr	= 348,
+    SP_MOVXTOD	= 349,
+    SP_MULXri	= 350,
+    SP_MULXrr	= 351,
+    SP_NOP	= 352,
+    SP_ORCCri	= 353,
+    SP_ORCCrr	= 354,
+    SP_ORNCCri	= 355,
+    SP_ORNCCrr	= 356,
+    SP_ORNri	= 357,
+    SP_ORNrr	= 358,
+    SP_ORXNrr	= 359,
+    SP_ORXri	= 360,
+    SP_ORXrr	= 361,
+    SP_ORri	= 362,
+    SP_ORrr	= 363,
+    SP_PDIST	= 364,
+    SP_PDISTN	= 365,
+    SP_POPCrr	= 366,
+    SP_RDY	= 367,
+    SP_RESTOREri	= 368,
+    SP_RESTORErr	= 369,
+    SP_RET	= 370,
+    SP_RETL	= 371,
+    SP_RETTri	= 372,
+    SP_RETTrr	= 373,
+    SP_SAVEri	= 374,
+    SP_SAVErr	= 375,
+    SP_SDIVCCri	= 376,
+    SP_SDIVCCrr	= 377,
+    SP_SDIVXri	= 378,
+    SP_SDIVXrr	= 379,
+    SP_SDIVri	= 380,
+    SP_SDIVrr	= 381,
+    SP_SELECT_CC_DFP_FCC	= 382,
+    SP_SELECT_CC_DFP_ICC	= 383,
+    SP_SELECT_CC_FP_FCC	= 384,
+    SP_SELECT_CC_FP_ICC	= 385,
+    SP_SELECT_CC_Int_FCC	= 386,
+    SP_SELECT_CC_Int_ICC	= 387,
+    SP_SELECT_CC_QFP_FCC	= 388,
+    SP_SELECT_CC_QFP_ICC	= 389,
+    SP_SETHIXi	= 390,
+    SP_SETHIi	= 391,
+    SP_SHUTDOWN	= 392,
+    SP_SIAM	= 393,
+    SP_SLLXri	= 394,
+    SP_SLLXrr	= 395,
+    SP_SLLri	= 396,
+    SP_SLLrr	= 397,
+    SP_SMULCCri	= 398,
+    SP_SMULCCrr	= 399,
+    SP_SMULri	= 400,
+    SP_SMULrr	= 401,
+    SP_SRAXri	= 402,
+    SP_SRAXrr	= 403,
+    SP_SRAri	= 404,
+    SP_SRArr	= 405,
+    SP_SRLXri	= 406,
+    SP_SRLXrr	= 407,
+    SP_SRLri	= 408,
+    SP_SRLrr	= 409,
+    SP_STBAR	= 410,
+    SP_STBri	= 411,
+    SP_STBrr	= 412,
+    SP_STDFri	= 413,
+    SP_STDFrr	= 414,
+    SP_STFri	= 415,
+    SP_STFrr	= 416,
+    SP_STHri	= 417,
+    SP_STHrr	= 418,
+    SP_STQFri	= 419,
+    SP_STQFrr	= 420,
+    SP_STXri	= 421,
+    SP_STXrr	= 422,
+    SP_STri	= 423,
+    SP_STrr	= 424,
+    SP_SUBCCri	= 425,
+    SP_SUBCCrr	= 426,
+    SP_SUBCri	= 427,
+    SP_SUBCrr	= 428,
+    SP_SUBEri	= 429,
+    SP_SUBErr	= 430,
+    SP_SUBXri	= 431,
+    SP_SUBXrr	= 432,
+    SP_SUBri	= 433,
+    SP_SUBrr	= 434,
+    SP_SWAPri	= 435,
+    SP_SWAPrr	= 436,
+    SP_TA3	= 437,
+    SP_TA5	= 438,
+    SP_TADDCCTVri	= 439,
+    SP_TADDCCTVrr	= 440,
+    SP_TADDCCri	= 441,
+    SP_TADDCCrr	= 442,
+    SP_TICCri	= 443,
+    SP_TICCrr	= 444,
+    SP_TLS_ADDXrr	= 445,
+    SP_TLS_ADDrr	= 446,
+    SP_TLS_CALL	= 447,
+    SP_TLS_LDXrr	= 448,
+    SP_TLS_LDrr	= 449,
+    SP_TSUBCCTVri	= 450,
+    SP_TSUBCCTVrr	= 451,
+    SP_TSUBCCri	= 452,
+    SP_TSUBCCrr	= 453,
+    SP_TXCCri	= 454,
+    SP_TXCCrr	= 455,
+    SP_UDIVCCri	= 456,
+    SP_UDIVCCrr	= 457,
+    SP_UDIVXri	= 458,
+    SP_UDIVXrr	= 459,
+    SP_UDIVri	= 460,
+    SP_UDIVrr	= 461,
+    SP_UMULCCri	= 462,
+    SP_UMULCCrr	= 463,
+    SP_UMULXHI	= 464,
+    SP_UMULri	= 465,
+    SP_UMULrr	= 466,
+    SP_UNIMP	= 467,
+    SP_V9FCMPD	= 468,
+    SP_V9FCMPED	= 469,
+    SP_V9FCMPEQ	= 470,
+    SP_V9FCMPES	= 471,
+    SP_V9FCMPQ	= 472,
+    SP_V9FCMPS	= 473,
+    SP_V9FMOVD_FCC	= 474,
+    SP_V9FMOVQ_FCC	= 475,
+    SP_V9FMOVS_FCC	= 476,
+    SP_V9MOVFCCri	= 477,
+    SP_V9MOVFCCrr	= 478,
+    SP_WRYri	= 479,
+    SP_WRYrr	= 480,
+    SP_XMULX	= 481,
+    SP_XMULXHI	= 482,
+    SP_XNORCCri	= 483,
+    SP_XNORCCrr	= 484,
+    SP_XNORXrr	= 485,
+    SP_XNORri	= 486,
+    SP_XNORrr	= 487,
+    SP_XORCCri	= 488,
+    SP_XORCCrr	= 489,
+    SP_XORXri	= 490,
+    SP_XORXrr	= 491,
+    SP_XORri	= 492,
+    SP_XORrr	= 493,
+    SP_INSTRUCTION_LIST_END = 494
+};
+
+#endif // GET_INSTRINFO_ENUM

thirdparty/capstone/arch/Sparc/SparcGenRegisterInfo.inc

@@ -0,0 +1,451 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|*Target Register Enum Values                                                 *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+
+
+#ifdef GET_REGINFO_ENUM
+#undef GET_REGINFO_ENUM
+
+enum {
+  SP_NoRegister,
+  SP_ICC = 1,
+  SP_Y = 2,
+  SP_D0 = 3,
+  SP_D1 = 4,
+  SP_D2 = 5,
+  SP_D3 = 6,
+  SP_D4 = 7,
+  SP_D5 = 8,
+  SP_D6 = 9,
+  SP_D7 = 10,
+  SP_D8 = 11,
+  SP_D9 = 12,
+  SP_D10 = 13,
+  SP_D11 = 14,
+  SP_D12 = 15,
+  SP_D13 = 16,
+  SP_D14 = 17,
+  SP_D15 = 18,
+  SP_D16 = 19,
+  SP_D17 = 20,
+  SP_D18 = 21,
+  SP_D19 = 22,
+  SP_D20 = 23,
+  SP_D21 = 24,
+  SP_D22 = 25,
+  SP_D23 = 26,
+  SP_D24 = 27,
+  SP_D25 = 28,
+  SP_D26 = 29,
+  SP_D27 = 30,
+  SP_D28 = 31,
+  SP_D29 = 32,
+  SP_D30 = 33,
+  SP_D31 = 34,
+  SP_F0 = 35,
+  SP_F1 = 36,
+  SP_F2 = 37,
+  SP_F3 = 38,
+  SP_F4 = 39,
+  SP_F5 = 40,
+  SP_F6 = 41,
+  SP_F7 = 42,
+  SP_F8 = 43,
+  SP_F9 = 44,
+  SP_F10 = 45,
+  SP_F11 = 46,
+  SP_F12 = 47,
+  SP_F13 = 48,
+  SP_F14 = 49,
+  SP_F15 = 50,
+  SP_F16 = 51,
+  SP_F17 = 52,
+  SP_F18 = 53,
+  SP_F19 = 54,
+  SP_F20 = 55,
+  SP_F21 = 56,
+  SP_F22 = 57,
+  SP_F23 = 58,
+  SP_F24 = 59,
+  SP_F25 = 60,
+  SP_F26 = 61,
+  SP_F27 = 62,
+  SP_F28 = 63,
+  SP_F29 = 64,
+  SP_F30 = 65,
+  SP_F31 = 66,
+  SP_FCC0 = 67,
+  SP_FCC1 = 68,
+  SP_FCC2 = 69,
+  SP_FCC3 = 70,
+  SP_G0 = 71,
+  SP_G1 = 72,
+  SP_G2 = 73,
+  SP_G3 = 74,
+  SP_G4 = 75,
+  SP_G5 = 76,
+  SP_G6 = 77,
+  SP_G7 = 78,
+  SP_I0 = 79,
+  SP_I1 = 80,
+  SP_I2 = 81,
+  SP_I3 = 82,
+  SP_I4 = 83,
+  SP_I5 = 84,
+  SP_I6 = 85,
+  SP_I7 = 86,
+  SP_L0 = 87,
+  SP_L1 = 88,
+  SP_L2 = 89,
+  SP_L3 = 90,
+  SP_L4 = 91,
+  SP_L5 = 92,
+  SP_L6 = 93,
+  SP_L7 = 94,
+  SP_O0 = 95,
+  SP_O1 = 96,
+  SP_O2 = 97,
+  SP_O3 = 98,
+  SP_O4 = 99,
+  SP_O5 = 100,
+  SP_O6 = 101,
+  SP_O7 = 102,
+  SP_Q0 = 103,
+  SP_Q1 = 104,
+  SP_Q2 = 105,
+  SP_Q3 = 106,
+  SP_Q4 = 107,
+  SP_Q5 = 108,
+  SP_Q6 = 109,
+  SP_Q7 = 110,
+  SP_Q8 = 111,
+  SP_Q9 = 112,
+  SP_Q10 = 113,
+  SP_Q11 = 114,
+  SP_Q12 = 115,
+  SP_Q13 = 116,
+  SP_Q14 = 117,
+  SP_Q15 = 118,
+  SP_NUM_TARGET_REGS 	// 119
+};
+
+// Register classes
+enum {
+  SP_FCCRegsRegClassID = 0,
+  SP_FPRegsRegClassID = 1,
+  SP_IntRegsRegClassID = 2,
+  SP_DFPRegsRegClassID = 3,
+  SP_I64RegsRegClassID = 4,
+  SP_DFPRegs_with_sub_evenRegClassID = 5,
+  SP_QFPRegsRegClassID = 6,
+  SP_QFPRegs_with_sub_evenRegClassID = 7
+};
+
+#endif // GET_REGINFO_ENUM
+
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|*MC Register Information                                                     *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+
+#ifdef GET_REGINFO_MC_DESC
+#undef GET_REGINFO_MC_DESC
+
+static const MCPhysReg SparcRegDiffLists[] = {
+  /* 0 */ -410, 1, 1, 1, 0,
+  /* 5 */ 32, 1, 0,
+  /* 8 */ -100, 32, 1, -32, 33, 1, 0,
+  /* 15 */ 34, 1, 0,
+  /* 18 */ -99, 34, 1, -34, 35, 1, 0,
+  /* 25 */ 36, 1, 0,
+  /* 28 */ -98, 36, 1, -36, 37, 1, 0,
+  /* 35 */ 38, 1, 0,
+  /* 38 */ -97, 38, 1, -38, 39, 1, 0,
+  /* 45 */ 40, 1, 0,
+  /* 48 */ -96, 40, 1, -40, 41, 1, 0,
+  /* 55 */ 42, 1, 0,
+  /* 58 */ -95, 42, 1, -42, 43, 1, 0,
+  /* 65 */ 44, 1, 0,
+  /* 68 */ -94, 44, 1, -44, 45, 1, 0,
+  /* 75 */ 46, 1, 0,
+  /* 78 */ -93, 46, 1, -46, 47, 1, 0,
+  /* 85 */ -188, 1, 0,
+  /* 88 */ -92, 1, 0,
+  /* 91 */ -91, 1, 0,
+  /* 94 */ -90, 1, 0,
+  /* 97 */ -89, 1, 0,
+  /* 100 */ -88, 1, 0,
+  /* 103 */ -87, 1, 0,
+  /* 106 */ -86, 1, 0,
+  /* 109 */ -85, 1, 0,
+  /* 112 */ -4, 1, 0,
+  /* 115 */ 15, 0,
+  /* 117 */ 84, 0,
+  /* 119 */ 85, 0,
+  /* 121 */ 86, 0,
+  /* 123 */ 87, 0,
+  /* 125 */ 88, 0,
+  /* 127 */ 89, 0,
+  /* 129 */ 90, 0,
+  /* 131 */ 91, 0,
+  /* 133 */ -48, 92, 0,
+  /* 136 */ -47, 92, 0,
+  /* 139 */ -47, 93, 0,
+  /* 142 */ -46, 93, 0,
+  /* 145 */ -45, 93, 0,
+  /* 148 */ -45, 94, 0,
+  /* 151 */ -44, 94, 0,
+  /* 154 */ -43, 94, 0,
+  /* 157 */ -43, 95, 0,
+  /* 160 */ -42, 95, 0,
+  /* 163 */ -41, 95, 0,
+  /* 166 */ -41, 96, 0,
+  /* 169 */ -40, 96, 0,
+  /* 172 */ -39, 96, 0,
+  /* 175 */ -39, 97, 0,
+  /* 178 */ -38, 97, 0,
+  /* 181 */ -37, 97, 0,
+  /* 184 */ -37, 98, 0,
+  /* 187 */ -36, 98, 0,
+  /* 190 */ -35, 98, 0,
+  /* 193 */ -35, 99, 0,
+  /* 196 */ -34, 99, 0,
+  /* 199 */ -33, 99, 0,
+  /* 202 */ -33, 100, 0,
+  /* 205 */ -32, 100, 0,
+  /* 208 */ -33, 0,
+  /* 210 */ -17, 0,
+  /* 212 */ -1, 0,
+};
+
+static const uint16_t SparcSubRegIdxLists[] = {
+  /* 0 */ 1, 3, 0,
+  /* 3 */ 2, 4, 0,
+  /* 6 */ 2, 1, 3, 4, 5, 6, 0,
+};
+
+static const MCRegisterDesc SparcRegDesc[] = { // Descriptors
+  { 3, 0, 0, 0, 0, 0 },
+  { 406, 4, 4, 2, 3393, 0 },
+  { 410, 4, 4, 2, 3393, 0 },
+  { 33, 5, 203, 0, 1794, 2 },
+  { 87, 12, 194, 0, 1794, 2 },
+  { 133, 15, 194, 0, 1794, 2 },
+  { 179, 22, 185, 0, 1794, 2 },
+  { 220, 25, 185, 0, 1794, 2 },
+  { 261, 32, 176, 0, 1794, 2 },
+  { 298, 35, 176, 0, 1794, 2 },
+  { 335, 42, 167, 0, 1794, 2 },
+  { 372, 45, 167, 0, 1794, 2 },
+  { 397, 52, 158, 0, 1794, 2 },
+  { 0, 55, 158, 0, 1794, 2 },
+  { 54, 62, 149, 0, 1794, 2 },
+  { 108, 65, 149, 0, 1794, 2 },
+  { 154, 72, 140, 0, 1794, 2 },
+  { 200, 75, 140, 0, 1794, 2 },
+  { 241, 82, 134, 0, 1794, 2 },
+  { 282, 4, 134, 2, 1841, 0 },
+  { 319, 4, 131, 2, 1841, 0 },
+  { 356, 4, 131, 2, 1841, 0 },
+  { 381, 4, 129, 2, 1841, 0 },
+  { 12, 4, 129, 2, 1841, 0 },
+  { 66, 4, 127, 2, 1841, 0 },
+  { 120, 4, 127, 2, 1841, 0 },
+  { 166, 4, 125, 2, 1841, 0 },
+  { 212, 4, 125, 2, 1841, 0 },
+  { 253, 4, 123, 2, 1841, 0 },
+  { 290, 4, 123, 2, 1841, 0 },
+  { 327, 4, 121, 2, 1841, 0 },
+  { 364, 4, 121, 2, 1841, 0 },
+  { 389, 4, 119, 2, 1841, 0 },
+  { 20, 4, 119, 2, 1841, 0 },
+  { 74, 4, 117, 2, 1841, 0 },
+  { 36, 4, 205, 2, 3329, 0 },
+  { 90, 4, 202, 2, 3329, 0 },
+  { 136, 4, 199, 2, 3329, 0 },
+  { 182, 4, 196, 2, 3329, 0 },
+  { 223, 4, 196, 2, 3329, 0 },
+  { 264, 4, 193, 2, 3329, 0 },
+  { 301, 4, 190, 2, 3329, 0 },
+  { 338, 4, 187, 2, 3329, 0 },
+  { 375, 4, 187, 2, 3329, 0 },
+  { 400, 4, 184, 2, 3329, 0 },
+  { 4, 4, 181, 2, 3329, 0 },
+  { 58, 4, 178, 2, 3329, 0 },
+  { 112, 4, 178, 2, 3329, 0 },
+  { 158, 4, 175, 2, 3329, 0 },
+  { 204, 4, 172, 2, 3329, 0 },
+  { 245, 4, 169, 2, 3329, 0 },
+  { 286, 4, 169, 2, 3329, 0 },
+  { 323, 4, 166, 2, 3329, 0 },
+  { 360, 4, 163, 2, 3329, 0 },
+  { 385, 4, 160, 2, 3329, 0 },
+  { 16, 4, 160, 2, 3329, 0 },
+  { 70, 4, 157, 2, 3329, 0 },
+  { 124, 4, 154, 2, 3329, 0 },
+  { 170, 4, 151, 2, 3329, 0 },
+  { 216, 4, 151, 2, 3329, 0 },
+  { 257, 4, 148, 2, 3329, 0 },
+  { 294, 4, 145, 2, 3329, 0 },
+  { 331, 4, 142, 2, 3329, 0 },
+  { 368, 4, 142, 2, 3329, 0 },
+  { 393, 4, 139, 2, 3329, 0 },
+  { 24, 4, 136, 2, 3329, 0 },
+  { 78, 4, 133, 2, 3329, 0 },
+  { 28, 4, 4, 2, 3361, 0 },
+  { 82, 4, 4, 2, 3361, 0 },
+  { 128, 4, 4, 2, 3361, 0 },
+  { 174, 4, 4, 2, 3361, 0 },
+  { 39, 4, 4, 2, 3361, 0 },
+  { 93, 4, 4, 2, 3361, 0 },
+  { 139, 4, 4, 2, 3361, 0 },
+  { 185, 4, 4, 2, 3361, 0 },
+  { 226, 4, 4, 2, 3361, 0 },
+  { 267, 4, 4, 2, 3361, 0 },
+  { 304, 4, 4, 2, 3361, 0 },
+  { 341, 4, 4, 2, 3361, 0 },
+  { 42, 4, 4, 2, 3361, 0 },
+  { 96, 4, 4, 2, 3361, 0 },
+  { 142, 4, 4, 2, 3361, 0 },
+  { 188, 4, 4, 2, 3361, 0 },
+  { 229, 4, 4, 2, 3361, 0 },
+  { 270, 4, 4, 2, 3361, 0 },
+  { 307, 4, 4, 2, 3361, 0 },
+  { 344, 4, 4, 2, 3361, 0 },
+  { 45, 4, 4, 2, 3361, 0 },
+  { 99, 4, 4, 2, 3361, 0 },
+  { 145, 4, 4, 2, 3361, 0 },
+  { 191, 4, 4, 2, 3361, 0 },
+  { 232, 4, 4, 2, 3361, 0 },
+  { 273, 4, 4, 2, 3361, 0 },
+  { 310, 4, 4, 2, 3361, 0 },
+  { 347, 4, 4, 2, 3361, 0 },
+  { 48, 4, 4, 2, 3361, 0 },
+  { 102, 4, 4, 2, 3361, 0 },
+  { 148, 4, 4, 2, 3361, 0 },
+  { 194, 4, 4, 2, 3361, 0 },
+  { 235, 4, 4, 2, 3361, 0 },
+  { 276, 4, 4, 2, 3361, 0 },
+  { 313, 4, 4, 2, 3361, 0 },
+  { 350, 4, 4, 2, 3361, 0 },
+  { 51, 8, 4, 6, 4, 5 },
+  { 105, 18, 4, 6, 4, 5 },
+  { 151, 28, 4, 6, 4, 5 },
+  { 197, 38, 4, 6, 4, 5 },
+  { 238, 48, 4, 6, 4, 5 },
+  { 279, 58, 4, 6, 4, 5 },
+  { 316, 68, 4, 6, 4, 5 },
+  { 353, 78, 4, 6, 4, 5 },
+  { 378, 88, 4, 3, 1362, 10 },
+  { 403, 91, 4, 3, 1362, 10 },
+  { 8, 94, 4, 3, 1362, 10 },
+  { 62, 97, 4, 3, 1362, 10 },
+  { 116, 100, 4, 3, 1362, 10 },
+  { 162, 103, 4, 3, 1362, 10 },
+  { 208, 106, 4, 3, 1362, 10 },
+  { 249, 109, 4, 3, 1362, 10 },
+};
+
+  // FCCRegs Register Class...
+  static const MCPhysReg FCCRegs[] = {
+    SP_FCC0, SP_FCC1, SP_FCC2, SP_FCC3,
+  };
+
+  // FCCRegs Bit set.
+  static const uint8_t FCCRegsBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
+  };
+
+  // FPRegs Register Class...
+  static const MCPhysReg FPRegs[] = {
+    SP_F0, SP_F1, SP_F2, SP_F3, SP_F4, SP_F5, SP_F6, SP_F7, SP_F8, SP_F9, SP_F10, SP_F11, SP_F12, SP_F13, SP_F14, SP_F15, SP_F16, SP_F17, SP_F18, SP_F19, SP_F20, SP_F21, SP_F22, SP_F23, SP_F24, SP_F25, SP_F26, SP_F27, SP_F28, SP_F29, SP_F30, SP_F31,
+  };
+
+  // FPRegs Bit set.
+  static const uint8_t FPRegsBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
+  };
+
+  // IntRegs Register Class...
+  static const MCPhysReg IntRegs[] = {
+    SP_I0, SP_I1, SP_I2, SP_I3, SP_I4, SP_I5, SP_I6, SP_I7, SP_G0, SP_G1, SP_G2, SP_G3, SP_G4, SP_G5, SP_G6, SP_G7, SP_L0, SP_L1, SP_L2, SP_L3, SP_L4, SP_L5, SP_L6, SP_L7, SP_O0, SP_O1, SP_O2, SP_O3, SP_O4, SP_O5, SP_O6, SP_O7,
+  };
+
+  // IntRegs Bit set.
+  static const uint8_t IntRegsBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f,
+  };
+
+  // DFPRegs Register Class...
+  static const MCPhysReg DFPRegs[] = {
+    SP_D0, SP_D1, SP_D2, SP_D3, SP_D4, SP_D5, SP_D6, SP_D7, SP_D8, SP_D9, SP_D10, SP_D11, SP_D12, SP_D13, SP_D14, SP_D15, SP_D16, SP_D17, SP_D18, SP_D19, SP_D20, SP_D21, SP_D22, SP_D23, SP_D24, SP_D25, SP_D26, SP_D27, SP_D28, SP_D29, SP_D30, SP_D31,
+  };
+
+  // DFPRegs Bit set.
+  static const uint8_t DFPRegsBits[] = {
+    0xf8, 0xff, 0xff, 0xff, 0x07,
+  };
+
+  // I64Regs Register Class...
+  static const MCPhysReg I64Regs[] = {
+    SP_I0, SP_I1, SP_I2, SP_I3, SP_I4, SP_I5, SP_I6, SP_I7, SP_G0, SP_G1, SP_G2, SP_G3, SP_G4, SP_G5, SP_G6, SP_G7, SP_L0, SP_L1, SP_L2, SP_L3, SP_L4, SP_L5, SP_L6, SP_L7, SP_O0, SP_O1, SP_O2, SP_O3, SP_O4, SP_O5, SP_O6, SP_O7,
+  };
+
+  // I64Regs Bit set.
+  static const uint8_t I64RegsBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f,
+  };
+
+  // DFPRegs_with_sub_even Register Class...
+  static const MCPhysReg DFPRegs_with_sub_even[] = {
+    SP_D0, SP_D1, SP_D2, SP_D3, SP_D4, SP_D5, SP_D6, SP_D7, SP_D8, SP_D9, SP_D10, SP_D11, SP_D12, SP_D13, SP_D14, SP_D15,
+  };
+
+  // DFPRegs_with_sub_even Bit set.
+  static const uint8_t DFPRegs_with_sub_evenBits[] = {
+    0xf8, 0xff, 0x07,
+  };
+
+  // QFPRegs Register Class...
+  static const MCPhysReg QFPRegs[] = {
+    SP_Q0, SP_Q1, SP_Q2, SP_Q3, SP_Q4, SP_Q5, SP_Q6, SP_Q7, SP_Q8, SP_Q9, SP_Q10, SP_Q11, SP_Q12, SP_Q13, SP_Q14, SP_Q15,
+  };
+
+  // QFPRegs Bit set.
+  static const uint8_t QFPRegsBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
+  };
+
+  // QFPRegs_with_sub_even Register Class...
+  static const MCPhysReg QFPRegs_with_sub_even[] = {
+    SP_Q0, SP_Q1, SP_Q2, SP_Q3, SP_Q4, SP_Q5, SP_Q6, SP_Q7,
+  };
+
+  // QFPRegs_with_sub_even Bit set.
+  static const uint8_t QFPRegs_with_sub_evenBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
+  };
+
+static const MCRegisterClass SparcMCRegisterClasses[] = {
+  { FCCRegs, FCCRegsBits, sizeof(FCCRegsBits) },
+  { FPRegs, FPRegsBits, sizeof(FPRegsBits) },
+  { IntRegs, IntRegsBits, sizeof(IntRegsBits) },
+  { DFPRegs, DFPRegsBits, sizeof(DFPRegsBits) },
+  { I64Regs, I64RegsBits, sizeof(I64RegsBits) },
+  { DFPRegs_with_sub_even, DFPRegs_with_sub_evenBits, sizeof(DFPRegs_with_sub_evenBits) },
+  { QFPRegs, QFPRegsBits, sizeof(QFPRegsBits) },
+  { QFPRegs_with_sub_even, QFPRegs_with_sub_evenBits, sizeof(QFPRegs_with_sub_evenBits) },
+};
+
+#endif // GET_REGINFO_MC_DESC

thirdparty/capstone/arch/Sparc/SparcGenSubtargetInfo.inc

@@ -0,0 +1,27 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|*Subtarget Enumeration Source Fragment                                       *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+
+#ifdef GET_SUBTARGETINFO_ENUM
+#undef GET_SUBTARGETINFO_ENUM
+
+enum {
+  Sparc_FeatureHardQuad =  1ULL << 0,
+  Sparc_FeatureV8Deprecated =  1ULL << 1,
+  Sparc_FeatureV9 =  1ULL << 2,
+  Sparc_FeatureVIS =  1ULL << 3,
+  Sparc_FeatureVIS2 =  1ULL << 4,
+  Sparc_FeatureVIS3 =  1ULL << 5,
+  Sparc_UsePopc =  1ULL << 6
+};
+
+#endif // GET_SUBTARGETINFO_ENUM
+

thirdparty/capstone/arch/Sparc/SparcInstPrinter.c

@@ -0,0 +1,446 @@
+//===-- SparcInstPrinter.cpp - Convert Sparc MCInst to assembly syntax --------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This class prints an Sparc MCInst to a .s file.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifdef CAPSTONE_HAS_SPARC
+
+#ifdef _MSC_VER
+#define _CRT_SECURE_NO_WARNINGS
+#endif
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <limits.h>
+
+#include "SparcInstPrinter.h"
+#include "../../MCInst.h"
+#include "../../utils.h"
+#include "../../SStream.h"
+#include "../../MCRegisterInfo.h"
+#include "../../MathExtras.h"
+#include "SparcMapping.h"
+
+#include "Sparc.h"
+
+static const char *getRegisterName(unsigned RegNo);
+static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI);
+static void printMemOperand(MCInst *MI, int opNum, SStream *O, const char *Modifier);
+static void printOperand(MCInst *MI, int opNum, SStream *O);
+
+static void Sparc_add_hint(MCInst *MI, unsigned int hint)
+{
+	if (MI->csh->detail_opt) {
+		MI->flat_insn->detail->sparc.hint = hint;
+	}
+}
+
+static void Sparc_add_reg(MCInst *MI, unsigned int reg)
+{
+	if (MI->csh->detail_opt) {
+		MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_REG;
+		MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].reg = reg;
+		MI->flat_insn->detail->sparc.op_count++;
+	}
+}
+
+static void set_mem_access(MCInst *MI, bool status)
+{
+	if (MI->csh->detail_opt != CS_OPT_ON)
+		return;
+
+	MI->csh->doing_mem = status;
+
+	if (status) {
+		MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_MEM;
+		MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.base = SPARC_REG_INVALID;
+		MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.disp = 0;
+	} else {
+		// done, create the next operand slot
+		MI->flat_insn->detail->sparc.op_count++;
+	}
+}
+
+void Sparc_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci)
+{
+	if (((cs_struct *)ud)->detail_opt != CS_OPT_ON)
+		return;
+
+	// fix up some instructions
+	if (insn->id == SPARC_INS_CASX) {
+		// first op is actually a memop, not regop
+		insn->detail->sparc.operands[0].type = SPARC_OP_MEM;
+		insn->detail->sparc.operands[0].mem.base = (uint8_t)insn->detail->sparc.operands[0].reg;
+		insn->detail->sparc.operands[0].mem.disp = 0;
+	}
+}
+
+static void printRegName(SStream *OS, unsigned RegNo)
+{
+	SStream_concat0(OS, "%");
+	SStream_concat0(OS, getRegisterName(RegNo));
+}
+
+#define GET_INSTRINFO_ENUM
+#include "SparcGenInstrInfo.inc"
+
+#define GET_REGINFO_ENUM
+#include "SparcGenRegisterInfo.inc"
+
+static bool printSparcAliasInstr(MCInst *MI, SStream *O)
+{
+	switch (MCInst_getOpcode(MI)) {
+		default: return false;
+		case SP_JMPLrr:
+		case SP_JMPLri:
+				 if (MCInst_getNumOperands(MI) != 3)
+					 return false;
+				 if (!MCOperand_isReg(MCInst_getOperand(MI, 0)))
+					 return false;
+
+				 switch (MCOperand_getReg(MCInst_getOperand(MI, 0))) {
+					 default: return false;
+					 case SP_G0: // jmp $addr | ret | retl
+							  if (MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+									MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
+								  switch(MCOperand_getReg(MCInst_getOperand(MI, 1))) {
+									  default: break;
+									  case SP_I7: SStream_concat0(O, "ret"); MCInst_setOpcodePub(MI, SPARC_INS_RET); return true;
+									  case SP_O7: SStream_concat0(O, "retl"); MCInst_setOpcodePub(MI, SPARC_INS_RETL); return true;
+								  }
+							  }
+
+							  SStream_concat0(O, "jmp\t");
+							  MCInst_setOpcodePub(MI, SPARC_INS_JMP);
+							  printMemOperand(MI, 1, O, NULL);
+							  return true;
+					 case SP_O7: // call $addr
+							  SStream_concat0(O, "call ");
+							  MCInst_setOpcodePub(MI, SPARC_INS_CALL);
+							  printMemOperand(MI, 1, O, NULL);
+							  return true;
+				 }
+		case SP_V9FCMPS:
+		case SP_V9FCMPD:
+		case SP_V9FCMPQ:
+		case SP_V9FCMPES:
+		case SP_V9FCMPED:
+		case SP_V9FCMPEQ:
+				 if (MI->csh->mode & CS_MODE_V9 || (MCInst_getNumOperands(MI) != 3) ||
+						 (!MCOperand_isReg(MCInst_getOperand(MI, 0))) ||
+						 (MCOperand_getReg(MCInst_getOperand(MI, 0)) != SP_FCC0))
+						 return false;
+				 // if V8, skip printing %fcc0.
+				 switch(MCInst_getOpcode(MI)) {
+					 default:
+					 case SP_V9FCMPS:  SStream_concat0(O, "fcmps\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPS); break;
+					 case SP_V9FCMPD:  SStream_concat0(O, "fcmpd\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPD); break;
+					 case SP_V9FCMPQ:  SStream_concat0(O, "fcmpq\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPQ); break;
+					 case SP_V9FCMPES: SStream_concat0(O, "fcmpes\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPES); break;
+					 case SP_V9FCMPED: SStream_concat0(O, "fcmped\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPED); break;
+					 case SP_V9FCMPEQ: SStream_concat0(O, "fcmpeq\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPEQ); break;
+				 }
+				 printOperand(MI, 1, O);
+				 SStream_concat0(O, ", ");
+				 printOperand(MI, 2, O);
+				 return true;
+	}
+}
+
+static void printOperand(MCInst *MI, int opNum, SStream *O)
+{
+	int64_t Imm;
+	unsigned reg;
+	MCOperand *MO = MCInst_getOperand(MI, opNum);
+
+	if (MCOperand_isReg(MO)) {
+		reg = MCOperand_getReg(MO);
+		printRegName(O, reg);
+		reg = Sparc_map_register(reg);
+
+		if (MI->csh->detail_opt) {
+			if (MI->csh->doing_mem) {
+				if (MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.base)
+					MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.index = (uint8_t)reg;
+				else
+					MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.base = (uint8_t)reg;
+			} else {
+				MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_REG;
+				MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].reg = reg;
+				MI->flat_insn->detail->sparc.op_count++;
+			}
+		}
+
+		return;
+	}
+
+	if (MCOperand_isImm(MO)) {
+		Imm = (int)MCOperand_getImm(MO);
+
+		// Conditional branches displacements needs to be signextended to be
+		// able to jump backwards.
+		//
+		// Displacements are measured as the number of instructions forward or
+		// backward, so they need to be multiplied by 4
+		switch (MI->Opcode) {
+			case SP_CALL:
+				// Imm = SignExtend32(Imm, 30);
+				Imm += MI->address;
+				break;
+
+			// Branch on integer condition with prediction (BPcc)
+			// Branch on floating point condition with prediction (FBPfcc)
+			case SP_BPICC:
+			case SP_BPICCA:
+			case SP_BPICCANT:
+			case SP_BPICCNT:
+			case SP_BPXCC:
+			case SP_BPXCCA:
+			case SP_BPXCCANT:
+			case SP_BPXCCNT:
+			case SP_BPFCC:
+			case SP_BPFCCA:
+			case SP_BPFCCANT:
+			case SP_BPFCCNT:
+				Imm = SignExtend32(Imm, 19);
+				Imm = MI->address + Imm * 4;
+				break;
+
+			// Branch on integer condition (Bicc)
+			// Branch on floating point condition (FBfcc)
+			case SP_BA:
+			case SP_BCOND:
+			case SP_BCONDA:
+			case SP_FBCOND:
+			case SP_FBCONDA:
+				Imm = SignExtend32(Imm, 22);
+				Imm = MI->address + Imm * 4;
+				break;
+
+			// Branch on integer register with prediction (BPr)
+			case SP_BPGEZapn:
+			case SP_BPGEZapt:
+			case SP_BPGEZnapn:
+			case SP_BPGEZnapt:
+			case SP_BPGZapn:
+			case SP_BPGZapt:
+			case SP_BPGZnapn:
+			case SP_BPGZnapt:
+			case SP_BPLEZapn:
+			case SP_BPLEZapt:
+			case SP_BPLEZnapn:
+			case SP_BPLEZnapt:
+			case SP_BPLZapn:
+			case SP_BPLZapt:
+			case SP_BPLZnapn:
+			case SP_BPLZnapt:
+			case SP_BPNZapn:
+			case SP_BPNZapt:
+			case SP_BPNZnapn:
+			case SP_BPNZnapt:
+			case SP_BPZapn:
+			case SP_BPZapt:
+			case SP_BPZnapn:
+			case SP_BPZnapt:
+				Imm = SignExtend32(Imm, 16);
+				Imm = MI->address + Imm * 4;
+				break;
+		}
+		
+		printInt64(O, Imm);
+
+		if (MI->csh->detail_opt) {
+			if (MI->csh->doing_mem) {
+				MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.disp = Imm;
+			} else {
+				MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_IMM;
+				MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].imm = Imm;
+				MI->flat_insn->detail->sparc.op_count++;
+			}
+		}
+	}
+
+	return;
+}
+
+static void printMemOperand(MCInst *MI, int opNum, SStream *O, const char *Modifier)
+{
+	MCOperand *MO;
+
+	set_mem_access(MI, true);
+	printOperand(MI, opNum, O);
+
+	// If this is an ADD operand, emit it like normal operands.
+	if (Modifier && !strcmp(Modifier, "arith")) {
+		SStream_concat0(O, ", ");
+		printOperand(MI, opNum + 1, O);
+		set_mem_access(MI, false);
+		return;
+	}
+
+	MO = MCInst_getOperand(MI, opNum + 1);
+
+	if (MCOperand_isReg(MO) && (MCOperand_getReg(MO) == SP_G0)) {
+		set_mem_access(MI, false);
+		return;   // don't print "+%g0"
+	}
+
+	if (MCOperand_isImm(MO) && (MCOperand_getImm(MO) == 0)) {
+		set_mem_access(MI, false);
+		return;   // don't print "+0"
+	}
+
+	SStream_concat0(O, "+");	// qq
+
+	printOperand(MI, opNum + 1, O);
+	set_mem_access(MI, false);
+}
+
+static void printCCOperand(MCInst *MI, int opNum, SStream *O)
+{
+	int CC = (int)MCOperand_getImm(MCInst_getOperand(MI, opNum)) + 256;
+
+	switch (MCInst_getOpcode(MI)) {
+		default: break;
+		case SP_FBCOND:
+		case SP_FBCONDA:
+		case SP_BPFCC:
+		case SP_BPFCCA:
+		case SP_BPFCCNT:
+		case SP_BPFCCANT:
+		case SP_MOVFCCrr:  case SP_V9MOVFCCrr:
+		case SP_MOVFCCri:  case SP_V9MOVFCCri:
+		case SP_FMOVS_FCC: case SP_V9FMOVS_FCC:
+		case SP_FMOVD_FCC: case SP_V9FMOVD_FCC:
+		case SP_FMOVQ_FCC: case SP_V9FMOVQ_FCC:
+				 // Make sure CC is a fp conditional flag.
+				 CC = (CC < 16+256) ? (CC + 16) : CC;
+				 break;
+	}
+
+	SStream_concat0(O, SPARCCondCodeToString((sparc_cc)CC));
+
+	if (MI->csh->detail_opt)
+		MI->flat_insn->detail->sparc.cc = (sparc_cc)CC;
+}
+
+
+static bool printGetPCX(MCInst *MI, unsigned opNum, SStream *O)
+{
+	return true;
+}
+
+
+#define PRINT_ALIAS_INSTR
+#include "SparcGenAsmWriter.inc"
+
+void Sparc_printInst(MCInst *MI, SStream *O, void *Info)
+{
+	char *mnem, *p;
+	char instr[64];	// Sparc has no instruction this long
+
+	mnem = printAliasInstr(MI, O, Info);
+	if (mnem) {
+		// fixup instruction id due to the change in alias instruction
+		unsigned cpy_len = sizeof(instr) - 1 < strlen(mnem) ? sizeof(instr) - 1 : strlen(mnem);
+		memcpy(instr, mnem, cpy_len);
+		instr[cpy_len] = '\0';
+		// does this contains hint with a coma?
+		p = strchr(instr, ',');
+		if (p)
+			*p = '\0';	// now instr only has instruction mnemonic
+		MCInst_setOpcodePub(MI, Sparc_map_insn(instr));
+		switch(MCInst_getOpcode(MI)) {
+			case SP_BCOND:
+			case SP_BCONDA:
+			case SP_BPICCANT:
+			case SP_BPICCNT:
+			case SP_BPXCCANT:
+			case SP_BPXCCNT:
+			case SP_TXCCri:
+			case SP_TXCCrr:
+				if (MI->csh->detail_opt) {
+					// skip 'b', 't'
+					MI->flat_insn->detail->sparc.cc = Sparc_map_ICC(instr + 1);
+					MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem);
+				}
+				break;
+			case SP_BPFCCANT:
+			case SP_BPFCCNT:
+				if (MI->csh->detail_opt) {
+					// skip 'fb'
+					MI->flat_insn->detail->sparc.cc = Sparc_map_FCC(instr + 2);
+					MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem);
+				}
+				break;
+			case SP_FMOVD_ICC:
+			case SP_FMOVD_XCC:
+			case SP_FMOVQ_ICC:
+			case SP_FMOVQ_XCC:
+			case SP_FMOVS_ICC:
+			case SP_FMOVS_XCC:
+				if (MI->csh->detail_opt) {
+					// skip 'fmovd', 'fmovq', 'fmovs'
+					MI->flat_insn->detail->sparc.cc = Sparc_map_ICC(instr + 5);
+					MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem);
+				}
+				break;
+			case SP_MOVICCri:
+			case SP_MOVICCrr:
+			case SP_MOVXCCri:
+			case SP_MOVXCCrr:
+				if (MI->csh->detail_opt) {
+					// skip 'mov'
+					MI->flat_insn->detail->sparc.cc = Sparc_map_ICC(instr + 3);
+					MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem);
+				}
+				break;
+			case SP_V9FMOVD_FCC:
+			case SP_V9FMOVQ_FCC:
+			case SP_V9FMOVS_FCC:
+				if (MI->csh->detail_opt) {
+					// skip 'fmovd', 'fmovq', 'fmovs'
+					MI->flat_insn->detail->sparc.cc = Sparc_map_FCC(instr + 5);
+					MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem);
+				}
+				break;
+			case SP_V9MOVFCCri:
+			case SP_V9MOVFCCrr:
+				if (MI->csh->detail_opt) {
+					// skip 'mov'
+					MI->flat_insn->detail->sparc.cc = Sparc_map_FCC(instr + 3);
+					MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem);
+				}
+				break;
+			default:
+				break;
+		}
+		cs_mem_free(mnem);
+	} else {
+		if (!printSparcAliasInstr(MI, O))
+			printInstruction(MI, O, NULL);
+	}
+}
+
+void Sparc_addReg(MCInst *MI, int reg)
+{
+	if (MI->csh->detail_opt) {
+		MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_REG;
+		MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].reg = reg;
+		MI->flat_insn->detail->sparc.op_count++;
+	}
+}
+
+#endif

thirdparty/capstone/arch/Sparc/SparcInstPrinter.h

@@ -0,0 +1,17 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifndef CS_SPARCINSTPRINTER_H
+#define CS_SPARCINSTPRINTER_H
+
+#include "../../MCInst.h"
+#include "../../MCRegisterInfo.h"
+#include "../../SStream.h"
+
+void Sparc_printInst(MCInst *MI, SStream *O, void *Info);
+
+void Sparc_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci);
+
+void Sparc_addReg(MCInst *MI, int reg);
+
+#endif

thirdparty/capstone/arch/Sparc/SparcMapping.c

@@ -0,0 +1,666 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifdef CAPSTONE_HAS_SPARC
+
+#include <stdio.h>	// debug
+#include <string.h>
+
+#include "../../Mapping.h"
+#include "../../utils.h"
+
+#include "SparcMapping.h"
+
+#define GET_INSTRINFO_ENUM
+#include "SparcGenInstrInfo.inc"
+
+#ifndef CAPSTONE_DIET
+static const name_map reg_name_maps[] = {
+	{ SPARC_REG_INVALID, NULL },
+
+	{ SPARC_REG_F0, "f0"},
+	{ SPARC_REG_F1, "f1"},
+	{ SPARC_REG_F2, "f2"},
+	{ SPARC_REG_F3, "f3"},
+	{ SPARC_REG_F4, "f4"},
+	{ SPARC_REG_F5, "f5"},
+	{ SPARC_REG_F6, "f6"},
+	{ SPARC_REG_F7, "f7"},
+	{ SPARC_REG_F8, "f8"},
+	{ SPARC_REG_F9, "f9"},
+	{ SPARC_REG_F10, "f10"},
+	{ SPARC_REG_F11, "f11"},
+	{ SPARC_REG_F12, "f12"},
+	{ SPARC_REG_F13, "f13"},
+	{ SPARC_REG_F14, "f14"},
+	{ SPARC_REG_F15, "f15"},
+	{ SPARC_REG_F16, "f16"},
+	{ SPARC_REG_F17, "f17"},
+	{ SPARC_REG_F18, "f18"},
+	{ SPARC_REG_F19, "f19"},
+	{ SPARC_REG_F20, "f20"},
+	{ SPARC_REG_F21, "f21"},
+	{ SPARC_REG_F22, "f22"},
+	{ SPARC_REG_F23, "f23"},
+	{ SPARC_REG_F24, "f24"},
+	{ SPARC_REG_F25, "f25"},
+	{ SPARC_REG_F26, "f26"},
+	{ SPARC_REG_F27, "f27"},
+	{ SPARC_REG_F28, "f28"},
+	{ SPARC_REG_F29, "f29"},
+	{ SPARC_REG_F30, "f30"},
+	{ SPARC_REG_F31, "f31"},
+	{ SPARC_REG_F32, "f32"},
+	{ SPARC_REG_F34, "f34"},
+	{ SPARC_REG_F36, "f36"},
+	{ SPARC_REG_F38, "f38"},
+	{ SPARC_REG_F40, "f40"},
+	{ SPARC_REG_F42, "f42"},
+	{ SPARC_REG_F44, "f44"},
+	{ SPARC_REG_F46, "f46"},
+	{ SPARC_REG_F48, "f48"},
+	{ SPARC_REG_F50, "f50"},
+	{ SPARC_REG_F52, "f52"},
+	{ SPARC_REG_F54, "f54"},
+	{ SPARC_REG_F56, "f56"},
+	{ SPARC_REG_F58, "f58"},
+	{ SPARC_REG_F60, "f60"},
+	{ SPARC_REG_F62, "f62"},
+	{ SPARC_REG_FCC0, "fcc0"},
+	{ SPARC_REG_FCC1, "fcc1"},
+	{ SPARC_REG_FCC2, "fcc2"},
+	{ SPARC_REG_FCC3, "fcc3"},
+	{ SPARC_REG_FP, "fp"},
+	{ SPARC_REG_G0, "g0"},
+	{ SPARC_REG_G1, "g1"},
+	{ SPARC_REG_G2, "g2"},
+	{ SPARC_REG_G3, "g3"},
+	{ SPARC_REG_G4, "g4"},
+	{ SPARC_REG_G5, "g5"},
+	{ SPARC_REG_G6, "g6"},
+	{ SPARC_REG_G7, "g7"},
+	{ SPARC_REG_I0, "i0"},
+	{ SPARC_REG_I1, "i1"},
+	{ SPARC_REG_I2, "i2"},
+	{ SPARC_REG_I3, "i3"},
+	{ SPARC_REG_I4, "i4"},
+	{ SPARC_REG_I5, "i5"},
+	{ SPARC_REG_I7, "i7"},
+	{ SPARC_REG_ICC, "icc"},
+	{ SPARC_REG_L0, "l0"},
+	{ SPARC_REG_L1, "l1"},
+	{ SPARC_REG_L2, "l2"},
+	{ SPARC_REG_L3, "l3"},
+	{ SPARC_REG_L4, "l4"},
+	{ SPARC_REG_L5, "l5"},
+	{ SPARC_REG_L6, "l6"},
+	{ SPARC_REG_L7, "l7"},
+	{ SPARC_REG_O0, "o0"},
+	{ SPARC_REG_O1, "o1"},
+	{ SPARC_REG_O2, "o2"},
+	{ SPARC_REG_O3, "o3"},
+	{ SPARC_REG_O4, "o4"},
+	{ SPARC_REG_O5, "o5"},
+	{ SPARC_REG_O7, "o7"},
+	{ SPARC_REG_SP, "sp"},
+	{ SPARC_REG_Y, "y"},
+
+	// special registers
+	{ SPARC_REG_XCC, "xcc"},
+};
+#endif
+
+const char *Sparc_reg_name(csh handle, unsigned int reg)
+{
+#ifndef CAPSTONE_DIET
+	if (reg >= ARR_SIZE(reg_name_maps))
+		return NULL;
+
+	return reg_name_maps[reg].name;
+#else
+	return NULL;
+#endif
+}
+
+static const insn_map insns[] = {
+	// dummy item
+	{
+		0, 0,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+	},
+
+#include "SparcMappingInsn.inc"
+};
+
+static struct hint_map {
+	unsigned int id;
+	uint8_t hints;
+} const insn_hints[] = {
+	{ SP_BPGEZapn, SPARC_HINT_A | SPARC_HINT_PN },
+	{ SP_BPGEZapt, SPARC_HINT_A | SPARC_HINT_PT },
+	{ SP_BPGEZnapn, SPARC_HINT_PN },
+	{ SP_BPGZapn, SPARC_HINT_A | SPARC_HINT_PN },
+	{ SP_BPGZapt, SPARC_HINT_A | SPARC_HINT_PT },
+	{ SP_BPGZnapn, SPARC_HINT_PN },
+	{ SP_BPLEZapn, SPARC_HINT_A | SPARC_HINT_PN },
+	{ SP_BPLEZapt, SPARC_HINT_A | SPARC_HINT_PT },
+	{ SP_BPLEZnapn, SPARC_HINT_PN },
+	{ SP_BPLZapn, SPARC_HINT_A | SPARC_HINT_PN },
+	{ SP_BPLZapt, SPARC_HINT_A | SPARC_HINT_PT },
+	{ SP_BPLZnapn, SPARC_HINT_PN },
+	{ SP_BPNZapn, SPARC_HINT_A | SPARC_HINT_PN },
+	{ SP_BPNZapt, SPARC_HINT_A | SPARC_HINT_PT },
+	{ SP_BPNZnapn, SPARC_HINT_PN },
+	{ SP_BPZapn, SPARC_HINT_A | SPARC_HINT_PN },
+	{ SP_BPZapt, SPARC_HINT_A | SPARC_HINT_PT },
+	{ SP_BPZnapn, SPARC_HINT_PN },
+};
+
+// given internal insn id, return public instruction info
+void Sparc_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
+{
+	unsigned short i;
+
+	i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache);
+	if (i != 0) {
+		insn->id = insns[i].mapid;
+
+		if (h->detail_opt) {
+#ifndef CAPSTONE_DIET
+			memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use));
+			insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use);
+
+			memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod));
+			insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod);
+
+			memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups));
+			insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups);
+
+			if (insns[i].branch || insns[i].indirect_branch) {
+				// this insn also belongs to JUMP group. add JUMP group
+				insn->detail->groups[insn->detail->groups_count] = SPARC_GRP_JUMP;
+				insn->detail->groups_count++;
+			}
+#endif
+			// hint code
+			for (i = 0; i < ARR_SIZE(insn_hints); i++) {
+				if (id == insn_hints[i].id) {
+					insn->detail->sparc.hint = insn_hints[i].hints;
+					break;
+				}
+			}
+		}
+	}
+}
+
+static const name_map insn_name_maps[] = {
+	{ SPARC_INS_INVALID, NULL },
+
+	{ SPARC_INS_ADDCC, "addcc" },
+	{ SPARC_INS_ADDX, "addx" },
+	{ SPARC_INS_ADDXCC, "addxcc" },
+	{ SPARC_INS_ADDXC, "addxc" },
+	{ SPARC_INS_ADDXCCC, "addxccc" },
+	{ SPARC_INS_ADD, "add" },
+	{ SPARC_INS_ALIGNADDR, "alignaddr" },
+	{ SPARC_INS_ALIGNADDRL, "alignaddrl" },
+	{ SPARC_INS_ANDCC, "andcc" },
+	{ SPARC_INS_ANDNCC, "andncc" },
+	{ SPARC_INS_ANDN, "andn" },
+	{ SPARC_INS_AND, "and" },
+	{ SPARC_INS_ARRAY16, "array16" },
+	{ SPARC_INS_ARRAY32, "array32" },
+	{ SPARC_INS_ARRAY8, "array8" },
+	{ SPARC_INS_B, "b" },
+	{ SPARC_INS_JMP, "jmp" },
+	{ SPARC_INS_BMASK, "bmask" },
+	{ SPARC_INS_FB, "fb" },
+	{ SPARC_INS_BRGEZ, "brgez" },
+	{ SPARC_INS_BRGZ, "brgz" },
+	{ SPARC_INS_BRLEZ, "brlez" },
+	{ SPARC_INS_BRLZ, "brlz" },
+	{ SPARC_INS_BRNZ, "brnz" },
+	{ SPARC_INS_BRZ, "brz" },
+	{ SPARC_INS_BSHUFFLE, "bshuffle" },
+	{ SPARC_INS_CALL, "call" },
+	{ SPARC_INS_CASX, "casx" },
+	{ SPARC_INS_CAS, "cas" },
+	{ SPARC_INS_CMASK16, "cmask16" },
+	{ SPARC_INS_CMASK32, "cmask32" },
+	{ SPARC_INS_CMASK8, "cmask8" },
+	{ SPARC_INS_CMP, "cmp" },
+	{ SPARC_INS_EDGE16, "edge16" },
+	{ SPARC_INS_EDGE16L, "edge16l" },
+	{ SPARC_INS_EDGE16LN, "edge16ln" },
+	{ SPARC_INS_EDGE16N, "edge16n" },
+	{ SPARC_INS_EDGE32, "edge32" },
+	{ SPARC_INS_EDGE32L, "edge32l" },
+	{ SPARC_INS_EDGE32LN, "edge32ln" },
+	{ SPARC_INS_EDGE32N, "edge32n" },
+	{ SPARC_INS_EDGE8, "edge8" },
+	{ SPARC_INS_EDGE8L, "edge8l" },
+	{ SPARC_INS_EDGE8LN, "edge8ln" },
+	{ SPARC_INS_EDGE8N, "edge8n" },
+	{ SPARC_INS_FABSD, "fabsd" },
+	{ SPARC_INS_FABSQ, "fabsq" },
+	{ SPARC_INS_FABSS, "fabss" },
+	{ SPARC_INS_FADDD, "faddd" },
+	{ SPARC_INS_FADDQ, "faddq" },
+	{ SPARC_INS_FADDS, "fadds" },
+	{ SPARC_INS_FALIGNDATA, "faligndata" },
+	{ SPARC_INS_FAND, "fand" },
+	{ SPARC_INS_FANDNOT1, "fandnot1" },
+	{ SPARC_INS_FANDNOT1S, "fandnot1s" },
+	{ SPARC_INS_FANDNOT2, "fandnot2" },
+	{ SPARC_INS_FANDNOT2S, "fandnot2s" },
+	{ SPARC_INS_FANDS, "fands" },
+	{ SPARC_INS_FCHKSM16, "fchksm16" },
+	{ SPARC_INS_FCMPD, "fcmpd" },
+	{ SPARC_INS_FCMPEQ16, "fcmpeq16" },
+	{ SPARC_INS_FCMPEQ32, "fcmpeq32" },
+	{ SPARC_INS_FCMPGT16, "fcmpgt16" },
+	{ SPARC_INS_FCMPGT32, "fcmpgt32" },
+	{ SPARC_INS_FCMPLE16, "fcmple16" },
+	{ SPARC_INS_FCMPLE32, "fcmple32" },
+	{ SPARC_INS_FCMPNE16, "fcmpne16" },
+	{ SPARC_INS_FCMPNE32, "fcmpne32" },
+	{ SPARC_INS_FCMPQ, "fcmpq" },
+	{ SPARC_INS_FCMPS, "fcmps" },
+	{ SPARC_INS_FDIVD, "fdivd" },
+	{ SPARC_INS_FDIVQ, "fdivq" },
+	{ SPARC_INS_FDIVS, "fdivs" },
+	{ SPARC_INS_FDMULQ, "fdmulq" },
+	{ SPARC_INS_FDTOI, "fdtoi" },
+	{ SPARC_INS_FDTOQ, "fdtoq" },
+	{ SPARC_INS_FDTOS, "fdtos" },
+	{ SPARC_INS_FDTOX, "fdtox" },
+	{ SPARC_INS_FEXPAND, "fexpand" },
+	{ SPARC_INS_FHADDD, "fhaddd" },
+	{ SPARC_INS_FHADDS, "fhadds" },
+	{ SPARC_INS_FHSUBD, "fhsubd" },
+	{ SPARC_INS_FHSUBS, "fhsubs" },
+	{ SPARC_INS_FITOD, "fitod" },
+	{ SPARC_INS_FITOQ, "fitoq" },
+	{ SPARC_INS_FITOS, "fitos" },
+	{ SPARC_INS_FLCMPD, "flcmpd" },
+	{ SPARC_INS_FLCMPS, "flcmps" },
+	{ SPARC_INS_FLUSHW, "flushw" },
+	{ SPARC_INS_FMEAN16, "fmean16" },
+	{ SPARC_INS_FMOVD, "fmovd" },
+	{ SPARC_INS_FMOVQ, "fmovq" },
+	{ SPARC_INS_FMOVRDGEZ, "fmovrdgez" },
+	{ SPARC_INS_FMOVRQGEZ, "fmovrqgez" },
+	{ SPARC_INS_FMOVRSGEZ, "fmovrsgez" },
+	{ SPARC_INS_FMOVRDGZ, "fmovrdgz" },
+	{ SPARC_INS_FMOVRQGZ, "fmovrqgz" },
+	{ SPARC_INS_FMOVRSGZ, "fmovrsgz" },
+	{ SPARC_INS_FMOVRDLEZ, "fmovrdlez" },
+	{ SPARC_INS_FMOVRQLEZ, "fmovrqlez" },
+	{ SPARC_INS_FMOVRSLEZ, "fmovrslez" },
+	{ SPARC_INS_FMOVRDLZ, "fmovrdlz" },
+	{ SPARC_INS_FMOVRQLZ, "fmovrqlz" },
+	{ SPARC_INS_FMOVRSLZ, "fmovrslz" },
+	{ SPARC_INS_FMOVRDNZ, "fmovrdnz" },
+	{ SPARC_INS_FMOVRQNZ, "fmovrqnz" },
+	{ SPARC_INS_FMOVRSNZ, "fmovrsnz" },
+	{ SPARC_INS_FMOVRDZ, "fmovrdz" },
+	{ SPARC_INS_FMOVRQZ, "fmovrqz" },
+	{ SPARC_INS_FMOVRSZ, "fmovrsz" },
+	{ SPARC_INS_FMOVS, "fmovs" },
+	{ SPARC_INS_FMUL8SUX16, "fmul8sux16" },
+	{ SPARC_INS_FMUL8ULX16, "fmul8ulx16" },
+	{ SPARC_INS_FMUL8X16, "fmul8x16" },
+	{ SPARC_INS_FMUL8X16AL, "fmul8x16al" },
+	{ SPARC_INS_FMUL8X16AU, "fmul8x16au" },
+	{ SPARC_INS_FMULD, "fmuld" },
+	{ SPARC_INS_FMULD8SUX16, "fmuld8sux16" },
+	{ SPARC_INS_FMULD8ULX16, "fmuld8ulx16" },
+	{ SPARC_INS_FMULQ, "fmulq" },
+	{ SPARC_INS_FMULS, "fmuls" },
+	{ SPARC_INS_FNADDD, "fnaddd" },
+	{ SPARC_INS_FNADDS, "fnadds" },
+	{ SPARC_INS_FNAND, "fnand" },
+	{ SPARC_INS_FNANDS, "fnands" },
+	{ SPARC_INS_FNEGD, "fnegd" },
+	{ SPARC_INS_FNEGQ, "fnegq" },
+	{ SPARC_INS_FNEGS, "fnegs" },
+	{ SPARC_INS_FNHADDD, "fnhaddd" },
+	{ SPARC_INS_FNHADDS, "fnhadds" },
+	{ SPARC_INS_FNOR, "fnor" },
+	{ SPARC_INS_FNORS, "fnors" },
+	{ SPARC_INS_FNOT1, "fnot1" },
+	{ SPARC_INS_FNOT1S, "fnot1s" },
+	{ SPARC_INS_FNOT2, "fnot2" },
+	{ SPARC_INS_FNOT2S, "fnot2s" },
+	{ SPARC_INS_FONE, "fone" },
+	{ SPARC_INS_FONES, "fones" },
+	{ SPARC_INS_FOR, "for" },
+	{ SPARC_INS_FORNOT1, "fornot1" },
+	{ SPARC_INS_FORNOT1S, "fornot1s" },
+	{ SPARC_INS_FORNOT2, "fornot2" },
+	{ SPARC_INS_FORNOT2S, "fornot2s" },
+	{ SPARC_INS_FORS, "fors" },
+	{ SPARC_INS_FPACK16, "fpack16" },
+	{ SPARC_INS_FPACK32, "fpack32" },
+	{ SPARC_INS_FPACKFIX, "fpackfix" },
+	{ SPARC_INS_FPADD16, "fpadd16" },
+	{ SPARC_INS_FPADD16S, "fpadd16s" },
+	{ SPARC_INS_FPADD32, "fpadd32" },
+	{ SPARC_INS_FPADD32S, "fpadd32s" },
+	{ SPARC_INS_FPADD64, "fpadd64" },
+	{ SPARC_INS_FPMERGE, "fpmerge" },
+	{ SPARC_INS_FPSUB16, "fpsub16" },
+	{ SPARC_INS_FPSUB16S, "fpsub16s" },
+	{ SPARC_INS_FPSUB32, "fpsub32" },
+	{ SPARC_INS_FPSUB32S, "fpsub32s" },
+	{ SPARC_INS_FQTOD, "fqtod" },
+	{ SPARC_INS_FQTOI, "fqtoi" },
+	{ SPARC_INS_FQTOS, "fqtos" },
+	{ SPARC_INS_FQTOX, "fqtox" },
+	{ SPARC_INS_FSLAS16, "fslas16" },
+	{ SPARC_INS_FSLAS32, "fslas32" },
+	{ SPARC_INS_FSLL16, "fsll16" },
+	{ SPARC_INS_FSLL32, "fsll32" },
+	{ SPARC_INS_FSMULD, "fsmuld" },
+	{ SPARC_INS_FSQRTD, "fsqrtd" },
+	{ SPARC_INS_FSQRTQ, "fsqrtq" },
+	{ SPARC_INS_FSQRTS, "fsqrts" },
+	{ SPARC_INS_FSRA16, "fsra16" },
+	{ SPARC_INS_FSRA32, "fsra32" },
+	{ SPARC_INS_FSRC1, "fsrc1" },
+	{ SPARC_INS_FSRC1S, "fsrc1s" },
+	{ SPARC_INS_FSRC2, "fsrc2" },
+	{ SPARC_INS_FSRC2S, "fsrc2s" },
+	{ SPARC_INS_FSRL16, "fsrl16" },
+	{ SPARC_INS_FSRL32, "fsrl32" },
+	{ SPARC_INS_FSTOD, "fstod" },
+	{ SPARC_INS_FSTOI, "fstoi" },
+	{ SPARC_INS_FSTOQ, "fstoq" },
+	{ SPARC_INS_FSTOX, "fstox" },
+	{ SPARC_INS_FSUBD, "fsubd" },
+	{ SPARC_INS_FSUBQ, "fsubq" },
+	{ SPARC_INS_FSUBS, "fsubs" },
+	{ SPARC_INS_FXNOR, "fxnor" },
+	{ SPARC_INS_FXNORS, "fxnors" },
+	{ SPARC_INS_FXOR, "fxor" },
+	{ SPARC_INS_FXORS, "fxors" },
+	{ SPARC_INS_FXTOD, "fxtod" },
+	{ SPARC_INS_FXTOQ, "fxtoq" },
+	{ SPARC_INS_FXTOS, "fxtos" },
+	{ SPARC_INS_FZERO, "fzero" },
+	{ SPARC_INS_FZEROS, "fzeros" },
+	{ SPARC_INS_JMPL, "jmpl" },
+	{ SPARC_INS_LDD, "ldd" },
+	{ SPARC_INS_LD, "ld" },
+	{ SPARC_INS_LDQ, "ldq" },
+	{ SPARC_INS_LDSB, "ldsb" },
+	{ SPARC_INS_LDSH, "ldsh" },
+	{ SPARC_INS_LDSW, "ldsw" },
+	{ SPARC_INS_LDUB, "ldub" },
+	{ SPARC_INS_LDUH, "lduh" },
+	{ SPARC_INS_LDX, "ldx" },
+	{ SPARC_INS_LZCNT, "lzcnt" },
+	{ SPARC_INS_MEMBAR, "membar" },
+	{ SPARC_INS_MOVDTOX, "movdtox" },
+	{ SPARC_INS_MOV, "mov" },
+	{ SPARC_INS_MOVRGEZ, "movrgez" },
+	{ SPARC_INS_MOVRGZ, "movrgz" },
+	{ SPARC_INS_MOVRLEZ, "movrlez" },
+	{ SPARC_INS_MOVRLZ, "movrlz" },
+	{ SPARC_INS_MOVRNZ, "movrnz" },
+	{ SPARC_INS_MOVRZ, "movrz" },
+	{ SPARC_INS_MOVSTOSW, "movstosw" },
+	{ SPARC_INS_MOVSTOUW, "movstouw" },
+	{ SPARC_INS_MULX, "mulx" },
+	{ SPARC_INS_NOP, "nop" },
+	{ SPARC_INS_ORCC, "orcc" },
+	{ SPARC_INS_ORNCC, "orncc" },
+	{ SPARC_INS_ORN, "orn" },
+	{ SPARC_INS_OR, "or" },
+	{ SPARC_INS_PDIST, "pdist" },
+	{ SPARC_INS_PDISTN, "pdistn" },
+	{ SPARC_INS_POPC, "popc" },
+	{ SPARC_INS_RD, "rd" },
+	{ SPARC_INS_RESTORE, "restore" },
+	{ SPARC_INS_RETT, "rett" },
+	{ SPARC_INS_SAVE, "save" },
+	{ SPARC_INS_SDIVCC, "sdivcc" },
+	{ SPARC_INS_SDIVX, "sdivx" },
+	{ SPARC_INS_SDIV, "sdiv" },
+	{ SPARC_INS_SETHI, "sethi" },
+	{ SPARC_INS_SHUTDOWN, "shutdown" },
+	{ SPARC_INS_SIAM, "siam" },
+	{ SPARC_INS_SLLX, "sllx" },
+	{ SPARC_INS_SLL, "sll" },
+	{ SPARC_INS_SMULCC, "smulcc" },
+	{ SPARC_INS_SMUL, "smul" },
+	{ SPARC_INS_SRAX, "srax" },
+	{ SPARC_INS_SRA, "sra" },
+	{ SPARC_INS_SRLX, "srlx" },
+	{ SPARC_INS_SRL, "srl" },
+	{ SPARC_INS_STBAR, "stbar" },
+	{ SPARC_INS_STB, "stb" },
+	{ SPARC_INS_STD, "std" },
+	{ SPARC_INS_ST, "st" },
+	{ SPARC_INS_STH, "sth" },
+	{ SPARC_INS_STQ, "stq" },
+	{ SPARC_INS_STX, "stx" },
+	{ SPARC_INS_SUBCC, "subcc" },
+	{ SPARC_INS_SUBX, "subx" },
+	{ SPARC_INS_SUBXCC, "subxcc" },
+	{ SPARC_INS_SUB, "sub" },
+	{ SPARC_INS_SWAP, "swap" },
+	{ SPARC_INS_TADDCCTV, "taddcctv" },
+	{ SPARC_INS_TADDCC, "taddcc" },
+	{ SPARC_INS_T, "t" },
+	{ SPARC_INS_TSUBCCTV, "tsubcctv" },
+	{ SPARC_INS_TSUBCC, "tsubcc" },
+	{ SPARC_INS_UDIVCC, "udivcc" },
+	{ SPARC_INS_UDIVX, "udivx" },
+	{ SPARC_INS_UDIV, "udiv" },
+	{ SPARC_INS_UMULCC, "umulcc" },
+	{ SPARC_INS_UMULXHI, "umulxhi" },
+	{ SPARC_INS_UMUL, "umul" },
+	{ SPARC_INS_UNIMP, "unimp" },
+	{ SPARC_INS_FCMPED, "fcmped" },
+	{ SPARC_INS_FCMPEQ, "fcmpeq" },
+	{ SPARC_INS_FCMPES, "fcmpes" },
+	{ SPARC_INS_WR, "wr" },
+	{ SPARC_INS_XMULX, "xmulx" },
+	{ SPARC_INS_XMULXHI, "xmulxhi" },
+	{ SPARC_INS_XNORCC, "xnorcc" },
+	{ SPARC_INS_XNOR, "xnor" },
+	{ SPARC_INS_XORCC, "xorcc" },
+	{ SPARC_INS_XOR, "xor" },
+
+	// alias instructions
+	{ SPARC_INS_RET, "ret" },
+	{ SPARC_INS_RETL, "retl" },
+};
+
+#ifndef CAPSTONE_DIET
+// special alias insn
+static const name_map alias_insn_names[] = {
+	{ 0, NULL }
+};
+#endif
+
+const char *Sparc_insn_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	unsigned int i;
+
+	if (id >= SPARC_INS_ENDING)
+		return NULL;
+
+	// handle special alias first
+	for (i = 0; i < ARR_SIZE(alias_insn_names); i++) {
+		if (alias_insn_names[i].id == id)
+			return alias_insn_names[i].name;
+	}
+
+	return insn_name_maps[id].name;
+#else
+	return NULL;
+#endif
+}
+
+#ifndef CAPSTONE_DIET
+static const name_map group_name_maps[] = {
+	// generic groups
+	{ SPARC_GRP_INVALID, NULL },
+	{ SPARC_GRP_JUMP, "jump" },
+
+	// architecture-specific groups
+	{ SPARC_GRP_HARDQUAD, "hardquad" },
+	{ SPARC_GRP_V9, "v9" },
+	{ SPARC_GRP_VIS, "vis" },
+	{ SPARC_GRP_VIS2, "vis2" },
+	{ SPARC_GRP_VIS3,  "vis3" },
+	{ SPARC_GRP_32BIT, "32bit" },
+	{ SPARC_GRP_64BIT, "64bit" },
+};
+#endif
+
+const char *Sparc_group_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
+#else
+	return NULL;
+#endif
+}
+
+// map internal raw register to 'public' register
+sparc_reg Sparc_map_register(unsigned int r)
+{
+	static const unsigned int map[] = { 0,
+		SPARC_REG_ICC, SPARC_REG_Y, SPARC_REG_F0, SPARC_REG_F2, SPARC_REG_F4,
+		SPARC_REG_F6, SPARC_REG_F8, SPARC_REG_F10, SPARC_REG_F12, SPARC_REG_F14,
+		SPARC_REG_F16, SPARC_REG_F18, SPARC_REG_F20, SPARC_REG_F22, SPARC_REG_F24,
+		SPARC_REG_F26, SPARC_REG_F28, SPARC_REG_F30, SPARC_REG_F32, SPARC_REG_F34,
+		SPARC_REG_F36, SPARC_REG_F38, SPARC_REG_F40, SPARC_REG_F42, SPARC_REG_F44,
+		SPARC_REG_F46, SPARC_REG_F48, SPARC_REG_F50, SPARC_REG_F52, SPARC_REG_F54,
+		SPARC_REG_F56, SPARC_REG_F58, SPARC_REG_F60, SPARC_REG_F62, SPARC_REG_F0,
+		SPARC_REG_F1, SPARC_REG_F2, SPARC_REG_F3, SPARC_REG_F4, SPARC_REG_F5,
+		SPARC_REG_F6, SPARC_REG_F7, SPARC_REG_F8, SPARC_REG_F9, SPARC_REG_F10,
+		SPARC_REG_F11, SPARC_REG_F12, SPARC_REG_F13, SPARC_REG_F14, SPARC_REG_F15,
+		SPARC_REG_F16, SPARC_REG_F17, SPARC_REG_F18, SPARC_REG_F19, SPARC_REG_F20,
+		SPARC_REG_F21, SPARC_REG_F22, SPARC_REG_F23, SPARC_REG_F24, SPARC_REG_F25,
+		SPARC_REG_F26, SPARC_REG_F27, SPARC_REG_F28, SPARC_REG_F29, SPARC_REG_F30,
+		SPARC_REG_F31, SPARC_REG_FCC0, SPARC_REG_FCC1, SPARC_REG_FCC2, SPARC_REG_FCC3,
+		SPARC_REG_G0, SPARC_REG_G1, SPARC_REG_G2, SPARC_REG_G3, SPARC_REG_G4,
+		SPARC_REG_G5, SPARC_REG_G6, SPARC_REG_G7, SPARC_REG_I0, SPARC_REG_I1,
+		SPARC_REG_I2, SPARC_REG_I3, SPARC_REG_I4, SPARC_REG_I5, SPARC_REG_FP,
+		SPARC_REG_I7, SPARC_REG_L0, SPARC_REG_L1, SPARC_REG_L2, SPARC_REG_L3,
+		SPARC_REG_L4, SPARC_REG_L5, SPARC_REG_L6, SPARC_REG_L7, SPARC_REG_O0,
+		SPARC_REG_O1, SPARC_REG_O2, SPARC_REG_O3, SPARC_REG_O4, SPARC_REG_O5,
+		SPARC_REG_SP, SPARC_REG_O7, SPARC_REG_F0, SPARC_REG_F4, SPARC_REG_F8,
+		SPARC_REG_F12, SPARC_REG_F16, SPARC_REG_F20, SPARC_REG_F24, SPARC_REG_F28,
+		SPARC_REG_F32, SPARC_REG_F36, SPARC_REG_F40, SPARC_REG_F44, SPARC_REG_F48,
+		SPARC_REG_F52, SPARC_REG_F56, SPARC_REG_F60,
+	};
+
+	if (r < ARR_SIZE(map))
+		return map[r];
+
+	// cannot find this register
+	return 0;
+}
+
+// map instruction name to instruction ID (public)
+sparc_reg Sparc_map_insn(const char *name)
+{
+	unsigned int i;
+
+	// NOTE: skip first NULL name in insn_name_maps
+	i = name2id(&insn_name_maps[1], ARR_SIZE(insn_name_maps) - 1, name);
+
+	return (i != -1)? i : SPARC_REG_INVALID;
+}
+
+// NOTE: put strings in the order of string length since
+// we are going to compare with mnemonic to find out CC
+static const name_map alias_icc_maps[] = {
+	{ SPARC_CC_ICC_LEU, "leu" },
+	{ SPARC_CC_ICC_POS, "pos" },
+	{ SPARC_CC_ICC_NEG, "neg" },
+	{ SPARC_CC_ICC_NE, "ne" },
+	{ SPARC_CC_ICC_LE, "le" },
+	{ SPARC_CC_ICC_GE, "ge" },
+	{ SPARC_CC_ICC_GU, "gu" },
+	{ SPARC_CC_ICC_CC, "cc" },
+	{ SPARC_CC_ICC_CS, "cs" },
+	{ SPARC_CC_ICC_VC, "vc" },
+	{ SPARC_CC_ICC_VS, "vs" },
+	{ SPARC_CC_ICC_A, "a" },
+	{ SPARC_CC_ICC_N, "n" },
+	{ SPARC_CC_ICC_E, "e" },
+	{ SPARC_CC_ICC_G, "g" },
+	{ SPARC_CC_ICC_L, "l" },
+};
+
+static const name_map alias_fcc_maps[] = {
+	{ SPARC_CC_FCC_UGE, "uge" },
+	{ SPARC_CC_FCC_ULE, "ule" },
+	{ SPARC_CC_FCC_UG, "ug" },
+	{ SPARC_CC_FCC_UL, "ul" },
+	{ SPARC_CC_FCC_LG, "lg" },
+	{ SPARC_CC_FCC_NE, "ne" },
+	{ SPARC_CC_FCC_UE, "ue" },
+	{ SPARC_CC_FCC_GE, "ge" },
+	{ SPARC_CC_FCC_LE, "le" },
+	{ SPARC_CC_FCC_A, "a" },
+	{ SPARC_CC_FCC_N, "n" },
+	{ SPARC_CC_FCC_U, "u" },
+	{ SPARC_CC_FCC_G, "g" },
+	{ SPARC_CC_FCC_L, "l" },
+	{ SPARC_CC_FCC_E, "e" },
+	{ SPARC_CC_FCC_O, "o" },
+};
+
+// map CC string to CC id
+sparc_cc Sparc_map_ICC(const char *name)
+{
+	unsigned int i;
+
+	i = name2id(alias_icc_maps, ARR_SIZE(alias_icc_maps), name);
+
+	return (i != -1)? i : SPARC_CC_INVALID;
+}
+
+sparc_cc Sparc_map_FCC(const char *name)
+{
+	unsigned int i;
+
+	i = name2id(alias_fcc_maps, ARR_SIZE(alias_fcc_maps), name);
+
+	return (i != -1)? i : SPARC_CC_INVALID;
+}
+
+static const name_map hint_maps[] = {
+	{ SPARC_HINT_A, ",a" },
+	{ SPARC_HINT_A | SPARC_HINT_PN, ",a,pn" },
+	{ SPARC_HINT_PN, ",pn" },
+};
+
+sparc_hint Sparc_map_hint(const char *name)
+{
+	size_t i, l1, l2;
+
+	l1 = strlen(name);
+	for(i = 0; i < ARR_SIZE(hint_maps); i++) {
+		l2 = strlen(hint_maps[i].name);
+		if (l1 > l2) {
+			// compare the last part of @name with this hint string
+			if (!strcmp(hint_maps[i].name, name + (l1 - l2)))
+				return hint_maps[i].id;
+		}
+	}
+
+	return SPARC_HINT_INVALID;
+}
+
+#endif

thirdparty/capstone/arch/Sparc/SparcMapping.h

@@ -0,0 +1,34 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifndef CS_SPARC_MAP_H
+#define CS_SPARC_MAP_H
+
+#include "capstone/capstone.h"
+
+// return name of register in friendly string
+const char *Sparc_reg_name(csh handle, unsigned int reg);
+
+// given internal insn id, return public instruction info
+void Sparc_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
+
+const char *Sparc_insn_name(csh handle, unsigned int id);
+
+const char *Sparc_group_name(csh handle, unsigned int id);
+
+// map internal raw register to 'public' register
+sparc_reg Sparc_map_register(unsigned int r);
+
+// map instruction name to instruction ID (public)
+// this is for alias instructions only
+sparc_reg Sparc_map_insn(const char *name);
+
+// map CC string to CC id
+sparc_cc Sparc_map_ICC(const char *name);
+
+sparc_cc Sparc_map_FCC(const char *name);
+
+sparc_hint Sparc_map_hint(const char *name);
+
+#endif
+

thirdparty/capstone/arch/Sparc/SparcModule.c

@@ -0,0 +1,45 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifdef CAPSTONE_HAS_SPARC
+
+#include "../../utils.h"
+#include "../../MCRegisterInfo.h"
+#include "SparcDisassembler.h"
+#include "SparcInstPrinter.h"
+#include "SparcMapping.h"
+#include "SparcModule.h"
+
+cs_err Sparc_global_init(cs_struct *ud)
+{
+	MCRegisterInfo *mri;
+	mri = cs_mem_malloc(sizeof(*mri));
+
+	Sparc_init(mri);
+	ud->printer = Sparc_printInst;
+	ud->printer_info = mri;
+	ud->getinsn_info = mri;
+	ud->disasm = Sparc_getInstruction;
+	ud->post_printer = Sparc_post_printer;
+
+	ud->reg_name = Sparc_reg_name;
+	ud->insn_id = Sparc_get_insn_id;
+	ud->insn_name = Sparc_insn_name;
+	ud->group_name = Sparc_group_name;
+
+	return CS_ERR_OK;
+}
+
+cs_err Sparc_option(cs_struct *handle, cs_opt_type type, size_t value)
+{
+	if (type == CS_OPT_SYNTAX)
+		handle->syntax = (int) value;
+
+	if (type == CS_OPT_MODE) {
+		handle->mode = (cs_mode)value;
+	}
+
+	return CS_ERR_OK;
+}
+
+#endif

thirdparty/capstone/arch/Sparc/SparcModule.h

@@ -0,0 +1,12 @@
+/* Capstone Disassembly Engine */
+/* By Travis Finkenauer <tmfinken@gmail.com>, 2018 */
+
+#ifndef CS_SPARC_MODULE_H
+#define CS_SPARC_MODULE_H
+
+#include "../../utils.h"
+
+cs_err Sparc_global_init(cs_struct *ud);
+cs_err Sparc_option(cs_struct *handle, cs_opt_type type, size_t value);
+
+#endif