Initial Commit

2025-07-24 22:13:57 +00:00 · 2024-09-07 18:00:09 +06:00
commit 0f9a53f75a
3352 changed files with 1563708 additions and 0 deletions
--- a/thirdparty/capstone/arch/SystemZ/SystemZDisassembler.c
+++ b/thirdparty/capstone/arch/SystemZ/SystemZDisassembler.c
@@ -0,0 +1,484 @@
+//===------ SystemZDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifdef CAPSTONE_HAS_SYSZ
+
+#include <stdio.h>	// DEBUG
+#include <stdlib.h>
+#include <string.h>
+
+#include "../../cs_priv.h"
+#include "../../utils.h"
+
+#include "SystemZDisassembler.h"
+
+#include "../../MCInst.h"
+#include "../../MCInstrDesc.h"
+#include "../../MCFixedLenDisassembler.h"
+#include "../../MCRegisterInfo.h"
+#include "../../MCDisassembler.h"
+#include "../../MathExtras.h"
+
+#include "SystemZMCTargetDesc.h"
+
+static uint64_t getFeatureBits(int mode)
+{
+	// support everything
+	return (uint64_t)-1;
+}
+
+static DecodeStatus decodeRegisterClass(MCInst *Inst, uint64_t RegNo, const unsigned *Regs)
+{
+	//assert(RegNo < 16 && "Invalid register");
+	RegNo = Regs[RegNo];
+	if (RegNo == 0)
+		return MCDisassembler_Fail;
+
+	MCOperand_CreateReg0(Inst, (unsigned)RegNo);
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeGR32BitRegisterClass(MCInst *Inst, uint64_t RegNo,
+		uint64_t Address, const void *Decoder)
+{
+	return decodeRegisterClass(Inst, RegNo, SystemZMC_GR32Regs);
+}
+
+static DecodeStatus DecodeGRH32BitRegisterClass(MCInst *Inst, uint64_t RegNo,
+		uint64_t Address, const void *Decoder)
+{
+	return decodeRegisterClass(Inst, RegNo, SystemZMC_GRH32Regs);
+}
+
+static DecodeStatus DecodeGR64BitRegisterClass(MCInst *Inst, uint64_t RegNo,
+		uint64_t Address, const void *Decoder)
+{
+	return decodeRegisterClass(Inst, RegNo, SystemZMC_GR64Regs);
+}
+
+static DecodeStatus DecodeGR128BitRegisterClass(MCInst *Inst, uint64_t RegNo,
+		uint64_t Address, const void *Decoder)
+{
+	return decodeRegisterClass(Inst, RegNo, SystemZMC_GR128Regs);
+}
+
+static DecodeStatus DecodeADDR64BitRegisterClass(MCInst *Inst, uint64_t RegNo,
+		uint64_t Address, const void *Decoder)
+{
+	return decodeRegisterClass(Inst, RegNo, SystemZMC_GR64Regs);
+}
+
+static DecodeStatus DecodeFP32BitRegisterClass(MCInst *Inst, uint64_t RegNo,
+		uint64_t Address, const void *Decoder) 
+{
+	return decodeRegisterClass(Inst, RegNo, SystemZMC_FP32Regs);
+}
+
+static DecodeStatus DecodeFP64BitRegisterClass(MCInst *Inst, uint64_t RegNo,
+		uint64_t Address, const void *Decoder)
+{
+	return decodeRegisterClass(Inst, RegNo, SystemZMC_FP64Regs);
+}
+
+static DecodeStatus DecodeFP128BitRegisterClass(MCInst *Inst, uint64_t RegNo,
+		uint64_t Address, const void *Decoder)
+{
+	return decodeRegisterClass(Inst, RegNo, SystemZMC_FP128Regs);
+}
+
+static DecodeStatus DecodeVR32BitRegisterClass(MCInst *Inst, uint64_t RegNo,
+		uint64_t Address, const void *Decoder)
+{
+	return decodeRegisterClass(Inst, RegNo, SystemZMC_VR32Regs);
+}
+
+static DecodeStatus DecodeVR64BitRegisterClass(MCInst *Inst, uint64_t RegNo,
+		uint64_t Address, const void *Decoder)
+{
+	return decodeRegisterClass(Inst, RegNo, SystemZMC_VR64Regs);
+}
+
+static DecodeStatus DecodeVR128BitRegisterClass(MCInst *Inst, uint64_t RegNo,
+		uint64_t Address, const void *Decoder)
+{
+	return decodeRegisterClass(Inst, RegNo, SystemZMC_VR128Regs);
+}
+
+static DecodeStatus DecodeAR32BitRegisterClass(MCInst *Inst, uint64_t RegNo,
+		uint64_t Address, const void *Decoder)
+{
+	return decodeRegisterClass(Inst, RegNo, SystemZMC_AR32Regs);
+}
+
+static DecodeStatus DecodeCR64BitRegisterClass(MCInst *Inst, uint64_t RegNo,
+		uint64_t Address, const void *Decoder)
+{
+	return decodeRegisterClass(Inst, RegNo, SystemZMC_CR64Regs);
+}
+
+static DecodeStatus decodeUImmOperand(MCInst *Inst, uint64_t Imm)
+{
+	//assert(isUInt<N>(Imm) && "Invalid immediate");
+	MCOperand_CreateImm0(Inst, Imm);
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus decodeSImmOperand(MCInst *Inst, uint64_t Imm, unsigned N)
+{
+	//assert(isUInt<N>(Imm) && "Invalid immediate");
+	MCOperand_CreateImm0(Inst, SignExtend64(Imm, N));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus decodeU1ImmOperand(MCInst *Inst, uint64_t Imm,
+		uint64_t Address, const void *Decoder)
+{
+	return decodeUImmOperand(Inst, Imm);
+}
+
+static DecodeStatus decodeU2ImmOperand(MCInst *Inst, uint64_t Imm,
+		uint64_t Address, const void *Decoder)
+{
+	return decodeUImmOperand(Inst, Imm);
+}
+
+static DecodeStatus decodeU3ImmOperand(MCInst *Inst, uint64_t Imm,
+		uint64_t Address, const void *Decoder)
+{
+	return decodeUImmOperand(Inst, Imm);
+}
+
+static DecodeStatus decodeU4ImmOperand(MCInst *Inst, uint64_t Imm,
+		uint64_t Address, const void *Decoder)
+{
+	return decodeUImmOperand(Inst, Imm);
+}
+
+static DecodeStatus decodeU6ImmOperand(MCInst *Inst, uint64_t Imm,
+		uint64_t Address, const void *Decoder)
+{
+	return decodeUImmOperand(Inst, Imm);
+}
+
+static DecodeStatus decodeU8ImmOperand(MCInst *Inst, uint64_t Imm,
+		uint64_t Address, const void *Decoder)
+{
+	return decodeUImmOperand(Inst, Imm);
+}
+
+static DecodeStatus decodeU12ImmOperand(MCInst *Inst, uint64_t Imm,
+		uint64_t Address, const void *Decoder)
+{
+	return decodeUImmOperand(Inst, Imm);
+}
+
+static DecodeStatus decodeU16ImmOperand(MCInst *Inst, uint64_t Imm,
+		uint64_t Address, const void *Decoder)
+{
+	return decodeUImmOperand(Inst, Imm);
+}
+
+static DecodeStatus decodeU32ImmOperand(MCInst *Inst, uint64_t Imm,
+		uint64_t Address, const void *Decoder)
+{
+	return decodeUImmOperand(Inst, Imm);
+}
+
+static DecodeStatus decodeS8ImmOperand(MCInst *Inst, uint64_t Imm,
+		uint64_t Address, const void *Decoder)
+{
+	return decodeSImmOperand(Inst, Imm, 8);
+}
+
+static DecodeStatus decodeS16ImmOperand(MCInst *Inst, uint64_t Imm,
+		uint64_t Address, const void *Decoder) 
+{
+	return decodeSImmOperand(Inst, Imm, 16);
+}
+
+static DecodeStatus decodeS32ImmOperand(MCInst *Inst, uint64_t Imm,
+		uint64_t Address, const void *Decoder)
+{
+	return decodeSImmOperand(Inst, Imm, 32);
+}
+
+static DecodeStatus decodePCDBLOperand(MCInst *Inst, uint64_t Imm,
+		uint64_t Address, unsigned N)
+{
+	//assert(isUInt<N>(Imm) && "Invalid PC-relative offset");
+	MCOperand_CreateImm0(Inst, SignExtend64(Imm, N) * 2 + Address);
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus decodePC12DBLBranchOperand(MCInst *Inst, uint64_t Imm,
+		uint64_t Address,
+		const void *Decoder)
+{
+	return decodePCDBLOperand(Inst, Imm, Address, 12);
+}
+
+static DecodeStatus decodePC16DBLBranchOperand(MCInst *Inst, uint64_t Imm,
+		uint64_t Address,
+		const void *Decoder)
+{
+	return decodePCDBLOperand(Inst, Imm, Address, 16);
+}
+
+static DecodeStatus decodePC24DBLBranchOperand(MCInst *Inst, uint64_t Imm,
+		uint64_t Address,
+		const void *Decoder)
+{
+	return decodePCDBLOperand(Inst, Imm, Address, 24);
+}
+
+static DecodeStatus decodePC32DBLBranchOperand(MCInst *Inst, uint64_t Imm,
+		uint64_t Address,
+		const void *Decoder)
+{
+	return decodePCDBLOperand(Inst, Imm, Address, 32);
+}
+
+static DecodeStatus decodePC32DBLOperand(MCInst *Inst, uint64_t Imm,
+		uint64_t Address,
+		const void *Decoder)
+{
+	return decodePCDBLOperand(Inst, Imm, Address, 32);
+}
+
+static DecodeStatus decodeBDAddr12Operand(MCInst *Inst, uint64_t Field,
+		const unsigned *Regs)
+{
+	uint64_t Base = Field >> 12;
+	uint64_t Disp = Field & 0xfff;
+	//assert(Base < 16 && "Invalid BDAddr12");
+
+	MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]);
+	MCOperand_CreateImm0(Inst, Disp);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus decodeBDAddr20Operand(MCInst *Inst, uint64_t Field,
+		const unsigned *Regs)
+{
+	uint64_t Base = Field >> 20;
+	uint64_t Disp = ((Field << 12) & 0xff000) | ((Field >> 8) & 0xfff);
+	//assert(Base < 16 && "Invalid BDAddr20");
+
+	MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]);
+	MCOperand_CreateImm0(Inst, SignExtend64(Disp, 20));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus decodeBDXAddr12Operand(MCInst *Inst, uint64_t Field,
+		const unsigned *Regs)
+{
+	uint64_t Index = Field >> 16;
+	uint64_t Base = (Field >> 12) & 0xf;
+	uint64_t Disp = Field & 0xfff;
+
+	//assert(Index < 16 && "Invalid BDXAddr12");
+	MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]);
+	MCOperand_CreateImm0(Inst, Disp);
+	MCOperand_CreateReg0(Inst, Index == 0 ? 0 : Regs[Index]);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus decodeBDXAddr20Operand(MCInst *Inst, uint64_t Field,
+		const unsigned *Regs)
+{
+	uint64_t Index = Field >> 24;
+	uint64_t Base = (Field >> 20) & 0xf;
+	uint64_t Disp = ((Field & 0xfff00) >> 8) | ((Field & 0xff) << 12);
+
+	//assert(Index < 16 && "Invalid BDXAddr20");
+	MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]);
+	MCOperand_CreateImm0(Inst, SignExtend64(Disp, 20));
+	MCOperand_CreateReg0(Inst, Index == 0 ? 0 : Regs[Index]);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus decodeBDLAddr12Len8Operand(MCInst *Inst, uint64_t Field,
+		const unsigned *Regs)
+{
+	uint64_t Length = Field >> 16;
+	uint64_t Base = (Field >> 12) & 0xf;
+	uint64_t Disp = Field & 0xfff;
+	//assert(Length < 256 && "Invalid BDLAddr12Len8");
+
+	MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]);
+	MCOperand_CreateImm0(Inst, Disp);
+	MCOperand_CreateImm0(Inst, Length + 1);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus decodeBDRAddr12Operand(MCInst *Inst, uint64_t Field,
+		const unsigned *Regs)
+{
+	uint64_t Length = Field >> 16;
+	uint64_t Base = (Field >> 12) & 0xf;
+	uint64_t Disp = Field & 0xfff;
+	//assert(Length < 16 && "Invalid BDRAddr12");
+
+	MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]);
+	MCOperand_CreateImm0(Inst, Disp);
+	MCOperand_CreateReg0(Inst, Regs[Length]);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus decodeBDVAddr12Operand(MCInst *Inst, uint64_t Field,
+		const unsigned *Regs)
+{
+	uint64_t Index = Field >> 16;
+	uint64_t Base = (Field >> 12) & 0xf;
+	uint64_t Disp = Field & 0xfff;
+	//assert(Index < 32 && "Invalid BDVAddr12");
+
+	MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]);
+	MCOperand_CreateImm0(Inst, Disp);
+	MCOperand_CreateReg0(Inst, SystemZMC_VR128Regs[Index]);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus decodeBDAddr32Disp12Operand(MCInst *Inst, uint64_t Field,
+		uint64_t Address, const void *Decoder)
+{
+	return decodeBDAddr12Operand(Inst, Field, SystemZMC_GR32Regs);
+}
+
+static DecodeStatus decodeBDAddr32Disp20Operand(MCInst *Inst, uint64_t Field,
+		uint64_t Address, const void *Decoder)
+{
+	return decodeBDAddr20Operand(Inst, Field, SystemZMC_GR32Regs);
+}
+
+static DecodeStatus decodeBDAddr64Disp12Operand(MCInst *Inst, uint64_t Field,
+		uint64_t Address, const void *Decoder)
+{
+	return decodeBDAddr12Operand(Inst, Field, SystemZMC_GR64Regs);
+}
+
+static DecodeStatus decodeBDAddr64Disp20Operand(MCInst *Inst, uint64_t Field,
+		uint64_t Address, const void *Decoder)
+{
+	return decodeBDAddr20Operand(Inst, Field, SystemZMC_GR64Regs);
+}
+
+static DecodeStatus decodeBDXAddr64Disp12Operand(MCInst *Inst, uint64_t Field,
+		uint64_t Address, const void *Decoder)
+{
+	return decodeBDXAddr12Operand(Inst, Field, SystemZMC_GR64Regs);
+}
+
+static DecodeStatus decodeBDXAddr64Disp20Operand(MCInst *Inst, uint64_t Field,
+		uint64_t Address, const void *Decoder)
+{
+	return decodeBDXAddr20Operand(Inst, Field, SystemZMC_GR64Regs);
+}
+
+static DecodeStatus decodeBDLAddr64Disp12Len4Operand(MCInst *Inst, uint64_t Field,
+		uint64_t Address, const void *Decoder)
+{
+	return decodeBDLAddr12Len8Operand(Inst, Field, SystemZMC_GR64Regs);
+}
+
+static DecodeStatus decodeBDLAddr64Disp12Len8Operand(MCInst *Inst, uint64_t Field,
+		uint64_t Address, const void *Decoder)
+{
+	return decodeBDLAddr12Len8Operand(Inst, Field, SystemZMC_GR64Regs);
+}
+
+static DecodeStatus decodeBDRAddr64Disp12Operand(MCInst *Inst, uint64_t Field,
+		uint64_t Address, const void *Decoder)
+{
+	return decodeBDRAddr12Operand(Inst, Field, SystemZMC_GR64Regs);
+}
+
+static DecodeStatus decodeBDVAddr64Disp12Operand(MCInst *Inst, uint64_t Field,
+		uint64_t Address, const void *Decoder)
+{
+	return decodeBDVAddr12Operand(Inst, Field, SystemZMC_GR64Regs);
+}
+
+
+#define GET_SUBTARGETINFO_ENUM
+#include "SystemZGenSubtargetInfo.inc"
+#include "SystemZGenDisassemblerTables.inc"
+bool SystemZ_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *MI,
+		uint16_t *size, uint64_t address, void *info)
+{
+	uint64_t Inst;
+	const uint8_t *Table;
+	uint16_t I; 
+
+	// The top 2 bits of the first byte specify the size.
+	if (*code < 0x40) {
+		*size = 2;
+		Table = DecoderTable16;
+	} else if (*code < 0xc0) {
+		*size = 4;
+		Table = DecoderTable32;
+	} else {
+		*size = 6;
+		Table = DecoderTable48;
+	}
+
+	if (code_len < *size)
+		// short of input data
+		return false;
+
+	if (MI->flat_insn->detail) {
+		memset(MI->flat_insn->detail, 0, offsetof(cs_detail, sysz)+sizeof(cs_sysz));
+	}
+
+	// Construct the instruction.
+	Inst = 0;
+	for (I = 0; I < *size; ++I)
+		Inst = (Inst << 8) | code[I];
+
+	return decodeInstruction(Table, MI, Inst, address, info, 0);
+}
+
+#define GET_REGINFO_ENUM
+#define GET_REGINFO_MC_DESC
+#include "SystemZGenRegisterInfo.inc"
+void SystemZ_init(MCRegisterInfo *MRI)
+{
+	/*
+	InitMCRegisterInfo(SystemZRegDesc, 98, RA, PC,
+			SystemZMCRegisterClasses, 12,
+			SystemZRegUnitRoots,
+			49,
+			SystemZRegDiffLists,
+			SystemZRegStrings,
+			SystemZSubRegIdxLists,
+			7,
+			SystemZSubRegIdxRanges,
+			SystemZRegEncodingTable);
+	*/
+
+	MCRegisterInfo_InitMCRegisterInfo(MRI, SystemZRegDesc, 194,
+			0, 0,
+			SystemZMCRegisterClasses, 21,
+			0, 0,
+			SystemZRegDiffLists,
+			0,
+			SystemZSubRegIdxLists, 7,
+			0);
+}
+
+#endif
--- a/thirdparty/capstone/arch/SystemZ/SystemZDisassembler.h
+++ b/thirdparty/capstone/arch/SystemZ/SystemZDisassembler.h
@@ -0,0 +1,17 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifndef CS_SYSZDISASSEMBLER_H
+#define CS_SYSZDISASSEMBLER_H
+
+#include "capstone/capstone.h"
+#include "../../MCRegisterInfo.h"
+#include "../../MCInst.h"
+
+void SystemZ_init(MCRegisterInfo *MRI);
+
+bool SystemZ_getInstruction(csh ud, const uint8_t *code, size_t code_len,
+		MCInst *instr, uint16_t *size, uint64_t address, void *info);
+
+#endif
+
--- a/thirdparty/capstone/arch/SystemZ/SystemZGenAsmWriter.inc
+++ b/thirdparty/capstone/arch/SystemZ/SystemZGenAsmWriter.inc
--- a/thirdparty/capstone/arch/SystemZ/SystemZGenDisassemblerTables.inc
+++ b/thirdparty/capstone/arch/SystemZ/SystemZGenDisassemblerTables.inc
--- a/thirdparty/capstone/arch/SystemZ/SystemZGenInsnNameMaps.inc
+++ b/thirdparty/capstone/arch/SystemZ/SystemZGenInsnNameMaps.inc
--- a/thirdparty/capstone/arch/SystemZ/SystemZGenInstrInfo.inc
+++ b/thirdparty/capstone/arch/SystemZ/SystemZGenInstrInfo.inc
--- a/thirdparty/capstone/arch/SystemZ/SystemZGenRegisterInfo.inc
+++ b/thirdparty/capstone/arch/SystemZ/SystemZGenRegisterInfo.inc
@@ -0,0 +1,741 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|* Target Register Enum Values                                                *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+
+
+#ifdef GET_REGINFO_ENUM
+#undef GET_REGINFO_ENUM
+
+enum {
+  SystemZ_NoRegister,
+  SystemZ_CC = 1,
+  SystemZ_A0 = 2,
+  SystemZ_A1 = 3,
+  SystemZ_A2 = 4,
+  SystemZ_A3 = 5,
+  SystemZ_A4 = 6,
+  SystemZ_A5 = 7,
+  SystemZ_A6 = 8,
+  SystemZ_A7 = 9,
+  SystemZ_A8 = 10,
+  SystemZ_A9 = 11,
+  SystemZ_A10 = 12,
+  SystemZ_A11 = 13,
+  SystemZ_A12 = 14,
+  SystemZ_A13 = 15,
+  SystemZ_A14 = 16,
+  SystemZ_A15 = 17,
+  SystemZ_C0 = 18,
+  SystemZ_C1 = 19,
+  SystemZ_C2 = 20,
+  SystemZ_C3 = 21,
+  SystemZ_C4 = 22,
+  SystemZ_C5 = 23,
+  SystemZ_C6 = 24,
+  SystemZ_C7 = 25,
+  SystemZ_C8 = 26,
+  SystemZ_C9 = 27,
+  SystemZ_C10 = 28,
+  SystemZ_C11 = 29,
+  SystemZ_C12 = 30,
+  SystemZ_C13 = 31,
+  SystemZ_C14 = 32,
+  SystemZ_C15 = 33,
+  SystemZ_V0 = 34,
+  SystemZ_V1 = 35,
+  SystemZ_V2 = 36,
+  SystemZ_V3 = 37,
+  SystemZ_V4 = 38,
+  SystemZ_V5 = 39,
+  SystemZ_V6 = 40,
+  SystemZ_V7 = 41,
+  SystemZ_V8 = 42,
+  SystemZ_V9 = 43,
+  SystemZ_V10 = 44,
+  SystemZ_V11 = 45,
+  SystemZ_V12 = 46,
+  SystemZ_V13 = 47,
+  SystemZ_V14 = 48,
+  SystemZ_V15 = 49,
+  SystemZ_V16 = 50,
+  SystemZ_V17 = 51,
+  SystemZ_V18 = 52,
+  SystemZ_V19 = 53,
+  SystemZ_V20 = 54,
+  SystemZ_V21 = 55,
+  SystemZ_V22 = 56,
+  SystemZ_V23 = 57,
+  SystemZ_V24 = 58,
+  SystemZ_V25 = 59,
+  SystemZ_V26 = 60,
+  SystemZ_V27 = 61,
+  SystemZ_V28 = 62,
+  SystemZ_V29 = 63,
+  SystemZ_V30 = 64,
+  SystemZ_V31 = 65,
+  SystemZ_F0D = 66,
+  SystemZ_F1D = 67,
+  SystemZ_F2D = 68,
+  SystemZ_F3D = 69,
+  SystemZ_F4D = 70,
+  SystemZ_F5D = 71,
+  SystemZ_F6D = 72,
+  SystemZ_F7D = 73,
+  SystemZ_F8D = 74,
+  SystemZ_F9D = 75,
+  SystemZ_F10D = 76,
+  SystemZ_F11D = 77,
+  SystemZ_F12D = 78,
+  SystemZ_F13D = 79,
+  SystemZ_F14D = 80,
+  SystemZ_F15D = 81,
+  SystemZ_F16D = 82,
+  SystemZ_F17D = 83,
+  SystemZ_F18D = 84,
+  SystemZ_F19D = 85,
+  SystemZ_F20D = 86,
+  SystemZ_F21D = 87,
+  SystemZ_F22D = 88,
+  SystemZ_F23D = 89,
+  SystemZ_F24D = 90,
+  SystemZ_F25D = 91,
+  SystemZ_F26D = 92,
+  SystemZ_F27D = 93,
+  SystemZ_F28D = 94,
+  SystemZ_F29D = 95,
+  SystemZ_F30D = 96,
+  SystemZ_F31D = 97,
+  SystemZ_F0Q = 98,
+  SystemZ_F1Q = 99,
+  SystemZ_F4Q = 100,
+  SystemZ_F5Q = 101,
+  SystemZ_F8Q = 102,
+  SystemZ_F9Q = 103,
+  SystemZ_F12Q = 104,
+  SystemZ_F13Q = 105,
+  SystemZ_F0S = 106,
+  SystemZ_F1S = 107,
+  SystemZ_F2S = 108,
+  SystemZ_F3S = 109,
+  SystemZ_F4S = 110,
+  SystemZ_F5S = 111,
+  SystemZ_F6S = 112,
+  SystemZ_F7S = 113,
+  SystemZ_F8S = 114,
+  SystemZ_F9S = 115,
+  SystemZ_F10S = 116,
+  SystemZ_F11S = 117,
+  SystemZ_F12S = 118,
+  SystemZ_F13S = 119,
+  SystemZ_F14S = 120,
+  SystemZ_F15S = 121,
+  SystemZ_F16S = 122,
+  SystemZ_F17S = 123,
+  SystemZ_F18S = 124,
+  SystemZ_F19S = 125,
+  SystemZ_F20S = 126,
+  SystemZ_F21S = 127,
+  SystemZ_F22S = 128,
+  SystemZ_F23S = 129,
+  SystemZ_F24S = 130,
+  SystemZ_F25S = 131,
+  SystemZ_F26S = 132,
+  SystemZ_F27S = 133,
+  SystemZ_F28S = 134,
+  SystemZ_F29S = 135,
+  SystemZ_F30S = 136,
+  SystemZ_F31S = 137,
+  SystemZ_R0D = 138,
+  SystemZ_R1D = 139,
+  SystemZ_R2D = 140,
+  SystemZ_R3D = 141,
+  SystemZ_R4D = 142,
+  SystemZ_R5D = 143,
+  SystemZ_R6D = 144,
+  SystemZ_R7D = 145,
+  SystemZ_R8D = 146,
+  SystemZ_R9D = 147,
+  SystemZ_R10D = 148,
+  SystemZ_R11D = 149,
+  SystemZ_R12D = 150,
+  SystemZ_R13D = 151,
+  SystemZ_R14D = 152,
+  SystemZ_R15D = 153,
+  SystemZ_R0H = 154,
+  SystemZ_R1H = 155,
+  SystemZ_R2H = 156,
+  SystemZ_R3H = 157,
+  SystemZ_R4H = 158,
+  SystemZ_R5H = 159,
+  SystemZ_R6H = 160,
+  SystemZ_R7H = 161,
+  SystemZ_R8H = 162,
+  SystemZ_R9H = 163,
+  SystemZ_R10H = 164,
+  SystemZ_R11H = 165,
+  SystemZ_R12H = 166,
+  SystemZ_R13H = 167,
+  SystemZ_R14H = 168,
+  SystemZ_R15H = 169,
+  SystemZ_R0L = 170,
+  SystemZ_R1L = 171,
+  SystemZ_R2L = 172,
+  SystemZ_R3L = 173,
+  SystemZ_R4L = 174,
+  SystemZ_R5L = 175,
+  SystemZ_R6L = 176,
+  SystemZ_R7L = 177,
+  SystemZ_R8L = 178,
+  SystemZ_R9L = 179,
+  SystemZ_R10L = 180,
+  SystemZ_R11L = 181,
+  SystemZ_R12L = 182,
+  SystemZ_R13L = 183,
+  SystemZ_R14L = 184,
+  SystemZ_R15L = 185,
+  SystemZ_R0Q = 186,
+  SystemZ_R2Q = 187,
+  SystemZ_R4Q = 188,
+  SystemZ_R6Q = 189,
+  SystemZ_R8Q = 190,
+  SystemZ_R10Q = 191,
+  SystemZ_R12Q = 192,
+  SystemZ_R14Q = 193,
+  SystemZ_NUM_TARGET_REGS 	// 194
+};
+
+// Register classes
+enum {
+  SystemZ_GRX32BitRegClassID = 0,
+  SystemZ_VR32BitRegClassID = 1,
+  SystemZ_AR32BitRegClassID = 2,
+  SystemZ_FP32BitRegClassID = 3,
+  SystemZ_GR32BitRegClassID = 4,
+  SystemZ_GRH32BitRegClassID = 5,
+  SystemZ_ADDR32BitRegClassID = 6,
+  SystemZ_CCRRegClassID = 7,
+  SystemZ_AnyRegBitRegClassID = 8,
+  SystemZ_AnyRegBit_with_subreg_r32RegClassID = 9,
+  SystemZ_VR64BitRegClassID = 10,
+  SystemZ_AnyRegBit_with_subreg_r64RegClassID = 11,
+  SystemZ_CR64BitRegClassID = 12,
+  SystemZ_FP64BitRegClassID = 13,
+  SystemZ_GR64BitRegClassID = 14,
+  SystemZ_ADDR64BitRegClassID = 15,
+  SystemZ_VR128BitRegClassID = 16,
+  SystemZ_VF128BitRegClassID = 17,
+  SystemZ_FP128BitRegClassID = 18,
+  SystemZ_GR128BitRegClassID = 19,
+  SystemZ_ADDR128BitRegClassID = 20,
+};
+#endif // GET_REGINFO_ENUM
+
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|* MC Register Information                                                    *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+
+#ifdef GET_REGINFO_MC_DESC
+#undef GET_REGINFO_MC_DESC
+
+static const MCPhysReg SystemZRegDiffLists[] = {
+  /* 0 */ -679, 1, 1, 1, 0,
+  /* 5 */ -211, 1, 0,
+  /* 8 */ -65, 2, 0,
+  /* 11 */ -63, 2, 0,
+  /* 14 */ -61, 2, 0,
+  /* 17 */ -59, 2, 0,
+  /* 20 */ 32, 40, 0,
+  /* 23 */ -30, 40, -42, 40, 0,
+  /* 28 */ -28, 40, -42, 40, 0,
+  /* 33 */ -26, 40, -42, 40, 0,
+  /* 38 */ -24, 40, -42, 40, 0,
+  /* 43 */ -32, 40, 0,
+  /* 46 */ -16, 40, 0,
+  /* 49 */ -32, 41, 0,
+  /* 52 */ -16, 41, 0,
+  /* 55 */ -32, 42, 0,
+  /* 58 */ -16, 42, 0,
+  /* 61 */ -32, 43, 0,
+  /* 64 */ -16, 43, 0,
+  /* 67 */ -32, 44, 0,
+  /* 70 */ -16, 44, 0,
+  /* 73 */ -32, 45, 0,
+  /* 76 */ -16, 45, 0,
+  /* 79 */ -32, 46, 0,
+  /* 82 */ -16, 46, 0,
+  /* 85 */ -32, 47, 0,
+  /* 88 */ -16, 47, 0,
+  /* 91 */ -32, 48, 0,
+  /* 94 */ -16, 48, 0,
+  /* 97 */ -40, -32, 56, 0,
+  /* 101 */ -40, -32, 58, 0,
+  /* 105 */ -40, -32, 60, 0,
+  /* 109 */ -40, -32, 62, 0,
+  /* 113 */ -40, -32, 64, 0,
+  /* 117 */ -275, 0,
+  /* 119 */ -242, 0,
+  /* 121 */ -73, 0,
+  /* 123 */ -33, 0,
+  /* 125 */ -40, -32, 0,
+  /* 128 */ -47, 32, -16, -17, 32, -16, 0,
+  /* 135 */ -46, 32, -16, -17, 32, -16, 0,
+  /* 142 */ -45, 32, -16, -17, 32, -16, 0,
+  /* 149 */ -44, 32, -16, -17, 32, -16, 0,
+  /* 156 */ -43, 32, -16, -17, 32, -16, 0,
+  /* 163 */ -42, 32, -16, -17, 32, -16, 0,
+  /* 170 */ -41, 32, -16, -17, 32, -16, 0,
+  /* 177 */ -40, 32, -16, -17, 32, -16, 0,
+  /* 184 */ -1, 0,
+};
+
+static const uint16_t SystemZSubRegIdxLists[] = {
+  /* 0 */ 6, 1, 0,
+  /* 3 */ 7, 6, 1, 2, 4, 3, 0,
+  /* 10 */ 7, 8, 2, 5, 0,
+  /* 15 */ 9, 8, 0,
+};
+
+static const MCRegisterDesc SystemZRegDesc[] = { // Descriptors
+  { 3, 0, 0, 0, 0, 0 },
+  { 226, 4, 4, 2, 2945, 0 },
+  { 20, 4, 4, 2, 2945, 0 },
+  { 49, 4, 4, 2, 2945, 0 },
+  { 74, 4, 4, 2, 2945, 0 },
+  { 99, 4, 4, 2, 2945, 0 },
+  { 124, 4, 4, 2, 2945, 0 },
+  { 149, 4, 4, 2, 2945, 0 },
+  { 166, 4, 4, 2, 2945, 0 },
+  { 183, 4, 4, 2, 2945, 0 },
+  { 200, 4, 4, 2, 2945, 0 },
+  { 217, 4, 4, 2, 2945, 0 },
+  { 0, 4, 4, 2, 2945, 0 },
+  { 29, 4, 4, 2, 2945, 0 },
+  { 58, 4, 4, 2, 2945, 0 },
+  { 83, 4, 4, 2, 2945, 0 },
+  { 108, 4, 4, 2, 2945, 0 },
+  { 133, 4, 4, 2, 2945, 0 },
+  { 23, 4, 4, 2, 2945, 0 },
+  { 52, 4, 4, 2, 2945, 0 },
+  { 77, 4, 4, 2, 2945, 0 },
+  { 102, 4, 4, 2, 2945, 0 },
+  { 127, 4, 4, 2, 2945, 0 },
+  { 152, 4, 4, 2, 2945, 0 },
+  { 169, 4, 4, 2, 2945, 0 },
+  { 186, 4, 4, 2, 2945, 0 },
+  { 203, 4, 4, 2, 2945, 0 },
+  { 220, 4, 4, 2, 2945, 0 },
+  { 4, 4, 4, 2, 2945, 0 },
+  { 33, 4, 4, 2, 2945, 0 },
+  { 62, 4, 4, 2, 2945, 0 },
+  { 87, 4, 4, 2, 2945, 0 },
+  { 112, 4, 4, 2, 2945, 0 },
+  { 137, 4, 4, 2, 2945, 0 },
+  { 26, 20, 4, 15, 2945, 8 },
+  { 55, 20, 4, 15, 2945, 8 },
+  { 80, 20, 4, 15, 2945, 8 },
+  { 105, 20, 4, 15, 2945, 8 },
+  { 130, 20, 4, 15, 2945, 8 },
+  { 155, 20, 4, 15, 2945, 8 },
+  { 172, 20, 4, 15, 2945, 8 },
+  { 189, 20, 4, 15, 2945, 8 },
+  { 206, 20, 4, 15, 2945, 8 },
+  { 223, 20, 4, 15, 2945, 8 },
+  { 8, 20, 4, 15, 2945, 8 },
+  { 37, 20, 4, 15, 2945, 8 },
+  { 66, 20, 4, 15, 2945, 8 },
+  { 91, 20, 4, 15, 2945, 8 },
+  { 116, 20, 4, 15, 2945, 8 },
+  { 141, 20, 4, 15, 2945, 8 },
+  { 158, 20, 4, 15, 2945, 8 },
+  { 175, 20, 4, 15, 2945, 8 },
+  { 192, 20, 4, 15, 2945, 8 },
+  { 209, 20, 4, 15, 2945, 8 },
+  { 12, 20, 4, 15, 2945, 8 },
+  { 41, 20, 4, 15, 2945, 8 },
+  { 70, 20, 4, 15, 2945, 8 },
+  { 95, 20, 4, 15, 2945, 8 },
+  { 120, 20, 4, 15, 2945, 8 },
+  { 145, 20, 4, 15, 2945, 8 },
+  { 162, 20, 4, 15, 2945, 8 },
+  { 179, 20, 4, 15, 2945, 8 },
+  { 196, 20, 4, 15, 2945, 8 },
+  { 213, 20, 4, 15, 2945, 8 },
+  { 16, 20, 4, 15, 2945, 8 },
+  { 45, 20, 4, 15, 2945, 8 },
+  { 249, 21, 114, 16, 1969, 8 },
+  { 277, 21, 114, 16, 1969, 8 },
+  { 300, 21, 110, 16, 1969, 8 },
+  { 323, 21, 110, 16, 1969, 8 },
+  { 346, 21, 110, 16, 1969, 8 },
+  { 369, 21, 110, 16, 1969, 8 },
+  { 387, 21, 106, 16, 1969, 8 },
+  { 405, 21, 106, 16, 1969, 8 },
+  { 423, 21, 106, 16, 1969, 8 },
+  { 441, 21, 106, 16, 1969, 8 },
+  { 229, 21, 102, 16, 1969, 8 },
+  { 257, 21, 102, 16, 1969, 8 },
+  { 285, 21, 102, 16, 1969, 8 },
+  { 308, 21, 102, 16, 1969, 8 },
+  { 331, 21, 98, 16, 1969, 8 },
+  { 354, 21, 98, 16, 1969, 8 },
+  { 377, 21, 126, 16, 1969, 8 },
+  { 395, 21, 126, 16, 1969, 8 },
+  { 413, 21, 126, 16, 1969, 8 },
+  { 431, 21, 126, 16, 1969, 8 },
+  { 239, 21, 126, 16, 1969, 8 },
+  { 267, 21, 126, 16, 1969, 8 },
+  { 295, 21, 126, 16, 1969, 8 },
+  { 318, 21, 126, 16, 1969, 8 },
+  { 341, 21, 126, 16, 1969, 8 },
+  { 364, 21, 126, 16, 1969, 8 },
+  { 382, 21, 126, 16, 1969, 8 },
+  { 400, 21, 126, 16, 1969, 8 },
+  { 418, 21, 126, 16, 1969, 8 },
+  { 436, 21, 126, 16, 1969, 8 },
+  { 244, 21, 126, 16, 1969, 8 },
+  { 272, 21, 126, 16, 1969, 8 },
+  { 594, 23, 4, 10, 129, 7 },
+  { 602, 23, 4, 10, 129, 7 },
+  { 630, 28, 4, 10, 177, 7 },
+  { 638, 28, 4, 10, 177, 7 },
+  { 646, 33, 4, 10, 225, 7 },
+  { 654, 33, 4, 10, 225, 7 },
+  { 606, 38, 4, 10, 273, 7 },
+  { 620, 38, 4, 10, 273, 7 },
+  { 673, 4, 113, 2, 1937, 0 },
+  { 692, 4, 113, 2, 1937, 0 },
+  { 706, 4, 109, 2, 1937, 0 },
+  { 720, 4, 109, 2, 1937, 0 },
+  { 734, 4, 109, 2, 1937, 0 },
+  { 748, 4, 109, 2, 1937, 0 },
+  { 762, 4, 105, 2, 1937, 0 },
+  { 776, 4, 105, 2, 1937, 0 },
+  { 790, 4, 105, 2, 1937, 0 },
+  { 804, 4, 105, 2, 1937, 0 },
+  { 658, 4, 101, 2, 1937, 0 },
+  { 677, 4, 101, 2, 1937, 0 },
+  { 696, 4, 101, 2, 1937, 0 },
+  { 710, 4, 101, 2, 1937, 0 },
+  { 724, 4, 97, 2, 1937, 0 },
+  { 738, 4, 97, 2, 1937, 0 },
+  { 752, 4, 125, 2, 1937, 0 },
+  { 766, 4, 125, 2, 1937, 0 },
+  { 780, 4, 125, 2, 1937, 0 },
+  { 794, 4, 125, 2, 1937, 0 },
+  { 663, 4, 125, 2, 1937, 0 },
+  { 682, 4, 125, 2, 1937, 0 },
+  { 701, 4, 125, 2, 1937, 0 },
+  { 715, 4, 125, 2, 1937, 0 },
+  { 729, 4, 125, 2, 1937, 0 },
+  { 743, 4, 125, 2, 1937, 0 },
+  { 757, 4, 125, 2, 1937, 0 },
+  { 771, 4, 125, 2, 1937, 0 },
+  { 785, 4, 125, 2, 1937, 0 },
+  { 799, 4, 125, 2, 1937, 0 },
+  { 668, 4, 125, 2, 1937, 0 },
+  { 687, 4, 125, 2, 1937, 0 },
+  { 253, 132, 92, 0, 82, 4 },
+  { 281, 132, 86, 0, 82, 4 },
+  { 304, 132, 86, 0, 82, 4 },
+  { 327, 132, 80, 0, 82, 4 },
+  { 350, 132, 80, 0, 82, 4 },
+  { 373, 132, 74, 0, 82, 4 },
+  { 391, 132, 74, 0, 82, 4 },
+  { 409, 132, 68, 0, 82, 4 },
+  { 427, 132, 68, 0, 82, 4 },
+  { 445, 132, 62, 0, 82, 4 },
+  { 234, 132, 62, 0, 82, 4 },
+  { 262, 132, 56, 0, 82, 4 },
+  { 290, 132, 56, 0, 82, 4 },
+  { 313, 132, 50, 0, 82, 4 },
+  { 336, 132, 50, 0, 82, 4 },
+  { 359, 132, 21, 0, 82, 4 },
+  { 454, 4, 94, 2, 1906, 0 },
+  { 463, 4, 88, 2, 1906, 0 },
+  { 472, 4, 88, 2, 1906, 0 },
+  { 481, 4, 82, 2, 1906, 0 },
+  { 490, 4, 82, 2, 1906, 0 },
+  { 499, 4, 76, 2, 1906, 0 },
+  { 503, 4, 76, 2, 1906, 0 },
+  { 507, 4, 70, 2, 1906, 0 },
+  { 511, 4, 70, 2, 1906, 0 },
+  { 515, 4, 64, 2, 1906, 0 },
+  { 449, 4, 64, 2, 1906, 0 },
+  { 458, 4, 58, 2, 1906, 0 },
+  { 467, 4, 58, 2, 1906, 0 },
+  { 476, 4, 52, 2, 1906, 0 },
+  { 485, 4, 52, 2, 1906, 0 },
+  { 494, 4, 46, 2, 1906, 0 },
+  { 524, 4, 91, 2, 1874, 0 },
+  { 533, 4, 85, 2, 1874, 0 },
+  { 542, 4, 85, 2, 1874, 0 },
+  { 551, 4, 79, 2, 1874, 0 },
+  { 560, 4, 79, 2, 1874, 0 },
+  { 569, 4, 73, 2, 1874, 0 },
+  { 573, 4, 73, 2, 1874, 0 },
+  { 577, 4, 67, 2, 1874, 0 },
+  { 581, 4, 67, 2, 1874, 0 },
+  { 585, 4, 61, 2, 1874, 0 },
+  { 519, 4, 61, 2, 1874, 0 },
+  { 528, 4, 55, 2, 1874, 0 },
+  { 537, 4, 55, 2, 1874, 0 },
+  { 546, 4, 49, 2, 1874, 0 },
+  { 555, 4, 49, 2, 1874, 0 },
+  { 564, 4, 43, 2, 1874, 0 },
+  { 598, 128, 4, 3, 4, 2 },
+  { 616, 135, 4, 3, 4, 2 },
+  { 634, 142, 4, 3, 4, 2 },
+  { 642, 149, 4, 3, 4, 2 },
+  { 650, 156, 4, 3, 4, 2 },
+  { 589, 163, 4, 3, 4, 2 },
+  { 611, 170, 4, 3, 4, 2 },
+  { 625, 177, 4, 3, 4, 2 },
+};
+
+  // GRX32Bit Register Class...
+  static const MCPhysReg GRX32Bit[] = {
+    SystemZ_R0L, SystemZ_R1L, SystemZ_R2L, SystemZ_R3L, SystemZ_R4L, SystemZ_R5L, SystemZ_R0H, SystemZ_R1H, SystemZ_R2H, SystemZ_R3H, SystemZ_R4H, SystemZ_R5H, SystemZ_R15L, SystemZ_R15H, SystemZ_R14L, SystemZ_R14H, SystemZ_R13L, SystemZ_R13H, SystemZ_R12L, SystemZ_R12H, SystemZ_R11L, SystemZ_R11H, SystemZ_R10L, SystemZ_R10H, SystemZ_R9L, SystemZ_R9H, SystemZ_R8L, SystemZ_R8H, SystemZ_R7L, SystemZ_R7H, SystemZ_R6L, SystemZ_R6H,
+  };
+
+  // GRX32Bit Bit set.
+  static const uint8_t GRX32BitBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03,
+  };
+
+  // VR32Bit Register Class...
+  static const MCPhysReg VR32Bit[] = {
+    SystemZ_F0S, SystemZ_F1S, SystemZ_F2S, SystemZ_F3S, SystemZ_F4S, SystemZ_F5S, SystemZ_F6S, SystemZ_F7S, SystemZ_F16S, SystemZ_F17S, SystemZ_F18S, SystemZ_F19S, SystemZ_F20S, SystemZ_F21S, SystemZ_F22S, SystemZ_F23S, SystemZ_F24S, SystemZ_F25S, SystemZ_F26S, SystemZ_F27S, SystemZ_F28S, SystemZ_F29S, SystemZ_F30S, SystemZ_F31S, SystemZ_F8S, SystemZ_F9S, SystemZ_F10S, SystemZ_F11S, SystemZ_F12S, SystemZ_F13S, SystemZ_F14S, SystemZ_F15S,
+  };
+
+  // VR32Bit Bit set.
+  static const uint8_t VR32BitBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03,
+  };
+
+  // AR32Bit Register Class...
+  static const MCPhysReg AR32Bit[] = {
+    SystemZ_A0, SystemZ_A1, SystemZ_A2, SystemZ_A3, SystemZ_A4, SystemZ_A5, SystemZ_A6, SystemZ_A7, SystemZ_A8, SystemZ_A9, SystemZ_A10, SystemZ_A11, SystemZ_A12, SystemZ_A13, SystemZ_A14, SystemZ_A15,
+  };
+
+  // AR32Bit Bit set.
+  static const uint8_t AR32BitBits[] = {
+    0xfc, 0xff, 0x03,
+  };
+
+  // FP32Bit Register Class...
+  static const MCPhysReg FP32Bit[] = {
+    SystemZ_F0S, SystemZ_F1S, SystemZ_F2S, SystemZ_F3S, SystemZ_F4S, SystemZ_F5S, SystemZ_F6S, SystemZ_F7S, SystemZ_F8S, SystemZ_F9S, SystemZ_F10S, SystemZ_F11S, SystemZ_F12S, SystemZ_F13S, SystemZ_F14S, SystemZ_F15S,
+  };
+
+  // FP32Bit Bit set.
+  static const uint8_t FP32BitBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03,
+  };
+
+  // GR32Bit Register Class...
+  static const MCPhysReg GR32Bit[] = {
+    SystemZ_R0L, SystemZ_R1L, SystemZ_R2L, SystemZ_R3L, SystemZ_R4L, SystemZ_R5L, SystemZ_R15L, SystemZ_R14L, SystemZ_R13L, SystemZ_R12L, SystemZ_R11L, SystemZ_R10L, SystemZ_R9L, SystemZ_R8L, SystemZ_R7L, SystemZ_R6L,
+  };
+
+  // GR32Bit Bit set.
+  static const uint8_t GR32BitBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03,
+  };
+
+  // GRH32Bit Register Class...
+  static const MCPhysReg GRH32Bit[] = {
+    SystemZ_R0H, SystemZ_R1H, SystemZ_R2H, SystemZ_R3H, SystemZ_R4H, SystemZ_R5H, SystemZ_R15H, SystemZ_R14H, SystemZ_R13H, SystemZ_R12H, SystemZ_R11H, SystemZ_R10H, SystemZ_R9H, SystemZ_R8H, SystemZ_R7H, SystemZ_R6H,
+  };
+
+  // GRH32Bit Bit set.
+  static const uint8_t GRH32BitBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03,
+  };
+
+  // ADDR32Bit Register Class...
+  static const MCPhysReg ADDR32Bit[] = {
+    SystemZ_R1L, SystemZ_R2L, SystemZ_R3L, SystemZ_R4L, SystemZ_R5L, SystemZ_R15L, SystemZ_R14L, SystemZ_R13L, SystemZ_R12L, SystemZ_R11L, SystemZ_R10L, SystemZ_R9L, SystemZ_R8L, SystemZ_R7L, SystemZ_R6L,
+  };
+
+  // ADDR32Bit Bit set.
+  static const uint8_t ADDR32BitBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03,
+  };
+
+  // CCR Register Class...
+  static const MCPhysReg CCR[] = {
+    SystemZ_CC,
+  };
+
+  // CCR Bit set.
+  static const uint8_t CCRBits[] = {
+    0x02,
+  };
+
+  // AnyRegBit Register Class...
+  static const MCPhysReg AnyRegBit[] = {
+    SystemZ_R0D, SystemZ_R1D, SystemZ_R2D, SystemZ_R3D, SystemZ_R4D, SystemZ_R5D, SystemZ_R6D, SystemZ_R7D, SystemZ_R8D, SystemZ_R9D, SystemZ_R10D, SystemZ_R11D, SystemZ_R12D, SystemZ_R13D, SystemZ_R14D, SystemZ_R15D, SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D, SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15,
+  };
+
+  // AnyRegBit Bit set.
+  static const uint8_t AnyRegBitBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 0x00, 0xfc, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03,
+  };
+
+  // AnyRegBit_with_subreg_r32 Register Class...
+  static const MCPhysReg AnyRegBit_with_subreg_r32[] = {
+    SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D, SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15,
+  };
+
+  // AnyRegBit_with_subreg_r32 Bit set.
+  static const uint8_t AnyRegBit_with_subreg_r32Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 0x00, 0xfc, 0xff, 0x03,
+  };
+
+  // VR64Bit Register Class...
+  static const MCPhysReg VR64Bit[] = {
+    SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, SystemZ_F16D, SystemZ_F17D, SystemZ_F18D, SystemZ_F19D, SystemZ_F20D, SystemZ_F21D, SystemZ_F22D, SystemZ_F23D, SystemZ_F24D, SystemZ_F25D, SystemZ_F26D, SystemZ_F27D, SystemZ_F28D, SystemZ_F29D, SystemZ_F30D, SystemZ_F31D, SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D,
+  };
+
+  // VR64Bit Bit set.
+  static const uint8_t VR64BitBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03,
+  };
+
+  // AnyRegBit_with_subreg_r64 Register Class...
+  static const MCPhysReg AnyRegBit_with_subreg_r64[] = {
+    SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15,
+  };
+
+  // AnyRegBit_with_subreg_r64 Bit set.
+  static const uint8_t AnyRegBit_with_subreg_r64Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03,
+  };
+
+  // CR64Bit Register Class...
+  static const MCPhysReg CR64Bit[] = {
+    SystemZ_C0, SystemZ_C1, SystemZ_C2, SystemZ_C3, SystemZ_C4, SystemZ_C5, SystemZ_C6, SystemZ_C7, SystemZ_C8, SystemZ_C9, SystemZ_C10, SystemZ_C11, SystemZ_C12, SystemZ_C13, SystemZ_C14, SystemZ_C15,
+  };
+
+  // CR64Bit Bit set.
+  static const uint8_t CR64BitBits[] = {
+    0x00, 0x00, 0xfc, 0xff, 0x03,
+  };
+
+  // FP64Bit Register Class...
+  static const MCPhysReg FP64Bit[] = {
+    SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D,
+  };
+
+  // FP64Bit Bit set.
+  static const uint8_t FP64BitBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03,
+  };
+
+  // GR64Bit Register Class...
+  static const MCPhysReg GR64Bit[] = {
+    SystemZ_R0D, SystemZ_R1D, SystemZ_R2D, SystemZ_R3D, SystemZ_R4D, SystemZ_R5D, SystemZ_R15D, SystemZ_R14D, SystemZ_R13D, SystemZ_R12D, SystemZ_R11D, SystemZ_R10D, SystemZ_R9D, SystemZ_R8D, SystemZ_R7D, SystemZ_R6D,
+  };
+
+  // GR64Bit Bit set.
+  static const uint8_t GR64BitBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03,
+  };
+
+  // ADDR64Bit Register Class...
+  static const MCPhysReg ADDR64Bit[] = {
+    SystemZ_R1D, SystemZ_R2D, SystemZ_R3D, SystemZ_R4D, SystemZ_R5D, SystemZ_R15D, SystemZ_R14D, SystemZ_R13D, SystemZ_R12D, SystemZ_R11D, SystemZ_R10D, SystemZ_R9D, SystemZ_R8D, SystemZ_R7D, SystemZ_R6D,
+  };
+
+  // ADDR64Bit Bit set.
+  static const uint8_t ADDR64BitBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03,
+  };
+
+  // VR128Bit Register Class...
+  static const MCPhysReg VR128Bit[] = {
+    SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, SystemZ_V16, SystemZ_V17, SystemZ_V18, SystemZ_V19, SystemZ_V20, SystemZ_V21, SystemZ_V22, SystemZ_V23, SystemZ_V24, SystemZ_V25, SystemZ_V26, SystemZ_V27, SystemZ_V28, SystemZ_V29, SystemZ_V30, SystemZ_V31, SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15,
+  };
+
+  // VR128Bit Bit set.
+  static const uint8_t VR128BitBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03,
+  };
+
+  // VF128Bit Register Class...
+  static const MCPhysReg VF128Bit[] = {
+    SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15,
+  };
+
+  // VF128Bit Bit set.
+  static const uint8_t VF128BitBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03,
+  };
+
+  // FP128Bit Register Class...
+  static const MCPhysReg FP128Bit[] = {
+    SystemZ_F0Q, SystemZ_F1Q, SystemZ_F4Q, SystemZ_F5Q, SystemZ_F8Q, SystemZ_F9Q, SystemZ_F12Q, SystemZ_F13Q,
+  };
+
+  // FP128Bit Bit set.
+  static const uint8_t FP128BitBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
+  };
+
+  // GR128Bit Register Class...
+  static const MCPhysReg GR128Bit[] = {
+    SystemZ_R0Q, SystemZ_R2Q, SystemZ_R4Q, SystemZ_R12Q, SystemZ_R10Q, SystemZ_R8Q, SystemZ_R6Q, SystemZ_R14Q,
+  };
+
+  // GR128Bit Bit set.
+  static const uint8_t GR128BitBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
+  };
+
+  // ADDR128Bit Register Class...
+  static const MCPhysReg ADDR128Bit[] = {
+    SystemZ_R2Q, SystemZ_R4Q, SystemZ_R12Q, SystemZ_R10Q, SystemZ_R8Q, SystemZ_R6Q, SystemZ_R14Q,
+  };
+
+  // ADDR128Bit Bit set.
+  static const uint8_t ADDR128BitBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03,
+  };
+
+static const MCRegisterClass SystemZMCRegisterClasses[] = {
+  { GRX32Bit, GRX32BitBits, sizeof(GRX32BitBits) },
+  { VR32Bit, VR32BitBits, sizeof(VR32BitBits) },
+  { AR32Bit, AR32BitBits, sizeof(AR32BitBits) },
+  { FP32Bit, FP32BitBits, sizeof(FP32BitBits) },
+  { GR32Bit, GR32BitBits, sizeof(GR32BitBits) },
+  { GRH32Bit, GRH32BitBits, sizeof(GRH32BitBits) },
+  { ADDR32Bit, ADDR32BitBits, sizeof(ADDR32BitBits) },
+  { CCR, CCRBits, sizeof(CCRBits) },
+  { AnyRegBit, AnyRegBitBits, sizeof(AnyRegBitBits) },
+  { AnyRegBit_with_subreg_r32, AnyRegBit_with_subreg_r32Bits, sizeof(AnyRegBit_with_subreg_r32Bits) },
+  { VR64Bit, VR64BitBits, sizeof(VR64BitBits) },
+  { AnyRegBit_with_subreg_r64, AnyRegBit_with_subreg_r64Bits, sizeof(AnyRegBit_with_subreg_r64Bits) },
+  { CR64Bit, CR64BitBits, sizeof(CR64BitBits) },
+  { FP64Bit, FP64BitBits, sizeof(FP64BitBits) },
+  { GR64Bit, GR64BitBits, sizeof(GR64BitBits) },
+  { ADDR64Bit, ADDR64BitBits, sizeof(ADDR64BitBits) },
+  { VR128Bit, VR128BitBits, sizeof(VR128BitBits) },
+  { VF128Bit, VF128BitBits, sizeof(VF128BitBits) },
+  { FP128Bit, FP128BitBits, sizeof(FP128BitBits) },
+  { GR128Bit, GR128BitBits, sizeof(GR128BitBits) },
+  { ADDR128Bit, ADDR128BitBits, sizeof(ADDR128BitBits) },
+};
+
+#endif // GET_REGINFO_MC_DESC
--- a/thirdparty/capstone/arch/SystemZ/SystemZGenSubtargetInfo.inc
+++ b/thirdparty/capstone/arch/SystemZ/SystemZGenSubtargetInfo.inc
@@ -0,0 +1,49 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|* Subtarget Enumeration Source Fragment                                      *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+
+#ifdef GET_SUBTARGETINFO_ENUM
+#undef GET_SUBTARGETINFO_ENUM
+
+enum {
+  SystemZ_FeatureDFPPackedConversion = 1ULL << 0,
+  SystemZ_FeatureDFPZonedConversion = 1ULL << 1,
+  SystemZ_FeatureDistinctOps = 1ULL << 2,
+  SystemZ_FeatureEnhancedDAT2 = 1ULL << 3,
+  SystemZ_FeatureExecutionHint = 1ULL << 4,
+  SystemZ_FeatureFPExtension = 1ULL << 5,
+  SystemZ_FeatureFastSerialization = 1ULL << 6,
+  SystemZ_FeatureGuardedStorage = 1ULL << 7,
+  SystemZ_FeatureHighWord = 1ULL << 8,
+  SystemZ_FeatureInsertReferenceBitsMultiple = 1ULL << 9,
+  SystemZ_FeatureInterlockedAccess1 = 1ULL << 10,
+  SystemZ_FeatureLoadAndTrap = 1ULL << 11,
+  SystemZ_FeatureLoadAndZeroRightmostByte = 1ULL << 12,
+  SystemZ_FeatureLoadStoreOnCond = 1ULL << 13,
+  SystemZ_FeatureLoadStoreOnCond2 = 1ULL << 14,
+  SystemZ_FeatureMessageSecurityAssist3 = 1ULL << 15,
+  SystemZ_FeatureMessageSecurityAssist4 = 1ULL << 16,
+  SystemZ_FeatureMessageSecurityAssist5 = 1ULL << 17,
+  SystemZ_FeatureMessageSecurityAssist7 = 1ULL << 18,
+  SystemZ_FeatureMessageSecurityAssist8 = 1ULL << 19,
+  SystemZ_FeatureMiscellaneousExtensions = 1ULL << 20,
+  SystemZ_FeatureMiscellaneousExtensions2 = 1ULL << 21,
+  SystemZ_FeaturePopulationCount = 1ULL << 22,
+  SystemZ_FeatureProcessorAssist = 1ULL << 23,
+  SystemZ_FeatureResetReferenceBitsMultiple = 1ULL << 24,
+  SystemZ_FeatureTransactionalExecution = 1ULL << 25,
+  SystemZ_FeatureVector = 1ULL << 26,
+  SystemZ_FeatureVectorEnhancements1 = 1ULL << 27,
+  SystemZ_FeatureVectorPackedDecimal = 1ULL << 28,
+};
+
+#endif // GET_SUBTARGETINFO_ENUM
+
--- a/thirdparty/capstone/arch/SystemZ/SystemZInstPrinter.c
+++ b/thirdparty/capstone/arch/SystemZ/SystemZInstPrinter.c
@@ -0,0 +1,433 @@
+//===-- SystemZInstPrinter.cpp - Convert SystemZ MCInst to assembly syntax --------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This class prints an SystemZ MCInst to a .s file.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifdef CAPSTONE_HAS_SYSZ
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <capstone/platform.h>
+
+#include "SystemZInstPrinter.h"
+#include "../../MCInst.h"
+#include "../../utils.h"
+#include "../../SStream.h"
+#include "../../MCRegisterInfo.h"
+#include "../../MathExtras.h"
+#include "SystemZMapping.h"
+
+static const char *getRegisterName(unsigned RegNo);
+
+void SystemZ_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci)
+{
+	/*
+	   if (((cs_struct *)ud)->detail != CS_OPT_ON)
+	   return;
+	 */
+}
+
+static void printAddress(MCInst *MI, unsigned Base, int64_t Disp, unsigned Index, SStream *O)
+{
+	printInt64(O, Disp);
+
+	if (Base) {
+		SStream_concat0(O, "(");
+		if (Index)
+			SStream_concat(O, "%%%s, ", getRegisterName(Index));
+		SStream_concat(O, "%%%s)", getRegisterName(Base));
+
+		if (MI->csh->detail_opt) {
+			MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_MEM;
+			MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.base = (uint8_t)SystemZ_map_register(Base);
+			MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.index = (uint8_t)SystemZ_map_register(Index);
+			MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.disp = Disp;
+			MI->flat_insn->detail->sysz.op_count++;
+		}
+	} else if (!Index) {
+		if (MI->csh->detail_opt) {
+			MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
+			MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Disp;
+			MI->flat_insn->detail->sysz.op_count++;
+		}
+	} else {
+		SStream_concat(O, "(%%%s)", getRegisterName(Index));
+		if (MI->csh->detail_opt) {
+			MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_MEM;
+			MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.base = (uint8_t)SystemZ_map_register(Base);
+			MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.index = (uint8_t)SystemZ_map_register(Index);
+			MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.disp = Disp;
+			MI->flat_insn->detail->sysz.op_count++;
+		}
+	}
+}
+
+static void _printOperand(MCInst *MI, MCOperand *MO, SStream *O)
+{
+	if (MCOperand_isReg(MO)) {
+		unsigned reg;
+
+		reg = MCOperand_getReg(MO);
+		SStream_concat(O, "%%%s", getRegisterName(reg));
+		reg = SystemZ_map_register(reg);
+
+		if (MI->csh->detail_opt) {
+			MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_REG;
+			MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].reg = reg;
+			MI->flat_insn->detail->sysz.op_count++;
+		}
+	} else if (MCOperand_isImm(MO)) {
+		int64_t Imm = MCOperand_getImm(MO);
+
+		printInt64(O, Imm);
+
+		if (MI->csh->detail_opt) {
+			MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
+			MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Imm;
+			MI->flat_insn->detail->sysz.op_count++;
+		}
+	}
+}
+
+static void printU1ImmOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+	// assert(isUInt<1>(Value) && "Invalid u1imm argument");
+	printInt64(O, Value);
+
+	if (MI->csh->detail_opt) {
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Value;
+		MI->flat_insn->detail->sysz.op_count++;
+	}
+}
+
+static void printU2ImmOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+	// assert(isUInt<2>(Value) && "Invalid u2imm argument");
+	printInt64(O, Value);
+
+	if (MI->csh->detail_opt) {
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Value;
+		MI->flat_insn->detail->sysz.op_count++;
+	}
+}
+
+static void printU3ImmOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+	// assert(isUInt<3>(Value) && "Invalid u4imm argument");
+	printInt64(O, Value);
+
+	if (MI->csh->detail_opt) {
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Value;
+		MI->flat_insn->detail->sysz.op_count++;
+	}
+}
+
+static void printU4ImmOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+	// assert(isUInt<4>(Value) && "Invalid u4imm argument");
+	printInt64(O, Value);
+
+	if (MI->csh->detail_opt) {
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Value;
+		MI->flat_insn->detail->sysz.op_count++;
+	}
+}
+
+static void printU6ImmOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	uint32_t Value = (uint32_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+	// assert(isUInt<6>(Value) && "Invalid u6imm argument");
+
+	printUInt32(O, Value);
+
+	if (MI->csh->detail_opt) {
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value;
+		MI->flat_insn->detail->sysz.op_count++;
+	}
+}
+
+static void printS8ImmOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	int8_t Value = (int8_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+	// assert(isInt<8>(Value) && "Invalid s8imm argument");
+
+	if (Value >= 0) {
+		if (Value > HEX_THRESHOLD)
+			SStream_concat(O, "0x%x", Value);
+		else
+			SStream_concat(O, "%u", Value);
+	} else {
+		if (Value < -HEX_THRESHOLD)
+			SStream_concat(O, "-0x%x", -Value);
+		else
+			SStream_concat(O, "-%u", -Value);
+	}
+
+	if (MI->csh->detail_opt) {
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value;
+		MI->flat_insn->detail->sysz.op_count++;
+	}
+}
+
+static void printU8ImmOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	uint8_t Value = (uint8_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+	// assert(isUInt<8>(Value) && "Invalid u8imm argument");
+
+	if (Value > HEX_THRESHOLD)
+		SStream_concat(O, "0x%x", Value);
+	else
+		SStream_concat(O, "%u", Value);
+
+	if (MI->csh->detail_opt) {
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value;
+		MI->flat_insn->detail->sysz.op_count++;
+	}
+}
+
+static void printU12ImmOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+	// assert(isUInt<12>(Value) && "Invalid u12imm argument");
+	printInt64(O, Value);
+
+	if (MI->csh->detail_opt) {
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Value;
+		MI->flat_insn->detail->sysz.op_count++;
+	}
+}
+
+static void printS16ImmOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	int16_t Value = (int16_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+	// assert(isInt<16>(Value) && "Invalid s16imm argument");
+
+	if (Value >= 0) {
+		if (Value > HEX_THRESHOLD)
+			SStream_concat(O, "0x%x", Value);
+		else
+			SStream_concat(O, "%u", Value);
+	} else {
+		if (Value < -HEX_THRESHOLD)
+			SStream_concat(O, "-0x%x", -Value);
+		else
+			SStream_concat(O, "-%u", -Value);
+	}
+
+	if (MI->csh->detail_opt) {
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value;
+		MI->flat_insn->detail->sysz.op_count++;
+	}
+}
+
+static void printU16ImmOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	uint16_t Value = (uint16_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+	// assert(isUInt<16>(Value) && "Invalid u16imm argument");
+
+	if (Value > HEX_THRESHOLD)
+		SStream_concat(O, "0x%x", Value);
+	else
+		SStream_concat(O, "%u", Value);
+
+	if (MI->csh->detail_opt) {
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value;
+		MI->flat_insn->detail->sysz.op_count++;
+	}
+}
+
+static void printS32ImmOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	int32_t Value = (int32_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+	// assert(isInt<32>(Value) && "Invalid s32imm argument");
+
+	printInt32(O, Value);
+
+	if (MI->csh->detail_opt) {
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value;
+		MI->flat_insn->detail->sysz.op_count++;
+	}
+}
+
+static void printU32ImmOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	uint32_t Value = (uint32_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+	// assert(isUInt<32>(Value) && "Invalid u32imm argument");
+
+	printUInt32(O, Value);
+
+	if (MI->csh->detail_opt) {
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value;
+		MI->flat_insn->detail->sysz.op_count++;
+	}
+}
+
+static void printU48ImmOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+	// assert(isUInt<48>(Value) && "Invalid u48imm argument");
+	printInt64(O, Value);
+
+	if (MI->csh->detail_opt) {
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Value;
+		MI->flat_insn->detail->sysz.op_count++;
+	}
+}
+
+static void printPCRelOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	MCOperand *MO = MCInst_getOperand(MI, OpNum);
+
+	if (MCOperand_isImm(MO)) {
+		int64_t imm = (int64_t)MCOperand_getImm(MO);
+
+		printInt64(O, imm);
+
+		if (MI->csh->detail_opt) {
+			MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
+			MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = imm;
+			MI->flat_insn->detail->sysz.op_count++;
+		}
+	}
+}
+
+static void printPCRelTLSOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	// Output the PC-relative operand.
+	printPCRelOperand(MI, OpNum, O);
+}
+
+static void printOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	_printOperand(MI, MCInst_getOperand(MI, OpNum), O);
+}
+
+static void printBDAddrOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	printAddress(MI, MCOperand_getReg(MCInst_getOperand(MI, OpNum)),
+			MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)), 0, O);
+}
+
+static void printBDXAddrOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	printAddress(MI, MCOperand_getReg(MCInst_getOperand(MI, OpNum)),
+			MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)),
+			MCOperand_getReg(MCInst_getOperand(MI, OpNum + 2)), O);
+}
+
+static void printBDLAddrOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	unsigned Base = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
+	uint64_t Disp = (uint64_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1));
+	uint64_t Length = (uint64_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 2));
+
+	if (Disp > HEX_THRESHOLD)
+		SStream_concat(O, "0x%"PRIx64, Disp);
+	else
+		SStream_concat(O, "%"PRIu64, Disp);
+
+	if (Length > HEX_THRESHOLD)
+		SStream_concat(O, "(0x%"PRIx64, Length);
+	else
+		SStream_concat(O, "(%"PRIu64, Length);
+
+	if (Base)
+		SStream_concat(O, ", %%%s", getRegisterName(Base));
+	SStream_concat0(O, ")");
+
+	if (MI->csh->detail_opt) {
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_MEM;
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.base = (uint8_t)SystemZ_map_register(Base);
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.length = Length;
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.disp = (int64_t)Disp;
+		MI->flat_insn->detail->sysz.op_count++;
+	}
+}
+
+static void printBDRAddrOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	unsigned Base = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
+	uint64_t Disp = (uint64_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1));
+	uint64_t Length = MCOperand_getReg(MCInst_getOperand(MI, OpNum + 2));
+
+	if (Disp > HEX_THRESHOLD)
+		SStream_concat(O, "0x%"PRIx64, Disp);
+	else
+		SStream_concat(O, "%"PRIu64, Disp);
+
+	SStream_concat0(O, "(");
+	SStream_concat(O, "%%%s", getRegisterName(Length));
+
+	if (Base)
+		SStream_concat(O, ", %%%s", getRegisterName(Base));
+	SStream_concat0(O, ")");
+
+	if (MI->csh->detail_opt) {
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_MEM;
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.base = (uint8_t)SystemZ_map_register(Base);
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.length = (uint8_t)SystemZ_map_register(Length);
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.disp = (int64_t)Disp;
+		MI->flat_insn->detail->sysz.op_count++;
+	}
+}
+
+static void printBDVAddrOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	printAddress(MI, MCOperand_getReg(MCInst_getOperand(MI, OpNum)),
+			MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)),
+			MCOperand_getReg(MCInst_getOperand(MI, OpNum + 2)), O);
+}
+
+static void printCond4Operand(MCInst *MI, int OpNum, SStream *O)
+{
+	static const char *const CondNames[] = {
+		"o", "h", "nle", "l", "nhe", "lh", "ne",
+		"e", "nlh", "he", "nl", "le", "nh", "no"
+	};
+
+	uint64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+	// assert(Imm > 0 && Imm < 15 && "Invalid condition");
+	SStream_concat0(O, CondNames[Imm - 1]);
+
+	if (MI->csh->detail_opt)
+		MI->flat_insn->detail->sysz.cc = (sysz_cc)Imm;
+}
+
+#define PRINT_ALIAS_INSTR
+#include "SystemZGenAsmWriter.inc"
+
+void SystemZ_printInst(MCInst *MI, SStream *O, void *Info)
+{
+	printInstruction(MI, O, Info);
+}
+
+#endif
--- a/thirdparty/capstone/arch/SystemZ/SystemZInstPrinter.h
+++ b/thirdparty/capstone/arch/SystemZ/SystemZInstPrinter.h
@@ -0,0 +1,15 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifndef CS_SYSZINSTPRINTER_H
+#define CS_SYSZINSTPRINTER_H
+
+#include "../../MCInst.h"
+#include "../../MCRegisterInfo.h"
+#include "../../SStream.h"
+
+void SystemZ_printInst(MCInst *MI, SStream *O, void *Info);
+
+void SystemZ_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci);
+
+#endif
--- a/thirdparty/capstone/arch/SystemZ/SystemZMCTargetDesc.c
+++ b/thirdparty/capstone/arch/SystemZ/SystemZMCTargetDesc.c
@@ -0,0 +1,195 @@
+//===-- SystemZMCTargetDesc.cpp - SystemZ target descriptions -------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifdef CAPSTONE_HAS_SYSZ
+
+#include <capstone/platform.h>
+#include "SystemZMCTargetDesc.h"
+
+#define GET_REGINFO_ENUM
+#include "SystemZGenRegisterInfo.inc"
+
+const unsigned SystemZMC_GR32Regs[16] = {
+	SystemZ_R0L, SystemZ_R1L, SystemZ_R2L, SystemZ_R3L,
+	SystemZ_R4L, SystemZ_R5L, SystemZ_R6L, SystemZ_R7L,
+	SystemZ_R8L, SystemZ_R9L, SystemZ_R10L, SystemZ_R11L,
+	SystemZ_R12L, SystemZ_R13L, SystemZ_R14L, SystemZ_R15L
+};
+
+const unsigned SystemZMC_GRH32Regs[16] = {
+	SystemZ_R0H, SystemZ_R1H, SystemZ_R2H, SystemZ_R3H,
+	SystemZ_R4H, SystemZ_R5H, SystemZ_R6H, SystemZ_R7H,
+	SystemZ_R8H, SystemZ_R9H, SystemZ_R10H, SystemZ_R11H,
+	SystemZ_R12H, SystemZ_R13H, SystemZ_R14H, SystemZ_R15H
+};
+
+const unsigned SystemZMC_GR64Regs[16] = {
+	SystemZ_R0D, SystemZ_R1D, SystemZ_R2D, SystemZ_R3D,
+	SystemZ_R4D, SystemZ_R5D, SystemZ_R6D, SystemZ_R7D,
+	SystemZ_R8D, SystemZ_R9D, SystemZ_R10D, SystemZ_R11D,
+	SystemZ_R12D, SystemZ_R13D, SystemZ_R14D, SystemZ_R15D
+};
+
+const unsigned SystemZMC_GR128Regs[16] = {
+	SystemZ_R0Q, 0, SystemZ_R2Q, 0,
+	SystemZ_R4Q, 0, SystemZ_R6Q, 0,
+	SystemZ_R8Q, 0, SystemZ_R10Q, 0,
+	SystemZ_R12Q, 0, SystemZ_R14Q, 0
+};
+
+const unsigned SystemZMC_FP32Regs[16] = {
+	SystemZ_F0S, SystemZ_F1S, SystemZ_F2S, SystemZ_F3S,
+	SystemZ_F4S, SystemZ_F5S, SystemZ_F6S, SystemZ_F7S,
+	SystemZ_F8S, SystemZ_F9S, SystemZ_F10S, SystemZ_F11S,
+	SystemZ_F12S, SystemZ_F13S, SystemZ_F14S, SystemZ_F15S
+};
+
+const unsigned SystemZMC_FP64Regs[16] = {
+	SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D,
+	SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D,
+	SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D,
+	SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D
+};
+
+const unsigned SystemZMC_FP128Regs[16] = {
+	SystemZ_F0Q, SystemZ_F1Q, 0, 0,
+	SystemZ_F4Q, SystemZ_F5Q, 0, 0,
+	SystemZ_F8Q, SystemZ_F9Q, 0, 0,
+	SystemZ_F12Q, SystemZ_F13Q, 0, 0
+};
+
+const unsigned SystemZMC_VR32Regs[32] = {
+  SystemZ_F0S, SystemZ_F1S, SystemZ_F2S, SystemZ_F3S,
+  SystemZ_F4S, SystemZ_F5S, SystemZ_F6S, SystemZ_F7S,
+  SystemZ_F8S, SystemZ_F9S, SystemZ_F10S, SystemZ_F11S,
+  SystemZ_F12S, SystemZ_F13S, SystemZ_F14S, SystemZ_F15S,
+  SystemZ_F16S, SystemZ_F17S, SystemZ_F18S, SystemZ_F19S,
+  SystemZ_F20S, SystemZ_F21S, SystemZ_F22S, SystemZ_F23S,
+  SystemZ_F24S, SystemZ_F25S, SystemZ_F26S, SystemZ_F27S,
+  SystemZ_F28S, SystemZ_F29S, SystemZ_F30S, SystemZ_F31S
+};
+
+const unsigned SystemZMC_VR64Regs[32] = {
+  SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D,
+  SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D,
+  SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D,
+  SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D,
+  SystemZ_F16D, SystemZ_F17D, SystemZ_F18D, SystemZ_F19D,
+  SystemZ_F20D, SystemZ_F21D, SystemZ_F22D, SystemZ_F23D,
+  SystemZ_F24D, SystemZ_F25D, SystemZ_F26D, SystemZ_F27D,
+  SystemZ_F28D, SystemZ_F29D, SystemZ_F30D, SystemZ_F31D
+};
+
+const unsigned SystemZMC_VR128Regs[32] = {
+  SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3,
+  SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7,
+  SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11,
+  SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15,
+  SystemZ_V16, SystemZ_V17, SystemZ_V18, SystemZ_V19,
+  SystemZ_V20, SystemZ_V21, SystemZ_V22, SystemZ_V23,
+  SystemZ_V24, SystemZ_V25, SystemZ_V26, SystemZ_V27,
+  SystemZ_V28, SystemZ_V29, SystemZ_V30, SystemZ_V31
+};
+
+const unsigned SystemZMC_AR32Regs[16] = {
+  SystemZ_A0, SystemZ_A1, SystemZ_A2, SystemZ_A3,
+  SystemZ_A4, SystemZ_A5, SystemZ_A6, SystemZ_A7,
+  SystemZ_A8, SystemZ_A9, SystemZ_A10, SystemZ_A11,
+  SystemZ_A12, SystemZ_A13, SystemZ_A14, SystemZ_A15
+};
+
+const unsigned SystemZMC_CR64Regs[16] = {
+  SystemZ_C0, SystemZ_C1, SystemZ_C2, SystemZ_C3,
+  SystemZ_C4, SystemZ_C5, SystemZ_C6, SystemZ_C7,
+  SystemZ_C8, SystemZ_C9, SystemZ_C10, SystemZ_C11,
+  SystemZ_C12, SystemZ_C13, SystemZ_C14, SystemZ_C15
+};
+
+/* All register classes that have 0-15.  */
+#define DEF_REG16(N) \
+    [SystemZ_R ## N ## L] = N, \
+    [SystemZ_R ## N ## H] = N, \
+    [SystemZ_R ## N ## D] = N, \
+    [SystemZ_F ## N ## S] = N, \
+    [SystemZ_F ## N ## D] = N, \
+    [SystemZ_V ## N] = N, \
+    [SystemZ_A ## N] = N, \
+    [SystemZ_C ## N] = N
+
+/* All register classes that (also) have 16-31.  */
+#define DEF_REG32(N) \
+    [SystemZ_F ## N ## S] = N, \
+    [SystemZ_F ## N ## D] = N, \
+    [SystemZ_V ## N] = N
+
+static const uint8_t Map[SystemZ_NUM_TARGET_REGS] = {
+    DEF_REG16(0),
+    DEF_REG16(1),
+    DEF_REG16(2),
+    DEF_REG16(3),
+    DEF_REG16(4),
+    DEF_REG16(5),
+    DEF_REG16(6),
+    DEF_REG16(8),
+    DEF_REG16(9),
+    DEF_REG16(10),
+    DEF_REG16(11),
+    DEF_REG16(12),
+    DEF_REG16(13),
+    DEF_REG16(14),
+    DEF_REG16(15),
+
+    DEF_REG32(16),
+    DEF_REG32(17),
+    DEF_REG32(18),
+    DEF_REG32(19),
+    DEF_REG32(20),
+    DEF_REG32(21),
+    DEF_REG32(22),
+    DEF_REG32(23),
+    DEF_REG32(24),
+    DEF_REG32(25),
+    DEF_REG32(26),
+    DEF_REG32(27),
+    DEF_REG32(28),
+    DEF_REG32(29),
+    DEF_REG32(30),
+    DEF_REG32(31),
+
+    /* The float Q registers are non-sequential.  */
+    [SystemZ_F0Q] = 0,
+    [SystemZ_F1Q] = 1,
+    [SystemZ_F4Q] = 4,
+    [SystemZ_F5Q] = 5,
+    [SystemZ_F8Q] = 8,
+    [SystemZ_F9Q] = 9,
+    [SystemZ_F12Q] = 12,
+    [SystemZ_F13Q] = 13,
+
+    /* The integer Q registers are all even.  */
+    [SystemZ_R0Q] = 0,
+    [SystemZ_R2Q] = 2,
+    [SystemZ_R4Q] = 4,
+    [SystemZ_R6Q] = 6,
+    [SystemZ_R8Q] = 8,
+    [SystemZ_R10Q] = 10,
+    [SystemZ_R12Q] = 12,
+    [SystemZ_R14Q] = 14,
+};
+
+unsigned SystemZMC_getFirstReg(unsigned Reg)
+{
+	// assert(Reg < SystemZ_NUM_TARGET_REGS);
+	return Map[Reg];
+}
+
+#endif
--- a/thirdparty/capstone/arch/SystemZ/SystemZMCTargetDesc.h
+++ b/thirdparty/capstone/arch/SystemZ/SystemZMCTargetDesc.h
@@ -0,0 +1,51 @@
+//===-- SystemZMCTargetDesc.h - SystemZ target descriptions -----*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifndef CS_SYSTEMZMCTARGETDESC_H
+#define CS_SYSTEMZMCTARGETDESC_H
+
+// Maps of asm register numbers to LLVM register numbers, with 0 indicating
+// an invalid register.  In principle we could use 32-bit and 64-bit register
+// classes directly, provided that we relegated the GPR allocation order
+// in SystemZRegisterInfo.td to an AltOrder and left the default order
+// as %r0-%r15.  It seems better to provide the same interface for
+// all classes though.
+extern const unsigned SystemZMC_GR32Regs[16];
+extern const unsigned SystemZMC_GRH32Regs[16];
+extern const unsigned SystemZMC_GR64Regs[16];
+extern const unsigned SystemZMC_GR128Regs[16];
+extern const unsigned SystemZMC_FP32Regs[16];
+extern const unsigned SystemZMC_FP64Regs[16];
+extern const unsigned SystemZMC_FP128Regs[16];
+extern const unsigned SystemZMC_VR32Regs[32];
+extern const unsigned SystemZMC_VR64Regs[32];
+extern const unsigned SystemZMC_VR128Regs[32];
+extern const unsigned SystemZMC_AR32Regs[16];
+extern const unsigned SystemZMC_CR64Regs[16];
+
+// Return the 0-based number of the first architectural register that
+// contains the given LLVM register.   E.g. R1D -> 1.
+unsigned SystemZMC_getFirstReg(unsigned Reg);
+
+// Defines symbolic names for SystemZ registers.
+// This defines a mapping from register name to register number.
+//#define GET_REGINFO_ENUM
+//#include "SystemZGenRegisterInfo.inc"
+
+// Defines symbolic names for the SystemZ instructions.
+//#define GET_INSTRINFO_ENUM
+//#include "SystemZGenInstrInfo.inc"
+
+//#define GET_SUBTARGETINFO_ENUM
+//#include "SystemZGenSubtargetInfo.inc"
+
+#endif
--- a/thirdparty/capstone/arch/SystemZ/SystemZMapping.c
+++ b/thirdparty/capstone/arch/SystemZ/SystemZMapping.c
@@ -0,0 +1,480 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifdef CAPSTONE_HAS_SYSZ
+
+#include <stdio.h>	// debug
+#include <string.h>
+
+#include "../../Mapping.h"
+#include "../../utils.h"
+
+#include "SystemZMapping.h"
+
+#define GET_INSTRINFO_ENUM
+#include "SystemZGenInstrInfo.inc"
+
+#ifndef CAPSTONE_DIET
+static const name_map reg_name_maps[] = {
+	{ SYSZ_REG_INVALID, NULL },
+
+	{ SYSZ_REG_0, "0" },
+	{ SYSZ_REG_1, "1" },
+	{ SYSZ_REG_2, "2" },
+	{ SYSZ_REG_3, "3" },
+	{ SYSZ_REG_4, "4" },
+	{ SYSZ_REG_5, "5" },
+	{ SYSZ_REG_6, "6" },
+	{ SYSZ_REG_7, "7" },
+	{ SYSZ_REG_8, "8" },
+	{ SYSZ_REG_9, "9" },
+	{ SYSZ_REG_10, "10" },
+	{ SYSZ_REG_11, "11" },
+	{ SYSZ_REG_12, "12" },
+	{ SYSZ_REG_13, "13" },
+	{ SYSZ_REG_14, "14" },
+	{ SYSZ_REG_15, "15" },
+	{ SYSZ_REG_CC, "cc"},
+	{ SYSZ_REG_F0, "f0" },
+	{ SYSZ_REG_F1, "f1" },
+	{ SYSZ_REG_F2, "f2" },
+	{ SYSZ_REG_F3, "f3" },
+	{ SYSZ_REG_F4, "f4" },
+	{ SYSZ_REG_F5, "f5" },
+	{ SYSZ_REG_F6, "f6" },
+	{ SYSZ_REG_F7, "f7" },
+	{ SYSZ_REG_F8, "f8" },
+	{ SYSZ_REG_F9, "f9" },
+	{ SYSZ_REG_F10, "f10" },
+	{ SYSZ_REG_F11, "f11" },
+	{ SYSZ_REG_F12, "f12" },
+	{ SYSZ_REG_F13, "f13" },
+	{ SYSZ_REG_F14, "f14" },
+	{ SYSZ_REG_F15, "f15" },
+	{ SYSZ_REG_R0L, "r0l" },
+	{ SYSZ_REG_A0, "a0" },
+	{ SYSZ_REG_A1, "a1" },
+	{ SYSZ_REG_A2, "a2" },
+	{ SYSZ_REG_A3, "a3" },
+	{ SYSZ_REG_A4, "a4" },
+	{ SYSZ_REG_A5, "a5" },
+	{ SYSZ_REG_A6, "a6" },
+	{ SYSZ_REG_A7, "a7" },
+	{ SYSZ_REG_A8, "a8" },
+	{ SYSZ_REG_A9, "a9" },
+	{ SYSZ_REG_A10, "a10" },
+	{ SYSZ_REG_A11, "a11" },
+	{ SYSZ_REG_A12, "a12" },
+	{ SYSZ_REG_A13, "a13" },
+	{ SYSZ_REG_A14, "a14" },
+	{ SYSZ_REG_A15, "a15" },
+	{ SYSZ_REG_C0, "c0" },
+	{ SYSZ_REG_C1, "c1" },
+	{ SYSZ_REG_C2, "c2" },
+	{ SYSZ_REG_C3, "c3" },
+	{ SYSZ_REG_C4, "c4" },
+	{ SYSZ_REG_C5, "c5" },
+	{ SYSZ_REG_C6, "c6" },
+	{ SYSZ_REG_C7, "c7" },
+	{ SYSZ_REG_C8, "c8" },
+	{ SYSZ_REG_C9, "c9" },
+	{ SYSZ_REG_C10, "c10" },
+	{ SYSZ_REG_C11, "c11" },
+	{ SYSZ_REG_C12, "c12" },
+	{ SYSZ_REG_C13, "c13" },
+	{ SYSZ_REG_C14, "c14" },
+	{ SYSZ_REG_C15, "c15" },
+	{ SYSZ_REG_V0, "v0" },
+	{ SYSZ_REG_V1, "v1" },
+	{ SYSZ_REG_V2, "v2" },
+	{ SYSZ_REG_V3, "v3" },
+	{ SYSZ_REG_V4, "v4" },
+	{ SYSZ_REG_V5, "v5" },
+	{ SYSZ_REG_V6, "v6" },
+	{ SYSZ_REG_V7, "v7" },
+	{ SYSZ_REG_V8, "v8" },
+	{ SYSZ_REG_V9, "v9" },
+	{ SYSZ_REG_V10, "v10" },
+	{ SYSZ_REG_V11, "v11" },
+	{ SYSZ_REG_V12, "v12" },
+	{ SYSZ_REG_V13, "v13" },
+	{ SYSZ_REG_V14, "v14" },
+	{ SYSZ_REG_V15, "v15" },
+	{ SYSZ_REG_V16, "v16" },
+	{ SYSZ_REG_V17, "v17" },
+	{ SYSZ_REG_V18, "v18" },
+	{ SYSZ_REG_V19, "v19" },
+	{ SYSZ_REG_V20, "v20" },
+	{ SYSZ_REG_V21, "v21" },
+	{ SYSZ_REG_V22, "v22" },
+	{ SYSZ_REG_V23, "v23" },
+	{ SYSZ_REG_V24, "v24" },
+	{ SYSZ_REG_V25, "v25" },
+	{ SYSZ_REG_V26, "v26" },
+	{ SYSZ_REG_V27, "v27" },
+	{ SYSZ_REG_V28, "v28" },
+	{ SYSZ_REG_V29, "v29" },
+	{ SYSZ_REG_V30, "v30" },
+	{ SYSZ_REG_V31, "v31" },
+	{ SYSZ_REG_F16, "f16" },
+	{ SYSZ_REG_F17, "f17" },
+	{ SYSZ_REG_F18, "f18" },
+	{ SYSZ_REG_F19, "f19" },
+	{ SYSZ_REG_F20, "f20" },
+	{ SYSZ_REG_F21, "f21" },
+	{ SYSZ_REG_F22, "f22" },
+	{ SYSZ_REG_F23, "f23" },
+	{ SYSZ_REG_F24, "f24" },
+	{ SYSZ_REG_F25, "f25" },
+	{ SYSZ_REG_F26, "f26" },
+	{ SYSZ_REG_F27, "f27" },
+	{ SYSZ_REG_F28, "f28" },
+	{ SYSZ_REG_F29, "f29" },
+	{ SYSZ_REG_F30, "f30" },
+	{ SYSZ_REG_F31, "f31" },
+	{ SYSZ_REG_F0Q, "f0q" },
+	{ SYSZ_REG_F4Q, "f4q" },
+};
+#endif
+
+const char *SystemZ_reg_name(csh handle, unsigned int reg)
+{
+#ifndef CAPSTONE_DIET
+	if (reg >= ARR_SIZE(reg_name_maps))
+		return NULL;
+
+	return reg_name_maps[reg].name;
+#else
+	return NULL;
+#endif
+}
+
+static const insn_map insns[] = {
+	// dummy item
+	{
+		0, 0,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+	},
+
+#include "SystemZMappingInsn.inc"
+};
+
+// given internal insn id, return public instruction info
+void SystemZ_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
+{
+	unsigned short i;
+
+	i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache);
+	if (i != 0) {
+		insn->id = insns[i].mapid;
+
+		if (h->detail_opt) {
+#ifndef CAPSTONE_DIET
+			memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use));
+			insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use);
+
+			memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod));
+			insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod);
+
+			memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups));
+			insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups);
+
+			if (insns[i].branch || insns[i].indirect_branch) {
+				// this insn also belongs to JUMP group. add JUMP group
+				insn->detail->groups[insn->detail->groups_count] = SYSZ_GRP_JUMP;
+				insn->detail->groups_count++;
+			}
+#endif
+		}
+	}
+}
+
+#ifndef CAPSTONE_DIET
+static const name_map insn_name_maps[] = {
+	{ SYSZ_INS_INVALID, NULL },
+
+#include "SystemZGenInsnNameMaps.inc"
+};
+
+// special alias insn
+static const name_map alias_insn_names[] = {
+	{ 0, NULL }
+};
+#endif
+
+const char *SystemZ_insn_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	unsigned int i;
+
+	if (id >= SYSZ_INS_ENDING)
+		return NULL;
+
+	// handle special alias first
+	for (i = 0; i < ARR_SIZE(alias_insn_names); i++) {
+		if (alias_insn_names[i].id == id)
+			return alias_insn_names[i].name;
+	}
+
+	return insn_name_maps[id].name;
+#else
+	return NULL;
+#endif
+}
+
+#ifndef CAPSTONE_DIET
+static const name_map group_name_maps[] = {
+	// generic groups
+	{ SYSZ_GRP_INVALID, NULL },
+	{ SYSZ_GRP_JUMP, "jump" },
+
+	// architecture-specific groups
+	{ SYSZ_GRP_DFPPACKEDCONVERSION, "dfppackedconversion" },
+	{ SYSZ_GRP_DFPZONEDCONVERSION, "dfpzonedconversion" },
+	{ SYSZ_GRP_DISTINCTOPS, "distinctops" },
+	{ SYSZ_GRP_ENHANCEDDAT2, "enhanceddat2" },
+	{ SYSZ_GRP_EXECUTIONHINT, "executionhint" },
+	{ SYSZ_GRP_FPEXTENSION, "fpextension" },
+	{ SYSZ_GRP_GUARDEDSTORAGE, "guardedstorage" },
+	{ SYSZ_GRP_HIGHWORD, "highword" },
+	{ SYSZ_GRP_INSERTREFERENCEBITSMULTIPLE, "insertreferencebitsmultiple" },
+	{ SYSZ_GRP_INTERLOCKEDACCESS1, "interlockedaccess1" },
+	{ SYSZ_GRP_LOADANDTRAP, "loadandtrap" },
+	{ SYSZ_GRP_LOADANDZERORIGHTMOSTBYTE, "loadandzerorightmostbyte" },
+	{ SYSZ_GRP_LOADSTOREONCOND, "loadstoreoncond" },
+	{ SYSZ_GRP_LOADSTOREONCOND2, "loadstoreoncond2" },
+	{ SYSZ_GRP_MESSAGESECURITYASSIST3, "messagesecurityassist3" },
+	{ SYSZ_GRP_MESSAGESECURITYASSIST4, "messagesecurityassist4" },
+	{ SYSZ_GRP_MESSAGESECURITYASSIST5, "messagesecurityassist5" },
+	{ SYSZ_GRP_MESSAGESECURITYASSIST7, "messagesecurityassist7" },
+	{ SYSZ_GRP_MESSAGESECURITYASSIST8, "messagesecurityassist8" },
+	{ SYSZ_GRP_MISCELLANEOUSEXTENSIONS, "miscellaneousextensions" },
+	{ SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, "miscellaneousextensions2" },
+	{ SYSZ_GRP_POPULATIONCOUNT, "populationcount" },
+	{ SYSZ_GRP_PROCESSORASSIST, "processorassist" },
+	{ SYSZ_GRP_RESETREFERENCEBITSMULTIPLE, "resetreferencebitsmultiple" },
+	{ SYSZ_GRP_TRANSACTIONALEXECUTION, "transactionalexecution" },
+	{ SYSZ_GRP_VECTOR, "vector" },
+	{ SYSZ_GRP_VECTORENHANCEMENTS1, "vectorenhancements1" },
+	{ SYSZ_GRP_VECTORPACKEDDECIMAL, "vectorpackeddecimal" },
+};
+#endif
+
+const char *SystemZ_group_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
+#else
+	return NULL;
+#endif
+}
+
+// map internal raw register to 'public' register
+sysz_reg SystemZ_map_register(unsigned int r)
+{
+	static const unsigned int map[] = { 0,
+		/* SystemZ_CC = 1 */ SYSZ_REG_CC,
+		/* SystemZ_A0 = 2 */ SYSZ_REG_A0,
+		/* SystemZ_A1 = 3 */ SYSZ_REG_A1,
+		/* SystemZ_A2 = 4 */ SYSZ_REG_A2,
+		/* SystemZ_A3 = 5 */ SYSZ_REG_A3,
+		/* SystemZ_A4 = 6 */ SYSZ_REG_A4,
+		/* SystemZ_A5 = 7 */ SYSZ_REG_A5,
+		/* SystemZ_A6 = 8 */ SYSZ_REG_A6,
+		/* SystemZ_A7 = 9 */ SYSZ_REG_A7,
+		/* SystemZ_A8 = 10 */ SYSZ_REG_A8,
+		/* SystemZ_A9 = 11 */ SYSZ_REG_A9,
+		/* SystemZ_A10 = 12 */ SYSZ_REG_A10,
+		/* SystemZ_A11 = 13 */ SYSZ_REG_A11,
+		/* SystemZ_A12 = 14 */ SYSZ_REG_A12,
+		/* SystemZ_A13 = 15 */ SYSZ_REG_A13,
+		/* SystemZ_A14 = 16 */ SYSZ_REG_A14,
+		/* SystemZ_A15 = 17 */ SYSZ_REG_A15,
+		/* SystemZ_C0 = 18 */ SYSZ_REG_C0,
+		/* SystemZ_C1 = 19 */ SYSZ_REG_C1,
+		/* SystemZ_C2 = 20 */ SYSZ_REG_C2,
+		/* SystemZ_C3 = 21 */ SYSZ_REG_C3,
+		/* SystemZ_C4 = 22 */ SYSZ_REG_C4,
+		/* SystemZ_C5 = 23 */ SYSZ_REG_C5,
+		/* SystemZ_C6 = 24 */ SYSZ_REG_C6,
+		/* SystemZ_C7 = 25 */ SYSZ_REG_C7,
+		/* SystemZ_C8 = 26 */ SYSZ_REG_C8,
+		/* SystemZ_C9 = 27 */ SYSZ_REG_C9,
+		/* SystemZ_C10 = 28 */ SYSZ_REG_C10,
+		/* SystemZ_C11 = 29 */ SYSZ_REG_C11,
+		/* SystemZ_C12 = 30 */ SYSZ_REG_C12,
+		/* SystemZ_C13 = 31 */ SYSZ_REG_C13,
+		/* SystemZ_C14 = 32 */ SYSZ_REG_C14,
+		/* SystemZ_C15 = 33 */ SYSZ_REG_C15,
+		/* SystemZ_V0 = 34 */ SYSZ_REG_V0,
+		/* SystemZ_V1 = 35 */ SYSZ_REG_V1,
+		/* SystemZ_V2 = 36 */ SYSZ_REG_V2,
+		/* SystemZ_V3 = 37 */ SYSZ_REG_V3,
+		/* SystemZ_V4 = 38 */ SYSZ_REG_V4,
+		/* SystemZ_V5 = 39 */ SYSZ_REG_V5,
+		/* SystemZ_V6 = 40 */ SYSZ_REG_V6,
+		/* SystemZ_V7 = 41 */ SYSZ_REG_V7,
+		/* SystemZ_V8 = 42 */ SYSZ_REG_V8,
+		/* SystemZ_V9 = 43 */ SYSZ_REG_V9,
+		/* SystemZ_V10 = 44 */ SYSZ_REG_V10,
+		/* SystemZ_V11 = 45 */ SYSZ_REG_V11,
+		/* SystemZ_V12 = 46 */ SYSZ_REG_V12,
+		/* SystemZ_V13 = 47 */ SYSZ_REG_V13,
+		/* SystemZ_V14 = 48 */ SYSZ_REG_V14,
+		/* SystemZ_V15 = 49 */ SYSZ_REG_V15,
+		/* SystemZ_V16 = 50 */ SYSZ_REG_V16,
+		/* SystemZ_V17 = 51 */ SYSZ_REG_V17,
+		/* SystemZ_V18 = 52 */ SYSZ_REG_V18,
+		/* SystemZ_V19 = 53 */ SYSZ_REG_V19,
+		/* SystemZ_V20 = 54 */ SYSZ_REG_V20,
+		/* SystemZ_V21 = 55 */ SYSZ_REG_V21,
+		/* SystemZ_V22 = 56 */ SYSZ_REG_V22,
+		/* SystemZ_V23 = 57 */ SYSZ_REG_V23,
+		/* SystemZ_V24 = 58 */ SYSZ_REG_V24,
+		/* SystemZ_V25 = 59 */ SYSZ_REG_V25,
+		/* SystemZ_V26 = 60 */ SYSZ_REG_V26,
+		/* SystemZ_V27 = 61 */ SYSZ_REG_V27,
+		/* SystemZ_V28 = 62 */ SYSZ_REG_V28,
+		/* SystemZ_V29 = 63 */ SYSZ_REG_V29,
+		/* SystemZ_V30 = 64 */ SYSZ_REG_V30,
+		/* SystemZ_V31 = 65 */ SYSZ_REG_V31,
+		/* SystemZ_F0D = 66 */ SYSZ_REG_F0,
+		/* SystemZ_F1D = 67 */ SYSZ_REG_F1,
+		/* SystemZ_F2D = 68 */ SYSZ_REG_F2,
+		/* SystemZ_F3D = 69 */ SYSZ_REG_F3,
+		/* SystemZ_F4D = 70 */ SYSZ_REG_F4,
+		/* SystemZ_F5D = 71 */ SYSZ_REG_F5,
+		/* SystemZ_F6D = 72 */ SYSZ_REG_F6,
+		/* SystemZ_F7D = 73 */ SYSZ_REG_F7,
+		/* SystemZ_F8D = 74 */ SYSZ_REG_F8,
+		/* SystemZ_F9D = 75 */ SYSZ_REG_F9,
+		/* SystemZ_F10D = 76 */ SYSZ_REG_F10,
+		/* SystemZ_F11D = 77 */ SYSZ_REG_F11,
+		/* SystemZ_F12D = 78 */ SYSZ_REG_F12,
+		/* SystemZ_F13D = 79 */ SYSZ_REG_F13,
+		/* SystemZ_F14D = 80 */ SYSZ_REG_F14,
+		/* SystemZ_F15D = 81 */ SYSZ_REG_F15,
+		/* SystemZ_F16D = 82 */ SYSZ_REG_F16,
+		/* SystemZ_F17D = 83 */ SYSZ_REG_F17,
+		/* SystemZ_F18D = 84 */ SYSZ_REG_F18,
+		/* SystemZ_F19D = 85 */ SYSZ_REG_F19,
+		/* SystemZ_F20D = 86 */ SYSZ_REG_F20,
+		/* SystemZ_F21D = 87 */ SYSZ_REG_F21,
+		/* SystemZ_F22D = 88 */ SYSZ_REG_F22,
+		/* SystemZ_F23D = 89 */ SYSZ_REG_F23,
+		/* SystemZ_F24D = 90 */ SYSZ_REG_F24,
+		/* SystemZ_F25D = 91 */ SYSZ_REG_F25,
+		/* SystemZ_F26D = 92 */ SYSZ_REG_F26,
+		/* SystemZ_F27D = 93 */ SYSZ_REG_F27,
+		/* SystemZ_F28D = 94 */ SYSZ_REG_F28,
+		/* SystemZ_F29D = 95 */ SYSZ_REG_F29,
+		/* SystemZ_F30D = 96 */ SYSZ_REG_F30,
+		/* SystemZ_F31D = 97 */ SYSZ_REG_F31,
+		/* SystemZ_F0Q = 98 */ SYSZ_REG_F0,
+		/* SystemZ_F1Q = 99 */ SYSZ_REG_F1,
+		/* SystemZ_F4Q = 100 */ SYSZ_REG_F4,
+		/* SystemZ_F5Q = 101 */ SYSZ_REG_F5,
+		/* SystemZ_F8Q = 102 */ SYSZ_REG_F8,
+		/* SystemZ_F9Q = 103 */ SYSZ_REG_F9,
+		/* SystemZ_F12Q = 104 */ SYSZ_REG_F12,
+		/* SystemZ_F13Q = 105 */ SYSZ_REG_F13,
+		/* SystemZ_F0S = 106 */ SYSZ_REG_F0,
+		/* SystemZ_F1S = 107 */ SYSZ_REG_F1,
+		/* SystemZ_F2S = 108 */ SYSZ_REG_F2,
+		/* SystemZ_F3S = 109 */ SYSZ_REG_F3,
+		/* SystemZ_F4S = 110 */ SYSZ_REG_F4,
+		/* SystemZ_F5S = 111 */ SYSZ_REG_F5,
+		/* SystemZ_F6S = 112 */ SYSZ_REG_F6,
+		/* SystemZ_F7S = 113 */ SYSZ_REG_F7,
+		/* SystemZ_F8S = 114 */ SYSZ_REG_F8,
+		/* SystemZ_F9S = 115 */ SYSZ_REG_F9,
+		/* SystemZ_F10S = 116 */ SYSZ_REG_F10,
+		/* SystemZ_F11S = 117 */ SYSZ_REG_F11,
+		/* SystemZ_F12S = 118 */ SYSZ_REG_F12,
+		/* SystemZ_F13S = 119 */ SYSZ_REG_F13,
+		/* SystemZ_F14S = 120 */ SYSZ_REG_F14,
+		/* SystemZ_F15S = 121 */ SYSZ_REG_F15,
+		/* SystemZ_F16S = 122 */ SYSZ_REG_F16,
+		/* SystemZ_F17S = 123 */ SYSZ_REG_F17,
+		/* SystemZ_F18S = 124 */ SYSZ_REG_F18,
+		/* SystemZ_F19S = 125 */ SYSZ_REG_F19,
+		/* SystemZ_F20S = 126 */ SYSZ_REG_F20,
+		/* SystemZ_F21S = 127 */ SYSZ_REG_F21,
+		/* SystemZ_F22S = 128 */ SYSZ_REG_F22,
+		/* SystemZ_F23S = 129 */ SYSZ_REG_F23,
+		/* SystemZ_F24S = 130 */ SYSZ_REG_F24,
+		/* SystemZ_F25S = 131 */ SYSZ_REG_F25,
+		/* SystemZ_F26S = 132 */ SYSZ_REG_F26,
+		/* SystemZ_F27S = 133 */ SYSZ_REG_F27,
+		/* SystemZ_F28S = 134 */ SYSZ_REG_F28,
+		/* SystemZ_F29S = 135 */ SYSZ_REG_F29,
+		/* SystemZ_F30S = 136 */ SYSZ_REG_F30,
+		/* SystemZ_F31S = 137 */ SYSZ_REG_F31,
+		/* SystemZ_R0D = 138 */ SYSZ_REG_0,
+		/* SystemZ_R1D = 139 */ SYSZ_REG_1,
+		/* SystemZ_R2D = 140 */ SYSZ_REG_2,
+		/* SystemZ_R3D = 141 */ SYSZ_REG_3,
+		/* SystemZ_R4D = 142 */ SYSZ_REG_4,
+		/* SystemZ_R5D = 143 */ SYSZ_REG_5,
+		/* SystemZ_R6D = 144 */ SYSZ_REG_6,
+		/* SystemZ_R7D = 145 */ SYSZ_REG_7,
+		/* SystemZ_R8D = 146 */ SYSZ_REG_8,
+		/* SystemZ_R9D = 147 */ SYSZ_REG_9,
+		/* SystemZ_R10D = 148 */ SYSZ_REG_10,
+		/* SystemZ_R11D = 149 */ SYSZ_REG_11,
+		/* SystemZ_R12D = 150 */ SYSZ_REG_12,
+		/* SystemZ_R13D = 151 */ SYSZ_REG_13,
+		/* SystemZ_R14D = 152 */ SYSZ_REG_14,
+		/* SystemZ_R15D = 153 */ SYSZ_REG_15,
+		/* SystemZ_R0H = 154 */ SYSZ_REG_0,
+		/* SystemZ_R1H = 155 */ SYSZ_REG_1,
+		/* SystemZ_R2H = 156 */ SYSZ_REG_2,
+		/* SystemZ_R3H = 157 */ SYSZ_REG_3,
+		/* SystemZ_R4H = 158 */ SYSZ_REG_4,
+		/* SystemZ_R5H = 159 */ SYSZ_REG_5,
+		/* SystemZ_R6H = 160 */ SYSZ_REG_6,
+		/* SystemZ_R7H = 161 */ SYSZ_REG_7,
+		/* SystemZ_R8H = 162 */ SYSZ_REG_8,
+		/* SystemZ_R9H = 163 */ SYSZ_REG_9,
+		/* SystemZ_R10H = 164 */ SYSZ_REG_10,
+		/* SystemZ_R11H = 165 */ SYSZ_REG_11,
+		/* SystemZ_R12H = 166 */ SYSZ_REG_12,
+		/* SystemZ_R13H = 167 */ SYSZ_REG_13,
+		/* SystemZ_R14H = 168 */ SYSZ_REG_14,
+		/* SystemZ_R15H = 169 */ SYSZ_REG_15,
+		/* SystemZ_R0L = 170 */ SYSZ_REG_0,
+		/* SystemZ_R1L = 171 */ SYSZ_REG_1,
+		/* SystemZ_R2L = 172 */ SYSZ_REG_2,
+		/* SystemZ_R3L = 173 */ SYSZ_REG_3,
+		/* SystemZ_R4L = 174 */ SYSZ_REG_4,
+		/* SystemZ_R5L = 175 */ SYSZ_REG_5,
+		/* SystemZ_R6L = 176 */ SYSZ_REG_6,
+		/* SystemZ_R7L = 177 */ SYSZ_REG_7,
+		/* SystemZ_R8L = 178 */ SYSZ_REG_8,
+		/* SystemZ_R9L = 179 */ SYSZ_REG_9,
+		/* SystemZ_R10L = 180 */ SYSZ_REG_10,
+		/* SystemZ_R11L = 181 */ SYSZ_REG_11,
+		/* SystemZ_R12L = 182 */ SYSZ_REG_12,
+		/* SystemZ_R13L = 183 */ SYSZ_REG_13,
+		/* SystemZ_R14L = 184 */ SYSZ_REG_14,
+		/* SystemZ_R15L = 185 */ SYSZ_REG_15,
+		/* SystemZ_R0Q = 186 */ SYSZ_REG_0,
+		/* SystemZ_R2Q = 187 */ SYSZ_REG_2,
+		/* SystemZ_R4Q = 188 */ SYSZ_REG_4,
+		/* SystemZ_R6Q = 189 */ SYSZ_REG_6,
+		/* SystemZ_R8Q = 190 */ SYSZ_REG_8,
+		/* SystemZ_R10Q = 191 */ SYSZ_REG_10,
+		/* SystemZ_R12Q = 192 */ SYSZ_REG_12,
+		/* SystemZ_R14Q = 193 */ SYSZ_REG_14,
+	};
+
+	if (r < ARR_SIZE(map))
+		return map[r];
+
+	// cannot find this register
+	return 0;
+}
+
+#endif
--- a/thirdparty/capstone/arch/SystemZ/SystemZMapping.h
+++ b/thirdparty/capstone/arch/SystemZ/SystemZMapping.h
@@ -0,0 +1,23 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifndef CS_SYSZ_MAP_H
+#define CS_SYSZ_MAP_H
+
+#include "capstone/capstone.h"
+
+// return name of register in friendly string
+const char *SystemZ_reg_name(csh handle, unsigned int reg);
+
+// given internal insn id, return public instruction info
+void SystemZ_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
+
+const char *SystemZ_insn_name(csh handle, unsigned int id);
+
+const char *SystemZ_group_name(csh handle, unsigned int id);
+
+// map internal raw register to 'public' register
+sysz_reg SystemZ_map_register(unsigned int r);
+
+#endif
+
--- a/thirdparty/capstone/arch/SystemZ/SystemZMappingInsn.inc
+++ b/thirdparty/capstone/arch/SystemZ/SystemZMappingInsn.inc
--- a/thirdparty/capstone/arch/SystemZ/SystemZModule.c
+++ b/thirdparty/capstone/arch/SystemZ/SystemZModule.c
@@ -0,0 +1,44 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifdef CAPSTONE_HAS_SYSZ
+
+#include "../../utils.h"
+#include "../../MCRegisterInfo.h"
+#include "SystemZDisassembler.h"
+#include "SystemZInstPrinter.h"
+#include "SystemZMapping.h"
+#include "SystemZModule.h"
+
+cs_err SystemZ_global_init(cs_struct *ud)
+{
+	MCRegisterInfo *mri;
+	mri = cs_mem_malloc(sizeof(*mri));
+
+	SystemZ_init(mri);
+	ud->printer = SystemZ_printInst;
+	ud->printer_info = mri;
+	ud->getinsn_info = mri;
+	ud->disasm = SystemZ_getInstruction;
+	ud->post_printer = SystemZ_post_printer;
+
+	ud->reg_name = SystemZ_reg_name;
+	ud->insn_id = SystemZ_get_insn_id;
+	ud->insn_name = SystemZ_insn_name;
+	ud->group_name = SystemZ_group_name;
+
+	return CS_ERR_OK;
+}
+
+cs_err SystemZ_option(cs_struct *handle, cs_opt_type type, size_t value)
+{
+	if (type == CS_OPT_SYNTAX)
+		handle->syntax = (int) value;
+
+	// Do not set mode because only CS_MODE_BIG_ENDIAN is valid; we cannot
+	// test for CS_MODE_LITTLE_ENDIAN because it is 0
+
+	return CS_ERR_OK;
+}
+
+#endif
--- a/thirdparty/capstone/arch/SystemZ/SystemZModule.h
+++ b/thirdparty/capstone/arch/SystemZ/SystemZModule.h
@@ -0,0 +1,12 @@
+/* Capstone Disassembly Engine */
+/* By Travis Finkenauer <tmfinken@gmail.com>, 2018 */
+
+#ifndef CS_SYSTEMZ_MODULE_H
+#define CS_SYSTEMZ_MODULE_H
+
+#include "../../utils.h"
+
+cs_err SystemZ_global_init(cs_struct *ud);
+cs_err SystemZ_option(cs_struct *handle, cs_opt_type type, size_t value);
+
+#endif