mirror of
https://github.com/hedge-dev/XenonRecomp.git
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Initial Commit
This commit is contained in:
Sajid
572
thirdparty/capstone/arch/TMS320C64x/TMS320C64xInstPrinter.c
vendored
Normal file
572
thirdparty/capstone/arch/TMS320C64x/TMS320C64xInstPrinter.c
vendored
Normal file
@@ -0,0 +1,572 @@
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/* Capstone Disassembly Engine */
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/* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */
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#ifdef CAPSTONE_HAS_TMS320C64X
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#ifdef _MSC_VER
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// Disable security warnings for strcpy
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#ifndef _CRT_SECURE_NO_WARNINGS
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#define _CRT_SECURE_NO_WARNINGS
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#endif
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// Banned API Usage : strcpy is a Banned API as listed in dontuse.h for
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// security purposes.
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#pragma warning(disable:28719)
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#endif
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#include <ctype.h>
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#include <string.h>
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#include "TMS320C64xInstPrinter.h"
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#include "../../MCInst.h"
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#include "../../utils.h"
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#include "../../SStream.h"
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#include "../../MCRegisterInfo.h"
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#include "../../MathExtras.h"
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#include "TMS320C64xMapping.h"
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#include "capstone/tms320c64x.h"
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static const char *getRegisterName(unsigned RegNo);
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static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
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static void printMemOperand(MCInst *MI, unsigned OpNo, SStream *O);
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static void printMemOperand2(MCInst *MI, unsigned OpNo, SStream *O);
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static void printRegPair(MCInst *MI, unsigned OpNo, SStream *O);
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void TMS320C64x_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci)
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{
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SStream ss;
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char *p, *p2, tmp[8];
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unsigned int unit = 0;
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int i;
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cs_tms320c64x *tms320c64x;
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if (mci->csh->detail_opt) {
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tms320c64x = &mci->flat_insn->detail->tms320c64x;
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for (i = 0; i < insn->detail->groups_count; i++) {
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switch(insn->detail->groups[i]) {
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case TMS320C64X_GRP_FUNIT_D:
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unit = TMS320C64X_FUNIT_D;
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break;
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case TMS320C64X_GRP_FUNIT_L:
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unit = TMS320C64X_FUNIT_L;
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break;
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case TMS320C64X_GRP_FUNIT_M:
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unit = TMS320C64X_FUNIT_M;
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break;
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case TMS320C64X_GRP_FUNIT_S:
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unit = TMS320C64X_FUNIT_S;
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break;
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case TMS320C64X_GRP_FUNIT_NO:
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unit = TMS320C64X_FUNIT_NO;
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break;
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}
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if (unit != 0)
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break;
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}
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tms320c64x->funit.unit = unit;
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SStream_Init(&ss);
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if (tms320c64x->condition.reg != TMS320C64X_REG_INVALID)
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SStream_concat(&ss, "[%c%s]|", (tms320c64x->condition.zero == 1) ? '!' : '|', cs_reg_name(ud, tms320c64x->condition.reg));
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p = strchr(insn_asm, '\t');
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if (p != NULL)
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*p++ = '\0';
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SStream_concat0(&ss, insn_asm);
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if ((p != NULL) && (((p2 = strchr(p, '[')) != NULL) || ((p2 = strchr(p, '(')) != NULL))) {
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while ((p2 > p) && ((*p2 != 'a') && (*p2 != 'b')))
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p2--;
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if (p2 == p) {
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strcpy(insn_asm, "Invalid!");
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return;
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}
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if (*p2 == 'a')
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strcpy(tmp, "1T");
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else
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strcpy(tmp, "2T");
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} else {
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tmp[0] = '\0';
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}
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switch(tms320c64x->funit.unit) {
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case TMS320C64X_FUNIT_D:
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SStream_concat(&ss, ".D%s%u", tmp, tms320c64x->funit.side);
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break;
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case TMS320C64X_FUNIT_L:
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SStream_concat(&ss, ".L%s%u", tmp, tms320c64x->funit.side);
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break;
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case TMS320C64X_FUNIT_M:
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SStream_concat(&ss, ".M%s%u", tmp, tms320c64x->funit.side);
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break;
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case TMS320C64X_FUNIT_S:
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SStream_concat(&ss, ".S%s%u", tmp, tms320c64x->funit.side);
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break;
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}
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if (tms320c64x->funit.crosspath > 0)
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SStream_concat0(&ss, "X");
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if (p != NULL)
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SStream_concat(&ss, "\t%s", p);
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if (tms320c64x->parallel != 0)
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SStream_concat0(&ss, "\t||");
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/* insn_asm is a buffer from an SStream, so there should be enough space */
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strcpy(insn_asm, ss.buffer);
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}
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}
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#define PRINT_ALIAS_INSTR
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#include "TMS320C64xGenAsmWriter.inc"
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#define GET_INSTRINFO_ENUM
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#include "TMS320C64xGenInstrInfo.inc"
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static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
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{
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MCOperand *Op = MCInst_getOperand(MI, OpNo);
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unsigned reg;
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if (MCOperand_isReg(Op)) {
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reg = MCOperand_getReg(Op);
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if ((MCInst_getOpcode(MI) == TMS320C64x_MVC_s1_rr) && (OpNo == 1)) {
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switch(reg) {
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case TMS320C64X_REG_EFR:
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SStream_concat0(O, "EFR");
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break;
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case TMS320C64X_REG_IFR:
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SStream_concat0(O, "IFR");
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break;
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default:
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SStream_concat0(O, getRegisterName(reg));
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break;
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}
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} else {
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SStream_concat0(O, getRegisterName(reg));
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}
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if (MI->csh->detail_opt) {
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MI->flat_insn->detail->tms320c64x.operands[MI->flat_insn->detail->tms320c64x.op_count].type = TMS320C64X_OP_REG;
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MI->flat_insn->detail->tms320c64x.operands[MI->flat_insn->detail->tms320c64x.op_count].reg = reg;
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MI->flat_insn->detail->tms320c64x.op_count++;
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}
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} else if (MCOperand_isImm(Op)) {
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int64_t Imm = MCOperand_getImm(Op);
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if (Imm >= 0) {
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if (Imm > HEX_THRESHOLD)
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SStream_concat(O, "0x%"PRIx64, Imm);
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else
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SStream_concat(O, "%"PRIu64, Imm);
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} else {
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if (Imm < -HEX_THRESHOLD)
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SStream_concat(O, "-0x%"PRIx64, -Imm);
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else
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SStream_concat(O, "-%"PRIu64, -Imm);
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}
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if (MI->csh->detail_opt) {
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MI->flat_insn->detail->tms320c64x.operands[MI->flat_insn->detail->tms320c64x.op_count].type = TMS320C64X_OP_IMM;
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MI->flat_insn->detail->tms320c64x.operands[MI->flat_insn->detail->tms320c64x.op_count].imm = Imm;
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MI->flat_insn->detail->tms320c64x.op_count++;
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}
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}
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}
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static void printMemOperand(MCInst *MI, unsigned OpNo, SStream *O)
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{
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MCOperand *Op = MCInst_getOperand(MI, OpNo);
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int64_t Val = MCOperand_getImm(Op);
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unsigned scaled, base, offset, mode, unit;
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cs_tms320c64x *tms320c64x;
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char st, nd;
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scaled = (Val >> 19) & 1;
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base = (Val >> 12) & 0x7f;
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offset = (Val >> 5) & 0x7f;
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mode = (Val >> 1) & 0xf;
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unit = Val & 1;
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if (scaled) {
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st = '[';
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nd = ']';
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} else {
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st = '(';
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nd = ')';
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}
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switch(mode) {
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case 0:
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SStream_concat(O, "*-%s%c%u%c", getRegisterName(base), st, offset, nd);
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break;
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case 1:
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SStream_concat(O, "*+%s%c%u%c", getRegisterName(base), st, offset, nd);
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break;
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case 4:
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SStream_concat(O, "*-%s%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
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break;
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case 5:
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SStream_concat(O, "*+%s%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
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break;
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case 8:
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SStream_concat(O, "*--%s%c%u%c", getRegisterName(base), st, offset, nd);
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break;
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case 9:
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SStream_concat(O, "*++%s%c%u%c", getRegisterName(base), st, offset, nd);
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break;
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case 10:
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SStream_concat(O, "*%s--%c%u%c", getRegisterName(base), st, offset, nd);
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break;
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case 11:
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SStream_concat(O, "*%s++%c%u%c", getRegisterName(base), st, offset, nd);
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break;
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case 12:
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SStream_concat(O, "*--%s%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
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break;
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case 13:
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SStream_concat(O, "*++%s%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
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break;
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case 14:
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SStream_concat(O, "*%s--%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
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break;
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case 15:
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SStream_concat(O, "*%s++%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
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break;
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}
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if (MI->csh->detail_opt) {
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tms320c64x = &MI->flat_insn->detail->tms320c64x;
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tms320c64x->operands[tms320c64x->op_count].type = TMS320C64X_OP_MEM;
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tms320c64x->operands[tms320c64x->op_count].mem.base = base;
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tms320c64x->operands[tms320c64x->op_count].mem.disp = offset;
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tms320c64x->operands[tms320c64x->op_count].mem.unit = unit + 1;
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tms320c64x->operands[tms320c64x->op_count].mem.scaled = scaled;
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switch(mode) {
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case 0:
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tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
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tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
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tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO;
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break;
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case 1:
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tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
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tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
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tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO;
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break;
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case 4:
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tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
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tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
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tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO;
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break;
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case 5:
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tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
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tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
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tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO;
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break;
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case 8:
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tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
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tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
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tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_PRE;
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break;
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case 9:
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tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
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tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
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tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_PRE;
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break;
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case 10:
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tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
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tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
|
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tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_POST;
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break;
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case 11:
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||||
tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
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tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
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tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_POST;
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break;
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case 12:
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tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
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||||
tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
|
||||
tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_PRE;
|
||||
break;
|
||||
case 13:
|
||||
tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
|
||||
tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
|
||||
tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_PRE;
|
||||
break;
|
||||
case 14:
|
||||
tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
|
||||
tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
|
||||
tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_POST;
|
||||
break;
|
||||
case 15:
|
||||
tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
|
||||
tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
|
||||
tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_POST;
|
||||
break;
|
||||
}
|
||||
tms320c64x->op_count++;
|
||||
}
|
||||
}
|
||||
|
||||
static void printMemOperand2(MCInst *MI, unsigned OpNo, SStream *O)
|
||||
{
|
||||
MCOperand *Op = MCInst_getOperand(MI, OpNo);
|
||||
int64_t Val = MCOperand_getImm(Op);
|
||||
uint16_t offset;
|
||||
unsigned basereg;
|
||||
cs_tms320c64x *tms320c64x;
|
||||
|
||||
basereg = Val & 0x7f;
|
||||
offset = (Val >> 7) & 0x7fff;
|
||||
SStream_concat(O, "*+%s[0x%x]", getRegisterName(basereg), offset);
|
||||
|
||||
if (MI->csh->detail_opt) {
|
||||
tms320c64x = &MI->flat_insn->detail->tms320c64x;
|
||||
|
||||
tms320c64x->operands[tms320c64x->op_count].type = TMS320C64X_OP_MEM;
|
||||
tms320c64x->operands[tms320c64x->op_count].mem.base = basereg;
|
||||
tms320c64x->operands[tms320c64x->op_count].mem.unit = 2;
|
||||
tms320c64x->operands[tms320c64x->op_count].mem.disp = offset;
|
||||
tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
|
||||
tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
|
||||
tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO;
|
||||
tms320c64x->op_count++;
|
||||
}
|
||||
}
|
||||
|
||||
static void printRegPair(MCInst *MI, unsigned OpNo, SStream *O)
|
||||
{
|
||||
MCOperand *Op = MCInst_getOperand(MI, OpNo);
|
||||
unsigned reg = MCOperand_getReg(Op);
|
||||
cs_tms320c64x *tms320c64x;
|
||||
|
||||
SStream_concat(O, "%s:%s", getRegisterName(reg + 1), getRegisterName(reg));
|
||||
|
||||
if (MI->csh->detail_opt) {
|
||||
tms320c64x = &MI->flat_insn->detail->tms320c64x;
|
||||
|
||||
tms320c64x->operands[tms320c64x->op_count].type = TMS320C64X_OP_REGPAIR;
|
||||
tms320c64x->operands[tms320c64x->op_count].reg = reg;
|
||||
tms320c64x->op_count++;
|
||||
}
|
||||
}
|
||||
|
||||
static bool printAliasInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
|
||||
{
|
||||
unsigned opcode = MCInst_getOpcode(MI);
|
||||
MCOperand *op;
|
||||
|
||||
switch(opcode) {
|
||||
/* ADD.Dx -i, x, y -> SUB.Dx x, i, y */
|
||||
case TMS320C64x_ADD_d2_rir:
|
||||
/* ADD.L -i, x, y -> SUB.L x, i, y */
|
||||
case TMS320C64x_ADD_l1_irr:
|
||||
case TMS320C64x_ADD_l1_ipp:
|
||||
/* ADD.S -i, x, y -> SUB.S x, i, y */
|
||||
case TMS320C64x_ADD_s1_irr:
|
||||
if ((MCInst_getNumOperands(MI) == 3) &&
|
||||
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
||||
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
||||
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
||||
(MCOperand_getImm(MCInst_getOperand(MI, 2)) < 0)) {
|
||||
|
||||
MCInst_setOpcodePub(MI, TMS320C64X_INS_SUB);
|
||||
op = MCInst_getOperand(MI, 2);
|
||||
MCOperand_setImm(op, -MCOperand_getImm(op));
|
||||
|
||||
SStream_concat0(O, "SUB\t");
|
||||
printOperand(MI, 1, O);
|
||||
SStream_concat0(O, ", ");
|
||||
printOperand(MI, 2, O);
|
||||
SStream_concat0(O, ", ");
|
||||
printOperand(MI, 0, O);
|
||||
|
||||
return true;
|
||||
}
|
||||
break;
|
||||
}
|
||||
switch(opcode) {
|
||||
/* ADD.D 0, x, y -> MV.D x, y */
|
||||
case TMS320C64x_ADD_d1_rir:
|
||||
/* OR.D x, 0, y -> MV.D x, y */
|
||||
case TMS320C64x_OR_d2_rir:
|
||||
/* ADD.L 0, x, y -> MV.L x, y */
|
||||
case TMS320C64x_ADD_l1_irr:
|
||||
case TMS320C64x_ADD_l1_ipp:
|
||||
/* OR.L 0, x, y -> MV.L x, y */
|
||||
case TMS320C64x_OR_l1_irr:
|
||||
/* ADD.S 0, x, y -> MV.S x, y */
|
||||
case TMS320C64x_ADD_s1_irr:
|
||||
/* OR.S 0, x, y -> MV.S x, y */
|
||||
case TMS320C64x_OR_s1_irr:
|
||||
if ((MCInst_getNumOperands(MI) == 3) &&
|
||||
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
||||
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
||||
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
||||
(MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) {
|
||||
|
||||
MCInst_setOpcodePub(MI, TMS320C64X_INS_MV);
|
||||
MI->size--;
|
||||
|
||||
SStream_concat0(O, "MV\t");
|
||||
printOperand(MI, 1, O);
|
||||
SStream_concat0(O, ", ");
|
||||
printOperand(MI, 0, O);
|
||||
|
||||
return true;
|
||||
}
|
||||
break;
|
||||
}
|
||||
switch(opcode) {
|
||||
/* XOR.D -1, x, y -> NOT.D x, y */
|
||||
case TMS320C64x_XOR_d2_rir:
|
||||
/* XOR.L -1, x, y -> NOT.L x, y */
|
||||
case TMS320C64x_XOR_l1_irr:
|
||||
/* XOR.S -1, x, y -> NOT.S x, y */
|
||||
case TMS320C64x_XOR_s1_irr:
|
||||
if ((MCInst_getNumOperands(MI) == 3) &&
|
||||
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
||||
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
||||
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
||||
(MCOperand_getImm(MCInst_getOperand(MI, 2)) == -1)) {
|
||||
|
||||
MCInst_setOpcodePub(MI, TMS320C64X_INS_NOT);
|
||||
MI->size--;
|
||||
|
||||
SStream_concat0(O, "NOT\t");
|
||||
printOperand(MI, 1, O);
|
||||
SStream_concat0(O, ", ");
|
||||
printOperand(MI, 0, O);
|
||||
|
||||
return true;
|
||||
}
|
||||
break;
|
||||
}
|
||||
switch(opcode) {
|
||||
/* MVK.D 0, x -> ZERO.D x */
|
||||
case TMS320C64x_MVK_d1_rr:
|
||||
/* MVK.L 0, x -> ZERO.L x */
|
||||
case TMS320C64x_MVK_l2_ir:
|
||||
if ((MCInst_getNumOperands(MI) == 2) &&
|
||||
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
||||
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
||||
(MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0)) {
|
||||
|
||||
MCInst_setOpcodePub(MI, TMS320C64X_INS_ZERO);
|
||||
MI->size--;
|
||||
|
||||
SStream_concat0(O, "ZERO\t");
|
||||
printOperand(MI, 0, O);
|
||||
|
||||
return true;
|
||||
}
|
||||
break;
|
||||
}
|
||||
switch(opcode) {
|
||||
/* SUB.L x, x, y -> ZERO.L y */
|
||||
case TMS320C64x_SUB_l1_rrp_x1:
|
||||
/* SUB.S x, x, y -> ZERO.S y */
|
||||
case TMS320C64x_SUB_s1_rrr:
|
||||
if ((MCInst_getNumOperands(MI) == 3) &&
|
||||
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
||||
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
||||
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
||||
(MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
|
||||
|
||||
MCInst_setOpcodePub(MI, TMS320C64X_INS_ZERO);
|
||||
MI->size -= 2;
|
||||
|
||||
SStream_concat0(O, "ZERO\t");
|
||||
printOperand(MI, 0, O);
|
||||
|
||||
return true;
|
||||
}
|
||||
break;
|
||||
}
|
||||
switch(opcode) {
|
||||
/* SUB.L 0, x, y -> NEG.L x, y */
|
||||
case TMS320C64x_SUB_l1_irr:
|
||||
case TMS320C64x_SUB_l1_ipp:
|
||||
/* SUB.S 0, x, y -> NEG.S x, y */
|
||||
case TMS320C64x_SUB_s1_irr:
|
||||
if ((MCInst_getNumOperands(MI) == 3) &&
|
||||
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
||||
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
||||
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
||||
(MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) {
|
||||
|
||||
MCInst_setOpcodePub(MI, TMS320C64X_INS_NEG);
|
||||
MI->size--;
|
||||
|
||||
SStream_concat0(O, "NEG\t");
|
||||
printOperand(MI, 1, O);
|
||||
SStream_concat0(O, ", ");
|
||||
printOperand(MI, 0, O);
|
||||
|
||||
return true;
|
||||
}
|
||||
break;
|
||||
}
|
||||
switch(opcode) {
|
||||
/* PACKLH2.L x, x, y -> SWAP2.L x, y */
|
||||
case TMS320C64x_PACKLH2_l1_rrr_x2:
|
||||
/* PACKLH2.S x, x, y -> SWAP2.S x, y */
|
||||
case TMS320C64x_PACKLH2_s1_rrr:
|
||||
if ((MCInst_getNumOperands(MI) == 3) &&
|
||||
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
||||
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
||||
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
||||
(MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
|
||||
|
||||
MCInst_setOpcodePub(MI, TMS320C64X_INS_SWAP2);
|
||||
MI->size--;
|
||||
|
||||
SStream_concat0(O, "SWAP2\t");
|
||||
printOperand(MI, 1, O);
|
||||
SStream_concat0(O, ", ");
|
||||
printOperand(MI, 0, O);
|
||||
|
||||
return true;
|
||||
}
|
||||
break;
|
||||
}
|
||||
switch(opcode) {
|
||||
/* NOP 16 -> IDLE */
|
||||
/* NOP 1 -> NOP */
|
||||
case TMS320C64x_NOP_n:
|
||||
if ((MCInst_getNumOperands(MI) == 1) &&
|
||||
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
||||
(MCOperand_getReg(MCInst_getOperand(MI, 0)) == 16)) {
|
||||
|
||||
MCInst_setOpcodePub(MI, TMS320C64X_INS_IDLE);
|
||||
MI->size--;
|
||||
|
||||
SStream_concat0(O, "IDLE");
|
||||
|
||||
return true;
|
||||
}
|
||||
if ((MCInst_getNumOperands(MI) == 1) &&
|
||||
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
||||
(MCOperand_getReg(MCInst_getOperand(MI, 0)) == 1)) {
|
||||
|
||||
MI->size--;
|
||||
|
||||
SStream_concat0(O, "NOP");
|
||||
|
||||
return true;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
void TMS320C64x_printInst(MCInst *MI, SStream *O, void *Info)
|
||||
{
|
||||
if (!printAliasInstruction(MI, O, Info))
|
||||
printInstruction(MI, O, Info);
|
||||
}
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user