Initial Commit

2025-07-24 22:13:57 +00:00 · 2024-09-07 18:00:09 +06:00
commit 0f9a53f75a
3352 changed files with 1563708 additions and 0 deletions
--- a/thirdparty/capstone/arch/TriCore/TriCore.td
+++ b/thirdparty/capstone/arch/TriCore/TriCore.td
@@ -0,0 +1,134 @@
+//===-- TriCore.td - Describe the TriCore Target Machine ---*- tablegen -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This is the top level entry point for the TriCore target.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Target-independent interfaces which we are implementing
+//===----------------------------------------------------------------------===//
+
+include "llvm/Target/Target.td"
+
+//===----------------------------------------------------------------------===//
+// Descriptions
+//===----------------------------------------------------------------------===//
+
+// Specify whether target support specific TRICORE ISA variants.
+
+def HasV110Ops   : SubtargetFeature<"v1.1", "HasV110Ops", "true",
+								   "Support TriCore v1.1 instructions",
+								   []>;
+def HasV120Ops   : SubtargetFeature<"v1.2", "HasV120Ops", "true",
+								   "Support TriCore v1.2 instructions",
+								   []>;
+def HasV130Ops   : SubtargetFeature<"v1.3", "HasV130Ops", "true",
+								   "Support TriCore v1.3 instructions",
+								   []>;
+def HasV131Ops   : SubtargetFeature<"v1.3.1", "HasV131Ops", "true",
+								   "Support TriCore v1.3.1 instructions",
+								   []>;
+def HasV160Ops   : SubtargetFeature<"v1.6", "HasV160Ops", "true",
+								   "Support TriCore v1.6 instructions",
+								   []>;
+def HasV161Ops   : SubtargetFeature<"v1.6.1", "HasV161Ops", "true",
+								   "Support TriCore v1.6.1 instructions",
+								   []>;
+def HasV162Ops   : SubtargetFeature<"v1.6.2", "HasV162Ops", "true",
+								   "Support TriCore v1.6.2 instructions",
+								   []>;
+
+def HasV110     : Predicate<"HasV120Ops()">, AssemblerPredicate<(all_of HasV110Ops), "v1.1">;
+def HasV120     : Predicate<"HasV120Ops()">, AssemblerPredicate<(all_of HasV120Ops), "v1.2">;
+def HasV130     : Predicate<"HasV130Ops()">, AssemblerPredicate<(all_of HasV130Ops), "v1.3">;
+def HasV131     : Predicate<"HasV131Ops()">, AssemblerPredicate<(all_of HasV131Ops), "v1.3.1">;
+def HasV160     : Predicate<"HasV160Ops()">, AssemblerPredicate<(all_of HasV160Ops), "v1.6">;
+def HasV161     : Predicate<"HasV161Ops()">, AssemblerPredicate<(all_of HasV161Ops), "v1.6.1">;
+def HasV162     : Predicate<"HasV162Ops()">, AssemblerPredicate<(all_of HasV162Ops), "v1.6.2">;
+
+def HasV120_UP  : Predicate<"HasV120Ops() || HasV130Ops() || HasV131Ops() || HasV160Ops() || HasV161Ops() || HasV162Ops()">
+				, AssemblerPredicate<(any_of HasV120Ops, HasV130Ops, HasV131Ops, HasV160Ops, HasV161Ops, HasV162Ops), "v120up">;
+def HasV130_UP  : Predicate<"HasV130Ops() || HasV131Ops() || HasV160Ops() || HasV161Ops() || HasV162Ops()">
+				, AssemblerPredicate<(any_of HasV130Ops, HasV131Ops, HasV160Ops, HasV161Ops, HasV162Ops), "v130up">;
+def HasV131_UP  : Predicate<"HasV131Ops() || HasV160Ops() || HasV161Ops() || HasV162Ops()">
+				, AssemblerPredicate<(any_of HasV131Ops, HasV160Ops, HasV161Ops, HasV162Ops), "v131up">;
+def HasV160_UP  : Predicate<"HasV160Ops() || HasV161Ops() || HasV162Ops()">
+				, AssemblerPredicate<(any_of HasV160Ops, HasV161Ops, HasV162Ops), "v160up">;
+def HasV161_UP  : Predicate<"HasV161Ops() || HasV162Ops()">
+				, AssemblerPredicate<(any_of HasV161Ops, HasV162Ops), "v161up">;
+def HasV162_UP  : Predicate<"HasV162Ops()">
+				, AssemblerPredicate<(any_of HasV162Ops), "v162up">;
+
+def HasV120_DN : Predicate<"HasV120Ops() || HasV110Ops()">,
+				AssemblerPredicate<(any_of HasV120Ops, HasV110Ops), "v120dn">;
+def HasV130_DN : Predicate<"HasV130Ops() || HasV120Ops() || HasV110Ops()">,
+				AssemblerPredicate<(any_of HasV130Ops, HasV120Ops, HasV110Ops), "v130dn">;
+def HasV131_DN : Predicate<"HasV131Ops() || HasV130Ops() || HasV120Ops() || HasV110Ops()">,
+				AssemblerPredicate<(any_of HasV131Ops, HasV130Ops, HasV120Ops, HasV110Ops), "v131dn">;
+def HasV160_DN : Predicate<"HasV160Ops() || HasV131Ops() || HasV130Ops() || HasV120Ops() || HasV110Ops()">,
+				AssemblerPredicate<(any_of HasV160Ops, HasV131Ops, HasV130Ops, HasV120Ops, HasV110Ops), "v160dn">;
+def HasV161_DN : Predicate<"HasV161Ops() || HasV160Ops() || HasV131Ops() || HasV130Ops() || HasV120Ops() || HasV110Ops()">,
+				AssemblerPredicate<(any_of HasV161Ops, HasV160Ops, HasV131Ops, HasV130Ops, HasV120Ops, HasV110Ops), "v161dn">;
+def HasV162_DN : Predicate<"HasV162Ops() || HasV161Ops() || HasV160Ops() || HasV131Ops() || HasV130Ops() || HasV120Ops() || HasV110Ops()">,
+				AssemblerPredicate<(any_of HasV162Ops, HasV161Ops, HasV160Ops, HasV131Ops, HasV130Ops, HasV120Ops, HasV110Ops), "v162dn">;
+
+
+class Architecture<string fname, string aname, list<SubtargetFeature> features = []>
+  : SubtargetFeature<fname, "TriCoreArch", aname,
+					 !strconcat(aname, " architecture"), features>;
+
+class ProcNoItin<string Name, list<SubtargetFeature> Features>
+  : Processor<Name, NoItineraries, Features>;
+
+
+def TRICORE_V1_1    : Architecture<"tricore-v1.1",    "TRICOREv110", [HasV110Ops]>;
+def TRICORE_V1_2    : Architecture<"tricore-V1.2",    "TRICOREv120", [HasV120Ops]>;
+def TRICORE_V1_3    : Architecture<"tricore-V1.3",    "TRICOREv130", [HasV130Ops]>;
+def TRICORE_V1_3_1  : Architecture<"tricore-V1.3.1",  "TRICOREv131", [HasV131Ops]>;
+def TRICORE_V1_6    : Architecture<"tricore-V1.6",    "TRICOREv160", [HasV160Ops]>;
+def TRICORE_V1_6_1  : Architecture<"tricore-V1.6.1",  "TRICOREv161", [HasV161Ops]>;
+def TRICORE_V1_6_2  : Architecture<"tricore-V1.6.2",  "TRICOREv162", [HasV162Ops]>;
+def TRICORE_PCP     : Architecture<"tricore-PCP",     "TRICOREpcp">;
+def TRICORE_PCP2    : Architecture<"tricore-PCP2",    "TRICOREpcp2">;
+
+def TRICORE_RIDER_A : Architecture<"tricore-rider-a", "TRICOREv110", [TRICORE_V1_1]>;
+
+
+include "TriCoreRegisterInfo.td"
+include "TriCoreInstrInfo.td"
+include "TriCoreCallingConv.td"
+
+//===----------------------------------------------------------------------===//
+// TriCore processors supported.
+//===----------------------------------------------------------------------===//
+
+def : ProcNoItin<"tc1796",  [TRICORE_V1_3]>;
+def : ProcNoItin<"tc1797",  [TRICORE_V1_3_1]>;
+def : ProcNoItin<"tc27x",   [TRICORE_V1_6_1]>;
+def : ProcNoItin<"tc161",   [TRICORE_V1_6_1]>;
+def : ProcNoItin<"tc162",   [TRICORE_V1_6_2]>;
+def : ProcNoItin<"tc16",    [TRICORE_V1_6]>;
+def : ProcNoItin<"tc131",   [TRICORE_V1_3_1]>;
+def : ProcNoItin<"tc13",    [TRICORE_V1_3]>;
+
+def TriCoreAsmWriter : AsmWriter {
+  int PassSubtarget = 1;
+}
+
+def TriCoreInstrInfo : InstrInfo;
+
+//===----------------------------------------------------------------------===//
+// Declare the target which we are implementing
+//===----------------------------------------------------------------------===//
+
+def TriCore : Target {
+  let InstructionSet = TriCoreInstrInfo;
+  let AssemblyWriters = [TriCoreAsmWriter];
+}
--- a/thirdparty/capstone/arch/TriCore/TriCoreCallingConv.td
+++ b/thirdparty/capstone/arch/TriCore/TriCoreCallingConv.td
@@ -0,0 +1,61 @@
+//=- TriCoreCallingConv.td - Calling Conventions for TriCore -*- tablegen -*-=//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+// This describes the calling conventions for TriCore architecture.
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// CCDelegate implemented form TriCore LLVM Thesis
+//===----------------------------------------------------------------------===//
+//def CC_TriCore_StackModel : CallingConv<[
+//CCAssignToStack<4, 4>
+//]>;
+
+//===----------------------------------------------------------------------===//
+// TriCore Return Value Calling Convention
+//===----------------------------------------------------------------------===//
+def RetCC_TriCore : CallingConv<[
+  // Promote i8/i16 arguments to i32.
+  CCIfType<[i8, i16], CCPromoteToType<i32>>,
+  
+  // i32 are returned in registers D2
+  CCIfType<[i32], CCAssignToReg<[D2]>>,
+
+  // Integer values get stored in stack slots that are 4 bytes in
+  // size and 4-byte aligned.
+  CCIfType<[i32], CCAssignToStack<4, 4>>
+]>;
+
+//===----------------------------------------------------------------------===//
+// TriCore Argument Calling Conventions
+//===----------------------------------------------------------------------===//
+def CC_TriCore : CallingConv<[
+  // Promote i8/i16 arguments to i32.
+  CCIfType<[i8, i16], CCPromoteToType<i32>>,
+
+	
+	// The first 4 integer arguments are passed in integer registers.
+	//	CCIfType<[i32], CCAssignToReg<[D4, D5, D6, D7]>>,
+	
+	//CCIfType<[i32], CCAssignToReg<[A4, A5, A6, A7]>>,
+	
+	// Pointer arguments are handled inside TriCoreIselLowering, because
+	// LLVM lowers i32** type into i32, hence there is no way to distingusish
+	// between a pointer type and an integer type.
+	
+
+	
+	
+  //CCDelegateTo<CC_TriCore_StackModel>
+  
+  // Integer values get stored in stack slots that are 4 bytes in
+  // size and 4-byte aligned.
+  CCIfType<[i32], CCAssignToStack<4, 4>>
+]>;
+
+//def CC_Save : CalleeSavedRegs<(add R4, R5, R6, R7, R8, R9)>;
--- a/thirdparty/capstone/arch/TriCore/TriCoreDisassembler.c
+++ b/thirdparty/capstone/arch/TriCore/TriCoreDisassembler.c
--- a/thirdparty/capstone/arch/TriCore/TriCoreDisassembler.h
+++ b/thirdparty/capstone/arch/TriCore/TriCoreDisassembler.h
@@ -0,0 +1,18 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifndef CS_TRICOREDISASSEMBLER_H
+#define CS_TRICOREDISASSEMBLER_H
+
+#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
+#include <stdint.h>
+#endif
+
+#include <capstone/capstone.h>
+#include "../../MCRegisterInfo.h"
+#include "../../MCInst.h"
+
+void TriCore_init_mri(MCRegisterInfo *MRI);
+bool TriCore_getFeatureBits(unsigned int mode, unsigned int feature);
+
+#endif
--- a/thirdparty/capstone/arch/TriCore/TriCoreGenAsmWriter.inc
+++ b/thirdparty/capstone/arch/TriCore/TriCoreGenAsmWriter.inc
--- a/thirdparty/capstone/arch/TriCore/TriCoreGenCSFeatureName.inc
+++ b/thirdparty/capstone/arch/TriCore/TriCoreGenCSFeatureName.inc
@@ -0,0 +1,22 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+{ TRICORE_FEATURE_HasV110, "HasV110" },
+{ TRICORE_FEATURE_HasV120_UP, "HasV120_UP" },
+{ TRICORE_FEATURE_HasV130_UP, "HasV130_UP" },
+{ TRICORE_FEATURE_HasV161, "HasV161" },
+{ TRICORE_FEATURE_HasV160_UP, "HasV160_UP" },
+{ TRICORE_FEATURE_HasV131_UP, "HasV131_UP" },
+{ TRICORE_FEATURE_HasV161_UP, "HasV161_UP" },
+{ TRICORE_FEATURE_HasV162, "HasV162" },
+{ TRICORE_FEATURE_HasV162_UP, "HasV162_UP" },
--- a/thirdparty/capstone/arch/TriCore/TriCoreGenCSMappingInsn.inc
+++ b/thirdparty/capstone/arch/TriCore/TriCoreGenCSMappingInsn.inc
--- a/thirdparty/capstone/arch/TriCore/TriCoreGenCSMappingInsnName.inc
+++ b/thirdparty/capstone/arch/TriCore/TriCoreGenCSMappingInsnName.inc
@@ -0,0 +1,404 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+  "invalid", // TRICORE_INS_INVALID
+  "absdifs.b", // TRICORE_INS_ABSDIFS_B
+  "absdifs.h", // TRICORE_INS_ABSDIFS_H
+  "absdifs", // TRICORE_INS_ABSDIFS
+  "absdif.b", // TRICORE_INS_ABSDIF_B
+  "absdif.h", // TRICORE_INS_ABSDIF_H
+  "absdif", // TRICORE_INS_ABSDIF
+  "abss.b", // TRICORE_INS_ABSS_B
+  "abss.h", // TRICORE_INS_ABSS_H
+  "abss", // TRICORE_INS_ABSS
+  "abs.b", // TRICORE_INS_ABS_B
+  "abs.h", // TRICORE_INS_ABS_H
+  "abs", // TRICORE_INS_ABS
+  "addc", // TRICORE_INS_ADDC
+  "addih.a", // TRICORE_INS_ADDIH_A
+  "addih", // TRICORE_INS_ADDIH
+  "addi", // TRICORE_INS_ADDI
+  "addsc.at", // TRICORE_INS_ADDSC_AT
+  "addsc.a", // TRICORE_INS_ADDSC_A
+  "adds.bu", // TRICORE_INS_ADDS_BU
+  "adds.b", // TRICORE_INS_ADDS_B
+  "adds.h", // TRICORE_INS_ADDS_H
+  "adds.hu", // TRICORE_INS_ADDS_HU
+  "adds.u", // TRICORE_INS_ADDS_U
+  "adds", // TRICORE_INS_ADDS
+  "addx", // TRICORE_INS_ADDX
+  "add.a", // TRICORE_INS_ADD_A
+  "add.b", // TRICORE_INS_ADD_B
+  "add.f", // TRICORE_INS_ADD_F
+  "add.h", // TRICORE_INS_ADD_H
+  "add", // TRICORE_INS_ADD
+  "andn.t", // TRICORE_INS_ANDN_T
+  "andn", // TRICORE_INS_ANDN
+  "and.andn.t", // TRICORE_INS_AND_ANDN_T
+  "and.and.t", // TRICORE_INS_AND_AND_T
+  "and.eq", // TRICORE_INS_AND_EQ
+  "and.ge.u", // TRICORE_INS_AND_GE_U
+  "and.ge", // TRICORE_INS_AND_GE
+  "and.lt.u", // TRICORE_INS_AND_LT_U
+  "and.lt", // TRICORE_INS_AND_LT
+  "and.ne", // TRICORE_INS_AND_NE
+  "and.nor.t", // TRICORE_INS_AND_NOR_T
+  "and.or.t", // TRICORE_INS_AND_OR_T
+  "and.t", // TRICORE_INS_AND_T
+  "and", // TRICORE_INS_AND
+  "bisr", // TRICORE_INS_BISR
+  "bmerge", // TRICORE_INS_BMERGE
+  "bsplit", // TRICORE_INS_BSPLIT
+  "cachea.i", // TRICORE_INS_CACHEA_I
+  "cachea.wi", // TRICORE_INS_CACHEA_WI
+  "cachea.w", // TRICORE_INS_CACHEA_W
+  "cachei.i", // TRICORE_INS_CACHEI_I
+  "cachei.wi", // TRICORE_INS_CACHEI_WI
+  "cachei.w", // TRICORE_INS_CACHEI_W
+  "caddn.a", // TRICORE_INS_CADDN_A
+  "caddn", // TRICORE_INS_CADDN
+  "cadd.a", // TRICORE_INS_CADD_A
+  "cadd", // TRICORE_INS_CADD
+  "calla", // TRICORE_INS_CALLA
+  "calli", // TRICORE_INS_CALLI
+  "call", // TRICORE_INS_CALL
+  "clo.b", // TRICORE_INS_CLO_B
+  "clo.h", // TRICORE_INS_CLO_H
+  "clo", // TRICORE_INS_CLO
+  "cls.b", // TRICORE_INS_CLS_B
+  "cls.h", // TRICORE_INS_CLS_H
+  "cls", // TRICORE_INS_CLS
+  "clz.b", // TRICORE_INS_CLZ_B
+  "clz.h", // TRICORE_INS_CLZ_H
+  "clz", // TRICORE_INS_CLZ
+  "cmovn", // TRICORE_INS_CMOVN
+  "cmov", // TRICORE_INS_CMOV
+  "cmpswap.w", // TRICORE_INS_CMPSWAP_W
+  "cmp.f", // TRICORE_INS_CMP_F
+  "crc32b.w", // TRICORE_INS_CRC32B_W
+  "crc32l.w", // TRICORE_INS_CRC32L_W
+  "crc32.b", // TRICORE_INS_CRC32_B
+  "crcn", // TRICORE_INS_CRCN
+  "csubn.a", // TRICORE_INS_CSUBN_A
+  "csubn", // TRICORE_INS_CSUBN
+  "csub.a", // TRICORE_INS_CSUB_A
+  "csub", // TRICORE_INS_CSUB
+  "debug", // TRICORE_INS_DEBUG
+  "dextr", // TRICORE_INS_DEXTR
+  "difsc.a", // TRICORE_INS_DIFSC_A
+  "disable", // TRICORE_INS_DISABLE
+  "div.f", // TRICORE_INS_DIV_F
+  "div.u", // TRICORE_INS_DIV_U
+  "div", // TRICORE_INS_DIV
+  "dsync", // TRICORE_INS_DSYNC
+  "dvadj", // TRICORE_INS_DVADJ
+  "dvinit.bu", // TRICORE_INS_DVINIT_BU
+  "dvinit.b", // TRICORE_INS_DVINIT_B
+  "dvinit.hu", // TRICORE_INS_DVINIT_HU
+  "dvinit.h", // TRICORE_INS_DVINIT_H
+  "dvinit.u", // TRICORE_INS_DVINIT_U
+  "dvinit", // TRICORE_INS_DVINIT
+  "dvstep.u", // TRICORE_INS_DVSTEP_U
+  "dvstep", // TRICORE_INS_DVSTEP
+  "enable", // TRICORE_INS_ENABLE
+  "eqany.b", // TRICORE_INS_EQANY_B
+  "eqany.h", // TRICORE_INS_EQANY_H
+  "eqz.a", // TRICORE_INS_EQZ_A
+  "eq.a", // TRICORE_INS_EQ_A
+  "eq.b", // TRICORE_INS_EQ_B
+  "eq.h", // TRICORE_INS_EQ_H
+  "eq.w", // TRICORE_INS_EQ_W
+  "eq", // TRICORE_INS_EQ
+  "extr.u", // TRICORE_INS_EXTR_U
+  "extr", // TRICORE_INS_EXTR
+  "fcalla", // TRICORE_INS_FCALLA
+  "fcalli", // TRICORE_INS_FCALLI
+  "fcall", // TRICORE_INS_FCALL
+  "fret", // TRICORE_INS_FRET
+  "ftohp", // TRICORE_INS_FTOHP
+  "ftoiz", // TRICORE_INS_FTOIZ
+  "ftoi", // TRICORE_INS_FTOI
+  "ftoq31z", // TRICORE_INS_FTOQ31Z
+  "ftoq31", // TRICORE_INS_FTOQ31
+  "ftouz", // TRICORE_INS_FTOUZ
+  "ftou", // TRICORE_INS_FTOU
+  "ge.a", // TRICORE_INS_GE_A
+  "ge.u", // TRICORE_INS_GE_U
+  "ge", // TRICORE_INS_GE
+  "hptof", // TRICORE_INS_HPTOF
+  "imask", // TRICORE_INS_IMASK
+  "insert", // TRICORE_INS_INSERT
+  "insn.t", // TRICORE_INS_INSN_T
+  "ins.t", // TRICORE_INS_INS_T
+  "isync", // TRICORE_INS_ISYNC
+  "itof", // TRICORE_INS_ITOF
+  "ixmax.u", // TRICORE_INS_IXMAX_U
+  "ixmax", // TRICORE_INS_IXMAX
+  "ixmin.u", // TRICORE_INS_IXMIN_U
+  "ixmin", // TRICORE_INS_IXMIN
+  "ja", // TRICORE_INS_JA
+  "jeq.a", // TRICORE_INS_JEQ_A
+  "jeq", // TRICORE_INS_JEQ
+  "jgez", // TRICORE_INS_JGEZ
+  "jge.u", // TRICORE_INS_JGE_U
+  "jge", // TRICORE_INS_JGE
+  "jgtz", // TRICORE_INS_JGTZ
+  "ji", // TRICORE_INS_JI
+  "jla", // TRICORE_INS_JLA
+  "jlez", // TRICORE_INS_JLEZ
+  "jli", // TRICORE_INS_JLI
+  "jltz", // TRICORE_INS_JLTZ
+  "jlt.u", // TRICORE_INS_JLT_U
+  "jlt", // TRICORE_INS_JLT
+  "jl", // TRICORE_INS_JL
+  "jned", // TRICORE_INS_JNED
+  "jnei", // TRICORE_INS_JNEI
+  "jne.a", // TRICORE_INS_JNE_A
+  "jne", // TRICORE_INS_JNE
+  "jnz.a", // TRICORE_INS_JNZ_A
+  "jnz.t", // TRICORE_INS_JNZ_T
+  "jnz", // TRICORE_INS_JNZ
+  "jz.a", // TRICORE_INS_JZ_A
+  "jz.t", // TRICORE_INS_JZ_T
+  "jz", // TRICORE_INS_JZ
+  "j", // TRICORE_INS_J
+  "ldlcx", // TRICORE_INS_LDLCX
+  "ldmst", // TRICORE_INS_LDMST
+  "lducx", // TRICORE_INS_LDUCX
+  "ld.a", // TRICORE_INS_LD_A
+  "ld.bu", // TRICORE_INS_LD_BU
+  "ld.b", // TRICORE_INS_LD_B
+  "ld.da", // TRICORE_INS_LD_DA
+  "ld.d", // TRICORE_INS_LD_D
+  "ld.hu", // TRICORE_INS_LD_HU
+  "ld.h", // TRICORE_INS_LD_H
+  "ld.q", // TRICORE_INS_LD_Q
+  "ld.w", // TRICORE_INS_LD_W
+  "lea", // TRICORE_INS_LEA
+  "lha", // TRICORE_INS_LHA
+  "loopu", // TRICORE_INS_LOOPU
+  "loop", // TRICORE_INS_LOOP
+  "lt.a", // TRICORE_INS_LT_A
+  "lt.b", // TRICORE_INS_LT_B
+  "lt.bu", // TRICORE_INS_LT_BU
+  "lt.h", // TRICORE_INS_LT_H
+  "lt.hu", // TRICORE_INS_LT_HU
+  "lt.u", // TRICORE_INS_LT_U
+  "lt.w", // TRICORE_INS_LT_W
+  "lt.wu", // TRICORE_INS_LT_WU
+  "lt", // TRICORE_INS_LT
+  "maddms.h", // TRICORE_INS_MADDMS_H
+  "maddms.u", // TRICORE_INS_MADDMS_U
+  "maddms", // TRICORE_INS_MADDMS
+  "maddm.h", // TRICORE_INS_MADDM_H
+  "maddm.q", // TRICORE_INS_MADDM_Q
+  "maddm.u", // TRICORE_INS_MADDM_U
+  "maddm", // TRICORE_INS_MADDM
+  "maddrs.h", // TRICORE_INS_MADDRS_H
+  "maddrs.q", // TRICORE_INS_MADDRS_Q
+  "maddr.h", // TRICORE_INS_MADDR_H
+  "maddr.q", // TRICORE_INS_MADDR_Q
+  "maddsums.h", // TRICORE_INS_MADDSUMS_H
+  "maddsum.h", // TRICORE_INS_MADDSUM_H
+  "maddsurs.h", // TRICORE_INS_MADDSURS_H
+  "maddsur.h", // TRICORE_INS_MADDSUR_H
+  "maddsus.h", // TRICORE_INS_MADDSUS_H
+  "maddsu.h", // TRICORE_INS_MADDSU_H
+  "madds.h", // TRICORE_INS_MADDS_H
+  "madds.q", // TRICORE_INS_MADDS_Q
+  "madds.u", // TRICORE_INS_MADDS_U
+  "madds", // TRICORE_INS_MADDS
+  "madd.f", // TRICORE_INS_MADD_F
+  "madd.h", // TRICORE_INS_MADD_H
+  "madd.q", // TRICORE_INS_MADD_Q
+  "madd.u", // TRICORE_INS_MADD_U
+  "madd", // TRICORE_INS_MADD
+  "max.b", // TRICORE_INS_MAX_B
+  "max.bu", // TRICORE_INS_MAX_BU
+  "max.h", // TRICORE_INS_MAX_H
+  "max.hu", // TRICORE_INS_MAX_HU
+  "max.u", // TRICORE_INS_MAX_U
+  "max", // TRICORE_INS_MAX
+  "mfcr", // TRICORE_INS_MFCR
+  "min.b", // TRICORE_INS_MIN_B
+  "min.bu", // TRICORE_INS_MIN_BU
+  "min.h", // TRICORE_INS_MIN_H
+  "min.hu", // TRICORE_INS_MIN_HU
+  "min.u", // TRICORE_INS_MIN_U
+  "min", // TRICORE_INS_MIN
+  "movh.a", // TRICORE_INS_MOVH_A
+  "movh", // TRICORE_INS_MOVH
+  "movz.a", // TRICORE_INS_MOVZ_A
+  "mov.aa", // TRICORE_INS_MOV_AA
+  "mov.a", // TRICORE_INS_MOV_A
+  "mov.d", // TRICORE_INS_MOV_D
+  "mov.u", // TRICORE_INS_MOV_U
+  "mov", // TRICORE_INS_MOV
+  "msubadms.h", // TRICORE_INS_MSUBADMS_H
+  "msubadm.h", // TRICORE_INS_MSUBADM_H
+  "msubadrs.h", // TRICORE_INS_MSUBADRS_H
+  "msubadr.h", // TRICORE_INS_MSUBADR_H
+  "msubads.h", // TRICORE_INS_MSUBADS_H
+  "msubad.h", // TRICORE_INS_MSUBAD_H
+  "msubms.h", // TRICORE_INS_MSUBMS_H
+  "msubms.u", // TRICORE_INS_MSUBMS_U
+  "msubms", // TRICORE_INS_MSUBMS
+  "msubm.h", // TRICORE_INS_MSUBM_H
+  "msubm.q", // TRICORE_INS_MSUBM_Q
+  "msubm.u", // TRICORE_INS_MSUBM_U
+  "msubm", // TRICORE_INS_MSUBM
+  "msubrs.h", // TRICORE_INS_MSUBRS_H
+  "msubrs.q", // TRICORE_INS_MSUBRS_Q
+  "msubr.h", // TRICORE_INS_MSUBR_H
+  "msubr.q", // TRICORE_INS_MSUBR_Q
+  "msubs.h", // TRICORE_INS_MSUBS_H
+  "msubs.q", // TRICORE_INS_MSUBS_Q
+  "msubs.u", // TRICORE_INS_MSUBS_U
+  "msubs", // TRICORE_INS_MSUBS
+  "msub.f", // TRICORE_INS_MSUB_F
+  "msub.h", // TRICORE_INS_MSUB_H
+  "msub.q", // TRICORE_INS_MSUB_Q
+  "msub.u", // TRICORE_INS_MSUB_U
+  "msub", // TRICORE_INS_MSUB
+  "mtcr", // TRICORE_INS_MTCR
+  "mulms.h", // TRICORE_INS_MULMS_H
+  "mulm.h", // TRICORE_INS_MULM_H
+  "mulm.u", // TRICORE_INS_MULM_U
+  "mulm", // TRICORE_INS_MULM
+  "mulr.h", // TRICORE_INS_MULR_H
+  "mulr.q", // TRICORE_INS_MULR_Q
+  "muls.u", // TRICORE_INS_MULS_U
+  "muls", // TRICORE_INS_MULS
+  "mul.f", // TRICORE_INS_MUL_F
+  "mul.h", // TRICORE_INS_MUL_H
+  "mul.q", // TRICORE_INS_MUL_Q
+  "mul.u", // TRICORE_INS_MUL_U
+  "mul", // TRICORE_INS_MUL
+  "nand.t", // TRICORE_INS_NAND_T
+  "nand", // TRICORE_INS_NAND
+  "nez.a", // TRICORE_INS_NEZ_A
+  "ne.a", // TRICORE_INS_NE_A
+  "ne", // TRICORE_INS_NE
+  "nop", // TRICORE_INS_NOP
+  "nor.t", // TRICORE_INS_NOR_T
+  "nor", // TRICORE_INS_NOR
+  "not", // TRICORE_INS_NOT
+  "orn.t", // TRICORE_INS_ORN_T
+  "orn", // TRICORE_INS_ORN
+  "or.andn.t", // TRICORE_INS_OR_ANDN_T
+  "or.and.t", // TRICORE_INS_OR_AND_T
+  "or.eq", // TRICORE_INS_OR_EQ
+  "or.ge.u", // TRICORE_INS_OR_GE_U
+  "or.ge", // TRICORE_INS_OR_GE
+  "or.lt.u", // TRICORE_INS_OR_LT_U
+  "or.lt", // TRICORE_INS_OR_LT
+  "or.ne", // TRICORE_INS_OR_NE
+  "or.nor.t", // TRICORE_INS_OR_NOR_T
+  "or.or.t", // TRICORE_INS_OR_OR_T
+  "or.t", // TRICORE_INS_OR_T
+  "or", // TRICORE_INS_OR
+  "pack", // TRICORE_INS_PACK
+  "parity", // TRICORE_INS_PARITY
+  "popcnt.w", // TRICORE_INS_POPCNT_W
+  "q31tof", // TRICORE_INS_Q31TOF
+  "qseed.f", // TRICORE_INS_QSEED_F
+  "restore", // TRICORE_INS_RESTORE
+  "ret", // TRICORE_INS_RET
+  "rfe", // TRICORE_INS_RFE
+  "rfm", // TRICORE_INS_RFM
+  "rslcx", // TRICORE_INS_RSLCX
+  "rstv", // TRICORE_INS_RSTV
+  "rsubs.u", // TRICORE_INS_RSUBS_U
+  "rsubs", // TRICORE_INS_RSUBS
+  "rsub", // TRICORE_INS_RSUB
+  "sat.bu", // TRICORE_INS_SAT_BU
+  "sat.b", // TRICORE_INS_SAT_B
+  "sat.hu", // TRICORE_INS_SAT_HU
+  "sat.h", // TRICORE_INS_SAT_H
+  "seln.a", // TRICORE_INS_SELN_A
+  "seln", // TRICORE_INS_SELN
+  "sel.a", // TRICORE_INS_SEL_A
+  "sel", // TRICORE_INS_SEL
+  "shas", // TRICORE_INS_SHAS
+  "sha.b", // TRICORE_INS_SHA_B
+  "sha.h", // TRICORE_INS_SHA_H
+  "sha", // TRICORE_INS_SHA
+  "shuffle", // TRICORE_INS_SHUFFLE
+  "sh.andn.t", // TRICORE_INS_SH_ANDN_T
+  "sh.and.t", // TRICORE_INS_SH_AND_T
+  "sh.b", // TRICORE_INS_SH_B
+  "sh.eq", // TRICORE_INS_SH_EQ
+  "sh.ge.u", // TRICORE_INS_SH_GE_U
+  "sh.ge", // TRICORE_INS_SH_GE
+  "sh.h", // TRICORE_INS_SH_H
+  "sh.lt.u", // TRICORE_INS_SH_LT_U
+  "sh.lt", // TRICORE_INS_SH_LT
+  "sh.nand.t", // TRICORE_INS_SH_NAND_T
+  "sh.ne", // TRICORE_INS_SH_NE
+  "sh.nor.t", // TRICORE_INS_SH_NOR_T
+  "sh.orn.t", // TRICORE_INS_SH_ORN_T
+  "sh.or.t", // TRICORE_INS_SH_OR_T
+  "sh.xnor.t", // TRICORE_INS_SH_XNOR_T
+  "sh.xor.t", // TRICORE_INS_SH_XOR_T
+  "sh", // TRICORE_INS_SH
+  "stlcx", // TRICORE_INS_STLCX
+  "stucx", // TRICORE_INS_STUCX
+  "st.a", // TRICORE_INS_ST_A
+  "st.b", // TRICORE_INS_ST_B
+  "st.da", // TRICORE_INS_ST_DA
+  "st.d", // TRICORE_INS_ST_D
+  "st.h", // TRICORE_INS_ST_H
+  "st.q", // TRICORE_INS_ST_Q
+  "st.t", // TRICORE_INS_ST_T
+  "st.w", // TRICORE_INS_ST_W
+  "subc", // TRICORE_INS_SUBC
+  "subsc.a", // TRICORE_INS_SUBSC_A
+  "subs.bu", // TRICORE_INS_SUBS_BU
+  "subs.b", // TRICORE_INS_SUBS_B
+  "subs.hu", // TRICORE_INS_SUBS_HU
+  "subs.h", // TRICORE_INS_SUBS_H
+  "subs.u", // TRICORE_INS_SUBS_U
+  "subs", // TRICORE_INS_SUBS
+  "subx", // TRICORE_INS_SUBX
+  "sub.a", // TRICORE_INS_SUB_A
+  "sub.b", // TRICORE_INS_SUB_B
+  "sub.f", // TRICORE_INS_SUB_F
+  "sub.h", // TRICORE_INS_SUB_H
+  "sub", // TRICORE_INS_SUB
+  "svlcx", // TRICORE_INS_SVLCX
+  "swapmsk.w", // TRICORE_INS_SWAPMSK_W
+  "swap.a", // TRICORE_INS_SWAP_A
+  "swap.w", // TRICORE_INS_SWAP_W
+  "syscall", // TRICORE_INS_SYSCALL
+  "tlbdemap", // TRICORE_INS_TLBDEMAP
+  "tlbflush.a", // TRICORE_INS_TLBFLUSH_A
+  "tlbflush.b", // TRICORE_INS_TLBFLUSH_B
+  "tlbmap", // TRICORE_INS_TLBMAP
+  "tlbprobe.a", // TRICORE_INS_TLBPROBE_A
+  "tlbprobe.i", // TRICORE_INS_TLBPROBE_I
+  "trapsv", // TRICORE_INS_TRAPSV
+  "trapv", // TRICORE_INS_TRAPV
+  "unpack", // TRICORE_INS_UNPACK
+  "updfl", // TRICORE_INS_UPDFL
+  "utof", // TRICORE_INS_UTOF
+  "wait", // TRICORE_INS_WAIT
+  "xnor.t", // TRICORE_INS_XNOR_T
+  "xnor", // TRICORE_INS_XNOR
+  "xor.eq", // TRICORE_INS_XOR_EQ
+  "xor.ge.u", // TRICORE_INS_XOR_GE_U
+  "xor.ge", // TRICORE_INS_XOR_GE
+  "xor.lt.u", // TRICORE_INS_XOR_LT_U
+  "xor.lt", // TRICORE_INS_XOR_LT
+  "xor.ne", // TRICORE_INS_XOR_NE
+  "xor.t", // TRICORE_INS_XOR_T
+  "xor", // TRICORE_INS_XOR
--- a/thirdparty/capstone/arch/TriCore/TriCoreGenCSMappingInsnOp.inc
+++ b/thirdparty/capstone/arch/TriCore/TriCoreGenCSMappingInsnOp.inc
--- a/thirdparty/capstone/arch/TriCore/TriCoreGenCSOpGroup.inc
+++ b/thirdparty/capstone/arch/TriCore/TriCoreGenCSOpGroup.inc
@@ -0,0 +1,32 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+  TRICORE_OP_GROUP_RegImmShift = 0,
+  TRICORE_OP_GROUP_LdStmModeOperand = 1,
+  TRICORE_OP_GROUP_MandatoryInvertedPredicateOperand = 2,
+  TRICORE_OP_GROUP_Operand = 3,
+  TRICORE_OP_GROUP_SExtImm_9 = 4,
+  TRICORE_OP_GROUP_ZExtImm_16 = 5,
+  TRICORE_OP_GROUP_SExtImm_16 = 6,
+  TRICORE_OP_GROUP_ZExtImm_2 = 7,
+  TRICORE_OP_GROUP_SExtImm_4 = 8,
+  TRICORE_OP_GROUP_ZExtImm_4 = 9,
+  TRICORE_OP_GROUP_ZExtImm_8 = 10,
+  TRICORE_OP_GROUP_SExtImm_10 = 11,
+  TRICORE_OP_GROUP_Disp24Imm = 12,
+  TRICORE_OP_GROUP_Disp8Imm = 13,
+  TRICORE_OP_GROUP_Disp15Imm = 14,
+  TRICORE_OP_GROUP_Disp4Imm = 15,
+  TRICORE_OP_GROUP_Off18Imm = 16,
+  TRICORE_OP_GROUP_OExtImm_4 = 17,
+  TRICORE_OP_GROUP_ZExtImm_9 = 18,
--- a/thirdparty/capstone/arch/TriCore/TriCoreGenDisassemblerTables.inc
+++ b/thirdparty/capstone/arch/TriCore/TriCoreGenDisassemblerTables.inc
--- a/thirdparty/capstone/arch/TriCore/TriCoreGenInstrInfo.inc
+++ b/thirdparty/capstone/arch/TriCore/TriCoreGenInstrInfo.inc
--- a/thirdparty/capstone/arch/TriCore/TriCoreGenRegisterInfo.inc
+++ b/thirdparty/capstone/arch/TriCore/TriCoreGenRegisterInfo.inc
@@ -0,0 +1,294 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+#ifdef GET_REGINFO_ENUM
+#undef GET_REGINFO_ENUM
+
+enum {
+  TRICORE_NoRegister,
+  TRICORE_FCX = 1,
+  TRICORE_PC = 2,
+  TRICORE_PCXI = 3,
+  TRICORE_PSW = 4,
+  TRICORE_A0 = 5,
+  TRICORE_A1 = 6,
+  TRICORE_A2 = 7,
+  TRICORE_A3 = 8,
+  TRICORE_A4 = 9,
+  TRICORE_A5 = 10,
+  TRICORE_A6 = 11,
+  TRICORE_A7 = 12,
+  TRICORE_A8 = 13,
+  TRICORE_A9 = 14,
+  TRICORE_A10 = 15,
+  TRICORE_A11 = 16,
+  TRICORE_A12 = 17,
+  TRICORE_A13 = 18,
+  TRICORE_A14 = 19,
+  TRICORE_A15 = 20,
+  TRICORE_D0 = 21,
+  TRICORE_D1 = 22,
+  TRICORE_D2 = 23,
+  TRICORE_D3 = 24,
+  TRICORE_D4 = 25,
+  TRICORE_D5 = 26,
+  TRICORE_D6 = 27,
+  TRICORE_D7 = 28,
+  TRICORE_D8 = 29,
+  TRICORE_D9 = 30,
+  TRICORE_D10 = 31,
+  TRICORE_D11 = 32,
+  TRICORE_D12 = 33,
+  TRICORE_D13 = 34,
+  TRICORE_D14 = 35,
+  TRICORE_D15 = 36,
+  TRICORE_E0 = 37,
+  TRICORE_E2 = 38,
+  TRICORE_E4 = 39,
+  TRICORE_E6 = 40,
+  TRICORE_E8 = 41,
+  TRICORE_E10 = 42,
+  TRICORE_E12 = 43,
+  TRICORE_E14 = 44,
+  TRICORE_P0 = 45,
+  TRICORE_P2 = 46,
+  TRICORE_P4 = 47,
+  TRICORE_P6 = 48,
+  TRICORE_P8 = 49,
+  TRICORE_P10 = 50,
+  TRICORE_P12 = 51,
+  TRICORE_P14 = 52,
+  TRICORE_A0_A1 = 53,
+  TRICORE_A2_A3 = 54,
+  TRICORE_A4_A5 = 55,
+  TRICORE_A6_A7 = 56,
+  TRICORE_A8_A9 = 57,
+  TRICORE_A10_A11 = 58,
+  TRICORE_A12_A13 = 59,
+  TRICORE_A14_A15 = 60,
+  NUM_TARGET_REGS // 61
+};
+
+// Register classes
+
+enum {
+  TriCore_RARegClassID = 0,
+  TriCore_RDRegClassID = 1,
+  TriCore_PSRegsRegClassID = 2,
+  TriCore_PairAddrRegsRegClassID = 3,
+  TriCore_RERegClassID = 4,
+  TriCore_RPRegClassID = 5,
+
+};
+
+// Subregister indices
+
+enum {
+  TriCore_NoSubRegister,
+  TriCore_subreg_even,	// 1
+  TriCore_subreg_odd,	// 2
+  TriCore_NUM_TARGET_SUBREGS
+};
+#endif // GET_REGINFO_ENUM
+
+#ifdef GET_REGINFO_MC_DESC
+#undef GET_REGINFO_MC_DESC
+
+static const MCPhysReg TriCoreRegDiffLists[] = {
+  /* 0 */ -102, 1, 0,
+  /* 3 */ -86, 1, 0,
+  /* 6 */ -54, 1, 0,
+  /* 9 */ -48, 1, 0,
+  /* 12 */ -47, 1, 0,
+  /* 15 */ -46, 1, 0,
+  /* 18 */ -45, 1, 0,
+  /* 21 */ -44, 1, 0,
+  /* 24 */ -43, 1, 0,
+  /* 27 */ -42, 1, 0,
+  /* 30 */ -41, 1, 0,
+  /* 33 */ -40, 1, 0,
+  /* 36 */ -39, 1, 0,
+  /* 39 */ -38, 1, 0,
+  /* 42 */ -37, 1, 0,
+  /* 45 */ -36, 1, 0,
+  /* 48 */ -35, 1, 0,
+  /* 51 */ -34, 1, 0,
+  /* 54 */ -33, 1, 0,
+  /* 57 */ -16, 1, 0,
+  /* 60 */ -15, 1, 0,
+  /* 63 */ -14, 1, 0,
+  /* 66 */ -13, 1, 0,
+  /* 69 */ -12, 1, 0,
+  /* 72 */ -11, 1, 0,
+  /* 75 */ -10, 1, 0,
+  /* 78 */ -9, 1, 0,
+  /* 81 */ 32, 8, 0,
+  /* 84 */ 33, 8, 0,
+  /* 87 */ 34, 8, 0,
+  /* 90 */ 35, 8, 0,
+  /* 93 */ 36, 8, 0,
+  /* 96 */ 37, 8, 0,
+  /* 99 */ 38, 8, 0,
+  /* 102 */ 39, 8, 0,
+  /* 105 */ 40, 8, 0,
+  /* 108 */ 9, 0,
+  /* 110 */ 10, 0,
+  /* 112 */ 11, 0,
+  /* 114 */ 12, 0,
+  /* 116 */ 13, 0,
+  /* 118 */ 14, 0,
+  /* 120 */ 15, 0,
+  /* 122 */ 16, 0,
+  /* 124 */ -1, 0,
+};
+
+static const uint16_t TriCoreSubRegIdxLists[] = {
+  /* 0 */ 1, 2, 0,
+};
+
+static const MCRegisterDesc TriCoreRegDesc[] = { // Descriptors
+  { 3, 0, 0, 0, 0, 0 },
+  { 201, 2, 2, 2, 1985, 0 },
+  { 189, 2, 2, 2, 1985, 0 },
+  { 192, 2, 2, 2, 1985, 0 },
+  { 197, 2, 2, 2, 1985, 0 },
+  { 16, 2, 105, 2, 1985, 0 },
+  { 43, 2, 102, 2, 1985, 0 },
+  { 65, 2, 102, 2, 1985, 0 },
+  { 92, 2, 99, 2, 1985, 0 },
+  { 114, 2, 99, 2, 1985, 0 },
+  { 141, 2, 96, 2, 1985, 0 },
+  { 147, 2, 96, 2, 1985, 0 },
+  { 162, 2, 93, 2, 1985, 0 },
+  { 168, 2, 93, 2, 1985, 0 },
+  { 183, 2, 90, 2, 1985, 0 },
+  { 0, 2, 90, 2, 1985, 0 },
+  { 32, 2, 87, 2, 1985, 0 },
+  { 49, 2, 87, 2, 1985, 0 },
+  { 81, 2, 84, 2, 1985, 0 },
+  { 98, 2, 84, 2, 1985, 0 },
+  { 130, 2, 81, 2, 1985, 0 },
+  { 19, 2, 122, 2, 1985, 0 },
+  { 46, 2, 120, 2, 1985, 0 },
+  { 68, 2, 120, 2, 1985, 0 },
+  { 95, 2, 118, 2, 1985, 0 },
+  { 117, 2, 118, 2, 1985, 0 },
+  { 144, 2, 116, 2, 1985, 0 },
+  { 150, 2, 116, 2, 1985, 0 },
+  { 165, 2, 114, 2, 1985, 0 },
+  { 171, 2, 114, 2, 1985, 0 },
+  { 186, 2, 112, 2, 1985, 0 },
+  { 4, 2, 112, 2, 1985, 0 },
+  { 36, 2, 110, 2, 1985, 0 },
+  { 53, 2, 110, 2, 1985, 0 },
+  { 85, 2, 108, 2, 1985, 0 },
+  { 102, 2, 108, 2, 1985, 0 },
+  { 134, 2, 82, 2, 1985, 0 },
+  { 22, 57, 2, 0, 98, 2 },
+  { 71, 60, 2, 0, 98, 2 },
+  { 120, 63, 2, 0, 98, 2 },
+  { 153, 66, 2, 0, 98, 2 },
+  { 174, 69, 2, 0, 98, 2 },
+  { 8, 72, 2, 0, 98, 2 },
+  { 57, 75, 2, 0, 98, 2 },
+  { 106, 78, 2, 0, 98, 2 },
+  { 25, 33, 2, 0, 50, 2 },
+  { 74, 36, 2, 0, 50, 2 },
+  { 123, 39, 2, 0, 50, 2 },
+  { 156, 42, 2, 0, 50, 2 },
+  { 177, 45, 2, 0, 50, 2 },
+  { 12, 48, 2, 0, 50, 2 },
+  { 61, 51, 2, 0, 50, 2 },
+  { 110, 54, 2, 0, 50, 2 },
+  { 40, 9, 2, 0, 2, 2 },
+  { 89, 12, 2, 0, 2, 2 },
+  { 138, 15, 2, 0, 2, 2 },
+  { 159, 18, 2, 0, 2, 2 },
+  { 180, 21, 2, 0, 2, 2 },
+  { 28, 24, 2, 0, 2, 2 },
+  { 77, 27, 2, 0, 2, 2 },
+  { 126, 30, 2, 0, 2, 2 },
+};
+
+  // RA Register Class...
+  static const MCPhysReg RA[] = {
+    TRICORE_A0, TRICORE_A1, TRICORE_A2, TRICORE_A3, TRICORE_A4, TRICORE_A5, TRICORE_A6, TRICORE_A7, TRICORE_A8, TRICORE_A9, TRICORE_A10, TRICORE_A11, TRICORE_A12, TRICORE_A13, TRICORE_A14, TRICORE_A15, 
+  };
+
+  // RA Bit set.
+  static const uint8_t RABits[] = {
+    0xe0, 0xff, 0x1f, 
+  };
+
+  // RD Register Class...
+  static const MCPhysReg RD[] = {
+    TRICORE_D0, TRICORE_D1, TRICORE_D2, TRICORE_D3, TRICORE_D4, TRICORE_D5, TRICORE_D6, TRICORE_D7, TRICORE_D8, TRICORE_D9, TRICORE_D10, TRICORE_D11, TRICORE_D12, TRICORE_D13, TRICORE_D14, TRICORE_D15, 
+  };
+
+  // RD Bit set.
+  static const uint8_t RDBits[] = {
+    0x00, 0x00, 0xe0, 0xff, 0x1f, 
+  };
+
+  // PSRegs Register Class...
+  static const MCPhysReg PSRegs[] = {
+    TRICORE_PSW, TRICORE_PCXI, TRICORE_PC, TRICORE_FCX, 
+  };
+
+  // PSRegs Bit set.
+  static const uint8_t PSRegsBits[] = {
+    0x1e, 
+  };
+
+  // PairAddrRegs Register Class...
+  static const MCPhysReg PairAddrRegs[] = {
+    TRICORE_A0_A1, TRICORE_A2_A3, TRICORE_A4_A5, TRICORE_A6_A7, TRICORE_A8_A9, TRICORE_A10_A11, TRICORE_A12_A13, TRICORE_A14_A15, 
+  };
+
+  // PairAddrRegs Bit set.
+  static const uint8_t PairAddrRegsBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
+  };
+
+  // RE Register Class...
+  static const MCPhysReg RE[] = {
+    TRICORE_E0, TRICORE_E2, TRICORE_E4, TRICORE_E6, TRICORE_E8, TRICORE_E10, TRICORE_E12, TRICORE_E14, 
+  };
+
+  // RE Bit set.
+  static const uint8_t REBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
+  };
+
+  // RP Register Class...
+  static const MCPhysReg RP[] = {
+    TRICORE_P0, TRICORE_P2, TRICORE_P4, TRICORE_P6, TRICORE_P8, TRICORE_P10, TRICORE_P12, TRICORE_P14, 
+  };
+
+  // RP Bit set.
+  static const uint8_t RPBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
+  };
+
+static const MCRegisterClass TriCoreMCRegisterClasses[] = {
+  { RA, RABits, sizeof(RABits) },
+  { RD, RDBits, sizeof(RDBits) },
+  { PSRegs, PSRegsBits, sizeof(PSRegsBits) },
+  { PairAddrRegs, PairAddrRegsBits, sizeof(PairAddrRegsBits) },
+  { RE, REBits, sizeof(REBits) },
+  { RP, RPBits, sizeof(RPBits) },
+};
+
+#endif // GET_REGINFO_MC_DESC
+
+
--- a/thirdparty/capstone/arch/TriCore/TriCoreGenSubtargetInfo.inc
+++ b/thirdparty/capstone/arch/TriCore/TriCoreGenSubtargetInfo.inc
@@ -0,0 +1,40 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+#ifdef GET_SUBTARGETINFO_ENUM
+#undef GET_SUBTARGETINFO_ENUM
+
+enum {
+  TRICORE_HasV110Ops = 0,
+  TRICORE_HasV120Ops = 1,
+  TRICORE_HasV130Ops = 2,
+  TRICORE_HasV131Ops = 3,
+  TRICORE_HasV160Ops = 4,
+  TRICORE_HasV161Ops = 5,
+  TRICORE_HasV162Ops = 6,
+  TRICORE_TRICORE_PCP = 7,
+  TRICORE_TRICORE_PCP2 = 8,
+  TRICORE_TRICORE_RIDER_A = 9,
+  TRICORE_TRICORE_V1_1 = 10,
+  TRICORE_TRICORE_V1_2 = 11,
+  TRICORE_TRICORE_V1_3 = 12,
+  TRICORE_TRICORE_V1_3_1 = 13,
+  TRICORE_TRICORE_V1_6 = 14,
+  TRICORE_TRICORE_V1_6_1 = 15,
+  TRICORE_TRICORE_V1_6_2 = 16,
+  TRICORE_NumSubtargetFeatures = 17
+};
+#endif // GET_SUBTARGETINFO_ENUM
+
+
+
--- a/thirdparty/capstone/arch/TriCore/TriCoreInstPrinter.c
+++ b/thirdparty/capstone/arch/TriCore/TriCoreInstPrinter.c
@@ -0,0 +1,489 @@
+//===- TriCoreInstPrinter.cpp - Convert TriCore MCInst to assembly syntax -===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This class prints an TriCore MCInst to a .s file.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifdef CAPSTONE_HAS_TRICORE
+
+#include <platform.h>
+
+#include "../../MCInst.h"
+#include "../../Mapping.h"
+#include "../../MathExtras.h"
+
+#include "TriCoreMapping.h"
+#include "TriCoreLinkage.h"
+
+static const char *getRegisterName(unsigned RegNo);
+
+static void printInstruction(MCInst *, uint64_t, SStream *);
+
+static void printOperand(MCInst *MI, int OpNum, SStream *O);
+
+#define GET_INSTRINFO_ENUM
+
+#include "TriCoreGenInstrInfo.inc"
+
+#define GET_REGINFO_ENUM
+
+#include "TriCoreGenRegisterInfo.inc"
+
+static uint32_t wrapping_u32(int64_t x)
+{
+	x %= (int64_t)(UINT32_MAX);
+	return (uint32_t)x;
+}
+
+static bool fill_mem(MCInst *MI, unsigned int reg, int64_t disp);
+
+static inline void set_mem(cs_tricore_op *op, uint8_t base, int64_t disp)
+{
+	op->type |= TRICORE_OP_MEM;
+	op->mem.base = base;
+	op->mem.disp = disp;
+}
+
+static inline void fill_reg(MCInst *MI, uint32_t reg)
+{
+	if (!detail_is_set(MI))
+		return;
+	cs_tricore_op *op = TriCore_get_detail_op(MI, 0);
+	op->type = TRICORE_OP_REG;
+	op->reg = reg;
+	TriCore_inc_op_count(MI);
+}
+
+static inline void fill_imm(MCInst *MI, int64_t imm)
+{
+	if (!detail_is_set(MI))
+		return;
+	cs_tricore *tricore = TriCore_get_detail(MI);
+	if (tricore->op_count >= 1) {
+		cs_tricore_op *op = TriCore_get_detail_op(MI, -1);
+		if (op->type == TRICORE_OP_REG && fill_mem(MI, op->reg, imm))
+			return;
+	}
+
+	cs_tricore_op *op = TriCore_get_detail_op(MI, 0);
+	op->type = TRICORE_OP_IMM;
+	op->imm = imm;
+	tricore->op_count++;
+}
+
+static bool fill_mem(MCInst *MI, unsigned int reg, int64_t disp)
+{
+	if (!detail_is_set(MI))
+		return false;
+	switch (MI->flat_insn->id) {
+	case TRICORE_INS_LDMST:
+	case TRICORE_INS_LDLCX:
+	case TRICORE_INS_LD_A:
+	case TRICORE_INS_LD_B:
+	case TRICORE_INS_LD_BU:
+	case TRICORE_INS_LD_H:
+	case TRICORE_INS_LD_HU:
+	case TRICORE_INS_LD_D:
+	case TRICORE_INS_LD_DA:
+	case TRICORE_INS_LD_W:
+	case TRICORE_INS_LD_Q:
+	case TRICORE_INS_STLCX:
+	case TRICORE_INS_STUCX:
+	case TRICORE_INS_ST_A:
+	case TRICORE_INS_ST_B:
+	case TRICORE_INS_ST_H:
+	case TRICORE_INS_ST_D:
+	case TRICORE_INS_ST_DA:
+	case TRICORE_INS_ST_W:
+	case TRICORE_INS_ST_Q:
+	case TRICORE_INS_CACHEI_I:
+	case TRICORE_INS_CACHEI_W:
+	case TRICORE_INS_CACHEI_WI:
+	case TRICORE_INS_CACHEA_I:
+	case TRICORE_INS_CACHEA_W:
+	case TRICORE_INS_CACHEA_WI:
+	case TRICORE_INS_CMPSWAP_W:
+	case TRICORE_INS_SWAP_A:
+	case TRICORE_INS_SWAP_W:
+	case TRICORE_INS_SWAPMSK_W:
+	case TRICORE_INS_LEA:
+	case TRICORE_INS_LHA: {
+		switch (MCInst_getOpcode(MI)) {
+		case TRICORE_LDMST_abs:
+		case TRICORE_LDLCX_abs:
+		case TRICORE_LD_A_abs:
+		case TRICORE_LD_B_abs:
+		case TRICORE_LD_BU_abs:
+		case TRICORE_LD_H_abs:
+		case TRICORE_LD_HU_abs:
+		case TRICORE_LD_D_abs:
+		case TRICORE_LD_DA_abs:
+		case TRICORE_LD_W_abs:
+		case TRICORE_LD_Q_abs:
+		case TRICORE_STLCX_abs:
+		case TRICORE_STUCX_abs:
+		case TRICORE_ST_A_abs:
+		case TRICORE_ST_B_abs:
+		case TRICORE_ST_H_abs:
+		case TRICORE_ST_D_abs:
+		case TRICORE_ST_DA_abs:
+		case TRICORE_ST_W_abs:
+		case TRICORE_ST_Q_abs:
+		case TRICORE_SWAP_A_abs:
+		case TRICORE_SWAP_W_abs:
+		case TRICORE_LEA_abs:
+		case TRICORE_LHA_abs: {
+			return false;
+		}
+		}
+		cs_tricore_op *op = TriCore_get_detail_op(MI, -1);
+		op->type = 0;
+		set_mem(op, reg, disp);
+		return true;
+	}
+	}
+	return false;
+}
+
+static void printOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	if (OpNum >= MI->size)
+		return;
+
+	MCOperand *Op = MCInst_getOperand(MI, OpNum);
+	if (MCOperand_isReg(Op)) {
+		unsigned reg = MCOperand_getReg(Op);
+		SStream_concat0(O, getRegisterName(reg));
+		fill_reg(MI, reg);
+	} else if (MCOperand_isImm(Op)) {
+		int64_t Imm = MCOperand_getImm(Op);
+		printUInt32Bang(O, wrapping_u32(Imm));
+		fill_imm(MI, Imm);
+	}
+}
+
+static void print_sign_ext(MCInst *MI, int OpNum, SStream *O, unsigned n)
+{
+	MCOperand *MO = MCInst_getOperand(MI, OpNum);
+	if (MCOperand_isImm(MO)) {
+		int64_t imm = MCOperand_getImm(MO);
+		int32_t res = SignExtend32(wrapping_u32(imm), n);
+		printInt32Bang(O, res);
+		fill_imm(MI, res);
+	} else
+		printOperand(MI, OpNum, O);
+}
+
+static void off4_fixup(MCInst *MI, int64_t *off4)
+{
+	switch (MCInst_getOpcode(MI)) {
+	case TRICORE_LD_A_slro:
+	case TRICORE_LD_A_sro:
+	case TRICORE_LD_W_slro:
+	case TRICORE_LD_W_sro:
+	case TRICORE_ST_A_sro:
+	case TRICORE_ST_A_ssro:
+	case TRICORE_ST_W_sro:
+	case TRICORE_ST_W_ssro: {
+		*off4 = *off4 * 4;
+		break;
+	}
+	case TRICORE_LD_H_sro:
+	case TRICORE_LD_H_slro:
+	case TRICORE_ST_H_sro:
+	case TRICORE_ST_H_ssro: {
+		*off4 = *off4 * 2;
+		break;
+	}
+	}
+}
+
+static void const8_fixup(MCInst *MI, int64_t *const8)
+{
+	switch (MCInst_getOpcode(MI)) {
+	case TRICORE_LD_A_sc:
+	case TRICORE_ST_A_sc:
+	case TRICORE_ST_W_sc:
+	case TRICORE_LD_W_sc: {
+		*const8 = *const8 * 4;
+		break;
+	}
+	}
+}
+
+static void print_zero_ext(MCInst *MI, int OpNum, SStream *O, unsigned n)
+{
+	MCOperand *MO = MCInst_getOperand(MI, OpNum);
+	if (MCOperand_isImm(MO)) {
+		int64_t imm = MCOperand_getImm(MO);
+		for (unsigned i = n + 1; i < 32; ++i) {
+			imm &= ~(1LL << i);
+		}
+		if (n == 4) {
+			off4_fixup(MI, &imm);
+		}
+		if (n == 8) {
+			const8_fixup(MI, &imm);
+		}
+
+		printUInt32Bang(O, wrapping_u32(imm));
+		fill_imm(MI, imm);
+	} else
+		printOperand(MI, OpNum, O);
+}
+
+static void printOff18Imm(MCInst *MI, int OpNum, SStream *O)
+{
+	MCOperand *MO = MCInst_getOperand(MI, OpNum);
+	if (MCOperand_isImm(MO)) {
+		int64_t imm = MCOperand_getImm(MO);
+		imm = ((wrapping_u32(imm) & 0x3C000) << 14) |
+		      (wrapping_u32(imm) & 0x3fff);
+		printUInt32Bang(O, wrapping_u32(imm));
+		fill_imm(MI, imm);
+	} else
+		printOperand(MI, OpNum, O);
+}
+
+// PC + sext(2 * disp)
+#define DISP1(N) ((int64_t)(MI->address) + SignExtend64(disp * 2, N))
+// PC + sext(disp) * 2
+#define DISP2(N) ((int64_t)(MI->address) + SignExtend64(disp, N) * 2)
+
+static void printDisp24Imm(MCInst *MI, int OpNum, SStream *O)
+{
+	MCOperand *MO = MCInst_getOperand(MI, OpNum);
+	if (MCOperand_isImm(MO)) {
+		int64_t disp = MCOperand_getImm(MO);
+		int64_t res = 0;
+		switch (MCInst_getOpcode(MI)) {
+		case TRICORE_CALL_b:
+		case TRICORE_FCALL_b: {
+			res = DISP1(24);
+			break;
+		}
+		case TRICORE_CALLA_b:
+		case TRICORE_FCALLA_b:
+		case TRICORE_JA_b:
+		case TRICORE_JLA_b:
+			// = {disp24[23:20], 7’b0000000, disp24[19:0], 1’b0};
+			res = ((wrapping_u32(disp) & 0xf00000) << 28) |
+			      ((wrapping_u32(disp) & 0xfffff) << 1);
+			break;
+		case TRICORE_J_b:
+		case TRICORE_JL_b:
+			res = DISP2(24);
+			break;
+		}
+
+		printUInt32Bang(O, wrapping_u32(res));
+		fill_imm(MI, res);
+	} else
+		printOperand(MI, OpNum, O);
+}
+
+static void printDisp15Imm(MCInst *MI, int OpNum, SStream *O)
+{
+	MCOperand *MO = MCInst_getOperand(MI, OpNum);
+	if (MCOperand_isImm(MO)) {
+		int64_t disp = MCOperand_getImm(MO);
+		int64_t res = 0;
+		switch (MCInst_getOpcode(MI)) {
+		case TRICORE_LOOP_brr:
+		case TRICORE_LOOPU_brr:
+			res = DISP1(15);
+			break;
+		case TRICORE_JEQ_brc:
+		case TRICORE_JEQ_brr:
+		case TRICORE_JEQ_A_brr:
+		case TRICORE_JGE_brc:
+		case TRICORE_JGE_brr:
+		case TRICORE_JGE_U_brc:
+		case TRICORE_JGE_U_brr:
+		case TRICORE_JLT_brc:
+		case TRICORE_JLT_brr:
+		case TRICORE_JLT_U_brc:
+		case TRICORE_JLT_U_brr:
+		case TRICORE_JNE_brc:
+		case TRICORE_JNE_brr:
+		case TRICORE_JNE_A_brr:
+		case TRICORE_JNED_brc:
+		case TRICORE_JNED_brr:
+		case TRICORE_JNEI_brc:
+		case TRICORE_JNEI_brr:
+		case TRICORE_JNZ_A_brr:
+		case TRICORE_JNZ_T_brn:
+		case TRICORE_JZ_A_brr:
+		case TRICORE_JZ_T_brn:
+			res = DISP2(15);
+			break;
+		default:
+			// handle other cases, if any
+			break;
+		}
+
+		printUInt32Bang(O, wrapping_u32(res));
+		fill_imm(MI, res);
+	} else
+		printOperand(MI, OpNum, O);
+}
+
+static void printDisp8Imm(MCInst *MI, int OpNum, SStream *O)
+{
+	MCOperand *MO = MCInst_getOperand(MI, OpNum);
+	if (MCOperand_isImm(MO)) {
+		int64_t disp = MCOperand_getImm(MO);
+		int64_t res = 0;
+		switch (MCInst_getOpcode(MI)) {
+		case TRICORE_CALL_sb:
+			disp = DISP1(8);
+			break;
+		case TRICORE_J_sb:
+		case TRICORE_JNZ_sb:
+		case TRICORE_JZ_sb:
+			res = DISP2(8);
+			break;
+		default:
+			// handle other cases, if any
+			break;
+		}
+
+		printUInt32Bang(O, wrapping_u32(res));
+		fill_imm(MI, res);
+	} else
+		printOperand(MI, OpNum, O);
+}
+
+static void printDisp4Imm(MCInst *MI, int OpNum, SStream *O)
+{
+	MCOperand *MO = MCInst_getOperand(MI, OpNum);
+	if (MCOperand_isImm(MO)) {
+		int64_t disp = MCOperand_getImm(MO);
+		int64_t res = 0;
+		switch (MCInst_getOpcode(MI)) {
+		case TRICORE_JEQ_sbc1:
+		case TRICORE_JEQ_sbr1:
+		case TRICORE_JGEZ_sbr:
+		case TRICORE_JGTZ_sbr:
+		case TRICORE_JLEZ_sbr:
+		case TRICORE_JLTZ_sbr:
+		case TRICORE_JNE_sbc1:
+		case TRICORE_JNE_sbr1:
+		case TRICORE_JNZ_sbr:
+		case TRICORE_JNZ_A_sbr:
+		case TRICORE_JNZ_T_sbrn:
+		case TRICORE_JZ_sbr:
+		case TRICORE_JZ_A_sbr:
+		case TRICORE_JZ_T_sbrn:
+			// PC + zero_ext(disp4) * 2;
+			res = (int64_t)(MI->address) + disp * 2;
+			break;
+		case TRICORE_JEQ_sbc2:
+		case TRICORE_JEQ_sbr2:
+		case TRICORE_JNE_sbc2:
+		case TRICORE_JNE_sbr2:
+			// PC + zero_ext(disp4 + 16) * 2;
+			res = (int64_t)(MI->address) + ((disp + 16) * 2);
+			break;
+		case TRICORE_LOOP_sbr:
+			// PC + {27b’111111111111111111111111111, disp4, 0};
+			res = (int64_t)MI->address +
+			      OneExtend32(wrapping_u32(disp) << 1, 5);
+			break;
+		default:
+			// handle other cases, if any
+			break;
+		}
+
+		printUInt32Bang(O, wrapping_u32(res));
+		fill_imm(MI, res);
+	} else
+		printOperand(MI, OpNum, O);
+}
+
+#define printSExtImm_(n) \
+	static void printSExtImm_##n(MCInst *MI, int OpNum, SStream *O) \
+	{ \
+		print_sign_ext(MI, OpNum, O, n); \
+	}
+
+#define printZExtImm_(n) \
+	static void printZExtImm_##n(MCInst *MI, int OpNum, SStream *O) \
+	{ \
+		print_zero_ext(MI, OpNum, O, n); \
+	}
+
+// clang-format off
+
+printSExtImm_(16)
+
+printSExtImm_(10)
+
+printSExtImm_(9)
+
+printSExtImm_(4)
+
+printZExtImm_(16)
+
+printZExtImm_(9)
+
+printZExtImm_(8)
+
+printZExtImm_(4)
+
+printZExtImm_(2);
+
+// clang-format on
+
+static void printOExtImm_4(MCInst *MI, int OpNum, SStream *O)
+{
+	MCOperand *MO = MCInst_getOperand(MI, OpNum);
+	if (MCOperand_isImm(MO)) {
+		int64_t disp = MCOperand_getImm(MO);
+		int64_t res = (int64_t)MI->address +
+			      (int64_t)OneExtend64(disp << 1, 5);
+		printUInt32Bang(O, wrapping_u32(res));
+		fill_imm(MI, res);
+	} else
+		printOperand(MI, OpNum, O);
+}
+
+/// Returned by getMnemonic() of the AsmPrinters.
+typedef struct {
+	const char *first; // Mnemonic
+	uint64_t second;   // Bits
+} MnemonicBitsInfo;
+
+static void set_mem_access(MCInst *MI, unsigned int access)
+{
+	// TODO: TriCore
+}
+
+#include "TriCoreGenAsmWriter.inc"
+
+const char *TriCore_LLVM_getRegisterName(unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	return getRegisterName(id);
+#else
+	return NULL;
+#endif
+}
+
+void TriCore_LLVM_printInst(MCInst *MI, uint64_t Address, SStream *O)
+{
+	printInstruction(MI, Address, O);
+	TriCore_set_access(MI);
+}
+
+#endif // CAPSTONE_HAS_TRICORE
--- a/thirdparty/capstone/arch/TriCore/TriCoreInstrFormats.td
+++ b/thirdparty/capstone/arch/TriCore/TriCoreInstrFormats.td
@@ -0,0 +1,773 @@
+//==-- TriCoreInstrFormats.td - TriCore Instruction Formats -*- tablegen -*-==//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+//  Describe TriCore instructions format
+//
+//  CPU INSTRUCTION FORMATS
+//
+//  op1     - primary operation code
+//  op2     - secondary operation code
+//  s1      - source register 1
+//  s2      - source register 2
+//  s3      - source register 3
+//  d       - destination register
+//  b       - bit value
+//  n       -
+//            - multiplication result shift value (0b00 or 0b01)
+//            - address shift value in add scale
+//            - default to zero in all other operations using the RR format
+//            - coprocessor number for coprocessor instructions
+//  const[b=(4|9|16)]  - b bits immediate value
+//  disp[b=(4|8|15|24)]  - b bits displacement value
+//  off[b=(4|10|16)] - b bits offset value
+//
+//===----------------------------------------------------------------------===//
+
+class InstTriCore<dag outs, dag ins, string asmstr, list<dag> pattern>
+    : Instruction {
+
+  let Namespace = "TriCore";
+  /// outs and ins are inherited from the instruction class.
+  dag OutOperandList = outs;
+  dag InOperandList  = ins;
+  let AsmString   = asmstr;
+  let Pattern = pattern;
+}
+
+// TriCore pseudo instructions format
+class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
+   : InstTriCore<outs, ins, asmstr, pattern> {
+  let isPseudo = 1;
+}
+
+//===----------------------------------------------------------------------===//
+// Generic 16-bit Instruction Format
+//===----------------------------------------------------------------------===//
+class T16<dag outs, dag ins, string asmstr, list<dag> pattern>
+    : InstTriCore<outs, ins, asmstr, pattern> {
+  field bits<16> Inst;
+  let Size = 2;
+  field bits<16> SoftFail = 0;
+}
+
+//===----------------------------------------------------------------------===//
+// Generic 32-bit Instruction Format
+//===----------------------------------------------------------------------===//
+class T32<dag outs, dag ins, string asmstr, list<dag> pattern>
+    : InstTriCore<outs, ins, asmstr, pattern> {
+  field bits<32> Inst;
+  let Size = 4;
+  field bits<32> SoftFail = 0;
+}
+
+//===----------------------------------------------------------------------===//
+// 16-bit SB Instruction Format: <disp8|op1>
+//===----------------------------------------------------------------------===//
+class SB<bits<8> op1, dag outs, dag ins, string asmstr, list<dag> pattern>
+        : T16<outs, ins, asmstr, pattern> {
+
+  bits<8> disp8;
+  let Inst{15-8} = disp8;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeSBInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 16-bit SBC Instruction Format: <const4|disp4|op1>
+//===----------------------------------------------------------------------===//
+class SBC<bits<8> op1, dag outs, dag ins, string asmstr, list<dag> pattern>
+        : T16<outs, ins, asmstr, pattern> {
+
+  bits<4> const4;
+  bits<4> disp4;
+
+  let Inst{15-12} = const4;
+  let Inst{11-8} = disp4;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeSBCInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 16-bit SBR Instruction Format: <s2|disp4|op1>
+//===----------------------------------------------------------------------===//
+class SBR<bits<8> op1, dag outs, dag ins, string asmstr, list<dag> pattern>
+        : T16<outs, ins, asmstr, pattern> {
+
+  bits<4> s2;
+  bits<4> disp4;
+
+  let Inst{15-12} = s2;
+  let Inst{11-8} = disp4;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeSBRInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 16-bit SBRN Instruction Format: <n|disp4|op1>
+//===----------------------------------------------------------------------===//
+class SBRN<bits<8> op1, dag outs, dag ins, string asmstr, list<dag> pattern>
+        : T16<outs, ins, asmstr, pattern> {
+
+  bits<4> n;
+  bits<4> disp4;
+
+  let Inst{15-12} = n;
+  let Inst{11-8} = disp4;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeSBRNInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 16-bit SC Instruction Format: <const8|op1>
+//===----------------------------------------------------------------------===//
+class SC<bits<8> op1, dag outs, dag ins, string asmstr, list<dag> pattern>
+    : T16<outs, ins, asmstr, pattern> {
+
+  bits<8> const8;
+
+  let Inst{15-8} = const8;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeSCInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 16-bit SLR Instruction Format: <s2|d|op1>
+//===----------------------------------------------------------------------===//
+class SLR<bits<8> op1, dag outs, dag ins, string asmstr, list<dag> pattern>
+    : T16<outs, ins, asmstr, pattern> {
+
+  bits<4> s2;
+  bits<4> d;
+
+  let Inst{15-12} = s2;
+  let Inst{11-8} = d;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeSLRInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 16-bit SLRO Instruction Format: <off4|d|op1>
+//===----------------------------------------------------------------------===//
+class SLRO<bits<8> op1, dag outs, dag ins, string asmstr, list<dag> pattern>
+    : T16<outs, ins, asmstr, pattern> {
+
+  bits<4> off4;
+  bits<4> d;
+
+  let Inst{15-12} = off4;
+  let Inst{11-8} = d;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeSLROInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 16-bit SR Instruction Format: <op2|s1/d|op1>
+//===----------------------------------------------------------------------===//
+class SR<bits<8> op1, bits<4> op2, dag outs, dag ins, string asmstr,
+      list<dag> pattern> : T16<outs, ins, asmstr, pattern> {
+
+  bits<4> s1_d;
+
+  let Inst{15-12} = op2;
+  let Inst{11-8} = s1_d;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeSRInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 16-bit SRC Instruction Format: <const4|s1/d|op1>
+//===----------------------------------------------------------------------===//
+class SRC<bits<8> op1, dag outs, dag ins, string asmstr, list<dag> pattern>
+    : T16<outs, ins, asmstr, pattern> {
+
+  bits<4> const4;
+  bits<4> s1_d;
+
+  let Inst{15-12} = const4;
+  let Inst{11-8} = s1_d;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeSRCInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 16-bit SRO Instruction Format: <s2|off4|op1>
+//===----------------------------------------------------------------------===//
+class SRO<bits<8> op1, dag outs, dag ins, string asmstr, list<dag> pattern>
+    : T16<outs, ins, asmstr, pattern> {
+
+  bits<4> s2;
+  bits<4> off4;
+
+  let Inst{15-12} = s2;
+  let Inst{11-8} = off4;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeSROInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 16-bit SRR Instruction Format: <s2|s1/d|op1>
+//===----------------------------------------------------------------------===//
+class SRR<bits<8> op1, dag outs, dag ins, string asmstr, list<dag> pattern>
+    : T16<outs, ins, asmstr, pattern> {
+
+  bits<4> s2;
+  bits<4> s1_d;
+
+  let Inst{15-12} = s2;
+  let Inst{11-8} = s1_d;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeSRRInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 16-bit SRRS Instruction Format: <s2|s1/d|n|op1>
+//===----------------------------------------------------------------------===//
+class SRRS<bits<6> op1, dag outs, dag ins, string asmstr, list<dag> pattern>
+    : T16<outs, ins, asmstr, pattern> {
+
+  bits<4> s2;
+  bits<4> s1_d;
+  bits<2> n;
+
+  let Inst{15-12} = s2;
+  let Inst{11-8} = s1_d;
+  let Inst{7-6} = n;
+  let Inst{5-0} = op1;
+  let DecoderMethod = "DecodeSRRSInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 16-bit SSR Instruction Format: <s2|s1/d|op1>
+//===----------------------------------------------------------------------===//
+class SSR<bits<8> op1, dag outs, dag ins, string asmstr, list<dag> pattern>
+    : T16<outs, ins, asmstr, pattern> {
+
+  bits<4> s2;
+  bits<4> s1;
+
+  let Inst{15-12} = s2;
+  let Inst{11-8} = s1;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeSSRInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 16-bit SSRO Instruction Format: <s2|s1/d|op1>
+//===----------------------------------------------------------------------===//
+class SSRO<bits<8> op1, dag outs, dag ins, string asmstr, list<dag> pattern>
+    : T16<outs, ins, asmstr, pattern> {
+
+  bits<4> off4;
+  bits<4> s1;
+
+  let Inst{15-12} = off4;
+  let Inst{11-8} = s1;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeSSROInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit ABS Instruction Format:
+// <off18[9:6]|op2|off18[13:10]|off18[5:0]|off18[17:14]|s1/d|op1>
+//===----------------------------------------------------------------------===//
+class ABS<bits<8> op1, bits<2> op2, dag outs, dag ins, string asmstr,
+                 list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<18> off18;
+  bits<4> s1_d;
+
+  let Inst{31-28} = off18{9-6};
+  let Inst{27-26} = op2;
+  let Inst{25-22} = off18{13-10};
+  let Inst{21-16} = off18{5-0};
+  let Inst{15-12} = off18{17-14};
+  let Inst{11-8} = s1_d;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeABSInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit ABSB Instruction Format:
+// <off18[9:6]|op2|off18[13:10]|off18[5:0]|off18[17:14]|b|bpos3|op1>
+//===----------------------------------------------------------------------===//
+class ABSB<bits<8> op1, bits<2> op2, dag outs, dag ins, string asmstr,
+                 list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<18> off18;
+  bits<1> b;
+  bits<3> bpos3;
+
+  let Inst{31-28} = off18{9-6};
+  let Inst{27-26} = op2;
+  let Inst{25-22} = off18{13-10};
+  let Inst{21-16} = off18{5-0};
+  let Inst{15-12} = off18{17-14};
+  let Inst{11} = b;
+  let Inst{10-8} = bpos3;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeABSBInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit B Instruction Format:
+// <disp24[15:0]|disp24[23:16]|op1>
+//===----------------------------------------------------------------------===//
+class B<bits<8> op1, dag outs, dag ins, string asmstr,
+                 list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<24> disp24;
+
+  let Inst{31-16} = disp24{15-0};
+  let Inst{15-8} = disp24{23-16};
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeBInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit BIT Instruction Format: <d|pos2|op2|pos1|s2|s1|op1>
+//===----------------------------------------------------------------------===//
+class BIT<bits<8> op1, bits<2> op2, dag outs, dag ins, string asmstr,
+                 list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<4> d;
+  bits<5> pos2;
+  bits<5> pos1;
+  bits<4> s2;
+  bits<4> s1;
+
+  let Inst{31-28} = d;
+  let Inst{27-23} = pos2;
+  let Inst{22-21} = op2;
+  let Inst{20-16} = pos1;
+  let Inst{15-12} = s2;
+  let Inst{11-8} = s1;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeBITInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit BO Instruction Format: <off10[9:6]|op2|off10[5:0]|s2|s1/d|op1>
+//===----------------------------------------------------------------------===//
+class BO<bits<8> op1, bits<6> op2, dag outs, dag ins, string asmstr,
+                 list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<10> off10;
+  bits<4> s2;
+  bits<4> s1_d;
+
+  let Inst{31-28} = off10{9-6};
+  let Inst{27-22} = op2;
+  let Inst{21-16} = off10{5-0};
+  let Inst{15-12} = s2;
+  let Inst{11-8} = s1_d;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeBOInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit BOL Instruction Format:
+// <off16[9:6]|off16[15:10]|off16[5:0]|s2|s1/d|op1>
+//===----------------------------------------------------------------------===//
+class BOL<bits<8> op1, dag outs, dag ins, string asmstr,
+                 list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<16> off16;
+  bits<4> s2;
+  bits<4> s1_d;
+
+  let Inst{31-28} = off16{9-6};
+  let Inst{27-22} = off16{15-10};
+  let Inst{21-16} = off16{5-0};
+  let Inst{15-12} = s2;
+  let Inst{11-8} = s1_d;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeBOLInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit BRC Instruction Format: <op2|disp15|const4|s1|op1>
+//===----------------------------------------------------------------------===//
+class BRC<bits<8> op1, bits<1> op2, dag outs, dag ins, string asmstr,
+                 list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<15> disp15;
+  bits<4> const4;
+  bits<4> s1;
+
+  let Inst{31} = op2;
+  let Inst{30-16} = disp15;
+  let Inst{15-12} = const4;
+  let Inst{11-8} = s1;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeBRCInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit BRN Instruction Format: <op2|disp15|n[3:0]|s1|n[4]|op1>
+//===----------------------------------------------------------------------===//
+class BRN<bits<7> op1, bits<1> op2, dag outs, dag ins, string asmstr,
+                 list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<15> disp15;
+  bits<5> n;
+  bits<4> s1;
+
+  let Inst{31} = op2;
+  let Inst{30-16} = disp15;
+  let Inst{15-12} = n{3-0};
+  let Inst{11-8} = s1;
+  let Inst{7} = n{4};
+  let Inst{6-0} = op1;
+  let DecoderMethod = "DecodeBRNInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit BRR Instruction Format: <op2|disp15|const4|s1|op1>
+//===----------------------------------------------------------------------===//
+class BRR<bits<8> op1, bits<1> op2, dag outs, dag ins, string asmstr,
+                 list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<15> disp15;
+  bits<4> s2;
+  bits<4> s1;
+
+  let Inst{31} = op2;
+  let Inst{30-16} = disp15;
+  let Inst{15-12} = s2;
+  let Inst{11-8} = s1;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeBRRInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit RC Instruction Format: <d|op2|const9|s1|op1>
+//===----------------------------------------------------------------------===//
+class RC<bits<8> op1, bits<7> op2, dag outs, dag ins, string asmstr,
+                  list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<4> d;
+  bits<9> const9;
+  bits<4> s1;
+
+  let Inst{31-28} = d;
+  let Inst{27-21} = op2;
+  let Inst{20-12} = const9;
+  let Inst{11-8} = s1;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeRCInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit RCPW Instruction Format: <d|pos|op2|width|const4|s1|op1>
+//===----------------------------------------------------------------------===//
+class RCPW<bits<8> op1, bits<2> op2 , dag outs, dag ins, string asmstr,
+                list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<4> d;
+  bits<5> pos;
+  bits<5> width;
+  bits<4> const4;
+  bits<4> s1;
+
+  let Inst{31-28} = d;
+  let Inst{27-23} = pos;
+  let Inst{22-21} = op2;
+  let Inst{20-16} = width;
+  let Inst{15-12} = const4;
+  let Inst{11-8} = s1;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeRCPWInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit RCR Instruction Format: <d|s3|op2|const9|s1|op1>
+//===----------------------------------------------------------------------===//
+class RCR<bits<8> op1, bits<3> op2, dag outs, dag ins, string asmstr,
+                list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<4> d;
+  bits<4> s3;
+  bits<9> const9;
+  bits<4> s1;
+
+  let Inst{31-28} = d;
+  let Inst{27-24} = s3;
+  let Inst{23-21} = op2;
+  let Inst{20-12} = const9;
+  let Inst{11-8} = s1;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeRCRInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit RCRR Instruction Format: <d|s3|op2|-|const4|s1|op1>
+//===----------------------------------------------------------------------===//
+class RCRR<bits<8> op1, bits<3> op2, dag outs, dag ins, string asmstr,
+                list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<4> d;
+  bits<4> s3;
+  bits<4> const4;
+  bits<4> s1;
+
+  let Inst{31-28} = d;
+  let Inst{27-24} = s3;
+  let Inst{23-21} = op2;
+  let Inst{20-16} = 0;
+  let Inst{15-12} = const4;
+  let Inst{11-8} = s1;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeRCRRInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit RCRW Instruction Format: <d|s3|op2|width|const4|s1|op1>
+//===----------------------------------------------------------------------===//
+class RCRW<bits<8> op1, bits<3> op2, dag outs, dag ins, string asmstr,
+                list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<4> d;
+  bits<4> s3;
+  bits<5> width;
+  bits<4> const4;
+  bits<4> s1;
+
+  let Inst{31-28} = d;
+  let Inst{27-24} = s3;
+  let Inst{23-21} = op2;
+  let Inst{20-16} = width;
+  let Inst{15-12} = const4;
+  let Inst{11-8} = s1;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeRCRWInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit RLC Instruction Format: <d|const16|s1|op1>
+//===----------------------------------------------------------------------===//
+class RLC<bits<8> op1, dag outs, dag ins, string asmstr,
+                 list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<4> d;
+  bits<16> const16;
+  bits<4> s1;
+
+  let Inst{31-28} = d;
+  let Inst{27-12} = const16;
+  let Inst{11-8} = s1;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeRLCInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit RR Instruction Format: <d|op2|-|n|s2|s1|op1>
+//===----------------------------------------------------------------------===//
+class RR<bits<8> op1, bits<8> op2, dag outs, dag ins, string asmstr,
+                 list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<4> d;
+  bits<2> n;
+  bits<4> s2;
+  bits<4> s1;
+
+  let Inst{31-28} = d;
+  let Inst{27-20} = op2;
+  let Inst{19-18} = 0;
+  let Inst{17-16} = n;
+  let Inst{15-12} = s2;
+  let Inst{11-8} = s1;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeRRInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit RR1 Instruction Format: <d|op2|n|s2|s1|op1>
+//===----------------------------------------------------------------------===//
+class RR1<bits<8> op1, bits<10> op2, dag outs, dag ins, string asmstr,
+                 list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<4> d;
+  bits<2> n;
+  bits<4> s2;
+  bits<4> s1;
+
+
+  let Inst{31-28} = d;
+  let Inst{27-18} = op2;
+  let Inst{17-16} = n;
+  let Inst{15-12} = s2;
+  let Inst{11-8} = s1;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeRR1Instruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit RR2 Instruction Format: <d|op2|s2|s1|op1>
+//===----------------------------------------------------------------------===//
+class RR2<bits<8> op1, bits<12> op2, dag outs, dag ins, string asmstr,
+                 list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<4> d;
+  bits<4> s2;
+  bits<4> s1;
+
+  let Inst{31-28} = d;
+  let Inst{27-16} = op2;
+  let Inst{15-12} = s2;
+  let Inst{11-8} = s1;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeRR2Instruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit RRPW Instruction Format: <d|pos|op2|width|s2|s1|op1>
+//===----------------------------------------------------------------------===//
+class RRPW<bits<8> op1, bits<2> op2, dag outs, dag ins, string asmstr,
+                list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<4> d;
+  bits<5> pos;
+  bits<5> width;
+  bits<4> s2;
+  bits<4> s1;
+
+  let Inst{31-28} = d;
+  let Inst{27-23} = pos;
+  let Inst{22-21} = op2;
+  let Inst{20-16} = width;
+  let Inst{15-12} = s2;
+  let Inst{11-8} = s1;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeRRPWInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit RRR Instruction Format: <d|s3|op2|-|n|s2|s1|op1>
+//===----------------------------------------------------------------------===//
+class RRR<bits<8> op1, bits<4> op2, dag outs, dag ins, string asmstr,
+                list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<4> d;
+  bits<4> s3;
+  bits<2> n;
+  bits<4> s2;
+  bits<4> s1;
+
+  let Inst{31-28} = d;
+  let Inst{27-24} = s3;
+  let Inst{23-20} = op2;
+  let Inst{19-18} = 0;
+  let Inst{17-16} = n;
+  let Inst{15-12} = s2;
+  let Inst{11-8} = s1;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeRRRInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit RRR1 Instruction Format: <d|s3|op2|n|s2|s1|op1>
+//===----------------------------------------------------------------------===//
+class RRR1<bits<8> op1, bits<6> op2, dag outs, dag ins, string asmstr,
+                list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<4> d;
+  bits<4> s3;
+  bits<2> n;
+  bits<4> s2;
+  bits<4> s1;
+
+  let Inst{31-28} = d;
+  let Inst{27-24} = s3;
+  let Inst{23-18} = op2;
+  let Inst{17-16} = n;
+  let Inst{15-12} = s2;
+  let Inst{11-8} = s1;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeRRR1Instruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit RRR2 Instruction Format: <d|s3|op2|s2|s1|op1>
+//===----------------------------------------------------------------------===//
+class RRR2<bits<8> op1, bits<8> op2, dag outs, dag ins, string asmstr,
+                list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<4> s1;
+  bits<4> s2;
+  bits<4> s3;
+  bits<4> d;
+
+  let Inst{31-28} = d;
+  let Inst{27-24} = s3;
+  let Inst{23-16} = op2;
+  let Inst{15-12} = s2;
+  let Inst{11-8} = s1;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeRRR2Instruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit RRRR Instruction Format: <d|s3|op2|-|s2|s1|op1>
+//===----------------------------------------------------------------------===//
+class RRRR<bits<8> op1, bits<3> op2, dag outs, dag ins, string asmstr,
+                list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<4> d;
+  bits<4> s3;
+  bits<4> s2;
+  bits<4> s1;
+
+  let Inst{31-28} = d;
+  let Inst{27-24} = s3;
+  let Inst{23-21} = op2;
+  let Inst{20-16} = 0;
+  let Inst{15-12} = s2;
+  let Inst{11-8} = s1;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeRRRRInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit RRRW Instruction Format: <d|s3|op2|width|s2|s1|op1>
+//===----------------------------------------------------------------------===//
+class RRRW<bits<8> op1, bits<3> op2, dag outs, dag ins, string asmstr,
+                list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<4> d;
+  bits<4> s3;
+  bits<5> width;
+  bits<4> s2;
+  bits<4> s1;  
+
+  let Inst{31-28} = d;
+  let Inst{27-24} = s3;
+  let Inst{23-21} = op2;
+  let Inst{20-16} = width;
+  let Inst{15-12} = s2;
+  let Inst{11-8} = s1;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeRRRWInstruction";
+}
+
+//===----------------------------------------------------------------------===//
+// 32-bit SYS Instruction Format: <-|op2|-|s1/d|op1>
+//===----------------------------------------------------------------------===//
+class SYS<bits<8> op1, bits<6> op2, dag outs, dag ins, string asmstr,
+                list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
+
+  bits<4> s1_d;
+
+  let Inst{31-28} = 0;
+  let Inst{27-22} = op2;
+  let Inst{21-12} = 0;
+  let Inst{11-8} = s1_d;
+  let Inst{7-0} = op1;
+  let DecoderMethod = "DecodeSYSInstruction";
+}
--- a/thirdparty/capstone/arch/TriCore/TriCoreInstrInfo.td
+++ b/thirdparty/capstone/arch/TriCore/TriCoreInstrInfo.td
--- a/thirdparty/capstone/arch/TriCore/TriCoreLinkage.h
+++ b/thirdparty/capstone/arch/TriCore/TriCoreLinkage.h
@@ -0,0 +1,21 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+
+#ifndef CS_TRICORE_LINKAGE_H
+#define CS_TRICORE_LINKAGE_H
+
+// Function definitions to call static LLVM functions.
+
+#include "../../MCDisassembler.h"
+#include "../../MCInst.h"
+#include "../../MCRegisterInfo.h"
+#include "../../SStream.h"
+#include "capstone/capstone.h"
+
+bool TriCore_LLVM_getInstruction(csh handle, const uint8_t *Bytes,
+				 size_t ByteLen, MCInst *MI, uint16_t *Size,
+				 uint64_t Address, void *Info);
+const char *TriCore_LLVM_getRegisterName(unsigned RegNo);
+void TriCore_LLVM_printInst(MCInst *MI, uint64_t Address, SStream *O);
+
+#endif // CS_TRICORE_LINKAGE_H
--- a/thirdparty/capstone/arch/TriCore/TriCoreMapping.c
+++ b/thirdparty/capstone/arch/TriCore/TriCoreMapping.c
@@ -0,0 +1,229 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifdef CAPSTONE_HAS_TRICORE
+
+#include <stdio.h> // debug
+#include <string.h>
+#include <assert.h>
+
+#include "../../Mapping.h"
+#include "../../utils.h"
+#include "../../cs_simple_types.h"
+
+#include "TriCoreMapping.h"
+#include "TriCoreLinkage.h"
+
+#define GET_INSTRINFO_ENUM
+
+#include "TriCoreGenInstrInfo.inc"
+
+static const insn_map insns[] = {
+	// dummy item
+	{ 0,
+	  0,
+#ifndef CAPSTONE_DIET
+	  { 0 },
+	  { 0 },
+	  { 0 },
+	  0,
+	  0
+#endif
+	},
+
+#include "TriCoreGenCSMappingInsn.inc"
+};
+
+void TriCore_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
+{
+	// Not used. Information is set after disassembly.
+}
+
+#ifndef CAPSTONE_DIET
+static const tricore_reg flag_regs[] = { TRICORE_REG_PSW };
+#endif // CAPSTONE_DIET
+
+static inline void check_updates_flags(MCInst *MI)
+{
+#ifndef CAPSTONE_DIET
+	if (!MI->flat_insn->detail)
+		return;
+	cs_detail *detail = MI->flat_insn->detail;
+	for (int i = 0; i < detail->regs_write_count; ++i) {
+		if (detail->regs_write[i] == 0)
+			return;
+		for (int j = 0; j < ARR_SIZE(flag_regs); ++j) {
+			if (detail->regs_write[i] == flag_regs[j]) {
+				detail->tricore.update_flags = true;
+				return;
+			}
+		}
+	}
+#endif // CAPSTONE_DIET
+}
+
+void TriCore_set_instr_map_data(MCInst *MI)
+{
+	map_cs_id(MI, insns, ARR_SIZE(insns));
+	map_implicit_reads(MI, insns);
+	map_implicit_writes(MI, insns);
+	check_updates_flags(MI);
+	map_groups(MI, insns);
+}
+
+#ifndef CAPSTONE_DIET
+
+static const char * const insn_names[] = {
+	NULL,
+
+#include "TriCoreGenCSMappingInsnName.inc"
+};
+
+// special alias insn
+static const name_map alias_insn_names[] = { { 0, NULL } };
+#endif
+
+const char *TriCore_insn_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	unsigned int i;
+
+	if (id >= TRICORE_INS_ENDING)
+		return NULL;
+
+	// handle special alias first
+	for (i = 0; i < ARR_SIZE(alias_insn_names); i++) {
+		if (alias_insn_names[i].id == id)
+			return alias_insn_names[i].name;
+	}
+
+	return insn_names[id];
+#else
+	return NULL;
+#endif
+}
+
+#ifndef CAPSTONE_DIET
+static const name_map group_name_maps[] = {
+	{ TRICORE_GRP_INVALID, NULL },
+	{ TRICORE_GRP_CALL, "call" },
+	{ TRICORE_GRP_JUMP, "jump" },
+};
+#endif
+
+const char *TriCore_group_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	if (id >= TRICORE_GRP_ENDING)
+		return NULL;
+
+	return group_name_maps[id].name;
+#else
+	return NULL;
+#endif
+}
+
+#ifndef CAPSTONE_DIET
+static const map_insn_ops insn_operands[] = {
+#include "TriCoreGenCSMappingInsnOp.inc"
+};
+#endif
+
+void TriCore_set_access(MCInst *MI)
+{
+#ifndef CAPSTONE_DIET
+	if (!(MI->csh->detail_opt == CS_OPT_ON && MI->flat_insn->detail))
+		return;
+
+	assert(MI->Opcode < ARR_SIZE(insn_operands));
+
+	cs_detail *detail = MI->flat_insn->detail;
+	cs_tricore *tc = &(detail->tricore);
+	for (int i = 0; i < tc->op_count; ++i) {
+		cs_ac_type ac = map_get_op_access(MI, i);
+		cs_tricore_op *op = &tc->operands[i];
+		op->access = ac;
+		cs_op_type op_type = map_get_op_type(MI, i);
+		if (op_type != CS_OP_REG) {
+			continue;
+		}
+		if (ac & CS_AC_READ) {
+			detail->regs_read[detail->regs_read_count++] = op->reg;
+		}
+		if (ac & CS_AC_WRITE) {
+			detail->regs_write[detail->regs_write_count++] =
+				op->reg;
+		}
+	}
+#endif
+}
+
+void TriCore_reg_access(const cs_insn *insn, cs_regs regs_read,
+			uint8_t *regs_read_count, cs_regs regs_write,
+			uint8_t *regs_write_count)
+{
+#ifndef CAPSTONE_DIET
+	uint8_t read_count, write_count;
+	cs_detail *detail = insn->detail;
+	read_count = detail->regs_read_count;
+	write_count = detail->regs_write_count;
+
+	// implicit registers
+	memcpy(regs_read, detail->regs_read,
+	       read_count * sizeof(detail->regs_read[0]));
+	memcpy(regs_write, detail->regs_write,
+	       write_count * sizeof(detail->regs_write[0]));
+
+	// explicit registers
+	cs_tricore *tc = &detail->tricore;
+	for (uint8_t i = 0; i < tc->op_count; i++) {
+		cs_tricore_op *op = &(tc->operands[i]);
+		switch ((int)op->type) {
+		case TRICORE_OP_REG:
+			if ((op->access & CS_AC_READ) &&
+			    !arr_exist(regs_read, read_count, op->reg)) {
+				regs_read[read_count] = (uint16_t)op->reg;
+				read_count++;
+			}
+			if ((op->access & CS_AC_WRITE) &&
+			    !arr_exist(regs_write, write_count, op->reg)) {
+				regs_write[write_count] = (uint16_t)op->reg;
+				write_count++;
+			}
+			break;
+		case TRICORE_OP_MEM:
+			// registers appeared in memory references always being read
+			if ((op->mem.base != ARM_REG_INVALID) &&
+			    !arr_exist(regs_read, read_count, op->mem.base)) {
+				regs_read[read_count] = (uint16_t)op->mem.base;
+				read_count++;
+			}
+		default:
+			break;
+		}
+	}
+
+	*regs_read_count = read_count;
+	*regs_write_count = write_count;
+#endif
+}
+
+bool TriCore_getInstruction(csh handle, const uint8_t *Bytes, size_t ByteLen,
+			    MCInst *MI, uint16_t *Size, uint64_t Address,
+			    void *Info)
+{
+	return TriCore_LLVM_getInstruction(handle, Bytes, ByteLen, MI, Size,
+					   Address, Info);
+}
+
+void TriCore_printInst(MCInst *MI, SStream *O, void *Info)
+{
+	TriCore_LLVM_printInst(MI, MI->address, O);
+}
+
+const char *TriCore_getRegisterName(csh handle, unsigned int RegNo)
+{
+	return TriCore_LLVM_getRegisterName(RegNo);
+}
+
+#endif // CAPSTONE_HAS_TRICORE
--- a/thirdparty/capstone/arch/TriCore/TriCoreMapping.h
+++ b/thirdparty/capstone/arch/TriCore/TriCoreMapping.h
@@ -0,0 +1,32 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifndef CS_TRICORE_MAP_H
+#define CS_TRICORE_MAP_H
+
+#include <capstone/capstone.h>
+
+// given internal insn id, return public instruction info
+void TriCore_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
+
+const char *TriCore_insn_name(csh handle, unsigned int id);
+
+const char *TriCore_group_name(csh handle, unsigned int id);
+
+void TriCore_reg_access(const cs_insn *insn, cs_regs regs_read,
+			uint8_t *regs_read_count, cs_regs regs_write,
+			uint8_t *regs_write_count);
+
+void TriCore_set_access(MCInst *MI);
+
+void TriCore_set_instr_map_data(MCInst *MI);
+
+bool TriCore_getInstruction(csh handle, const uint8_t *Bytes, size_t ByteLen,
+			    MCInst *MI, uint16_t *Size, uint64_t Address,
+			    void *Info);
+
+void TriCore_printInst(MCInst *MI, SStream *O, void *Info);
+
+const char *TriCore_getRegisterName(csh handle, unsigned int RegNo);
+
+#endif
--- a/thirdparty/capstone/arch/TriCore/TriCoreModule.c
+++ b/thirdparty/capstone/arch/TriCore/TriCoreModule.c
@@ -0,0 +1,47 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifdef CAPSTONE_HAS_TRICORE
+
+#include "../../utils.h"
+#include "TriCoreMapping.h"
+#include "TriCoreModule.h"
+#include "TriCoreDisassembler.h"
+
+cs_err TRICORE_global_init(cs_struct *ud)
+{
+	MCRegisterInfo *mri;
+
+	mri = cs_mem_malloc(sizeof(*mri));
+
+	TriCore_init_mri(mri);
+	ud->printer = TriCore_printInst;
+	ud->printer_info = mri;
+	ud->getinsn_info = mri;
+	ud->disasm = TriCore_getInstruction;
+	ud->post_printer = NULL;
+
+	ud->reg_name = TriCore_getRegisterName;
+	ud->insn_id = TriCore_get_insn_id;
+	ud->insn_name = TriCore_insn_name;
+	ud->group_name = TriCore_group_name;
+
+#ifndef CAPSTONE_DIET
+	ud->reg_access = TriCore_reg_access;
+#endif
+
+	return CS_ERR_OK;
+}
+
+cs_err TRICORE_option(cs_struct *handle, cs_opt_type type, size_t value)
+{
+	if (type == CS_OPT_SYNTAX) {
+		handle->syntax = (int)value;
+	} else if (type == CS_OPT_MODE) {
+		handle->mode = (cs_mode)value;
+	}
+
+	return CS_ERR_OK;
+}
+
+#endif
--- a/thirdparty/capstone/arch/TriCore/TriCoreModule.h
+++ b/thirdparty/capstone/arch/TriCore/TriCoreModule.h
@@ -0,0 +1,11 @@
+//
+// Created by aya on 3/4/23.
+//
+
+#ifndef CAPSTONE_TRICODEMODULE_H
+#define CAPSTONE_TRICODEMODULE_H
+
+cs_err TRICORE_global_init(cs_struct *ud);
+cs_err TRICORE_option(cs_struct *handle, cs_opt_type type, size_t value);
+
+#endif // CAPSTONE_TRICODEMODULE_H
--- a/thirdparty/capstone/arch/TriCore/TriCoreRegisterInfo.td
+++ b/thirdparty/capstone/arch/TriCore/TriCoreRegisterInfo.td
@@ -0,0 +1,153 @@
+//==-- TriCoreRegisterInfo.td - TriCore Register defs ------*- tablegen -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+//  Declarations that describe the TriCore register file
+//===----------------------------------------------------------------------===//
+
+class TriCoreReg<string n, list<string> altNames = []> : Register<n, altNames> {
+  field bits<16> Num;
+  let Namespace = "TriCore";
+  let HWEncoding = Num;
+}
+
+// General Purpose Data Registers
+class TriCoreDataReg<bits<16> num, string n, list<string> altNames = []> : TriCoreReg<n, altNames> {
+  let Num = num;
+}
+
+// General Purpose Address Registers
+class TriCoreAddrReg<bits<16> num, string n, list<string> altNames = []> : TriCoreReg<n, altNames> {
+  let Num = num;
+}
+
+// Program Status Register
+class TriCorePSReg<bits<16> num, string n, list<string> altNames = []> : TriCoreReg<n, altNames> {
+  let Num = num;
+}
+
+class TriCoreRegWithSubregs<bits<16> num, string n, list<Register> subregs>
+: RegisterWithSubRegs<n, subregs> {
+  field bits<16> Num;
+
+  let Num = num;
+  let Namespace = "TriCore";
+}
+
+//===----------------------------------------------------------------------===//
+//@Registers
+//===----------------------------------------------------------------------===//
+// The register string, such as "d0" or "d13" will show on "llvm-objdump -d"
+
+def D0 : TriCoreDataReg<0, "d0">, DwarfRegNum<[0]>;
+def D1 : TriCoreDataReg<1, "d1">, DwarfRegNum<[1]>;
+def D2 : TriCoreDataReg<2, "d2">, DwarfRegNum<[2]>;
+def D3 : TriCoreDataReg<3, "d3">, DwarfRegNum<[3]>;
+def D4 : TriCoreDataReg<4, "d4">, DwarfRegNum<[4]>;
+def D5 : TriCoreDataReg<5, "d5">, DwarfRegNum<[5]>;
+def D6 : TriCoreDataReg<6, "d6">, DwarfRegNum<[6]>;
+def D7 : TriCoreDataReg<7, "d7">, DwarfRegNum<[7]>;
+def D8 : TriCoreDataReg<8, "d8">, DwarfRegNum<[8]>;
+def D9 : TriCoreDataReg<9, "d9">, DwarfRegNum<[9]>;
+def D10 : TriCoreDataReg<10, "d10">, DwarfRegNum<[10]>;
+def D11 : TriCoreDataReg<11, "d11">, DwarfRegNum<[11]>;
+def D12 : TriCoreDataReg<12, "d12">, DwarfRegNum<[12]>;
+def D13 : TriCoreDataReg<13, "d13">, DwarfRegNum<[13]>;
+def D14 : TriCoreDataReg<14, "d14">, DwarfRegNum<[14]>;
+def D15 : TriCoreDataReg<15, "d15">, DwarfRegNum<[15]>;
+
+
+def A0 : TriCoreAddrReg<0, "a0">, DwarfRegNum<[16]>;
+def A1 : TriCoreAddrReg<1, "a1">, DwarfRegNum<[17]>;
+def A2 : TriCoreAddrReg<2, "a2">, DwarfRegNum<[18]>;
+def A3 : TriCoreAddrReg<3, "a3">, DwarfRegNum<[19]>;
+def A4 : TriCoreAddrReg<4, "a4">, DwarfRegNum<[20]>;
+def A5 : TriCoreAddrReg<5, "a5">, DwarfRegNum<[21]>;
+def A6 : TriCoreAddrReg<6, "a6">, DwarfRegNum<[22]>;
+def A7 : TriCoreAddrReg<7, "a7">, DwarfRegNum<[23]>;
+def A8 : TriCoreAddrReg<8, "a8">, DwarfRegNum<[24]>;
+def A9 : TriCoreAddrReg<9, "a9">, DwarfRegNum<[25]>;
+def A10 : TriCoreAddrReg<10, "sp", ["a10"]>, DwarfRegNum<[26]>;
+def A11 : TriCoreAddrReg<11, "a11">, DwarfRegNum<[27]>;
+def A12 : TriCoreAddrReg<12, "a12">, DwarfRegNum<[28]>;
+def A13 : TriCoreAddrReg<13, "a13">, DwarfRegNum<[29]>;
+def A14 : TriCoreAddrReg<14, "a14">, DwarfRegNum<[30]>;
+def A15 : TriCoreAddrReg<15, "a15">, DwarfRegNum<[31]>;
+
+let Namespace = "TriCore" in {
+def subreg_even : SubRegIndex<32>;
+def subreg_odd  : SubRegIndex<32, 32>;
+}
+
+//Extended 64-bit registers
+let SubRegIndices = [subreg_even, subreg_odd] in {
+def E0 : TriCoreRegWithSubregs<0,   "e0",  [D0,D1]   >, DwarfRegNum<[32]>;
+def E2 : TriCoreRegWithSubregs<2,   "e2",  [D2,D3]   >, DwarfRegNum<[33]>;
+def E4 : TriCoreRegWithSubregs<4,   "e4",  [D4,D5]   >, DwarfRegNum<[34]>;
+def E6 : TriCoreRegWithSubregs<6,   "e6",  [D6,D7]   >, DwarfRegNum<[35]>;
+def E8 : TriCoreRegWithSubregs<8,   "e8",  [D8,D9]   >, DwarfRegNum<[36]>;
+def E10 : TriCoreRegWithSubregs<10, "e10", [D10,D11] >, DwarfRegNum<[37]>;
+def E12 : TriCoreRegWithSubregs<12, "e12", [D12,D13] >, DwarfRegNum<[38]>;
+def E14 : TriCoreRegWithSubregs<14, "e14", [D14,D15] >, DwarfRegNum<[39]>;
+}
+
+let SubRegIndices = [subreg_even, subreg_odd] in {
+def P0 : TriCoreRegWithSubregs<0,   "p0",  [A0,A1]   >, DwarfRegNum<[40]>;
+def P2 : TriCoreRegWithSubregs<2,   "p2",  [A2,A3]   >, DwarfRegNum<[41]>;
+def P4 : TriCoreRegWithSubregs<4,   "p4",  [A4,A5]   >, DwarfRegNum<[42]>;
+def P6 : TriCoreRegWithSubregs<6,   "p6",  [A6,A7]   >, DwarfRegNum<[43]>;
+def P8 : TriCoreRegWithSubregs<8,   "p8",  [A8,A9]   >, DwarfRegNum<[44]>;
+def P10 : TriCoreRegWithSubregs<10, "p10", [A10,A11] >, DwarfRegNum<[45]>;
+def P12 : TriCoreRegWithSubregs<12, "p12", [A12,A13] >, DwarfRegNum<[46]>;
+def P14 : TriCoreRegWithSubregs<14, "p14", [A14,A15] >, DwarfRegNum<[47]>;
+}
+
+//Program Status Information Registers
+def PSW  : TriCorePSReg<0, "psw">, DwarfRegNum<[40]>;
+def PCXI : TriCorePSReg<1, "pcxi">, DwarfRegNum<[41]>;
+def PC   : TriCorePSReg<2, "pc">, DwarfRegNum<[42]>;
+def FCX  : TriCorePSReg<3, "fcx">, DwarfRegNum<[43]>;
+
+//===----------------------------------------------------------------------===//
+//@Register Classes
+//===----------------------------------------------------------------------===//
+
+def RD : RegisterClass<"TriCore", [i32], 32, (add
+    D0,  D1,  D2,  D3,  D4,
+    D5,  D6,  D7,  D8,  D9,
+    D10, D11, D12, D13, D14,
+    D15)>;
+
+def RA : RegisterClass<"TriCore", [i32], 32, (add
+    A0,  A1,  A2,  A3,  A4,
+    A5,  A6,  A7,  A8,  A9,
+    A10, A11, A12, A13, A14,
+    A15)>;
+
+def RE : RegisterClass<"TriCore", [i64], 64, (add
+    E0, E2, E4,
+    E6, E8, E10,
+    E12, E14)>;
+
+def RP : RegisterClass<"TriCore", [i64], 64, (add
+    P0, P2, P4,
+    P6, P8, P10,
+    P12, P14)>;
+
+def PSRegs : RegisterClass<"TriCore", [i32], 32, (add
+    PSW, PCXI, PC, FCX)>;
+
+def TuplesPairAddrRegs : RegisterTuples<[subreg_even, subreg_odd],
+                                        [(add A0,A2,A4,A6,A8,A10,A12,A14),
+                                        (add A1,A3,A5,A7,A9,A11,A13,A15)]>;
+
+def PairAddrRegs : RegisterClass<"TriCore", [i64], 64,
+                                (add TuplesPairAddrRegs)> {
+    let Size = 64;
+}