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Sajid
2024-09-07 18:00:09 +06:00
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8
thirdparty/capstone/bindings/python/.gitignore vendored Normal file
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MANIFEST
dist/
capstone/lib
capstone/include
pyx/lib
pyx/include
pyx/*.c
pyx/*.pyx

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0. This documentation explains how to install the Python bindings for Capstone
from source. If you want to install it from a PyPi package (recommended if
you are on Windows), see README.txt.
1. To install Capstone and the Python bindings on *nix, run the command below:
```
pip install bindings/python/
```
2. The tests directory contains some test code to show how to use the Capstone API.
- test_lite.py
Similarly to test_basic.py, but this code shows how to use disasm_lite(), a lighter
method to disassemble binary. Unlike disasm() API (used by test_basic.py), which returns
CsInsn objects, this API just returns tuples of (address, size, mnemonic, op_str).
The main reason for using this API is better performance: disasm_lite() is at least
20% faster than disasm(). Memory usage is also less. So if you just need basic
information out of disassembler, use disasm_lite() instead of disasm().

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This is the software license for Capstone disassembly framework.
Capstone has been designed & implemented by Nguyen Anh Quynh <aquynh@gmail.com>
See http://www.capstone-engine.org for further information.
Copyright (c) 2013, COSEINC.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
* Neither the name of the developer(s) nor the names of its
contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.

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recursive-include src *
include LICENSE.TXT
include README.txt
include BUILDING.txt
include Makefile

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PYTHON3 ?= python3
.PHONY: gen_const install sdist bdist clean check
gen_const:
cd .. && $(PYTHON3) const_generator.py python
install:
rm -rf src/
if test -n "${DESTDIR}"; then \
$(PYTHON3) setup.py build install --root="${DESTDIR}"; \
else \
$(PYTHON3) setup.py build install; \
fi
# build & upload PyPi package with source code of the core
sdist:
rm -rf src/ dist/
$(PYTHON3) setup.py sdist register upload
# build & upload PyPi package with prebuilt core
bdist:
rm -rf src/ dist/
$(PYTHON3) setup.py bdist_wheel register upload
clean:
rm -rf build/ src/ dist/ *.egg-info
rm -rf capstone/lib capstone/include pyx/lib pyx/include
rm -f pyx/*.c pyx/__init__.py
for f in capstone/*.py; do rm -f pyx/$$(basename $$f)x; done
rm -f MANIFEST
rm -f *.pyc capstone/*.pyc
TESTS = test_basic.py test_detail.py test_arm.py test_aarch64.py test_m68k.py test_mips.py
TESTS += test_ppc.py test_sparc.py test_systemz.py test_x86.py test_xcore.py test_tms320c64x.py
TESTS += test_m680x.py test_skipdata.py test_mos65xx.py test_bpf.py test_riscv.py
TESTS += test_evm.py test_tricore.py test_wasm.py test_sh.py test_hppa.py
TESTS += test_lite.py test_iter.py test_customized_mnem.py test_alpha.py
check:
@for t in $(TESTS); do \
echo Check $$t ... ; \
./tests/$$t > /dev/null; \
if [ $$? -eq 0 ]; then echo OK; else echo FAILED; exit 1; fi \
done

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To install Capstone, you should run `pip install capstone`.
If you would like to build Capstone with just the source distribution, without
pip, just run `python setup.py install` in the folder with setup.py in it.
In order to use this source distribution, you will need an environment that can
compile C code. On Linux, this is usually easy, but on Windows, this involves
installing Visual Studio and using the "Developer Command Prompt" to perform the
installation. See BUILDING.txt for more information.
By default, attempting to install the python bindings will trigger a build of
the capstone native core. If this is undesirable for whatever reason, for
instance, you already have a globally installed copy of libcapstone, you may
inhibit the build by setting the environment variable LIBCAPSTONE_PATH. The
exact value is not checked, just setting it will inhibit the build. During
execution, this variable may be set to the path of a directory containing a
specific version of libcapstone you would like to use.
If you don't want to build your own copy of Capstone, you can use a precompiled
binary distribution from PyPI. Saying `pip install capstone` should
automatically obtain an appropriate copy for your system. If it does not, please
open an issue at https://github.com/capstone-engine/capstone.
--------------------------------------------------------------------------------
Capstone is a disassembly framework with the target of becoming the ultimate
disasm engine for binary analysis and reversing in the security community.
Created by Nguyen Anh Quynh, then developed and maintained by a small community,
Capstone offers some unparalleled features:
- Support multiple hardware architectures: ARM, AARCH64 (ARMv8), Mips, PPC, Sparc,
SystemZ, XCore and X86 (including X86_64).
- Having clean/simple/lightweight/intuitive architecture-neutral API.
- Provide details on disassembled instruction (called “decomposer” by others).
- Provide semantics of the disassembled instruction, such as list of implicit
registers read & written.
- Implemented in pure C language, with lightweight wrappers for C++, C#, Go,
Java, NodeJS, Ocaml, Python, Ruby & Vala ready (available in main code,
or provided externally by the community).
- Native support for all popular platforms: Windows, Mac OSX, iOS, Android,
Linux, *BSD, Solaris, etc.
- Thread-safe by design.
- Special support for embedding into firmware or OS kernel.
- High performance & suitable for malware analysis (capable of handling various
X86 malware tricks).
- Distributed under the open source BSD license.
Further information is available at http://www.capstone-engine.org
[License]
This project is released under the BSD license. If you redistribute the binary
or source code of Capstone, please attach file LICENSE.TXT with your products.

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#!/bin/bash
set -e -x
cd bindings/python
if [ -f /opt/python/cp311-cp311/bin/python3 ];then
# Use manylinux Python
/opt/python/cp311-cp311/bin/python3 -m pip install wheel
/opt/python/cp311-cp311/bin/python3 setup.py bdist_wheel
else
python3 -m pip install wheel
python3 setup.py bdist_wheel
fi
cd dist
auditwheel repair *.whl
mv -f wheelhouse/*.whl .

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# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
import ctypes
from . import copy_ctypes_list
from .aarch64_const import *
# define the API
class AArch64OpMem(ctypes.Structure):
_fields_ = (
('base', ctypes.c_uint),
('index', ctypes.c_uint),
('disp', ctypes.c_int32),
)
class AArch64ImmRange(ctypes.Structure):
_fields_ = (
('first', ctypes.c_int8),
('offset', ctypes.c_int8),
)
class AArch64SMESliceOffset(ctypes.Union):
_fields_ = (
('imm', ctypes.c_int8),
('imm_range', AArch64ImmRange)
)
class AArch64OpSme(ctypes.Structure):
_fields_ = (
('type', ctypes.c_uint),
('tile', ctypes.c_uint),
('slice_reg', ctypes.c_uint),
('slice_offset', AArch64SMESliceOffset),
('has_range_offset', ctypes.c_bool),
('is_vertical', ctypes.c_bool),
)
class AArch64OpPred(ctypes.Structure):
_fields_ = (
('reg', ctypes.c_uint),
('vec_select', ctypes.c_uint),
('imm_index', ctypes.c_int),
)
class AArch64OpShift(ctypes.Structure):
_fields_ = (
('type', ctypes.c_uint),
('value', ctypes.c_uint),
)
class AArch64SysOpSysReg(ctypes.Union):
_fields_ = (
('sysreg', ctypes.c_uint),
('tlbi', ctypes.c_uint),
('ic', ctypes.c_uint),
('raw_val', ctypes.c_uint64),
)
class AArch64SysOpSysImm(ctypes.Union):
_fields_ = (
('dbnxs', ctypes.c_uint),
('exactfpimm', ctypes.c_uint),
('raw_val', ctypes.c_uint64),
)
class AArch64SysOpSysAlias(ctypes.Union):
_fields_ = (
('svcr', ctypes.c_uint),
('at', ctypes.c_uint),
('db', ctypes.c_uint),
('dc', ctypes.c_uint),
('isb', ctypes.c_uint),
('tsb', ctypes.c_uint),
('prfm', ctypes.c_uint),
('sveprfm', ctypes.c_uint),
('rprfm', ctypes.c_uint),
('pstateimm0_15', ctypes.c_uint),
('pstateimm0_1', ctypes.c_uint),
('psb', ctypes.c_uint),
('bti', ctypes.c_uint),
('svepredpat', ctypes.c_uint),
('sveveclenspecifier', ctypes.c_uint),
('raw_val', ctypes.c_uint64),
)
class AArch64SysOp(ctypes.Structure):
_fields_ = (
('reg', AArch64SysOpSysReg),
('imm', AArch64SysOpSysImm),
('alias', AArch64SysOpSysAlias),
('sub_type', ctypes.c_uint),
)
class AArch64OpValue(ctypes.Union):
_fields_ = (
('reg', ctypes.c_uint),
('imm', ctypes.c_int64),
('imm_range', AArch64ImmRange),
('fp', ctypes.c_double),
('mem', AArch64OpMem),
('sysop', AArch64SysOp),
('sme', AArch64OpSme),
('pred', AArch64OpPred),
)
class AArch64Op(ctypes.Structure):
_fields_ = (
('vector_index', ctypes.c_int),
('vas', ctypes.c_uint),
('shift', AArch64OpShift),
('ext', ctypes.c_uint),
('type', ctypes.c_uint),
('is_vreg', ctypes.c_bool),
('value', AArch64OpValue),
('access', ctypes.c_uint8),
('is_list_member', ctypes.c_bool),
)
@property
def imm(self):
return self.value.imm
@property
def reg(self):
return self.value.reg
@property
def fp(self):
return self.value.fp
@property
def mem(self):
return self.value.mem
@property
def imm_range(self):
return self.value.imm_range
@property
def sysop(self):
return self.value.sysop
@property
def sme(self):
return self.value.sme
class CsAArch64(ctypes.Structure):
_fields_ = (
('cc', ctypes.c_uint),
('update_flags', ctypes.c_bool),
('post_index', ctypes.c_bool),
('is_doing_sme', ctypes.c_bool),
('op_count', ctypes.c_uint8),
('operands', AArch64Op * 8),
)
def get_arch_info(a):
return (a.cc, a.update_flags, a.post_index, copy_ctypes_list(a.operands[:a.op_count]))

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import ctypes
from . import copy_ctypes_list
from .alpha_const import *
class AlphaOpMem(ctypes.Structure):
_fields_ = (
('base', ctypes.c_uint8),
('disp', ctypes.c_int32),
)
class AlphaOpValue(ctypes.Union):
_fields_ = (
('reg', ctypes.c_uint),
('imm', ctypes.c_int32),
)
class AlphaOp(ctypes.Structure):
_fields_ = (
('type', ctypes.c_uint),
('value', AlphaOpValue),
('access', ctypes.c_uint8)
)
@property
def imm(self):
return self.value.imm
@property
def reg(self):
return self.value.reg
# Instruction structure
class CsAlpha(ctypes.Structure):
_fields_ = (
('op_count', ctypes.c_uint8),
('operands', AlphaOp * 3)
)
def get_arch_info(a):
return (copy_ctypes_list(a.operands[:a.op_count]))

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from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [alpha_const.py]
# Operand type for instruction's operands
ALPHA_OP_INVALID = CS_OP_INVALID
ALPHA_OP_REG = CS_OP_REG
ALPHA_OP_IMM = CS_OP_IMM
# Alpha registers
Alpha_REG_INVALID = 0
Alpha_REG_F0 = 1
Alpha_REG_F1 = 2
Alpha_REG_F2 = 3
Alpha_REG_F3 = 4
Alpha_REG_F4 = 5
Alpha_REG_F5 = 6
Alpha_REG_F6 = 7
Alpha_REG_F7 = 8
Alpha_REG_F8 = 9
Alpha_REG_F9 = 10
Alpha_REG_F10 = 11
Alpha_REG_F11 = 12
Alpha_REG_F12 = 13
Alpha_REG_F13 = 14
Alpha_REG_F14 = 15
Alpha_REG_F15 = 16
Alpha_REG_F16 = 17
Alpha_REG_F17 = 18
Alpha_REG_F18 = 19
Alpha_REG_F19 = 20
Alpha_REG_F20 = 21
Alpha_REG_F21 = 22
Alpha_REG_F22 = 23
Alpha_REG_F23 = 24
Alpha_REG_F24 = 25
Alpha_REG_F25 = 26
Alpha_REG_F26 = 27
Alpha_REG_F27 = 28
Alpha_REG_F28 = 29
Alpha_REG_F29 = 30
Alpha_REG_F30 = 31
Alpha_REG_F31 = 32
Alpha_REG_R0 = 33
Alpha_REG_R1 = 34
Alpha_REG_R2 = 35
Alpha_REG_R3 = 36
Alpha_REG_R4 = 37
Alpha_REG_R5 = 38
Alpha_REG_R6 = 39
Alpha_REG_R7 = 40
Alpha_REG_R8 = 41
Alpha_REG_R9 = 42
Alpha_REG_R10 = 43
Alpha_REG_R11 = 44
Alpha_REG_R12 = 45
Alpha_REG_R13 = 46
Alpha_REG_R14 = 47
Alpha_REG_R15 = 48
Alpha_REG_R16 = 49
Alpha_REG_R17 = 50
Alpha_REG_R18 = 51
Alpha_REG_R19 = 52
Alpha_REG_R20 = 53
Alpha_REG_R21 = 54
Alpha_REG_R22 = 55
Alpha_REG_R23 = 56
Alpha_REG_R24 = 57
Alpha_REG_R25 = 58
Alpha_REG_R26 = 59
Alpha_REG_R27 = 60
Alpha_REG_R28 = 61
Alpha_REG_R29 = 62
Alpha_REG_R30 = 63
Alpha_REG_R31 = 64
Alpha_REG_ENDING = 65
# Alpha instruction
Alpha_INS_INVALID = 0
Alpha_INS_ADDL = 1
Alpha_INS_ADDQ = 2
Alpha_INS_ADDSsSU = 3
Alpha_INS_ADDTsSU = 4
Alpha_INS_AND = 5
Alpha_INS_BEQ = 6
Alpha_INS_BGE = 7
Alpha_INS_BGT = 8
Alpha_INS_BIC = 9
Alpha_INS_BIS = 10
Alpha_INS_BLBC = 11
Alpha_INS_BLBS = 12
Alpha_INS_BLE = 13
Alpha_INS_BLT = 14
Alpha_INS_BNE = 15
Alpha_INS_BR = 16
Alpha_INS_BSR = 17
Alpha_INS_CMOVEQ = 18
Alpha_INS_CMOVGE = 19
Alpha_INS_CMOVGT = 20
Alpha_INS_CMOVLBC = 21
Alpha_INS_CMOVLBS = 22
Alpha_INS_CMOVLE = 23
Alpha_INS_CMOVLT = 24
Alpha_INS_CMOVNE = 25
Alpha_INS_CMPBGE = 26
Alpha_INS_CMPEQ = 27
Alpha_INS_CMPLE = 28
Alpha_INS_CMPLT = 29
Alpha_INS_CMPTEQsSU = 30
Alpha_INS_CMPTLEsSU = 31
Alpha_INS_CMPTLTsSU = 32
Alpha_INS_CMPTUNsSU = 33
Alpha_INS_CMPULE = 34
Alpha_INS_CMPULT = 35
Alpha_INS_COND_BRANCH = 36
Alpha_INS_CPYSE = 37
Alpha_INS_CPYSN = 38
Alpha_INS_CPYS = 39
Alpha_INS_CTLZ = 40
Alpha_INS_CTPOP = 41
Alpha_INS_CTTZ = 42
Alpha_INS_CVTQSsSUI = 43
Alpha_INS_CVTQTsSUI = 44
Alpha_INS_CVTSTsS = 45
Alpha_INS_CVTTQsSVC = 46
Alpha_INS_CVTTSsSUI = 47
Alpha_INS_DIVSsSU = 48
Alpha_INS_DIVTsSU = 49
Alpha_INS_ECB = 50
Alpha_INS_EQV = 51
Alpha_INS_EXCB = 52
Alpha_INS_EXTBL = 53
Alpha_INS_EXTLH = 54
Alpha_INS_EXTLL = 55
Alpha_INS_EXTQH = 56
Alpha_INS_EXTQL = 57
Alpha_INS_EXTWH = 58
Alpha_INS_EXTWL = 59
Alpha_INS_FBEQ = 60
Alpha_INS_FBGE = 61
Alpha_INS_FBGT = 62
Alpha_INS_FBLE = 63
Alpha_INS_FBLT = 64
Alpha_INS_FBNE = 65
Alpha_INS_FCMOVEQ = 66
Alpha_INS_FCMOVGE = 67
Alpha_INS_FCMOVGT = 68
Alpha_INS_FCMOVLE = 69
Alpha_INS_FCMOVLT = 70
Alpha_INS_FCMOVNE = 71
Alpha_INS_FETCH = 72
Alpha_INS_FETCH_M = 73
Alpha_INS_FTOIS = 74
Alpha_INS_FTOIT = 75
Alpha_INS_INSBL = 76
Alpha_INS_INSLH = 77
Alpha_INS_INSLL = 78
Alpha_INS_INSQH = 79
Alpha_INS_INSQL = 80
Alpha_INS_INSWH = 81
Alpha_INS_INSWL = 82
Alpha_INS_ITOFS = 83
Alpha_INS_ITOFT = 84
Alpha_INS_JMP = 85
Alpha_INS_JSR = 86
Alpha_INS_JSR_COROUTINE = 87
Alpha_INS_LDA = 88
Alpha_INS_LDAH = 89
Alpha_INS_LDBU = 90
Alpha_INS_LDL = 91
Alpha_INS_LDL_L = 92
Alpha_INS_LDQ = 93
Alpha_INS_LDQ_L = 94
Alpha_INS_LDQ_U = 95
Alpha_INS_LDS = 96
Alpha_INS_LDT = 97
Alpha_INS_LDWU = 98
Alpha_INS_MB = 99
Alpha_INS_MSKBL = 100
Alpha_INS_MSKLH = 101
Alpha_INS_MSKLL = 102
Alpha_INS_MSKQH = 103
Alpha_INS_MSKQL = 104
Alpha_INS_MSKWH = 105
Alpha_INS_MSKWL = 106
Alpha_INS_MULL = 107
Alpha_INS_MULQ = 108
Alpha_INS_MULSsSU = 109
Alpha_INS_MULTsSU = 110
Alpha_INS_ORNOT = 111
Alpha_INS_RC = 112
Alpha_INS_RET = 113
Alpha_INS_RPCC = 114
Alpha_INS_RS = 115
Alpha_INS_S4ADDL = 116
Alpha_INS_S4ADDQ = 117
Alpha_INS_S4SUBL = 118
Alpha_INS_S4SUBQ = 119
Alpha_INS_S8ADDL = 120
Alpha_INS_S8ADDQ = 121
Alpha_INS_S8SUBL = 122
Alpha_INS_S8SUBQ = 123
Alpha_INS_SEXTB = 124
Alpha_INS_SEXTW = 125
Alpha_INS_SLL = 126
Alpha_INS_SQRTSsSU = 127
Alpha_INS_SQRTTsSU = 128
Alpha_INS_SRA = 129
Alpha_INS_SRL = 130
Alpha_INS_STB = 131
Alpha_INS_STL = 132
Alpha_INS_STL_C = 133
Alpha_INS_STQ = 134
Alpha_INS_STQ_C = 135
Alpha_INS_STQ_U = 136
Alpha_INS_STS = 137
Alpha_INS_STT = 138
Alpha_INS_STW = 139
Alpha_INS_SUBL = 140
Alpha_INS_SUBQ = 141
Alpha_INS_SUBSsSU = 142
Alpha_INS_SUBTsSU = 143
Alpha_INS_TRAPB = 144
Alpha_INS_UMULH = 145
Alpha_INS_WH64 = 146
Alpha_INS_WH64EN = 147
Alpha_INS_WMB = 148
Alpha_INS_XOR = 149
Alpha_INS_ZAPNOT = 150
ALPHA_INS_ENDING = 151
# Group of Alpha instructions
Alpha_GRP_INVALID = 0
# Generic groups
Alpha_GRP_CALL = 1
Alpha_GRP_JUMP = 2
Alpha_GRP_BRANCH_RELATIVE = 3
Alpha_GRP_ENDING = 4

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# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
import ctypes
from . import copy_ctypes_list
from .arm_const import *
# define the API
class ArmOpMem(ctypes.Structure):
_fields_ = (
('base', ctypes.c_uint),
('index', ctypes.c_uint),
('scale', ctypes.c_int),
('disp', ctypes.c_int),
('lshift', ctypes.c_int),
('align', ctypes.c_uint),
)
class ArmOpShift(ctypes.Structure):
_fields_ = (
('type', ctypes.c_uint),
('value', ctypes.c_uint),
)
class ArmSysopReg(ctypes.Union):
_fields_ = (
('mclasssysreg', ctypes.c_uint),
('bankedreg', ctypes.c_uint),
)
class ArmOpSysop(ctypes.Structure):
_fields_ = (
('reg', ArmSysopReg),
('psr_bits', ctypes.c_uint),
('sysm', ctypes.c_uint16),
('msr_mask', ctypes.c_uint8),
)
class ArmOpValue(ctypes.Union):
_fields_ = (
('reg', ctypes.c_uint),
('sysop', ArmOpSysop),
('imm', ctypes.c_int64),
('pred', ctypes.c_int),
('fp', ctypes.c_double),
('mem', ArmOpMem),
('setend', ctypes.c_int),
)
class ArmOp(ctypes.Structure):
_fields_ = (
('vector_index', ctypes.c_int),
('shift', ArmOpShift),
('type', ctypes.c_uint),
('value', ArmOpValue),
('subtracted', ctypes.c_bool),
('access', ctypes.c_uint8),
('neon_lane', ctypes.c_int8),
)
@property
def reg(self):
return self.value.reg
@property
def sysop(self):
return self.value.sysop
@property
def imm(self):
return self.value.imm
@property
def pred(self):
return self.value.pred
@property
def fp(self):
return self.value.fp
@property
def mem(self):
return self.value.mem
@property
def setend(self):
return self.value.setend
class CsArm(ctypes.Structure):
_fields_ = (
('usermode', ctypes.c_bool),
('vector_size', ctypes.c_int),
('vector_data', ctypes.c_int),
('cps_mode', ctypes.c_int),
('cps_flag', ctypes.c_int),
('cc', ctypes.c_uint),
('vcc', ctypes.c_uint),
('update_flags', ctypes.c_bool),
('post_index', ctypes.c_bool),
('mem_barrier', ctypes.c_int),
('pred_mask', ctypes.c_uint8),
('op_count', ctypes.c_uint8),
('operands', ArmOp * 36),
)
def get_arch_info(a):
return (a.usermode, a.vector_size, a.vector_data, a.cps_mode, a.cps_flag, a.cc, a.vcc, a.update_flags, \
a.post_index, a.mem_barrier, a.pred_mask, copy_ctypes_list(a.operands[:a.op_count]))

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thirdparty/capstone/bindings/python/capstone/bpf.py vendored Normal file
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# Capstone Python bindings
# BPF by david942j <david942j@gmail.com>, 2019
import ctypes
from . import copy_ctypes_list
from .bpf_const import *
class BPFOpMem(ctypes.Structure):
_fields_ = (
('base', ctypes.c_uint8),
('disp', ctypes.c_int32),
)
class BPFOpValue(ctypes.Union):
_fields_ = (
('reg', ctypes.c_uint8),
('imm', ctypes.c_uint64),
('off', ctypes.c_uint32),
('mem', BPFOpMem),
('mmem', ctypes.c_uint32),
('msh', ctypes.c_uint32),
('ext', ctypes.c_uint32),
)
class BPFOp(ctypes.Structure):
_fields_ = (
('type', ctypes.c_uint),
('value', BPFOpValue),
('access', ctypes.c_uint8),
)
@property
def reg(self):
return self.value.reg
@property
def imm(self):
return self.value.imm
@property
def off(self):
return self.value.off
@property
def mem(self):
return self.value.mem
@property
def mmem(self):
return self.value.mmem
@property
def msh(self):
return self.value.msh
@property
def ext(self):
return self.value.ext
class CsBPF(ctypes.Structure):
_fields_ = (
('op_count', ctypes.c_uint8),
('operands', BPFOp * 4),
)
def get_arch_info(a):
return (copy_ctypes_list(a.operands[:a.op_count]))

118
thirdparty/capstone/bindings/python/capstone/bpf_const.py vendored Normal file
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from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [bpf_const.py]
BPF_OP_INVALID = 0
BPF_OP_REG = 1
BPF_OP_IMM = 2
BPF_OP_OFF = 3
BPF_OP_MEM = 4
BPF_OP_MMEM = 5
BPF_OP_MSH = 6
BPF_OP_EXT = 7
BPF_REG_INVALID = 0
BPF_REG_A = 1
BPF_REG_X = 2
BPF_REG_R0 = 3
BPF_REG_R1 = 4
BPF_REG_R2 = 5
BPF_REG_R3 = 6
BPF_REG_R4 = 7
BPF_REG_R5 = 8
BPF_REG_R6 = 9
BPF_REG_R7 = 10
BPF_REG_R8 = 11
BPF_REG_R9 = 12
BPF_REG_R10 = 13
BPF_REG_ENDING = 14
BPF_EXT_INVALID = 0
BPF_EXT_LEN = 1
BPF_INS_INVALID = 0
BPF_INS_ADD = 1
BPF_INS_SUB = 2
BPF_INS_MUL = 3
BPF_INS_DIV = 4
BPF_INS_OR = 5
BPF_INS_AND = 6
BPF_INS_LSH = 7
BPF_INS_RSH = 8
BPF_INS_NEG = 9
BPF_INS_MOD = 10
BPF_INS_XOR = 11
BPF_INS_MOV = 12
BPF_INS_ARSH = 13
BPF_INS_ADD64 = 14
BPF_INS_SUB64 = 15
BPF_INS_MUL64 = 16
BPF_INS_DIV64 = 17
BPF_INS_OR64 = 18
BPF_INS_AND64 = 19
BPF_INS_LSH64 = 20
BPF_INS_RSH64 = 21
BPF_INS_NEG64 = 22
BPF_INS_MOD64 = 23
BPF_INS_XOR64 = 24
BPF_INS_MOV64 = 25
BPF_INS_ARSH64 = 26
BPF_INS_LE16 = 27
BPF_INS_LE32 = 28
BPF_INS_LE64 = 29
BPF_INS_BE16 = 30
BPF_INS_BE32 = 31
BPF_INS_BE64 = 32
BPF_INS_BSWAP16 = 33
BPF_INS_BSWAP32 = 34
BPF_INS_BSWAP64 = 35
BPF_INS_LDW = 36
BPF_INS_LDH = 37
BPF_INS_LDB = 38
BPF_INS_LDDW = 39
BPF_INS_LDXW = 40
BPF_INS_LDXH = 41
BPF_INS_LDXB = 42
BPF_INS_LDXDW = 43
BPF_INS_STW = 44
BPF_INS_STH = 45
BPF_INS_STB = 46
BPF_INS_STDW = 47
BPF_INS_STXW = 48
BPF_INS_STXH = 49
BPF_INS_STXB = 50
BPF_INS_STXDW = 51
BPF_INS_XADDW = 52
BPF_INS_XADDDW = 53
BPF_INS_JMP = 54
BPF_INS_JEQ = 55
BPF_INS_JGT = 56
BPF_INS_JGE = 57
BPF_INS_JSET = 58
BPF_INS_JNE = 59
BPF_INS_JSGT = 60
BPF_INS_JSGE = 61
BPF_INS_CALL = 62
BPF_INS_CALLX = 63
BPF_INS_EXIT = 64
BPF_INS_JLT = 65
BPF_INS_JLE = 66
BPF_INS_JSLT = 67
BPF_INS_JSLE = 68
BPF_INS_RET = 69
BPF_INS_TAX = 70
BPF_INS_TXA = 71
BPF_INS_ENDING = 72
BPF_INS_LD = BPF_INS_LDW
BPF_INS_LDX = BPF_INS_LDXW
BPF_INS_ST = BPF_INS_STW
BPF_INS_STX = BPF_INS_STXW
BPF_GRP_INVALID = 0
BPF_GRP_LOAD = 1
BPF_GRP_STORE = 2
BPF_GRP_ALU = 3
BPF_GRP_JUMP = 4
BPF_GRP_CALL = 5
BPF_GRP_RETURN = 6
BPF_GRP_MISC = 7
BPF_GRP_ENDING = 8

17
thirdparty/capstone/bindings/python/capstone/evm.py vendored Normal file
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# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
import ctypes
from . import copy_ctypes_list
from .evm_const import *
# define the API
class CsEvm(ctypes.Structure):
_fields_ = (
('pop', ctypes.c_byte),
('push', ctypes.c_byte),
('fee', ctypes.c_uint),
)
def get_arch_info(a):
return (a.pop, a.push, a.fee)

152
thirdparty/capstone/bindings/python/capstone/evm_const.py vendored Normal file
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from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [evm_const.py]
EVM_INS_STOP = 0
EVM_INS_ADD = 1
EVM_INS_MUL = 2
EVM_INS_SUB = 3
EVM_INS_DIV = 4
EVM_INS_SDIV = 5
EVM_INS_MOD = 6
EVM_INS_SMOD = 7
EVM_INS_ADDMOD = 8
EVM_INS_MULMOD = 9
EVM_INS_EXP = 10
EVM_INS_SIGNEXTEND = 11
EVM_INS_LT = 16
EVM_INS_GT = 17
EVM_INS_SLT = 18
EVM_INS_SGT = 19
EVM_INS_EQ = 20
EVM_INS_ISZERO = 21
EVM_INS_AND = 22
EVM_INS_OR = 23
EVM_INS_XOR = 24
EVM_INS_NOT = 25
EVM_INS_BYTE = 26
EVM_INS_SHA3 = 32
EVM_INS_ADDRESS = 48
EVM_INS_BALANCE = 49
EVM_INS_ORIGIN = 50
EVM_INS_CALLER = 51
EVM_INS_CALLVALUE = 52
EVM_INS_CALLDATALOAD = 53
EVM_INS_CALLDATASIZE = 54
EVM_INS_CALLDATACOPY = 55
EVM_INS_CODESIZE = 56
EVM_INS_CODECOPY = 57
EVM_INS_GASPRICE = 58
EVM_INS_EXTCODESIZE = 59
EVM_INS_EXTCODECOPY = 60
EVM_INS_RETURNDATASIZE = 61
EVM_INS_RETURNDATACOPY = 62
EVM_INS_BLOCKHASH = 64
EVM_INS_COINBASE = 65
EVM_INS_TIMESTAMP = 66
EVM_INS_NUMBER = 67
EVM_INS_DIFFICULTY = 68
EVM_INS_GASLIMIT = 69
EVM_INS_POP = 80
EVM_INS_MLOAD = 81
EVM_INS_MSTORE = 82
EVM_INS_MSTORE8 = 83
EVM_INS_SLOAD = 84
EVM_INS_SSTORE = 85
EVM_INS_JUMP = 86
EVM_INS_JUMPI = 87
EVM_INS_PC = 88
EVM_INS_MSIZE = 89
EVM_INS_GAS = 90
EVM_INS_JUMPDEST = 91
EVM_INS_PUSH1 = 96
EVM_INS_PUSH2 = 97
EVM_INS_PUSH3 = 98
EVM_INS_PUSH4 = 99
EVM_INS_PUSH5 = 100
EVM_INS_PUSH6 = 101
EVM_INS_PUSH7 = 102
EVM_INS_PUSH8 = 103
EVM_INS_PUSH9 = 104
EVM_INS_PUSH10 = 105
EVM_INS_PUSH11 = 106
EVM_INS_PUSH12 = 107
EVM_INS_PUSH13 = 108
EVM_INS_PUSH14 = 109
EVM_INS_PUSH15 = 110
EVM_INS_PUSH16 = 111
EVM_INS_PUSH17 = 112
EVM_INS_PUSH18 = 113
EVM_INS_PUSH19 = 114
EVM_INS_PUSH20 = 115
EVM_INS_PUSH21 = 116
EVM_INS_PUSH22 = 117
EVM_INS_PUSH23 = 118
EVM_INS_PUSH24 = 119
EVM_INS_PUSH25 = 120
EVM_INS_PUSH26 = 121
EVM_INS_PUSH27 = 122
EVM_INS_PUSH28 = 123
EVM_INS_PUSH29 = 124
EVM_INS_PUSH30 = 125
EVM_INS_PUSH31 = 126
EVM_INS_PUSH32 = 127
EVM_INS_DUP1 = 128
EVM_INS_DUP2 = 129
EVM_INS_DUP3 = 130
EVM_INS_DUP4 = 131
EVM_INS_DUP5 = 132
EVM_INS_DUP6 = 133
EVM_INS_DUP7 = 134
EVM_INS_DUP8 = 135
EVM_INS_DUP9 = 136
EVM_INS_DUP10 = 137
EVM_INS_DUP11 = 138
EVM_INS_DUP12 = 139
EVM_INS_DUP13 = 140
EVM_INS_DUP14 = 141
EVM_INS_DUP15 = 142
EVM_INS_DUP16 = 143
EVM_INS_SWAP1 = 144
EVM_INS_SWAP2 = 145
EVM_INS_SWAP3 = 146
EVM_INS_SWAP4 = 147
EVM_INS_SWAP5 = 148
EVM_INS_SWAP6 = 149
EVM_INS_SWAP7 = 150
EVM_INS_SWAP8 = 151
EVM_INS_SWAP9 = 152
EVM_INS_SWAP10 = 153
EVM_INS_SWAP11 = 154
EVM_INS_SWAP12 = 155
EVM_INS_SWAP13 = 156
EVM_INS_SWAP14 = 157
EVM_INS_SWAP15 = 158
EVM_INS_SWAP16 = 159
EVM_INS_LOG0 = 160
EVM_INS_LOG1 = 161
EVM_INS_LOG2 = 162
EVM_INS_LOG3 = 163
EVM_INS_LOG4 = 164
EVM_INS_CREATE = 240
EVM_INS_CALL = 241
EVM_INS_CALLCODE = 242
EVM_INS_RETURN = 243
EVM_INS_DELEGATECALL = 244
EVM_INS_CALLBLACKBOX = 245
EVM_INS_STATICCALL = 250
EVM_INS_REVERT = 253
EVM_INS_SUICIDE = 255
EVM_INS_INVALID = 512
EVM_INS_ENDING = 513
EVM_GRP_INVALID = 0
EVM_GRP_JUMP = 1
EVM_GRP_MATH = 8
EVM_GRP_STACK_WRITE = 9
EVM_GRP_STACK_READ = 10
EVM_GRP_MEM_WRITE = 11
EVM_GRP_MEM_READ = 12
EVM_GRP_STORE_WRITE = 13
EVM_GRP_STORE_READ = 14
EVM_GRP_HALT = 15
EVM_GRP_ENDING = 16

72
thirdparty/capstone/bindings/python/capstone/hppa.py vendored Normal file
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# Capstone Python bindings, by Dmitry Sibirtsev <sibirtsevdl@gmail.com>
import ctypes
from . import copy_ctypes_list
from .hppa_const import *
class HPPAOpMem(ctypes.Structure):
_fields_ = (
('base', ctypes.c_uint),
('space', ctypes.c_uint),
('base_access', ctypes.c_uint8),
)
class HPPAModifierValue(ctypes.Union):
_fields_ = (
('str_mod', ctypes.c_char_p),
('int_mod', ctypes.c_uint32)
)
class HPPAModifier(ctypes.Structure):
_fields_ = (
('type', ctypes.c_int),
('value', HPPAModifierValue)
)
class HPPAExt(ctypes.Structure):
_fields_ = (
('modifiers', HPPAModifier * 5),
('mod_num', ctypes.c_uint8),
('b_writable', ctypes.c_bool),
('cmplt', ctypes.c_bool)
)
class HPPAOpValue(ctypes.Union):
_fields_ = (
('reg', ctypes.c_uint),
('imm', ctypes.c_int64),
('mem', HPPAOpMem)
)
class HPPAOp(ctypes.Structure):
_fields_ = (
('type', ctypes.c_uint8),
('value', HPPAOpValue),
('access', ctypes.c_uint8)
)
@property
def imm(self):
return self.value.imm
@property
def reg(self):
return self.value.reg
@property
def mem(self):
return self.value.mem
# Instruction structure
class CsHPPA(ctypes.Structure):
_fields_ = (
('op_count', ctypes.c_uint8),
('operands', HPPAOp * 5)
)
def get_arch_info(a):
return (copy_ctypes_list(a.operands[:a.op_count]))

453
thirdparty/capstone/bindings/python/capstone/hppa_const.py vendored Normal file
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from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [hppa_const.py]
HPPA_MAX_OPS = 5
HPPA_STR_MODIFIER_LEN = 8
HPPA_MAX_MODIFIERS_LEN = 5
HPPA_OP_INVALID = 0
HPPA_OP_REG = 1
HPPA_OP_IMM = 2
HPPA_OP_IDX_REG = 3
HPPA_OP_DISP = 4
HPPA_OP_MEM = 5
HPPA_OP_TARGET = 6
# HPPA registers
HPPA_REG_INVALID = 0
HPPA_REG_GR0 = 1
HPPA_REG_GR1 = 2
HPPA_REG_GR2 = 3
HPPA_REG_GR3 = 4
HPPA_REG_GR4 = 5
HPPA_REG_GR5 = 6
HPPA_REG_GR6 = 7
HPPA_REG_GR7 = 8
HPPA_REG_GR8 = 9
HPPA_REG_GR9 = 10
HPPA_REG_GR10 = 11
HPPA_REG_GR11 = 12
HPPA_REG_GR12 = 13
HPPA_REG_GR13 = 14
HPPA_REG_GR14 = 15
HPPA_REG_GR15 = 16
HPPA_REG_GR16 = 17
HPPA_REG_GR17 = 18
HPPA_REG_GR18 = 19
HPPA_REG_GR19 = 20
HPPA_REG_GR20 = 21
HPPA_REG_GR21 = 22
HPPA_REG_GR22 = 23
HPPA_REG_GR23 = 24
HPPA_REG_GR24 = 25
HPPA_REG_GR25 = 26
HPPA_REG_GR26 = 27
HPPA_REG_GR27 = 28
HPPA_REG_GR28 = 29
HPPA_REG_GR29 = 30
HPPA_REG_GR30 = 31
HPPA_REG_GR31 = 32
HPPA_REG_FPR0 = 33
HPPA_REG_FPR1 = 34
HPPA_REG_FPR2 = 35
HPPA_REG_FPR3 = 36
HPPA_REG_FPR4 = 37
HPPA_REG_FPR5 = 38
HPPA_REG_FPR6 = 39
HPPA_REG_FPR7 = 40
HPPA_REG_FPR8 = 41
HPPA_REG_FPR9 = 42
HPPA_REG_FPR10 = 43
HPPA_REG_FPR11 = 44
HPPA_REG_FPR12 = 45
HPPA_REG_FPR13 = 46
HPPA_REG_FPR14 = 47
HPPA_REG_FPR15 = 48
HPPA_REG_FPR16 = 49
HPPA_REG_FPR17 = 50
HPPA_REG_FPR18 = 51
HPPA_REG_FPR19 = 52
HPPA_REG_FPR20 = 53
HPPA_REG_FPR21 = 54
HPPA_REG_FPR22 = 55
HPPA_REG_FPR23 = 56
HPPA_REG_FPR24 = 57
HPPA_REG_FPR25 = 58
HPPA_REG_FPR26 = 59
HPPA_REG_FPR27 = 60
HPPA_REG_FPR28 = 61
HPPA_REG_FPR29 = 62
HPPA_REG_FPR30 = 63
HPPA_REG_FPR31 = 64
HPPA_REG_SR0 = 65
HPPA_REG_SR1 = 66
HPPA_REG_SR2 = 67
HPPA_REG_SR3 = 68
HPPA_REG_SR4 = 69
HPPA_REG_SR5 = 70
HPPA_REG_SR6 = 71
HPPA_REG_SR7 = 72
HPPA_REG_CR0 = 73
HPPA_REG_CR1 = 74
HPPA_REG_CR2 = 75
HPPA_REG_CR3 = 76
HPPA_REG_CR4 = 77
HPPA_REG_CR5 = 78
HPPA_REG_CR6 = 79
HPPA_REG_CR7 = 80
HPPA_REG_CR8 = 81
HPPA_REG_CR9 = 82
HPPA_REG_CR10 = 83
HPPA_REG_CR11 = 84
HPPA_REG_CR12 = 85
HPPA_REG_CR13 = 86
HPPA_REG_CR14 = 87
HPPA_REG_CR15 = 88
HPPA_REG_CR16 = 89
HPPA_REG_CR17 = 90
HPPA_REG_CR18 = 91
HPPA_REG_CR19 = 92
HPPA_REG_CR20 = 93
HPPA_REG_CR21 = 94
HPPA_REG_CR22 = 95
HPPA_REG_CR23 = 96
HPPA_REG_CR24 = 97
HPPA_REG_CR25 = 98
HPPA_REG_CR26 = 99
HPPA_REG_CR27 = 100
HPPA_REG_CR28 = 101
HPPA_REG_CR29 = 102
HPPA_REG_CR30 = 103
HPPA_REG_CR31 = 104
HPPA_REG_FPE0 = 105
HPPA_REG_FPE1 = 106
HPPA_REG_FPE2 = 107
HPPA_REG_FPE3 = 108
HPPA_REG_FPE4 = 109
HPPA_REG_FPE5 = 110
HPPA_REG_FPE6 = 111
HPPA_REG_FPE7 = 112
HPPA_REG_FPE8 = 113
HPPA_REG_FPE9 = 114
HPPA_REG_FPE10 = 115
HPPA_REG_FPE11 = 116
HPPA_REG_FPE12 = 117
HPPA_REG_FPE13 = 118
HPPA_REG_FPE14 = 119
HPPA_REG_FPE15 = 120
HPPA_REG_FPE16 = 121
HPPA_REG_FPE17 = 122
HPPA_REG_FPE18 = 123
HPPA_REG_FPE19 = 124
HPPA_REG_FPE20 = 125
HPPA_REG_FPE21 = 126
HPPA_REG_FPE22 = 127
HPPA_REG_FPE23 = 128
HPPA_REG_FPE24 = 129
HPPA_REG_FPE25 = 130
HPPA_REG_FPE26 = 131
HPPA_REG_FPE27 = 132
HPPA_REG_FPE28 = 133
HPPA_REG_FPE29 = 134
HPPA_REG_FPE30 = 135
HPPA_REG_FPE31 = 136
HPPA_REG_SP_FPR0 = 137
HPPA_REG_SP_FPR1 = 138
HPPA_REG_SP_FPR2 = 139
HPPA_REG_SP_FPR3 = 140
HPPA_REG_SP_FPR4 = 141
HPPA_REG_SP_FPR5 = 142
HPPA_REG_SP_FPR6 = 143
HPPA_REG_SP_FPR7 = 144
HPPA_REG_SP_FPR8 = 145
HPPA_REG_SP_FPR9 = 146
HPPA_REG_SP_FPR10 = 147
HPPA_REG_SP_FPR11 = 148
HPPA_REG_SP_FPR12 = 149
HPPA_REG_SP_FPR13 = 150
HPPA_REG_SP_FPR14 = 151
HPPA_REG_SP_FPR15 = 152
HPPA_REG_SP_FPR16 = 153
HPPA_REG_SP_FPR17 = 154
HPPA_REG_SP_FPR18 = 155
HPPA_REG_SP_FPR19 = 156
HPPA_REG_SP_FPR20 = 157
HPPA_REG_SP_FPR21 = 158
HPPA_REG_SP_FPR22 = 159
HPPA_REG_SP_FPR23 = 160
HPPA_REG_SP_FPR24 = 161
HPPA_REG_SP_FPR25 = 162
HPPA_REG_SP_FPR26 = 163
HPPA_REG_SP_FPR27 = 164
HPPA_REG_SP_FPR28 = 165
HPPA_REG_SP_FPR29 = 166
HPPA_REG_SP_FPR30 = 167
HPPA_REG_SP_FPR31 = 168
HPPA_REG_ENDING = 169
HPPA_INS_INVALID = 0
HPPA_INS_ADD = 1
HPPA_INS_ADDI = 2
HPPA_INS_ADDIO = 3
HPPA_INS_ADDIT = 4
HPPA_INS_ADDITO = 5
HPPA_INS_ADDB = 6
HPPA_INS_ADDBT = 7
HPPA_INS_ADDBF = 8
HPPA_INS_ADDIB = 9
HPPA_INS_ADDIBT = 10
HPPA_INS_ADDIBF = 11
HPPA_INS_ADDIL = 12
HPPA_INS_ADDC = 13
HPPA_INS_ADDCO = 14
HPPA_INS_ADDL = 15
HPPA_INS_ADDO = 16
HPPA_INS_AND = 17
HPPA_INS_ANDCM = 18
HPPA_INS_B = 19
HPPA_INS_BB = 20
HPPA_INS_BE = 21
HPPA_INS_BL = 22
HPPA_INS_BLE = 23
HPPA_INS_BLR = 24
HPPA_INS_BREAK = 25
HPPA_INS_BV = 26
HPPA_INS_BVB = 27
HPPA_INS_BVE = 28
HPPA_INS_CALL = 29
HPPA_INS_CLDD = 30
HPPA_INS_CLDDS = 31
HPPA_INS_CLDDX = 32
HPPA_INS_CLDW = 33
HPPA_INS_CLDWS = 34
HPPA_INS_CLDWX = 35
HPPA_INS_CLRBTS = 36
HPPA_INS_CMPB = 37
HPPA_INS_CMPCLR = 38
HPPA_INS_CMPIB = 39
HPPA_INS_CMPICLR = 40
HPPA_INS_COMB = 41
HPPA_INS_COMBT = 42
HPPA_INS_COMBF = 43
HPPA_INS_COMCLR = 44
HPPA_INS_COMIB = 45
HPPA_INS_COMIBT = 46
HPPA_INS_COMIBF = 47
HPPA_INS_COMICLR = 48
HPPA_INS_COPR = 49
HPPA_INS_COPY = 50
HPPA_INS_CSTD = 51
HPPA_INS_CSTDS = 52
HPPA_INS_CSTDX = 53
HPPA_INS_CSTW = 54
HPPA_INS_CSTWS = 55
HPPA_INS_CSTWX = 56
HPPA_INS_DCOR = 57
HPPA_INS_DEP = 58
HPPA_INS_DEPI = 59
HPPA_INS_DEPD = 60
HPPA_INS_DEPDI = 61
HPPA_INS_DEPW = 62
HPPA_INS_DEPWI = 63
HPPA_INS_DIAG = 64
HPPA_INS_DS = 65
HPPA_INS_EXTRD = 66
HPPA_INS_EXTRS = 67
HPPA_INS_EXTRU = 68
HPPA_INS_EXTRW = 69
HPPA_INS_FABS = 70
HPPA_INS_FADD = 71
HPPA_INS_FCMP = 72
HPPA_INS_FCNV = 73
HPPA_INS_FCNVFF = 74
HPPA_INS_FCNVFX = 75
HPPA_INS_FCNVFXT = 76
HPPA_INS_FCNVXF = 77
HPPA_INS_FCPY = 78
HPPA_INS_FDC = 79
HPPA_INS_FDCE = 80
HPPA_INS_FDIV = 81
HPPA_INS_FIC = 82
HPPA_INS_FICE = 83
HPPA_INS_FID = 84
HPPA_INS_FLDD = 85
HPPA_INS_FLDDS = 86
HPPA_INS_FLDDX = 87
HPPA_INS_FLDW = 88
HPPA_INS_FLDWS = 89
HPPA_INS_FLDWX = 90
HPPA_INS_FMPY = 91
HPPA_INS_FMPYADD = 92
HPPA_INS_FMPYFADD = 93
HPPA_INS_FMPYNFADD = 94
HPPA_INS_FMPYSUB = 95
HPPA_INS_FNEG = 96
HPPA_INS_FNEGABS = 97
HPPA_INS_FREM = 98
HPPA_INS_FRND = 99
HPPA_INS_FSQRT = 100
HPPA_INS_FSTD = 101
HPPA_INS_FSTDS = 102
HPPA_INS_FSTDX = 103
HPPA_INS_FSTW = 104
HPPA_INS_FSTWS = 105
HPPA_INS_FSTWX = 106
HPPA_INS_FSTQS = 107
HPPA_INS_FSTQX = 108
HPPA_INS_FSUB = 109
HPPA_INS_FTEST = 110
HPPA_INS_GATE = 111
HPPA_INS_GFR = 112
HPPA_INS_GFW = 113
HPPA_INS_GRSHDW = 114
HPPA_INS_HADD = 115
HPPA_INS_HAVG = 116
HPPA_INS_HSHL = 117
HPPA_INS_HSHLADD = 118
HPPA_INS_HSHR = 119
HPPA_INS_HSHRADD = 120
HPPA_INS_HSUB = 121
HPPA_INS_IDTLBA = 122
HPPA_INS_IDTLBP = 123
HPPA_INS_IDTLBT = 124
HPPA_INS_IDCOR = 125
HPPA_INS_IITLBA = 126
HPPA_INS_IITLBP = 127
HPPA_INS_IITLBT = 128
HPPA_INS_LCI = 129
HPPA_INS_LDB = 130
HPPA_INS_LDBS = 131
HPPA_INS_LDBX = 132
HPPA_INS_LDCD = 133
HPPA_INS_LDCW = 134
HPPA_INS_LDCWS = 135
HPPA_INS_LDCWX = 136
HPPA_INS_LDD = 137
HPPA_INS_LDDA = 138
HPPA_INS_LDH = 139
HPPA_INS_LDHS = 140
HPPA_INS_LDHX = 141
HPPA_INS_LDI = 142
HPPA_INS_LDIL = 143
HPPA_INS_LDO = 144
HPPA_INS_LDSID = 145
HPPA_INS_LDW = 146
HPPA_INS_LDWA = 147
HPPA_INS_LDWAS = 148
HPPA_INS_LDWAX = 149
HPPA_INS_LDWM = 150
HPPA_INS_LDWS = 151
HPPA_INS_LDWX = 152
HPPA_INS_LPA = 153
HPPA_INS_MFCPU = 154
HPPA_INS_MFCTL = 155
HPPA_INS_MFIA = 156
HPPA_INS_MFSP = 157
HPPA_INS_MIXH = 158
HPPA_INS_MIXW = 159
HPPA_INS_MOVB = 160
HPPA_INS_MOVIB = 161
HPPA_INS_MTCPU = 162
HPPA_INS_MTCTL = 163
HPPA_INS_MTSAR = 164
HPPA_INS_MTSARCM = 165
HPPA_INS_MTSM = 166
HPPA_INS_MTSP = 167
HPPA_INS_NOP = 168
HPPA_INS_OR = 169
HPPA_INS_PDC = 170
HPPA_INS_PDTLB = 171
HPPA_INS_PDTLBE = 172
HPPA_INS_PERMH = 173
HPPA_INS_PITLB = 174
HPPA_INS_PITLBE = 175
HPPA_INS_PMDIS = 176
HPPA_INS_PMENB = 177
HPPA_INS_POPBTS = 178
HPPA_INS_PROBE = 179
HPPA_INS_PROBEI = 180
HPPA_INS_PROBER = 181
HPPA_INS_PROBERI = 182
HPPA_INS_PROBEW = 183
HPPA_INS_PROBEWI = 184
HPPA_INS_PUSHBTS = 185
HPPA_INS_PUSHNOM = 186
HPPA_INS_RET = 187
HPPA_INS_RFI = 188
HPPA_INS_RFIR = 189
HPPA_INS_RSM = 190
HPPA_INS_SHDWGR = 191
HPPA_INS_SHLADD = 192
HPPA_INS_SH1ADD = 193
HPPA_INS_SH1ADDL = 194
HPPA_INS_SH1ADDO = 195
HPPA_INS_SH2ADD = 196
HPPA_INS_SH2ADDL = 197
HPPA_INS_SH2ADDO = 198
HPPA_INS_SH3ADD = 199
HPPA_INS_SH3ADDL = 200
HPPA_INS_SH3ADDO = 201
HPPA_INS_SHD = 202
HPPA_INS_SHRPD = 203
HPPA_INS_SHRPW = 204
HPPA_INS_SPOP0 = 205
HPPA_INS_SPOP1 = 206
HPPA_INS_SPOP2 = 207
HPPA_INS_SPOP3 = 208
HPPA_INS_SSM = 209
HPPA_INS_STB = 210
HPPA_INS_STBS = 211
HPPA_INS_STBY = 212
HPPA_INS_STBYS = 213
HPPA_INS_STD = 214
HPPA_INS_STDA = 215
HPPA_INS_STDBY = 216
HPPA_INS_STH = 217
HPPA_INS_STHS = 218
HPPA_INS_STW = 219
HPPA_INS_STWA = 220
HPPA_INS_STWAS = 221
HPPA_INS_STWS = 222
HPPA_INS_STWM = 223
HPPA_INS_SUB = 224
HPPA_INS_SUBB = 225
HPPA_INS_SUBBO = 226
HPPA_INS_SUBI = 227
HPPA_INS_SUBIO = 228
HPPA_INS_SUBO = 229
HPPA_INS_SUBT = 230
HPPA_INS_SUBTO = 231
HPPA_INS_SYNC = 232
HPPA_INS_SYNCDMA = 233
HPPA_INS_TOCDIS = 234
HPPA_INS_TOCEN = 235
HPPA_INS_UADDCM = 236
HPPA_INS_UADDCMT = 237
HPPA_INS_UXOR = 238
HPPA_INS_VDEP = 239
HPPA_INS_VDEPI = 240
HPPA_INS_VEXTRS = 241
HPPA_INS_VEXTRU = 242
HPPA_INS_VSHD = 243
HPPA_INS_XMPYU = 244
HPPA_INS_XOR = 245
HPPA_INS_ZDEP = 246
HPPA_INS_ZDEPI = 247
HPPA_INS_ZVDEP = 248
HPPA_INS_ZVDEPI = 249
HPPA_INS_ENDING = 250
HPPA_MOD_STR = 0
HPPA_MOD_INT = 1
HPPA_GRP_INVALID = 0
HPPA_GRP_COMPUTATION = 128
HPPA_GRP_MULTIMEDIA = 129
HPPA_GRP_MEM_REF = 130
HPPA_GRP_LONG_IMM = 131
HPPA_GRP_BRANCH = 132
HPPA_GRP_SYSCTRL = 133
HPPA_GRP_ASSIST = 134
HPPA_GRP_FLOAT = 135
HPPA_GRP_PERFMON = 136
HPPA_GRP_ENDING = 137

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thirdparty/capstone/bindings/python/capstone/loongarch.py vendored Normal file
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# Copyright © 2024 Rot127 <unisono@quyllur.org>
# SPDX-License-Identifier: BSD-3
import ctypes
from . import copy_ctypes_list
from .loongarch_const import *
class LoongArchOpMem(ctypes.Structure):
_fields_ = (
("base", ctypes.c_uint),
("index", ctypes.c_uint),
("disp", ctypes.c_int64),
)
class LoongArchOpValue(ctypes.Union):
_fields_ = (
("reg", ctypes.c_uint),
("imm", ctypes.c_int64),
("mem", LoongArchOpMem),
)
class LoongArchOp(ctypes.Structure):
_fields_ = (
("type", ctypes.c_uint8),
("value", LoongArchOpValue),
("access", ctypes.c_uint8),
)
@property
def imm(self):
return self.value.imm
@property
def reg(self):
return self.value.reg
@property
def mem(self):
return self.value.mem
# Instruction structure
class CsLoongArch(ctypes.Structure):
_fields_ = (
("format", ctypes.c_int),
("op_count", ctypes.c_uint8),
("operands", LoongArchOp * 8)
)
def get_arch_info(a):
return a.format, copy_ctypes_list(a.operands[: a.op_count])

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thirdparty/capstone/bindings/python/capstone/loongarch_const.py vendored Normal file
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88
thirdparty/capstone/bindings/python/capstone/m680x.py vendored Normal file
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# Capstone Python bindings, by Wolfgang Schwotzer <wolfgang.schwotzer@gmx.net>
import ctypes
from . import copy_ctypes_list
from .m680x_const import *
# define the API
class M680xOpIdx(ctypes.Structure):
_fields_ = (
('base_reg', ctypes.c_uint),
('offset_reg', ctypes.c_uint),
('offset', ctypes.c_int16),
('offset_addr', ctypes.c_uint16),
('offset_bits', ctypes.c_uint8),
('inc_dec', ctypes.c_int8),
('flags', ctypes.c_uint8),
)
class M680xOpRel(ctypes.Structure):
_fields_ = (
('address', ctypes.c_uint16),
('offset', ctypes.c_int16),
)
class M680xOpExt(ctypes.Structure):
_fields_ = (
('address', ctypes.c_uint16),
('indirect', ctypes.c_bool),
)
class M680xOpValue(ctypes.Union):
_fields_ = (
('imm', ctypes.c_int32),
('reg', ctypes.c_uint),
('idx', M680xOpIdx),
('rel', M680xOpRel),
('ext', M680xOpExt),
('direct_addr', ctypes.c_uint8),
('const_val', ctypes.c_uint8),
)
class M680xOp(ctypes.Structure):
_fields_ = (
('type', ctypes.c_uint),
('value', M680xOpValue),
('size', ctypes.c_uint8),
('access', ctypes.c_uint8),
)
@property
def imm(self):
return self.value.imm
@property
def reg(self):
return self.value.reg
@property
def idx(self):
return self.value.idx
@property
def rel(self):
return self.value.rel
@property
def ext(self):
return self.value.ext
@property
def direct_addr(self):
return self.value.direct_addr
@property
def const_val(self):
return self.value.const_val
class CsM680x(ctypes.Structure):
_fields_ = (
('flags', ctypes.c_uint8),
('op_count', ctypes.c_uint8),
('operands', M680xOp * 9),
)
def get_arch_info(a):
return (a.flags, copy_ctypes_list(a.operands[:a.op_count]))

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thirdparty/capstone/bindings/python/capstone/m680x_const.py vendored Normal file
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from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [m680x_const.py]
M680X_OPERAND_COUNT = 9
M680X_REG_INVALID = 0
M680X_REG_A = 1
M680X_REG_B = 2
M680X_REG_E = 3
M680X_REG_F = 4
M680X_REG_0 = 5
M680X_REG_D = 6
M680X_REG_W = 7
M680X_REG_CC = 8
M680X_REG_DP = 9
M680X_REG_MD = 10
M680X_REG_HX = 11
M680X_REG_H = 12
M680X_REG_X = 13
M680X_REG_Y = 14
M680X_REG_S = 15
M680X_REG_U = 16
M680X_REG_V = 17
M680X_REG_Q = 18
M680X_REG_PC = 19
M680X_REG_TMP2 = 20
M680X_REG_TMP3 = 21
M680X_REG_ENDING = 22
M680X_OP_INVALID = 0
M680X_OP_REGISTER = 1
M680X_OP_IMMEDIATE = 2
M680X_OP_INDEXED = 3
M680X_OP_EXTENDED = 4
M680X_OP_DIRECT = 5
M680X_OP_RELATIVE = 6
M680X_OP_CONSTANT = 7
M680X_OFFSET_NONE = 0
M680X_OFFSET_BITS_5 = 5
M680X_OFFSET_BITS_8 = 8
M680X_OFFSET_BITS_9 = 9
M680X_OFFSET_BITS_16 = 16
M680X_IDX_INDIRECT = 1
M680X_IDX_NO_COMMA = 2
M680X_IDX_POST_INC_DEC = 4
M680X_GRP_INVALID = 0
M680X_GRP_JUMP = 1
M680X_GRP_CALL = 2
M680X_GRP_RET = 3
M680X_GRP_INT = 4
M680X_GRP_IRET = 5
M680X_GRP_PRIV = 6
M680X_GRP_BRAREL = 7
M680X_GRP_ENDING = 8
M680X_FIRST_OP_IN_MNEM = 1
M680X_SECOND_OP_IN_MNEM = 2
M680X_INS_INVLD = 0
M680X_INS_ABA = 1
M680X_INS_ABX = 2
M680X_INS_ABY = 3
M680X_INS_ADC = 4
M680X_INS_ADCA = 5
M680X_INS_ADCB = 6
M680X_INS_ADCD = 7
M680X_INS_ADCR = 8
M680X_INS_ADD = 9
M680X_INS_ADDA = 10
M680X_INS_ADDB = 11
M680X_INS_ADDD = 12
M680X_INS_ADDE = 13
M680X_INS_ADDF = 14
M680X_INS_ADDR = 15
M680X_INS_ADDW = 16
M680X_INS_AIM = 17
M680X_INS_AIS = 18
M680X_INS_AIX = 19
M680X_INS_AND = 20
M680X_INS_ANDA = 21
M680X_INS_ANDB = 22
M680X_INS_ANDCC = 23
M680X_INS_ANDD = 24
M680X_INS_ANDR = 25
M680X_INS_ASL = 26
M680X_INS_ASLA = 27
M680X_INS_ASLB = 28
M680X_INS_ASLD = 29
M680X_INS_ASR = 30
M680X_INS_ASRA = 31
M680X_INS_ASRB = 32
M680X_INS_ASRD = 33
M680X_INS_ASRX = 34
M680X_INS_BAND = 35
M680X_INS_BCC = 36
M680X_INS_BCLR = 37
M680X_INS_BCS = 38
M680X_INS_BEOR = 39
M680X_INS_BEQ = 40
M680X_INS_BGE = 41
M680X_INS_BGND = 42
M680X_INS_BGT = 43
M680X_INS_BHCC = 44
M680X_INS_BHCS = 45
M680X_INS_BHI = 46
M680X_INS_BIAND = 47
M680X_INS_BIEOR = 48
M680X_INS_BIH = 49
M680X_INS_BIL = 50
M680X_INS_BIOR = 51
M680X_INS_BIT = 52
M680X_INS_BITA = 53
M680X_INS_BITB = 54
M680X_INS_BITD = 55
M680X_INS_BITMD = 56
M680X_INS_BLE = 57
M680X_INS_BLS = 58
M680X_INS_BLT = 59
M680X_INS_BMC = 60
M680X_INS_BMI = 61
M680X_INS_BMS = 62
M680X_INS_BNE = 63
M680X_INS_BOR = 64
M680X_INS_BPL = 65
M680X_INS_BRCLR = 66
M680X_INS_BRSET = 67
M680X_INS_BRA = 68
M680X_INS_BRN = 69
M680X_INS_BSET = 70
M680X_INS_BSR = 71
M680X_INS_BVC = 72
M680X_INS_BVS = 73
M680X_INS_CALL = 74
M680X_INS_CBA = 75
M680X_INS_CBEQ = 76
M680X_INS_CBEQA = 77
M680X_INS_CBEQX = 78
M680X_INS_CLC = 79
M680X_INS_CLI = 80
M680X_INS_CLR = 81
M680X_INS_CLRA = 82
M680X_INS_CLRB = 83
M680X_INS_CLRD = 84
M680X_INS_CLRE = 85
M680X_INS_CLRF = 86
M680X_INS_CLRH = 87
M680X_INS_CLRW = 88
M680X_INS_CLRX = 89
M680X_INS_CLV = 90
M680X_INS_CMP = 91
M680X_INS_CMPA = 92
M680X_INS_CMPB = 93
M680X_INS_CMPD = 94
M680X_INS_CMPE = 95
M680X_INS_CMPF = 96
M680X_INS_CMPR = 97
M680X_INS_CMPS = 98
M680X_INS_CMPU = 99
M680X_INS_CMPW = 100
M680X_INS_CMPX = 101
M680X_INS_CMPY = 102
M680X_INS_COM = 103
M680X_INS_COMA = 104
M680X_INS_COMB = 105
M680X_INS_COMD = 106
M680X_INS_COME = 107
M680X_INS_COMF = 108
M680X_INS_COMW = 109
M680X_INS_COMX = 110
M680X_INS_CPD = 111
M680X_INS_CPHX = 112
M680X_INS_CPS = 113
M680X_INS_CPX = 114
M680X_INS_CPY = 115
M680X_INS_CWAI = 116
M680X_INS_DAA = 117
M680X_INS_DBEQ = 118
M680X_INS_DBNE = 119
M680X_INS_DBNZ = 120
M680X_INS_DBNZA = 121
M680X_INS_DBNZX = 122
M680X_INS_DEC = 123
M680X_INS_DECA = 124
M680X_INS_DECB = 125
M680X_INS_DECD = 126
M680X_INS_DECE = 127
M680X_INS_DECF = 128
M680X_INS_DECW = 129
M680X_INS_DECX = 130
M680X_INS_DES = 131
M680X_INS_DEX = 132
M680X_INS_DEY = 133
M680X_INS_DIV = 134
M680X_INS_DIVD = 135
M680X_INS_DIVQ = 136
M680X_INS_EDIV = 137
M680X_INS_EDIVS = 138
M680X_INS_EIM = 139
M680X_INS_EMACS = 140
M680X_INS_EMAXD = 141
M680X_INS_EMAXM = 142
M680X_INS_EMIND = 143
M680X_INS_EMINM = 144
M680X_INS_EMUL = 145
M680X_INS_EMULS = 146
M680X_INS_EOR = 147
M680X_INS_EORA = 148
M680X_INS_EORB = 149
M680X_INS_EORD = 150
M680X_INS_EORR = 151
M680X_INS_ETBL = 152
M680X_INS_EXG = 153
M680X_INS_FDIV = 154
M680X_INS_IBEQ = 155
M680X_INS_IBNE = 156
M680X_INS_IDIV = 157
M680X_INS_IDIVS = 158
M680X_INS_ILLGL = 159
M680X_INS_INC = 160
M680X_INS_INCA = 161
M680X_INS_INCB = 162
M680X_INS_INCD = 163
M680X_INS_INCE = 164
M680X_INS_INCF = 165
M680X_INS_INCW = 166
M680X_INS_INCX = 167
M680X_INS_INS = 168
M680X_INS_INX = 169
M680X_INS_INY = 170
M680X_INS_JMP = 171
M680X_INS_JSR = 172
M680X_INS_LBCC = 173
M680X_INS_LBCS = 174
M680X_INS_LBEQ = 175
M680X_INS_LBGE = 176
M680X_INS_LBGT = 177
M680X_INS_LBHI = 178
M680X_INS_LBLE = 179
M680X_INS_LBLS = 180
M680X_INS_LBLT = 181
M680X_INS_LBMI = 182
M680X_INS_LBNE = 183
M680X_INS_LBPL = 184
M680X_INS_LBRA = 185
M680X_INS_LBRN = 186
M680X_INS_LBSR = 187
M680X_INS_LBVC = 188
M680X_INS_LBVS = 189
M680X_INS_LDA = 190
M680X_INS_LDAA = 191
M680X_INS_LDAB = 192
M680X_INS_LDB = 193
M680X_INS_LDBT = 194
M680X_INS_LDD = 195
M680X_INS_LDE = 196
M680X_INS_LDF = 197
M680X_INS_LDHX = 198
M680X_INS_LDMD = 199
M680X_INS_LDQ = 200
M680X_INS_LDS = 201
M680X_INS_LDU = 202
M680X_INS_LDW = 203
M680X_INS_LDX = 204
M680X_INS_LDY = 205
M680X_INS_LEAS = 206
M680X_INS_LEAU = 207
M680X_INS_LEAX = 208
M680X_INS_LEAY = 209
M680X_INS_LSL = 210
M680X_INS_LSLA = 211
M680X_INS_LSLB = 212
M680X_INS_LSLD = 213
M680X_INS_LSLX = 214
M680X_INS_LSR = 215
M680X_INS_LSRA = 216
M680X_INS_LSRB = 217
M680X_INS_LSRD = 218
M680X_INS_LSRW = 219
M680X_INS_LSRX = 220
M680X_INS_MAXA = 221
M680X_INS_MAXM = 222
M680X_INS_MEM = 223
M680X_INS_MINA = 224
M680X_INS_MINM = 225
M680X_INS_MOV = 226
M680X_INS_MOVB = 227
M680X_INS_MOVW = 228
M680X_INS_MUL = 229
M680X_INS_MULD = 230
M680X_INS_NEG = 231
M680X_INS_NEGA = 232
M680X_INS_NEGB = 233
M680X_INS_NEGD = 234
M680X_INS_NEGX = 235
M680X_INS_NOP = 236
M680X_INS_NSA = 237
M680X_INS_OIM = 238
M680X_INS_ORA = 239
M680X_INS_ORAA = 240
M680X_INS_ORAB = 241
M680X_INS_ORB = 242
M680X_INS_ORCC = 243
M680X_INS_ORD = 244
M680X_INS_ORR = 245
M680X_INS_PSHA = 246
M680X_INS_PSHB = 247
M680X_INS_PSHC = 248
M680X_INS_PSHD = 249
M680X_INS_PSHH = 250
M680X_INS_PSHS = 251
M680X_INS_PSHSW = 252
M680X_INS_PSHU = 253
M680X_INS_PSHUW = 254
M680X_INS_PSHX = 255
M680X_INS_PSHY = 256
M680X_INS_PULA = 257
M680X_INS_PULB = 258
M680X_INS_PULC = 259
M680X_INS_PULD = 260
M680X_INS_PULH = 261
M680X_INS_PULS = 262
M680X_INS_PULSW = 263
M680X_INS_PULU = 264
M680X_INS_PULUW = 265
M680X_INS_PULX = 266
M680X_INS_PULY = 267
M680X_INS_REV = 268
M680X_INS_REVW = 269
M680X_INS_ROL = 270
M680X_INS_ROLA = 271
M680X_INS_ROLB = 272
M680X_INS_ROLD = 273
M680X_INS_ROLW = 274
M680X_INS_ROLX = 275
M680X_INS_ROR = 276
M680X_INS_RORA = 277
M680X_INS_RORB = 278
M680X_INS_RORD = 279
M680X_INS_RORW = 280
M680X_INS_RORX = 281
M680X_INS_RSP = 282
M680X_INS_RTC = 283
M680X_INS_RTI = 284
M680X_INS_RTS = 285
M680X_INS_SBA = 286
M680X_INS_SBC = 287
M680X_INS_SBCA = 288
M680X_INS_SBCB = 289
M680X_INS_SBCD = 290
M680X_INS_SBCR = 291
M680X_INS_SEC = 292
M680X_INS_SEI = 293
M680X_INS_SEV = 294
M680X_INS_SEX = 295
M680X_INS_SEXW = 296
M680X_INS_SLP = 297
M680X_INS_STA = 298
M680X_INS_STAA = 299
M680X_INS_STAB = 300
M680X_INS_STB = 301
M680X_INS_STBT = 302
M680X_INS_STD = 303
M680X_INS_STE = 304
M680X_INS_STF = 305
M680X_INS_STOP = 306
M680X_INS_STHX = 307
M680X_INS_STQ = 308
M680X_INS_STS = 309
M680X_INS_STU = 310
M680X_INS_STW = 311
M680X_INS_STX = 312
M680X_INS_STY = 313
M680X_INS_SUB = 314
M680X_INS_SUBA = 315
M680X_INS_SUBB = 316
M680X_INS_SUBD = 317
M680X_INS_SUBE = 318
M680X_INS_SUBF = 319
M680X_INS_SUBR = 320
M680X_INS_SUBW = 321
M680X_INS_SWI = 322
M680X_INS_SWI2 = 323
M680X_INS_SWI3 = 324
M680X_INS_SYNC = 325
M680X_INS_TAB = 326
M680X_INS_TAP = 327
M680X_INS_TAX = 328
M680X_INS_TBA = 329
M680X_INS_TBEQ = 330
M680X_INS_TBL = 331
M680X_INS_TBNE = 332
M680X_INS_TEST = 333
M680X_INS_TFM = 334
M680X_INS_TFR = 335
M680X_INS_TIM = 336
M680X_INS_TPA = 337
M680X_INS_TST = 338
M680X_INS_TSTA = 339
M680X_INS_TSTB = 340
M680X_INS_TSTD = 341
M680X_INS_TSTE = 342
M680X_INS_TSTF = 343
M680X_INS_TSTW = 344
M680X_INS_TSTX = 345
M680X_INS_TSX = 346
M680X_INS_TSY = 347
M680X_INS_TXA = 348
M680X_INS_TXS = 349
M680X_INS_TYS = 350
M680X_INS_WAI = 351
M680X_INS_WAIT = 352
M680X_INS_WAV = 353
M680X_INS_WAVR = 354
M680X_INS_XGDX = 355
M680X_INS_XGDY = 356
M680X_INS_ENDING = 357

100
thirdparty/capstone/bindings/python/capstone/m68k.py vendored Normal file
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# Capstone Python bindings, by Nicolas PLANEL <nplanel@gmail.com>
import ctypes
from . import copy_ctypes_list
from .m68k_const import *
# define the API
class M68KOpMem(ctypes.Structure):
_fields_ = (
('base_reg', ctypes.c_uint),
('index_reg', ctypes.c_uint),
('in_base_reg', ctypes.c_uint),
('in_disp', ctypes.c_uint),
('out_disp', ctypes.c_uint),
('disp', ctypes.c_short),
('scale', ctypes.c_ubyte),
('bitfield', ctypes.c_ubyte),
('width', ctypes.c_ubyte),
('offset', ctypes.c_ubyte),
('index_size', ctypes.c_ubyte),
)
class M68KOpRegPair(ctypes.Structure):
_fields_ = (
('reg_0', ctypes.c_uint),
('reg_1', ctypes.c_uint),
)
class M68KOpValue(ctypes.Union):
_fields_ = (
('imm', ctypes.c_int64),
('dimm', ctypes.c_double),
('simm', ctypes.c_float),
('reg', ctypes.c_uint),
('reg_pair', M68KOpRegPair),
)
class M68KOpBrDisp(ctypes.Structure):
_fields_ = (
('disp', ctypes.c_int),
('disp_size', ctypes.c_ubyte),
)
class M68KOp(ctypes.Structure):
_fields_ = (
('value', M68KOpValue),
('mem', M68KOpMem),
('br_disp', M68KOpBrDisp),
('register_bits', ctypes.c_uint),
('type', ctypes.c_uint),
('address_mode', ctypes.c_uint),
)
@property
def imm(self):
return self.value.imm
@property
def dimm(self):
return self.value.dimm
@property
def simm(self):
return self.value.simm
@property
def reg(self):
return self.value.reg
@property
def reg_pair(self):
return self.value.reg_pair
@property
def mem(self):
return self.mem
@property
def register_bits(self):
return self.register_bits
class M68KOpSize(ctypes.Structure):
_fields_ = (
('type', ctypes.c_uint),
('size', ctypes.c_uint),
)
def get(a):
return copy_ctypes_list(type, size)
class CsM68K(ctypes.Structure):
M68K_OPERAND_COUNT = 4
_fields_ = (
('operands', M68KOp * M68K_OPERAND_COUNT),
('op_size', M68KOpSize),
('op_count', ctypes.c_uint8),
)
def get_arch_info(a):
return (copy_ctypes_list(a.operands[:a.op_count]), a.op_size)

486
thirdparty/capstone/bindings/python/capstone/m68k_const.py vendored Normal file
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from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [m68k_const.py]
M68K_OPERAND_COUNT = 4
M68K_REG_INVALID = 0
M68K_REG_D0 = 1
M68K_REG_D1 = 2
M68K_REG_D2 = 3
M68K_REG_D3 = 4
M68K_REG_D4 = 5
M68K_REG_D5 = 6
M68K_REG_D6 = 7
M68K_REG_D7 = 8
M68K_REG_A0 = 9
M68K_REG_A1 = 10
M68K_REG_A2 = 11
M68K_REG_A3 = 12
M68K_REG_A4 = 13
M68K_REG_A5 = 14
M68K_REG_A6 = 15
M68K_REG_A7 = 16
M68K_REG_FP0 = 17
M68K_REG_FP1 = 18
M68K_REG_FP2 = 19
M68K_REG_FP3 = 20
M68K_REG_FP4 = 21
M68K_REG_FP5 = 22
M68K_REG_FP6 = 23
M68K_REG_FP7 = 24
M68K_REG_PC = 25
M68K_REG_SR = 26
M68K_REG_CCR = 27
M68K_REG_SFC = 28
M68K_REG_DFC = 29
M68K_REG_USP = 30
M68K_REG_VBR = 31
M68K_REG_CACR = 32
M68K_REG_CAAR = 33
M68K_REG_MSP = 34
M68K_REG_ISP = 35
M68K_REG_TC = 36
M68K_REG_ITT0 = 37
M68K_REG_ITT1 = 38
M68K_REG_DTT0 = 39
M68K_REG_DTT1 = 40
M68K_REG_MMUSR = 41
M68K_REG_URP = 42
M68K_REG_SRP = 43
M68K_REG_FPCR = 44
M68K_REG_FPSR = 45
M68K_REG_FPIAR = 46
M68K_REG_ENDING = 47
M68K_AM_NONE = 0
M68K_AM_REG_DIRECT_DATA = 1
M68K_AM_REG_DIRECT_ADDR = 2
M68K_AM_REGI_ADDR = 3
M68K_AM_REGI_ADDR_POST_INC = 4
M68K_AM_REGI_ADDR_PRE_DEC = 5
M68K_AM_REGI_ADDR_DISP = 6
M68K_AM_AREGI_INDEX_8_BIT_DISP = 7
M68K_AM_AREGI_INDEX_BASE_DISP = 8
M68K_AM_MEMI_POST_INDEX = 9
M68K_AM_MEMI_PRE_INDEX = 10
M68K_AM_PCI_DISP = 11
M68K_AM_PCI_INDEX_8_BIT_DISP = 12
M68K_AM_PCI_INDEX_BASE_DISP = 13
M68K_AM_PC_MEMI_POST_INDEX = 14
M68K_AM_PC_MEMI_PRE_INDEX = 15
M68K_AM_ABSOLUTE_DATA_SHORT = 16
M68K_AM_ABSOLUTE_DATA_LONG = 17
M68K_AM_IMMEDIATE = 18
M68K_AM_BRANCH_DISPLACEMENT = 19
M68K_OP_INVALID = 0
M68K_OP_REG = 1
M68K_OP_IMM = 2
M68K_OP_MEM = 3
M68K_OP_FP_SINGLE = 4
M68K_OP_FP_DOUBLE = 5
M68K_OP_REG_BITS = 6
M68K_OP_REG_PAIR = 7
M68K_OP_BR_DISP = 8
M68K_OP_BR_DISP_SIZE_INVALID = 0
M68K_OP_BR_DISP_SIZE_BYTE = 1
M68K_OP_BR_DISP_SIZE_WORD = 2
M68K_OP_BR_DISP_SIZE_LONG = 4
M68K_CPU_SIZE_NONE = 0
M68K_CPU_SIZE_BYTE = 1
M68K_CPU_SIZE_WORD = 2
M68K_CPU_SIZE_LONG = 4
M68K_FPU_SIZE_NONE = 0
M68K_FPU_SIZE_SINGLE = 4
M68K_FPU_SIZE_DOUBLE = 8
M68K_FPU_SIZE_EXTENDED = 12
M68K_SIZE_TYPE_INVALID = 0
M68K_SIZE_TYPE_CPU = 1
M68K_SIZE_TYPE_FPU = 2
M68K_INS_INVALID = 0
M68K_INS_ABCD = 1
M68K_INS_ADD = 2
M68K_INS_ADDA = 3
M68K_INS_ADDI = 4
M68K_INS_ADDQ = 5
M68K_INS_ADDX = 6
M68K_INS_AND = 7
M68K_INS_ANDI = 8
M68K_INS_ASL = 9
M68K_INS_ASR = 10
M68K_INS_BHS = 11
M68K_INS_BLO = 12
M68K_INS_BHI = 13
M68K_INS_BLS = 14
M68K_INS_BCC = 15
M68K_INS_BCS = 16
M68K_INS_BNE = 17
M68K_INS_BEQ = 18
M68K_INS_BVC = 19
M68K_INS_BVS = 20
M68K_INS_BPL = 21
M68K_INS_BMI = 22
M68K_INS_BGE = 23
M68K_INS_BLT = 24
M68K_INS_BGT = 25
M68K_INS_BLE = 26
M68K_INS_BRA = 27
M68K_INS_BSR = 28
M68K_INS_BCHG = 29
M68K_INS_BCLR = 30
M68K_INS_BSET = 31
M68K_INS_BTST = 32
M68K_INS_BFCHG = 33
M68K_INS_BFCLR = 34
M68K_INS_BFEXTS = 35
M68K_INS_BFEXTU = 36
M68K_INS_BFFFO = 37
M68K_INS_BFINS = 38
M68K_INS_BFSET = 39
M68K_INS_BFTST = 40
M68K_INS_BKPT = 41
M68K_INS_CALLM = 42
M68K_INS_CAS = 43
M68K_INS_CAS2 = 44
M68K_INS_CHK = 45
M68K_INS_CHK2 = 46
M68K_INS_CLR = 47
M68K_INS_CMP = 48
M68K_INS_CMPA = 49
M68K_INS_CMPI = 50
M68K_INS_CMPM = 51
M68K_INS_CMP2 = 52
M68K_INS_CINVL = 53
M68K_INS_CINVP = 54
M68K_INS_CINVA = 55
M68K_INS_CPUSHL = 56
M68K_INS_CPUSHP = 57
M68K_INS_CPUSHA = 58
M68K_INS_DBT = 59
M68K_INS_DBF = 60
M68K_INS_DBHI = 61
M68K_INS_DBLS = 62
M68K_INS_DBCC = 63
M68K_INS_DBCS = 64
M68K_INS_DBNE = 65
M68K_INS_DBEQ = 66
M68K_INS_DBVC = 67
M68K_INS_DBVS = 68
M68K_INS_DBPL = 69
M68K_INS_DBMI = 70
M68K_INS_DBGE = 71
M68K_INS_DBLT = 72
M68K_INS_DBGT = 73
M68K_INS_DBLE = 74
M68K_INS_DBRA = 75
M68K_INS_DIVS = 76
M68K_INS_DIVSL = 77
M68K_INS_DIVU = 78
M68K_INS_DIVUL = 79
M68K_INS_EOR = 80
M68K_INS_EORI = 81
M68K_INS_EXG = 82
M68K_INS_EXT = 83
M68K_INS_EXTB = 84
M68K_INS_FABS = 85
M68K_INS_FSABS = 86
M68K_INS_FDABS = 87
M68K_INS_FACOS = 88
M68K_INS_FADD = 89
M68K_INS_FSADD = 90
M68K_INS_FDADD = 91
M68K_INS_FASIN = 92
M68K_INS_FATAN = 93
M68K_INS_FATANH = 94
M68K_INS_FBF = 95
M68K_INS_FBEQ = 96
M68K_INS_FBOGT = 97
M68K_INS_FBOGE = 98
M68K_INS_FBOLT = 99
M68K_INS_FBOLE = 100
M68K_INS_FBOGL = 101
M68K_INS_FBOR = 102
M68K_INS_FBUN = 103
M68K_INS_FBUEQ = 104
M68K_INS_FBUGT = 105
M68K_INS_FBUGE = 106
M68K_INS_FBULT = 107
M68K_INS_FBULE = 108
M68K_INS_FBNE = 109
M68K_INS_FBT = 110
M68K_INS_FBSF = 111
M68K_INS_FBSEQ = 112
M68K_INS_FBGT = 113
M68K_INS_FBGE = 114
M68K_INS_FBLT = 115
M68K_INS_FBLE = 116
M68K_INS_FBGL = 117
M68K_INS_FBGLE = 118
M68K_INS_FBNGLE = 119
M68K_INS_FBNGL = 120
M68K_INS_FBNLE = 121
M68K_INS_FBNLT = 122
M68K_INS_FBNGE = 123
M68K_INS_FBNGT = 124
M68K_INS_FBSNE = 125
M68K_INS_FBST = 126
M68K_INS_FCMP = 127
M68K_INS_FCOS = 128
M68K_INS_FCOSH = 129
M68K_INS_FDBF = 130
M68K_INS_FDBEQ = 131
M68K_INS_FDBOGT = 132
M68K_INS_FDBOGE = 133
M68K_INS_FDBOLT = 134
M68K_INS_FDBOLE = 135
M68K_INS_FDBOGL = 136
M68K_INS_FDBOR = 137
M68K_INS_FDBUN = 138
M68K_INS_FDBUEQ = 139
M68K_INS_FDBUGT = 140
M68K_INS_FDBUGE = 141
M68K_INS_FDBULT = 142
M68K_INS_FDBULE = 143
M68K_INS_FDBNE = 144
M68K_INS_FDBT = 145
M68K_INS_FDBSF = 146
M68K_INS_FDBSEQ = 147
M68K_INS_FDBGT = 148
M68K_INS_FDBGE = 149
M68K_INS_FDBLT = 150
M68K_INS_FDBLE = 151
M68K_INS_FDBGL = 152
M68K_INS_FDBGLE = 153
M68K_INS_FDBNGLE = 154
M68K_INS_FDBNGL = 155
M68K_INS_FDBNLE = 156
M68K_INS_FDBNLT = 157
M68K_INS_FDBNGE = 158
M68K_INS_FDBNGT = 159
M68K_INS_FDBSNE = 160
M68K_INS_FDBST = 161
M68K_INS_FDIV = 162
M68K_INS_FSDIV = 163
M68K_INS_FDDIV = 164
M68K_INS_FETOX = 165
M68K_INS_FETOXM1 = 166
M68K_INS_FGETEXP = 167
M68K_INS_FGETMAN = 168
M68K_INS_FINT = 169
M68K_INS_FINTRZ = 170
M68K_INS_FLOG10 = 171
M68K_INS_FLOG2 = 172
M68K_INS_FLOGN = 173
M68K_INS_FLOGNP1 = 174
M68K_INS_FMOD = 175
M68K_INS_FMOVE = 176
M68K_INS_FSMOVE = 177
M68K_INS_FDMOVE = 178
M68K_INS_FMOVECR = 179
M68K_INS_FMOVEM = 180
M68K_INS_FMUL = 181
M68K_INS_FSMUL = 182
M68K_INS_FDMUL = 183
M68K_INS_FNEG = 184
M68K_INS_FSNEG = 185
M68K_INS_FDNEG = 186
M68K_INS_FNOP = 187
M68K_INS_FREM = 188
M68K_INS_FRESTORE = 189
M68K_INS_FSAVE = 190
M68K_INS_FSCALE = 191
M68K_INS_FSGLDIV = 192
M68K_INS_FSGLMUL = 193
M68K_INS_FSIN = 194
M68K_INS_FSINCOS = 195
M68K_INS_FSINH = 196
M68K_INS_FSQRT = 197
M68K_INS_FSSQRT = 198
M68K_INS_FDSQRT = 199
M68K_INS_FSF = 200
M68K_INS_FSBEQ = 201
M68K_INS_FSOGT = 202
M68K_INS_FSOGE = 203
M68K_INS_FSOLT = 204
M68K_INS_FSOLE = 205
M68K_INS_FSOGL = 206
M68K_INS_FSOR = 207
M68K_INS_FSUN = 208
M68K_INS_FSUEQ = 209
M68K_INS_FSUGT = 210
M68K_INS_FSUGE = 211
M68K_INS_FSULT = 212
M68K_INS_FSULE = 213
M68K_INS_FSNE = 214
M68K_INS_FST = 215
M68K_INS_FSSF = 216
M68K_INS_FSSEQ = 217
M68K_INS_FSGT = 218
M68K_INS_FSGE = 219
M68K_INS_FSLT = 220
M68K_INS_FSLE = 221
M68K_INS_FSGL = 222
M68K_INS_FSGLE = 223
M68K_INS_FSNGLE = 224
M68K_INS_FSNGL = 225
M68K_INS_FSNLE = 226
M68K_INS_FSNLT = 227
M68K_INS_FSNGE = 228
M68K_INS_FSNGT = 229
M68K_INS_FSSNE = 230
M68K_INS_FSST = 231
M68K_INS_FSUB = 232
M68K_INS_FSSUB = 233
M68K_INS_FDSUB = 234
M68K_INS_FTAN = 235
M68K_INS_FTANH = 236
M68K_INS_FTENTOX = 237
M68K_INS_FTRAPF = 238
M68K_INS_FTRAPEQ = 239
M68K_INS_FTRAPOGT = 240
M68K_INS_FTRAPOGE = 241
M68K_INS_FTRAPOLT = 242
M68K_INS_FTRAPOLE = 243
M68K_INS_FTRAPOGL = 244
M68K_INS_FTRAPOR = 245
M68K_INS_FTRAPUN = 246
M68K_INS_FTRAPUEQ = 247
M68K_INS_FTRAPUGT = 248
M68K_INS_FTRAPUGE = 249
M68K_INS_FTRAPULT = 250
M68K_INS_FTRAPULE = 251
M68K_INS_FTRAPNE = 252
M68K_INS_FTRAPT = 253
M68K_INS_FTRAPSF = 254
M68K_INS_FTRAPSEQ = 255
M68K_INS_FTRAPGT = 256
M68K_INS_FTRAPGE = 257
M68K_INS_FTRAPLT = 258
M68K_INS_FTRAPLE = 259
M68K_INS_FTRAPGL = 260
M68K_INS_FTRAPGLE = 261
M68K_INS_FTRAPNGLE = 262
M68K_INS_FTRAPNGL = 263
M68K_INS_FTRAPNLE = 264
M68K_INS_FTRAPNLT = 265
M68K_INS_FTRAPNGE = 266
M68K_INS_FTRAPNGT = 267
M68K_INS_FTRAPSNE = 268
M68K_INS_FTRAPST = 269
M68K_INS_FTST = 270
M68K_INS_FTWOTOX = 271
M68K_INS_HALT = 272
M68K_INS_ILLEGAL = 273
M68K_INS_JMP = 274
M68K_INS_JSR = 275
M68K_INS_LEA = 276
M68K_INS_LINK = 277
M68K_INS_LPSTOP = 278
M68K_INS_LSL = 279
M68K_INS_LSR = 280
M68K_INS_MOVE = 281
M68K_INS_MOVEA = 282
M68K_INS_MOVEC = 283
M68K_INS_MOVEM = 284
M68K_INS_MOVEP = 285
M68K_INS_MOVEQ = 286
M68K_INS_MOVES = 287
M68K_INS_MOVE16 = 288
M68K_INS_MULS = 289
M68K_INS_MULU = 290
M68K_INS_NBCD = 291
M68K_INS_NEG = 292
M68K_INS_NEGX = 293
M68K_INS_NOP = 294
M68K_INS_NOT = 295
M68K_INS_OR = 296
M68K_INS_ORI = 297
M68K_INS_PACK = 298
M68K_INS_PEA = 299
M68K_INS_PFLUSH = 300
M68K_INS_PFLUSHA = 301
M68K_INS_PFLUSHAN = 302
M68K_INS_PFLUSHN = 303
M68K_INS_PLOADR = 304
M68K_INS_PLOADW = 305
M68K_INS_PLPAR = 306
M68K_INS_PLPAW = 307
M68K_INS_PMOVE = 308
M68K_INS_PMOVEFD = 309
M68K_INS_PTESTR = 310
M68K_INS_PTESTW = 311
M68K_INS_PULSE = 312
M68K_INS_REMS = 313
M68K_INS_REMU = 314
M68K_INS_RESET = 315
M68K_INS_ROL = 316
M68K_INS_ROR = 317
M68K_INS_ROXL = 318
M68K_INS_ROXR = 319
M68K_INS_RTD = 320
M68K_INS_RTE = 321
M68K_INS_RTM = 322
M68K_INS_RTR = 323
M68K_INS_RTS = 324
M68K_INS_SBCD = 325
M68K_INS_ST = 326
M68K_INS_SF = 327
M68K_INS_SHI = 328
M68K_INS_SLS = 329
M68K_INS_SCC = 330
M68K_INS_SHS = 331
M68K_INS_SCS = 332
M68K_INS_SLO = 333
M68K_INS_SNE = 334
M68K_INS_SEQ = 335
M68K_INS_SVC = 336
M68K_INS_SVS = 337
M68K_INS_SPL = 338
M68K_INS_SMI = 339
M68K_INS_SGE = 340
M68K_INS_SLT = 341
M68K_INS_SGT = 342
M68K_INS_SLE = 343
M68K_INS_STOP = 344
M68K_INS_SUB = 345
M68K_INS_SUBA = 346
M68K_INS_SUBI = 347
M68K_INS_SUBQ = 348
M68K_INS_SUBX = 349
M68K_INS_SWAP = 350
M68K_INS_TAS = 351
M68K_INS_TRAP = 352
M68K_INS_TRAPV = 353
M68K_INS_TRAPT = 354
M68K_INS_TRAPF = 355
M68K_INS_TRAPHI = 356
M68K_INS_TRAPLS = 357
M68K_INS_TRAPCC = 358
M68K_INS_TRAPHS = 359
M68K_INS_TRAPCS = 360
M68K_INS_TRAPLO = 361
M68K_INS_TRAPNE = 362
M68K_INS_TRAPEQ = 363
M68K_INS_TRAPVC = 364
M68K_INS_TRAPVS = 365
M68K_INS_TRAPPL = 366
M68K_INS_TRAPMI = 367
M68K_INS_TRAPGE = 368
M68K_INS_TRAPLT = 369
M68K_INS_TRAPGT = 370
M68K_INS_TRAPLE = 371
M68K_INS_TST = 372
M68K_INS_UNLK = 373
M68K_INS_UNPK = 374
M68K_INS_ENDING = 375
M68K_GRP_INVALID = 0
M68K_GRP_JUMP = 1
M68K_GRP_RET = 3
M68K_GRP_IRET = 5
M68K_GRP_BRANCH_RELATIVE = 7
M68K_GRP_ENDING = 8

48
thirdparty/capstone/bindings/python/capstone/mips.py vendored Normal file
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# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
import ctypes
from . import copy_ctypes_list
from .mips_const import *
# define the API
class MipsOpMem(ctypes.Structure):
_fields_ = (
('base', ctypes.c_uint),
('disp', ctypes.c_int64),
)
class MipsOpValue(ctypes.Union):
_fields_ = (
('reg', ctypes.c_uint),
('imm', ctypes.c_int64),
('mem', MipsOpMem),
)
class MipsOp(ctypes.Structure):
_fields_ = (
('type', ctypes.c_uint),
('value', MipsOpValue),
)
@property
def imm(self):
return self.value.imm
@property
def reg(self):
return self.value.reg
@property
def mem(self):
return self.value.mem
class CsMips(ctypes.Structure):
_fields_ = (
('op_count', ctypes.c_uint8),
('operands', MipsOp * 10),
)
def get_arch_info(a):
return copy_ctypes_list(a.operands[:a.op_count])

862
thirdparty/capstone/bindings/python/capstone/mips_const.py vendored Normal file
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from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [mips_const.py]
MIPS_OP_INVALID = 0
MIPS_OP_REG = 1
MIPS_OP_IMM = 2
MIPS_OP_MEM = 3
MIPS_REG_INVALID = 0
MIPS_REG_PC = 1
MIPS_REG_0 = 2
MIPS_REG_1 = 3
MIPS_REG_2 = 4
MIPS_REG_3 = 5
MIPS_REG_4 = 6
MIPS_REG_5 = 7
MIPS_REG_6 = 8
MIPS_REG_7 = 9
MIPS_REG_8 = 10
MIPS_REG_9 = 11
MIPS_REG_10 = 12
MIPS_REG_11 = 13
MIPS_REG_12 = 14
MIPS_REG_13 = 15
MIPS_REG_14 = 16
MIPS_REG_15 = 17
MIPS_REG_16 = 18
MIPS_REG_17 = 19
MIPS_REG_18 = 20
MIPS_REG_19 = 21
MIPS_REG_20 = 22
MIPS_REG_21 = 23
MIPS_REG_22 = 24
MIPS_REG_23 = 25
MIPS_REG_24 = 26
MIPS_REG_25 = 27
MIPS_REG_26 = 28
MIPS_REG_27 = 29
MIPS_REG_28 = 30
MIPS_REG_29 = 31
MIPS_REG_30 = 32
MIPS_REG_31 = 33
MIPS_REG_DSPCCOND = 34
MIPS_REG_DSPCARRY = 35
MIPS_REG_DSPEFI = 36
MIPS_REG_DSPOUTFLAG = 37
MIPS_REG_DSPOUTFLAG16_19 = 38
MIPS_REG_DSPOUTFLAG20 = 39
MIPS_REG_DSPOUTFLAG21 = 40
MIPS_REG_DSPOUTFLAG22 = 41
MIPS_REG_DSPOUTFLAG23 = 42
MIPS_REG_DSPPOS = 43
MIPS_REG_DSPSCOUNT = 44
MIPS_REG_AC0 = 45
MIPS_REG_AC1 = 46
MIPS_REG_AC2 = 47
MIPS_REG_AC3 = 48
MIPS_REG_CC0 = 49
MIPS_REG_CC1 = 50
MIPS_REG_CC2 = 51
MIPS_REG_CC3 = 52
MIPS_REG_CC4 = 53
MIPS_REG_CC5 = 54
MIPS_REG_CC6 = 55
MIPS_REG_CC7 = 56
MIPS_REG_F0 = 57
MIPS_REG_F1 = 58
MIPS_REG_F2 = 59
MIPS_REG_F3 = 60
MIPS_REG_F4 = 61
MIPS_REG_F5 = 62
MIPS_REG_F6 = 63
MIPS_REG_F7 = 64
MIPS_REG_F8 = 65
MIPS_REG_F9 = 66
MIPS_REG_F10 = 67
MIPS_REG_F11 = 68
MIPS_REG_F12 = 69
MIPS_REG_F13 = 70
MIPS_REG_F14 = 71
MIPS_REG_F15 = 72
MIPS_REG_F16 = 73
MIPS_REG_F17 = 74
MIPS_REG_F18 = 75
MIPS_REG_F19 = 76
MIPS_REG_F20 = 77
MIPS_REG_F21 = 78
MIPS_REG_F22 = 79
MIPS_REG_F23 = 80
MIPS_REG_F24 = 81
MIPS_REG_F25 = 82
MIPS_REG_F26 = 83
MIPS_REG_F27 = 84
MIPS_REG_F28 = 85
MIPS_REG_F29 = 86
MIPS_REG_F30 = 87
MIPS_REG_F31 = 88
MIPS_REG_FCC0 = 89
MIPS_REG_FCC1 = 90
MIPS_REG_FCC2 = 91
MIPS_REG_FCC3 = 92
MIPS_REG_FCC4 = 93
MIPS_REG_FCC5 = 94
MIPS_REG_FCC6 = 95
MIPS_REG_FCC7 = 96
MIPS_REG_W0 = 97
MIPS_REG_W1 = 98
MIPS_REG_W2 = 99
MIPS_REG_W3 = 100
MIPS_REG_W4 = 101
MIPS_REG_W5 = 102
MIPS_REG_W6 = 103
MIPS_REG_W7 = 104
MIPS_REG_W8 = 105
MIPS_REG_W9 = 106
MIPS_REG_W10 = 107
MIPS_REG_W11 = 108
MIPS_REG_W12 = 109
MIPS_REG_W13 = 110
MIPS_REG_W14 = 111
MIPS_REG_W15 = 112
MIPS_REG_W16 = 113
MIPS_REG_W17 = 114
MIPS_REG_W18 = 115
MIPS_REG_W19 = 116
MIPS_REG_W20 = 117
MIPS_REG_W21 = 118
MIPS_REG_W22 = 119
MIPS_REG_W23 = 120
MIPS_REG_W24 = 121
MIPS_REG_W25 = 122
MIPS_REG_W26 = 123
MIPS_REG_W27 = 124
MIPS_REG_W28 = 125
MIPS_REG_W29 = 126
MIPS_REG_W30 = 127
MIPS_REG_W31 = 128
MIPS_REG_HI = 129
MIPS_REG_LO = 130
MIPS_REG_P0 = 131
MIPS_REG_P1 = 132
MIPS_REG_P2 = 133
MIPS_REG_MPL0 = 134
MIPS_REG_MPL1 = 135
MIPS_REG_MPL2 = 136
MIPS_REG_ENDING = 137
MIPS_REG_ZERO = MIPS_REG_0
MIPS_REG_AT = MIPS_REG_1
MIPS_REG_V0 = MIPS_REG_2
MIPS_REG_V1 = MIPS_REG_3
MIPS_REG_A0 = MIPS_REG_4
MIPS_REG_A1 = MIPS_REG_5
MIPS_REG_A2 = MIPS_REG_6
MIPS_REG_A3 = MIPS_REG_7
MIPS_REG_T0 = MIPS_REG_8
MIPS_REG_T1 = MIPS_REG_9
MIPS_REG_T2 = MIPS_REG_10
MIPS_REG_T3 = MIPS_REG_11
MIPS_REG_T4 = MIPS_REG_12
MIPS_REG_T5 = MIPS_REG_13
MIPS_REG_T6 = MIPS_REG_14
MIPS_REG_T7 = MIPS_REG_15
MIPS_REG_S0 = MIPS_REG_16
MIPS_REG_S1 = MIPS_REG_17
MIPS_REG_S2 = MIPS_REG_18
MIPS_REG_S3 = MIPS_REG_19
MIPS_REG_S4 = MIPS_REG_20
MIPS_REG_S5 = MIPS_REG_21
MIPS_REG_S6 = MIPS_REG_22
MIPS_REG_S7 = MIPS_REG_23
MIPS_REG_T8 = MIPS_REG_24
MIPS_REG_T9 = MIPS_REG_25
MIPS_REG_K0 = MIPS_REG_26
MIPS_REG_K1 = MIPS_REG_27
MIPS_REG_GP = MIPS_REG_28
MIPS_REG_SP = MIPS_REG_29
MIPS_REG_FP = MIPS_REG_30
MIPS_REG_S8 = MIPS_REG_30
MIPS_REG_RA = MIPS_REG_31
MIPS_REG_HI0 = MIPS_REG_AC0
MIPS_REG_HI1 = MIPS_REG_AC1
MIPS_REG_HI2 = MIPS_REG_AC2
MIPS_REG_HI3 = MIPS_REG_AC3
MIPS_REG_LO0 = MIPS_REG_HI0
MIPS_REG_LO1 = MIPS_REG_HI1
MIPS_REG_LO2 = MIPS_REG_HI2
MIPS_REG_LO3 = MIPS_REG_HI3
MIPS_INS_INVALID = 0
MIPS_INS_ABSQ_S = 1
MIPS_INS_ADD = 2
MIPS_INS_ADDIUPC = 3
MIPS_INS_ADDIUR1SP = 4
MIPS_INS_ADDIUR2 = 5
MIPS_INS_ADDIUS5 = 6
MIPS_INS_ADDIUSP = 7
MIPS_INS_ADDQH = 8
MIPS_INS_ADDQH_R = 9
MIPS_INS_ADDQ = 10
MIPS_INS_ADDQ_S = 11
MIPS_INS_ADDSC = 12
MIPS_INS_ADDS_A = 13
MIPS_INS_ADDS_S = 14
MIPS_INS_ADDS_U = 15
MIPS_INS_ADDU16 = 16
MIPS_INS_ADDUH = 17
MIPS_INS_ADDUH_R = 18
MIPS_INS_ADDU = 19
MIPS_INS_ADDU_S = 20
MIPS_INS_ADDVI = 21
MIPS_INS_ADDV = 22
MIPS_INS_ADDWC = 23
MIPS_INS_ADD_A = 24
MIPS_INS_ADDI = 25
MIPS_INS_ADDIU = 26
MIPS_INS_ALIGN = 27
MIPS_INS_ALUIPC = 28
MIPS_INS_AND = 29
MIPS_INS_AND16 = 30
MIPS_INS_ANDI16 = 31
MIPS_INS_ANDI = 32
MIPS_INS_APPEND = 33
MIPS_INS_ASUB_S = 34
MIPS_INS_ASUB_U = 35
MIPS_INS_AUI = 36
MIPS_INS_AUIPC = 37
MIPS_INS_AVER_S = 38
MIPS_INS_AVER_U = 39
MIPS_INS_AVE_S = 40
MIPS_INS_AVE_U = 41
MIPS_INS_B16 = 42
MIPS_INS_BADDU = 43
MIPS_INS_BAL = 44
MIPS_INS_BALC = 45
MIPS_INS_BALIGN = 46
MIPS_INS_BBIT0 = 47
MIPS_INS_BBIT032 = 48
MIPS_INS_BBIT1 = 49
MIPS_INS_BBIT132 = 50
MIPS_INS_BC = 51
MIPS_INS_BC0F = 52
MIPS_INS_BC0FL = 53
MIPS_INS_BC0T = 54
MIPS_INS_BC0TL = 55
MIPS_INS_BC1EQZ = 56
MIPS_INS_BC1F = 57
MIPS_INS_BC1FL = 58
MIPS_INS_BC1NEZ = 59
MIPS_INS_BC1T = 60
MIPS_INS_BC1TL = 61
MIPS_INS_BC2EQZ = 62
MIPS_INS_BC2F = 63
MIPS_INS_BC2FL = 64
MIPS_INS_BC2NEZ = 65
MIPS_INS_BC2T = 66
MIPS_INS_BC2TL = 67
MIPS_INS_BC3F = 68
MIPS_INS_BC3FL = 69
MIPS_INS_BC3T = 70
MIPS_INS_BC3TL = 71
MIPS_INS_BCLRI = 72
MIPS_INS_BCLR = 73
MIPS_INS_BEQ = 74
MIPS_INS_BEQC = 75
MIPS_INS_BEQL = 76
MIPS_INS_BEQZ16 = 77
MIPS_INS_BEQZALC = 78
MIPS_INS_BEQZC = 79
MIPS_INS_BGEC = 80
MIPS_INS_BGEUC = 81
MIPS_INS_BGEZ = 82
MIPS_INS_BGEZAL = 83
MIPS_INS_BGEZALC = 84
MIPS_INS_BGEZALL = 85
MIPS_INS_BGEZALS = 86
MIPS_INS_BGEZC = 87
MIPS_INS_BGEZL = 88
MIPS_INS_BGTZ = 89
MIPS_INS_BGTZALC = 90
MIPS_INS_BGTZC = 91
MIPS_INS_BGTZL = 92
MIPS_INS_BINSLI = 93
MIPS_INS_BINSL = 94
MIPS_INS_BINSRI = 95
MIPS_INS_BINSR = 96
MIPS_INS_BITREV = 97
MIPS_INS_BITSWAP = 98
MIPS_INS_BLEZ = 99
MIPS_INS_BLEZALC = 100
MIPS_INS_BLEZC = 101
MIPS_INS_BLEZL = 102
MIPS_INS_BLTC = 103
MIPS_INS_BLTUC = 104
MIPS_INS_BLTZ = 105
MIPS_INS_BLTZAL = 106
MIPS_INS_BLTZALC = 107
MIPS_INS_BLTZALL = 108
MIPS_INS_BLTZALS = 109
MIPS_INS_BLTZC = 110
MIPS_INS_BLTZL = 111
MIPS_INS_BMNZI = 112
MIPS_INS_BMNZ = 113
MIPS_INS_BMZI = 114
MIPS_INS_BMZ = 115
MIPS_INS_BNE = 116
MIPS_INS_BNEC = 117
MIPS_INS_BNEGI = 118
MIPS_INS_BNEG = 119
MIPS_INS_BNEL = 120
MIPS_INS_BNEZ16 = 121
MIPS_INS_BNEZALC = 122
MIPS_INS_BNEZC = 123
MIPS_INS_BNVC = 124
MIPS_INS_BNZ = 125
MIPS_INS_BOVC = 126
MIPS_INS_BPOSGE32 = 127
MIPS_INS_BREAK = 128
MIPS_INS_BREAK16 = 129
MIPS_INS_BSELI = 130
MIPS_INS_BSEL = 131
MIPS_INS_BSETI = 132
MIPS_INS_BSET = 133
MIPS_INS_BZ = 134
MIPS_INS_BEQZ = 135
MIPS_INS_B = 136
MIPS_INS_BNEZ = 137
MIPS_INS_BTEQZ = 138
MIPS_INS_BTNEZ = 139
MIPS_INS_CACHE = 140
MIPS_INS_CEIL = 141
MIPS_INS_CEQI = 142
MIPS_INS_CEQ = 143
MIPS_INS_CFC1 = 144
MIPS_INS_CFCMSA = 145
MIPS_INS_CINS = 146
MIPS_INS_CINS32 = 147
MIPS_INS_CLASS = 148
MIPS_INS_CLEI_S = 149
MIPS_INS_CLEI_U = 150
MIPS_INS_CLE_S = 151
MIPS_INS_CLE_U = 152
MIPS_INS_CLO = 153
MIPS_INS_CLTI_S = 154
MIPS_INS_CLTI_U = 155
MIPS_INS_CLT_S = 156
MIPS_INS_CLT_U = 157
MIPS_INS_CLZ = 158
MIPS_INS_CMPGDU = 159
MIPS_INS_CMPGU = 160
MIPS_INS_CMPU = 161
MIPS_INS_CMP = 162
MIPS_INS_COPY_S = 163
MIPS_INS_COPY_U = 164
MIPS_INS_CTC1 = 165
MIPS_INS_CTCMSA = 166
MIPS_INS_CVT = 167
MIPS_INS_C = 168
MIPS_INS_CMPI = 169
MIPS_INS_DADD = 170
MIPS_INS_DADDI = 171
MIPS_INS_DADDIU = 172
MIPS_INS_DADDU = 173
MIPS_INS_DAHI = 174
MIPS_INS_DALIGN = 175
MIPS_INS_DATI = 176
MIPS_INS_DAUI = 177
MIPS_INS_DBITSWAP = 178
MIPS_INS_DCLO = 179
MIPS_INS_DCLZ = 180
MIPS_INS_DDIV = 181
MIPS_INS_DDIVU = 182
MIPS_INS_DERET = 183
MIPS_INS_DEXT = 184
MIPS_INS_DEXTM = 185
MIPS_INS_DEXTU = 186
MIPS_INS_DI = 187
MIPS_INS_DINS = 188
MIPS_INS_DINSM = 189
MIPS_INS_DINSU = 190
MIPS_INS_DIV = 191
MIPS_INS_DIVU = 192
MIPS_INS_DIV_S = 193
MIPS_INS_DIV_U = 194
MIPS_INS_DLSA = 195
MIPS_INS_DMFC0 = 196
MIPS_INS_DMFC1 = 197
MIPS_INS_DMFC2 = 198
MIPS_INS_DMOD = 199
MIPS_INS_DMODU = 200
MIPS_INS_DMTC0 = 201
MIPS_INS_DMTC1 = 202
MIPS_INS_DMTC2 = 203
MIPS_INS_DMUH = 204
MIPS_INS_DMUHU = 205
MIPS_INS_DMUL = 206
MIPS_INS_DMULT = 207
MIPS_INS_DMULTU = 208
MIPS_INS_DMULU = 209
MIPS_INS_DOTP_S = 210
MIPS_INS_DOTP_U = 211
MIPS_INS_DPADD_S = 212
MIPS_INS_DPADD_U = 213
MIPS_INS_DPAQX_SA = 214
MIPS_INS_DPAQX_S = 215
MIPS_INS_DPAQ_SA = 216
MIPS_INS_DPAQ_S = 217
MIPS_INS_DPAU = 218
MIPS_INS_DPAX = 219
MIPS_INS_DPA = 220
MIPS_INS_DPOP = 221
MIPS_INS_DPSQX_SA = 222
MIPS_INS_DPSQX_S = 223
MIPS_INS_DPSQ_SA = 224
MIPS_INS_DPSQ_S = 225
MIPS_INS_DPSUB_S = 226
MIPS_INS_DPSUB_U = 227
MIPS_INS_DPSU = 228
MIPS_INS_DPSX = 229
MIPS_INS_DPS = 230
MIPS_INS_DROTR = 231
MIPS_INS_DROTR32 = 232
MIPS_INS_DROTRV = 233
MIPS_INS_DSBH = 234
MIPS_INS_DSHD = 235
MIPS_INS_DSLL = 236
MIPS_INS_DSLL32 = 237
MIPS_INS_DSLLV = 238
MIPS_INS_DSRA = 239
MIPS_INS_DSRA32 = 240
MIPS_INS_DSRAV = 241
MIPS_INS_DSRL = 242
MIPS_INS_DSRL32 = 243
MIPS_INS_DSRLV = 244
MIPS_INS_DSUB = 245
MIPS_INS_DSUBU = 246
MIPS_INS_EHB = 247
MIPS_INS_EI = 248
MIPS_INS_ERET = 249
MIPS_INS_EXT = 250
MIPS_INS_EXTP = 251
MIPS_INS_EXTPDP = 252
MIPS_INS_EXTPDPV = 253
MIPS_INS_EXTPV = 254
MIPS_INS_EXTRV_RS = 255
MIPS_INS_EXTRV_R = 256
MIPS_INS_EXTRV_S = 257
MIPS_INS_EXTRV = 258
MIPS_INS_EXTR_RS = 259
MIPS_INS_EXTR_R = 260
MIPS_INS_EXTR_S = 261
MIPS_INS_EXTR = 262
MIPS_INS_EXTS = 263
MIPS_INS_EXTS32 = 264
MIPS_INS_ABS = 265
MIPS_INS_FADD = 266
MIPS_INS_FCAF = 267
MIPS_INS_FCEQ = 268
MIPS_INS_FCLASS = 269
MIPS_INS_FCLE = 270
MIPS_INS_FCLT = 271
MIPS_INS_FCNE = 272
MIPS_INS_FCOR = 273
MIPS_INS_FCUEQ = 274
MIPS_INS_FCULE = 275
MIPS_INS_FCULT = 276
MIPS_INS_FCUNE = 277
MIPS_INS_FCUN = 278
MIPS_INS_FDIV = 279
MIPS_INS_FEXDO = 280
MIPS_INS_FEXP2 = 281
MIPS_INS_FEXUPL = 282
MIPS_INS_FEXUPR = 283
MIPS_INS_FFINT_S = 284
MIPS_INS_FFINT_U = 285
MIPS_INS_FFQL = 286
MIPS_INS_FFQR = 287
MIPS_INS_FILL = 288
MIPS_INS_FLOG2 = 289
MIPS_INS_FLOOR = 290
MIPS_INS_FMADD = 291
MIPS_INS_FMAX_A = 292
MIPS_INS_FMAX = 293
MIPS_INS_FMIN_A = 294
MIPS_INS_FMIN = 295
MIPS_INS_MOV = 296
MIPS_INS_FMSUB = 297
MIPS_INS_FMUL = 298
MIPS_INS_MUL = 299
MIPS_INS_NEG = 300
MIPS_INS_FRCP = 301
MIPS_INS_FRINT = 302
MIPS_INS_FRSQRT = 303
MIPS_INS_FSAF = 304
MIPS_INS_FSEQ = 305
MIPS_INS_FSLE = 306
MIPS_INS_FSLT = 307
MIPS_INS_FSNE = 308
MIPS_INS_FSOR = 309
MIPS_INS_FSQRT = 310
MIPS_INS_SQRT = 311
MIPS_INS_FSUB = 312
MIPS_INS_SUB = 313
MIPS_INS_FSUEQ = 314
MIPS_INS_FSULE = 315
MIPS_INS_FSULT = 316
MIPS_INS_FSUNE = 317
MIPS_INS_FSUN = 318
MIPS_INS_FTINT_S = 319
MIPS_INS_FTINT_U = 320
MIPS_INS_FTQ = 321
MIPS_INS_FTRUNC_S = 322
MIPS_INS_FTRUNC_U = 323
MIPS_INS_HADD_S = 324
MIPS_INS_HADD_U = 325
MIPS_INS_HSUB_S = 326
MIPS_INS_HSUB_U = 327
MIPS_INS_ILVEV = 328
MIPS_INS_ILVL = 329
MIPS_INS_ILVOD = 330
MIPS_INS_ILVR = 331
MIPS_INS_INS = 332
MIPS_INS_INSERT = 333
MIPS_INS_INSV = 334
MIPS_INS_INSVE = 335
MIPS_INS_J = 336
MIPS_INS_JAL = 337
MIPS_INS_JALR = 338
MIPS_INS_JALRS16 = 339
MIPS_INS_JALRS = 340
MIPS_INS_JALS = 341
MIPS_INS_JALX = 342
MIPS_INS_JIALC = 343
MIPS_INS_JIC = 344
MIPS_INS_JR = 345
MIPS_INS_JR16 = 346
MIPS_INS_JRADDIUSP = 347
MIPS_INS_JRC = 348
MIPS_INS_JALRC = 349
MIPS_INS_LB = 350
MIPS_INS_LBU16 = 351
MIPS_INS_LBUX = 352
MIPS_INS_LBU = 353
MIPS_INS_LD = 354
MIPS_INS_LDC1 = 355
MIPS_INS_LDC2 = 356
MIPS_INS_LDC3 = 357
MIPS_INS_LDI = 358
MIPS_INS_LDL = 359
MIPS_INS_LDPC = 360
MIPS_INS_LDR = 361
MIPS_INS_LDXC1 = 362
MIPS_INS_LH = 363
MIPS_INS_LHU16 = 364
MIPS_INS_LHX = 365
MIPS_INS_LHU = 366
MIPS_INS_LI16 = 367
MIPS_INS_LL = 368
MIPS_INS_LLD = 369
MIPS_INS_LSA = 370
MIPS_INS_LUXC1 = 371
MIPS_INS_LUI = 372
MIPS_INS_LW = 373
MIPS_INS_LW16 = 374
MIPS_INS_LWC1 = 375
MIPS_INS_LWC2 = 376
MIPS_INS_LWC3 = 377
MIPS_INS_LWL = 378
MIPS_INS_LWM16 = 379
MIPS_INS_LWM32 = 380
MIPS_INS_LWPC = 381
MIPS_INS_LWP = 382
MIPS_INS_LWR = 383
MIPS_INS_LWUPC = 384
MIPS_INS_LWU = 385
MIPS_INS_LWX = 386
MIPS_INS_LWXC1 = 387
MIPS_INS_LWXS = 388
MIPS_INS_LI = 389
MIPS_INS_MADD = 390
MIPS_INS_MADDF = 391
MIPS_INS_MADDR_Q = 392
MIPS_INS_MADDU = 393
MIPS_INS_MADDV = 394
MIPS_INS_MADD_Q = 395
MIPS_INS_MAQ_SA = 396
MIPS_INS_MAQ_S = 397
MIPS_INS_MAXA = 398
MIPS_INS_MAXI_S = 399
MIPS_INS_MAXI_U = 400
MIPS_INS_MAX_A = 401
MIPS_INS_MAX = 402
MIPS_INS_MAX_S = 403
MIPS_INS_MAX_U = 404
MIPS_INS_MFC0 = 405
MIPS_INS_MFC1 = 406
MIPS_INS_MFC2 = 407
MIPS_INS_MFHC1 = 408
MIPS_INS_MFHI = 409
MIPS_INS_MFLO = 410
MIPS_INS_MINA = 411
MIPS_INS_MINI_S = 412
MIPS_INS_MINI_U = 413
MIPS_INS_MIN_A = 414
MIPS_INS_MIN = 415
MIPS_INS_MIN_S = 416
MIPS_INS_MIN_U = 417
MIPS_INS_MOD = 418
MIPS_INS_MODSUB = 419
MIPS_INS_MODU = 420
MIPS_INS_MOD_S = 421
MIPS_INS_MOD_U = 422
MIPS_INS_MOVE = 423
MIPS_INS_MOVEP = 424
MIPS_INS_MOVF = 425
MIPS_INS_MOVN = 426
MIPS_INS_MOVT = 427
MIPS_INS_MOVZ = 428
MIPS_INS_MSUB = 429
MIPS_INS_MSUBF = 430
MIPS_INS_MSUBR_Q = 431
MIPS_INS_MSUBU = 432
MIPS_INS_MSUBV = 433
MIPS_INS_MSUB_Q = 434
MIPS_INS_MTC0 = 435
MIPS_INS_MTC1 = 436
MIPS_INS_MTC2 = 437
MIPS_INS_MTHC1 = 438
MIPS_INS_MTHI = 439
MIPS_INS_MTHLIP = 440
MIPS_INS_MTLO = 441
MIPS_INS_MTM0 = 442
MIPS_INS_MTM1 = 443
MIPS_INS_MTM2 = 444
MIPS_INS_MTP0 = 445
MIPS_INS_MTP1 = 446
MIPS_INS_MTP2 = 447
MIPS_INS_MUH = 448
MIPS_INS_MUHU = 449
MIPS_INS_MULEQ_S = 450
MIPS_INS_MULEU_S = 451
MIPS_INS_MULQ_RS = 452
MIPS_INS_MULQ_S = 453
MIPS_INS_MULR_Q = 454
MIPS_INS_MULSAQ_S = 455
MIPS_INS_MULSA = 456
MIPS_INS_MULT = 457
MIPS_INS_MULTU = 458
MIPS_INS_MULU = 459
MIPS_INS_MULV = 460
MIPS_INS_MUL_Q = 461
MIPS_INS_MUL_S = 462
MIPS_INS_NLOC = 463
MIPS_INS_NLZC = 464
MIPS_INS_NMADD = 465
MIPS_INS_NMSUB = 466
MIPS_INS_NOR = 467
MIPS_INS_NORI = 468
MIPS_INS_NOT16 = 469
MIPS_INS_NOT = 470
MIPS_INS_OR = 471
MIPS_INS_OR16 = 472
MIPS_INS_ORI = 473
MIPS_INS_PACKRL = 474
MIPS_INS_PAUSE = 475
MIPS_INS_PCKEV = 476
MIPS_INS_PCKOD = 477
MIPS_INS_PCNT = 478
MIPS_INS_PICK = 479
MIPS_INS_POP = 480
MIPS_INS_PRECEQU = 481
MIPS_INS_PRECEQ = 482
MIPS_INS_PRECEU = 483
MIPS_INS_PRECRQU_S = 484
MIPS_INS_PRECRQ = 485
MIPS_INS_PRECRQ_RS = 486
MIPS_INS_PRECR = 487
MIPS_INS_PRECR_SRA = 488
MIPS_INS_PRECR_SRA_R = 489
MIPS_INS_PREF = 490
MIPS_INS_PREPEND = 491
MIPS_INS_RADDU = 492
MIPS_INS_RDDSP = 493
MIPS_INS_RDHWR = 494
MIPS_INS_REPLV = 495
MIPS_INS_REPL = 496
MIPS_INS_RINT = 497
MIPS_INS_ROTR = 498
MIPS_INS_ROTRV = 499
MIPS_INS_ROUND = 500
MIPS_INS_SAT_S = 501
MIPS_INS_SAT_U = 502
MIPS_INS_SB = 503
MIPS_INS_SB16 = 504
MIPS_INS_SC = 505
MIPS_INS_SCD = 506
MIPS_INS_SD = 507
MIPS_INS_SDBBP = 508
MIPS_INS_SDBBP16 = 509
MIPS_INS_SDC1 = 510
MIPS_INS_SDC2 = 511
MIPS_INS_SDC3 = 512
MIPS_INS_SDL = 513
MIPS_INS_SDR = 514
MIPS_INS_SDXC1 = 515
MIPS_INS_SEB = 516
MIPS_INS_SEH = 517
MIPS_INS_SELEQZ = 518
MIPS_INS_SELNEZ = 519
MIPS_INS_SEL = 520
MIPS_INS_SEQ = 521
MIPS_INS_SEQI = 522
MIPS_INS_SH = 523
MIPS_INS_SH16 = 524
MIPS_INS_SHF = 525
MIPS_INS_SHILO = 526
MIPS_INS_SHILOV = 527
MIPS_INS_SHLLV = 528
MIPS_INS_SHLLV_S = 529
MIPS_INS_SHLL = 530
MIPS_INS_SHLL_S = 531
MIPS_INS_SHRAV = 532
MIPS_INS_SHRAV_R = 533
MIPS_INS_SHRA = 534
MIPS_INS_SHRA_R = 535
MIPS_INS_SHRLV = 536
MIPS_INS_SHRL = 537
MIPS_INS_SLDI = 538
MIPS_INS_SLD = 539
MIPS_INS_SLL = 540
MIPS_INS_SLL16 = 541
MIPS_INS_SLLI = 542
MIPS_INS_SLLV = 543
MIPS_INS_SLT = 544
MIPS_INS_SLTI = 545
MIPS_INS_SLTIU = 546
MIPS_INS_SLTU = 547
MIPS_INS_SNE = 548
MIPS_INS_SNEI = 549
MIPS_INS_SPLATI = 550
MIPS_INS_SPLAT = 551
MIPS_INS_SRA = 552
MIPS_INS_SRAI = 553
MIPS_INS_SRARI = 554
MIPS_INS_SRAR = 555
MIPS_INS_SRAV = 556
MIPS_INS_SRL = 557
MIPS_INS_SRL16 = 558
MIPS_INS_SRLI = 559
MIPS_INS_SRLRI = 560
MIPS_INS_SRLR = 561
MIPS_INS_SRLV = 562
MIPS_INS_SSNOP = 563
MIPS_INS_ST = 564
MIPS_INS_SUBQH = 565
MIPS_INS_SUBQH_R = 566
MIPS_INS_SUBQ = 567
MIPS_INS_SUBQ_S = 568
MIPS_INS_SUBSUS_U = 569
MIPS_INS_SUBSUU_S = 570
MIPS_INS_SUBS_S = 571
MIPS_INS_SUBS_U = 572
MIPS_INS_SUBU16 = 573
MIPS_INS_SUBUH = 574
MIPS_INS_SUBUH_R = 575
MIPS_INS_SUBU = 576
MIPS_INS_SUBU_S = 577
MIPS_INS_SUBVI = 578
MIPS_INS_SUBV = 579
MIPS_INS_SUXC1 = 580
MIPS_INS_SW = 581
MIPS_INS_SW16 = 582
MIPS_INS_SWC1 = 583
MIPS_INS_SWC2 = 584
MIPS_INS_SWC3 = 585
MIPS_INS_SWL = 586
MIPS_INS_SWM16 = 587
MIPS_INS_SWM32 = 588
MIPS_INS_SWP = 589
MIPS_INS_SWR = 590
MIPS_INS_SWXC1 = 591
MIPS_INS_SYNC = 592
MIPS_INS_SYNCI = 593
MIPS_INS_SYSCALL = 594
MIPS_INS_TEQ = 595
MIPS_INS_TEQI = 596
MIPS_INS_TGE = 597
MIPS_INS_TGEI = 598
MIPS_INS_TGEIU = 599
MIPS_INS_TGEU = 600
MIPS_INS_TLBP = 601
MIPS_INS_TLBR = 602
MIPS_INS_TLBWI = 603
MIPS_INS_TLBWR = 604
MIPS_INS_TLT = 605
MIPS_INS_TLTI = 606
MIPS_INS_TLTIU = 607
MIPS_INS_TLTU = 608
MIPS_INS_TNE = 609
MIPS_INS_TNEI = 610
MIPS_INS_TRUNC = 611
MIPS_INS_V3MULU = 612
MIPS_INS_VMM0 = 613
MIPS_INS_VMULU = 614
MIPS_INS_VSHF = 615
MIPS_INS_WAIT = 616
MIPS_INS_WRDSP = 617
MIPS_INS_WSBH = 618
MIPS_INS_XOR = 619
MIPS_INS_XOR16 = 620
MIPS_INS_XORI = 621
# some alias instructions
MIPS_INS_NOP = 622
MIPS_INS_NEGU = 623
# special instructions
MIPS_INS_JALR_HB = 624
MIPS_INS_JR_HB = 625
MIPS_INS_ENDING = 626
MIPS_GRP_INVALID = 0
MIPS_GRP_JUMP = 1
MIPS_GRP_CALL = 2
MIPS_GRP_RET = 3
MIPS_GRP_INT = 4
MIPS_GRP_IRET = 5
MIPS_GRP_PRIVILEGE = 6
MIPS_GRP_BRANCH_RELATIVE = 7
MIPS_GRP_BITCOUNT = 128
MIPS_GRP_DSP = 129
MIPS_GRP_DSPR2 = 130
MIPS_GRP_FPIDX = 131
MIPS_GRP_MSA = 132
MIPS_GRP_MIPS32R2 = 133
MIPS_GRP_MIPS64 = 134
MIPS_GRP_MIPS64R2 = 135
MIPS_GRP_SEINREG = 136
MIPS_GRP_STDENC = 137
MIPS_GRP_SWAP = 138
MIPS_GRP_MICROMIPS = 139
MIPS_GRP_MIPS16MODE = 140
MIPS_GRP_FP64BIT = 141
MIPS_GRP_NONANSFPMATH = 142
MIPS_GRP_NOTFP64BIT = 143
MIPS_GRP_NOTINMICROMIPS = 144
MIPS_GRP_NOTNACL = 145
MIPS_GRP_NOTMIPS32R6 = 146
MIPS_GRP_NOTMIPS64R6 = 147
MIPS_GRP_CNMIPS = 148
MIPS_GRP_MIPS32 = 149
MIPS_GRP_MIPS32R6 = 150
MIPS_GRP_MIPS64R6 = 151
MIPS_GRP_MIPS2 = 152
MIPS_GRP_MIPS3 = 153
MIPS_GRP_MIPS3_32 = 154
MIPS_GRP_MIPS3_32R2 = 155
MIPS_GRP_MIPS4_32 = 156
MIPS_GRP_MIPS4_32R2 = 157
MIPS_GRP_MIPS5_32R2 = 158
MIPS_GRP_GP32BIT = 159
MIPS_GRP_GP64BIT = 160
MIPS_GRP_ENDING = 161

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thirdparty/capstone/bindings/python/capstone/mos65xx.py vendored Normal file
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# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
import ctypes
from . import copy_ctypes_list
from .mos65xx_const import *
# define the API
class MOS65xxOpValue(ctypes.Union):
_fields_ = (
('reg', ctypes.c_uint),
('imm', ctypes.c_uint16),
('mem', ctypes.c_uint32),
)
class MOS65xxOp(ctypes.Structure):
_fields_ = (
('type', ctypes.c_uint),
('value', MOS65xxOpValue),
)
@property
def imm(self):
return self.value.imm
@property
def reg(self):
return self.value.reg
@property
def mem(self):
return self.value.mem
class CsMOS65xx(ctypes.Structure):
_fields_ = (
('am', ctypes.c_uint),
('modifies_flags', ctypes.c_uint8),
('op_count', ctypes.c_uint8),
('operands', MOS65xxOp * 3),
)
def get_arch_info(a):
return (a.am, a.modifies_flags, copy_ctypes_list(a.operands[:a.op_count]))

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thirdparty/capstone/bindings/python/capstone/mos65xx_const.py vendored Normal file
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from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [mos65xx_const.py]
MOS65XX_REG_INVALID = 0
MOS65XX_REG_ACC = 1
MOS65XX_REG_X = 2
MOS65XX_REG_Y = 3
MOS65XX_REG_P = 4
MOS65XX_REG_SP = 5
MOS65XX_REG_DP = 6
MOS65XX_REG_B = 7
MOS65XX_REG_K = 8
MOS65XX_REG_ENDING = 9
MOS65XX_AM_NONE = 0
MOS65XX_AM_IMP = 1
MOS65XX_AM_ACC = 2
MOS65XX_AM_IMM = 3
MOS65XX_AM_REL = 4
MOS65XX_AM_INT = 5
MOS65XX_AM_BLOCK = 6
MOS65XX_AM_ZP = 7
MOS65XX_AM_ZP_X = 8
MOS65XX_AM_ZP_Y = 9
MOS65XX_AM_ZP_REL = 10
MOS65XX_AM_ZP_IND = 11
MOS65XX_AM_ZP_X_IND = 12
MOS65XX_AM_ZP_IND_Y = 13
MOS65XX_AM_ZP_IND_LONG = 14
MOS65XX_AM_ZP_IND_LONG_Y = 15
MOS65XX_AM_ABS = 16
MOS65XX_AM_ABS_X = 17
MOS65XX_AM_ABS_Y = 18
MOS65XX_AM_ABS_IND = 19
MOS65XX_AM_ABS_X_IND = 20
MOS65XX_AM_ABS_IND_LONG = 21
MOS65XX_AM_ABS_LONG = 22
MOS65XX_AM_ABS_LONG_X = 23
MOS65XX_AM_SR = 24
MOS65XX_AM_SR_IND_Y = 25
MOS65XX_INS_INVALID = 0
MOS65XX_INS_ADC = 1
MOS65XX_INS_AND = 2
MOS65XX_INS_ASL = 3
MOS65XX_INS_BBR = 4
MOS65XX_INS_BBS = 5
MOS65XX_INS_BCC = 6
MOS65XX_INS_BCS = 7
MOS65XX_INS_BEQ = 8
MOS65XX_INS_BIT = 9
MOS65XX_INS_BMI = 10
MOS65XX_INS_BNE = 11
MOS65XX_INS_BPL = 12
MOS65XX_INS_BRA = 13
MOS65XX_INS_BRK = 14
MOS65XX_INS_BRL = 15
MOS65XX_INS_BVC = 16
MOS65XX_INS_BVS = 17
MOS65XX_INS_CLC = 18
MOS65XX_INS_CLD = 19
MOS65XX_INS_CLI = 20
MOS65XX_INS_CLV = 21
MOS65XX_INS_CMP = 22
MOS65XX_INS_COP = 23
MOS65XX_INS_CPX = 24
MOS65XX_INS_CPY = 25
MOS65XX_INS_DEC = 26
MOS65XX_INS_DEX = 27
MOS65XX_INS_DEY = 28
MOS65XX_INS_EOR = 29
MOS65XX_INS_INC = 30
MOS65XX_INS_INX = 31
MOS65XX_INS_INY = 32
MOS65XX_INS_JML = 33
MOS65XX_INS_JMP = 34
MOS65XX_INS_JSL = 35
MOS65XX_INS_JSR = 36
MOS65XX_INS_LDA = 37
MOS65XX_INS_LDX = 38
MOS65XX_INS_LDY = 39
MOS65XX_INS_LSR = 40
MOS65XX_INS_MVN = 41
MOS65XX_INS_MVP = 42
MOS65XX_INS_NOP = 43
MOS65XX_INS_ORA = 44
MOS65XX_INS_PEA = 45
MOS65XX_INS_PEI = 46
MOS65XX_INS_PER = 47
MOS65XX_INS_PHA = 48
MOS65XX_INS_PHB = 49
MOS65XX_INS_PHD = 50
MOS65XX_INS_PHK = 51
MOS65XX_INS_PHP = 52
MOS65XX_INS_PHX = 53
MOS65XX_INS_PHY = 54
MOS65XX_INS_PLA = 55
MOS65XX_INS_PLB = 56
MOS65XX_INS_PLD = 57
MOS65XX_INS_PLP = 58
MOS65XX_INS_PLX = 59
MOS65XX_INS_PLY = 60
MOS65XX_INS_REP = 61
MOS65XX_INS_RMB = 62
MOS65XX_INS_ROL = 63
MOS65XX_INS_ROR = 64
MOS65XX_INS_RTI = 65
MOS65XX_INS_RTL = 66
MOS65XX_INS_RTS = 67
MOS65XX_INS_SBC = 68
MOS65XX_INS_SEC = 69
MOS65XX_INS_SED = 70
MOS65XX_INS_SEI = 71
MOS65XX_INS_SEP = 72
MOS65XX_INS_SMB = 73
MOS65XX_INS_STA = 74
MOS65XX_INS_STP = 75
MOS65XX_INS_STX = 76
MOS65XX_INS_STY = 77
MOS65XX_INS_STZ = 78
MOS65XX_INS_TAX = 79
MOS65XX_INS_TAY = 80
MOS65XX_INS_TCD = 81
MOS65XX_INS_TCS = 82
MOS65XX_INS_TDC = 83
MOS65XX_INS_TRB = 84
MOS65XX_INS_TSB = 85
MOS65XX_INS_TSC = 86
MOS65XX_INS_TSX = 87
MOS65XX_INS_TXA = 88
MOS65XX_INS_TXS = 89
MOS65XX_INS_TXY = 90
MOS65XX_INS_TYA = 91
MOS65XX_INS_TYX = 92
MOS65XX_INS_WAI = 93
MOS65XX_INS_WDM = 94
MOS65XX_INS_XBA = 95
MOS65XX_INS_XCE = 96
MOS65XX_INS_ENDING = 97
MOS65XX_GRP_INVALID = 0
MOS65XX_GRP_JUMP = 1
MOS65XX_GRP_CALL = 2
MOS65XX_GRP_RET = 3
MOS65XX_GRP_INT = 4
MOS65XX_GRP_IRET = 5
MOS65XX_GRP_BRANCH_RELATIVE = 6
MOS65XX_GRP_ENDING = 7
MOS65XX_OP_INVALID = 0
MOS65XX_OP_REG = 1
MOS65XX_OP_IMM = 2
MOS65XX_OP_MEM = 3

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thirdparty/capstone/bindings/python/capstone/ppc.py vendored Normal file
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# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
import ctypes
from . import copy_ctypes_list
from .ppc_const import *
# define the API
class PpcOpMem(ctypes.Structure):
_fields_ = (
('base', ctypes.c_uint),
('disp', ctypes.c_int32),
('offset', ctypes.c_uint),
)
class PpcOpValue(ctypes.Union):
_fields_ = (
('reg', ctypes.c_uint),
('imm', ctypes.c_int64),
('mem', PpcOpMem),
)
class PpcOp(ctypes.Structure):
_fields_ = (
('type', ctypes.c_uint),
('value', PpcOpValue),
('access', ctypes.c_uint),
)
@property
def imm(self):
return self.value.imm
@property
def reg(self):
return self.value.reg
@property
def mem(self):
return self.value.mem
class PpcBC(ctypes.Structure):
_fields_ = (
('bo', ctypes.c_uint8),
('bi', ctypes.c_uint8),
('crX_bit', ctypes.c_uint),
('crX', ctypes.c_uint),
('hint', ctypes.c_uint),
('pred_cr', ctypes.c_uint),
('pred_ctr', ctypes.c_uint),
('bh', ctypes.c_uint),
)
class CsPpc(ctypes.Structure):
_fields_ = (
('bc', PpcBC),
('update_cr0', ctypes.c_bool),
('format', ctypes.c_uint32),
('op_count', ctypes.c_uint8),
('operands', PpcOp * 8),
)
def get_arch_info(a):
return (a.bc, a.update_cr0, a.format, copy_ctypes_list(a.operands[:a.op_count]))

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50
thirdparty/capstone/bindings/python/capstone/riscv.py vendored Normal file
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# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
import ctypes
from . import copy_ctypes_list
from .riscv_const import *
# define the API
class RISCVOpMem(ctypes.Structure):
_fields_ = (
('base', ctypes.c_uint),
('disp', ctypes.c_int64),
)
class RISCVOpValue(ctypes.Union):
_fields_ = (
('reg', ctypes.c_uint),
('imm', ctypes.c_int64),
('mem', RISCVOpMem),
)
class RISCVOp(ctypes.Structure):
_fields_ = (
('type', ctypes.c_uint),
('value', RISCVOpValue),
('access', ctypes.c_uint8),
)
@property
def imm(self):
return self.value.imm
@property
def reg(self):
return self.value.reg
@property
def mem(self):
return self.value.mem
class CsRISCV(ctypes.Structure):
_fields_ = (
('need_effective_addr', ctypes.c_bool),
('op_count', ctypes.c_uint8),
('operands', RISCVOp * 8),
)
def get_arch_info(a):
return (a.need_effective_addr, copy_ctypes_list(a.operands[:a.op_count]))

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thirdparty/capstone/bindings/python/capstone/riscv_const.py vendored Normal file
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from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [riscv_const.py]
# Operand type for instruction's operands
RISCV_OP_INVALID = 0
RISCV_OP_REG = 1
RISCV_OP_IMM = 2
RISCV_OP_MEM = 3
# RISCV registers
RISCV_REG_INVALID = 0
# General purpose registers
RISCV_REG_X0 = 1
RISCV_REG_ZERO = RISCV_REG_X0
RISCV_REG_X1 = 2
RISCV_REG_RA = RISCV_REG_X1
RISCV_REG_X2 = 3
RISCV_REG_SP = RISCV_REG_X2
RISCV_REG_X3 = 4
RISCV_REG_GP = RISCV_REG_X3
RISCV_REG_X4 = 5
RISCV_REG_TP = RISCV_REG_X4
RISCV_REG_X5 = 6
RISCV_REG_T0 = RISCV_REG_X5
RISCV_REG_X6 = 7
RISCV_REG_T1 = RISCV_REG_X6
RISCV_REG_X7 = 8
RISCV_REG_T2 = RISCV_REG_X7
RISCV_REG_X8 = 9
RISCV_REG_S0 = RISCV_REG_X8
RISCV_REG_FP = RISCV_REG_X8
RISCV_REG_X9 = 10
RISCV_REG_S1 = RISCV_REG_X9
RISCV_REG_X10 = 11
RISCV_REG_A0 = RISCV_REG_X10
RISCV_REG_X11 = 12
RISCV_REG_A1 = RISCV_REG_X11
RISCV_REG_X12 = 13
RISCV_REG_A2 = RISCV_REG_X12
RISCV_REG_X13 = 14
RISCV_REG_A3 = RISCV_REG_X13
RISCV_REG_X14 = 15
RISCV_REG_A4 = RISCV_REG_X14
RISCV_REG_X15 = 16
RISCV_REG_A5 = RISCV_REG_X15
RISCV_REG_X16 = 17
RISCV_REG_A6 = RISCV_REG_X16
RISCV_REG_X17 = 18
RISCV_REG_A7 = RISCV_REG_X17
RISCV_REG_X18 = 19
RISCV_REG_S2 = RISCV_REG_X18
RISCV_REG_X19 = 20
RISCV_REG_S3 = RISCV_REG_X19
RISCV_REG_X20 = 21
RISCV_REG_S4 = RISCV_REG_X20
RISCV_REG_X21 = 22
RISCV_REG_S5 = RISCV_REG_X21
RISCV_REG_X22 = 23
RISCV_REG_S6 = RISCV_REG_X22
RISCV_REG_X23 = 24
RISCV_REG_S7 = RISCV_REG_X23
RISCV_REG_X24 = 25
RISCV_REG_S8 = RISCV_REG_X24
RISCV_REG_X25 = 26
RISCV_REG_S9 = RISCV_REG_X25
RISCV_REG_X26 = 27
RISCV_REG_S10 = RISCV_REG_X26
RISCV_REG_X27 = 28
RISCV_REG_S11 = RISCV_REG_X27
RISCV_REG_X28 = 29
RISCV_REG_T3 = RISCV_REG_X28
RISCV_REG_X29 = 30
RISCV_REG_T4 = RISCV_REG_X29
RISCV_REG_X30 = 31
RISCV_REG_T5 = RISCV_REG_X30
RISCV_REG_X31 = 32
RISCV_REG_T6 = RISCV_REG_X31
# Floating-point registers
RISCV_REG_F0_32 = 33
RISCV_REG_F0_64 = 34
RISCV_REG_F1_32 = 35
RISCV_REG_F1_64 = 36
RISCV_REG_F2_32 = 37
RISCV_REG_F2_64 = 38
RISCV_REG_F3_32 = 39
RISCV_REG_F3_64 = 40
RISCV_REG_F4_32 = 41
RISCV_REG_F4_64 = 42
RISCV_REG_F5_32 = 43
RISCV_REG_F5_64 = 44
RISCV_REG_F6_32 = 45
RISCV_REG_F6_64 = 46
RISCV_REG_F7_32 = 47
RISCV_REG_F7_64 = 48
RISCV_REG_F8_32 = 49
RISCV_REG_F8_64 = 50
RISCV_REG_F9_32 = 51
RISCV_REG_F9_64 = 52
RISCV_REG_F10_32 = 53
RISCV_REG_F10_64 = 54
RISCV_REG_F11_32 = 55
RISCV_REG_F11_64 = 56
RISCV_REG_F12_32 = 57
RISCV_REG_F12_64 = 58
RISCV_REG_F13_32 = 59
RISCV_REG_F13_64 = 60
RISCV_REG_F14_32 = 61
RISCV_REG_F14_64 = 62
RISCV_REG_F15_32 = 63
RISCV_REG_F15_64 = 64
RISCV_REG_F16_32 = 65
RISCV_REG_F16_64 = 66
RISCV_REG_F17_32 = 67
RISCV_REG_F17_64 = 68
RISCV_REG_F18_32 = 69
RISCV_REG_F18_64 = 70
RISCV_REG_F19_32 = 71
RISCV_REG_F19_64 = 72
RISCV_REG_F20_32 = 73
RISCV_REG_F20_64 = 74
RISCV_REG_F21_32 = 75
RISCV_REG_F21_64 = 76
RISCV_REG_F22_32 = 77
RISCV_REG_F22_64 = 78
RISCV_REG_F23_32 = 79
RISCV_REG_F23_64 = 80
RISCV_REG_F24_32 = 81
RISCV_REG_F24_64 = 82
RISCV_REG_F25_32 = 83
RISCV_REG_F25_64 = 84
RISCV_REG_F26_32 = 85
RISCV_REG_F26_64 = 86
RISCV_REG_F27_32 = 87
RISCV_REG_F27_64 = 88
RISCV_REG_F28_32 = 89
RISCV_REG_F28_64 = 90
RISCV_REG_F29_32 = 91
RISCV_REG_F29_64 = 92
RISCV_REG_F30_32 = 93
RISCV_REG_F30_64 = 94
RISCV_REG_F31_32 = 95
RISCV_REG_F31_64 = 96
RISCV_REG_ENDING = 97
# RISCV instruction
RISCV_INS_INVALID = 0
RISCV_INS_ADD = 1
RISCV_INS_ADDI = 2
RISCV_INS_ADDIW = 3
RISCV_INS_ADDW = 4
RISCV_INS_AMOADD_D = 5
RISCV_INS_AMOADD_D_AQ = 6
RISCV_INS_AMOADD_D_AQ_RL = 7
RISCV_INS_AMOADD_D_RL = 8
RISCV_INS_AMOADD_W = 9
RISCV_INS_AMOADD_W_AQ = 10
RISCV_INS_AMOADD_W_AQ_RL = 11
RISCV_INS_AMOADD_W_RL = 12
RISCV_INS_AMOAND_D = 13
RISCV_INS_AMOAND_D_AQ = 14
RISCV_INS_AMOAND_D_AQ_RL = 15
RISCV_INS_AMOAND_D_RL = 16
RISCV_INS_AMOAND_W = 17
RISCV_INS_AMOAND_W_AQ = 18
RISCV_INS_AMOAND_W_AQ_RL = 19
RISCV_INS_AMOAND_W_RL = 20
RISCV_INS_AMOMAXU_D = 21
RISCV_INS_AMOMAXU_D_AQ = 22
RISCV_INS_AMOMAXU_D_AQ_RL = 23
RISCV_INS_AMOMAXU_D_RL = 24
RISCV_INS_AMOMAXU_W = 25
RISCV_INS_AMOMAXU_W_AQ = 26
RISCV_INS_AMOMAXU_W_AQ_RL = 27
RISCV_INS_AMOMAXU_W_RL = 28
RISCV_INS_AMOMAX_D = 29
RISCV_INS_AMOMAX_D_AQ = 30
RISCV_INS_AMOMAX_D_AQ_RL = 31
RISCV_INS_AMOMAX_D_RL = 32
RISCV_INS_AMOMAX_W = 33
RISCV_INS_AMOMAX_W_AQ = 34
RISCV_INS_AMOMAX_W_AQ_RL = 35
RISCV_INS_AMOMAX_W_RL = 36
RISCV_INS_AMOMINU_D = 37
RISCV_INS_AMOMINU_D_AQ = 38
RISCV_INS_AMOMINU_D_AQ_RL = 39
RISCV_INS_AMOMINU_D_RL = 40
RISCV_INS_AMOMINU_W = 41
RISCV_INS_AMOMINU_W_AQ = 42
RISCV_INS_AMOMINU_W_AQ_RL = 43
RISCV_INS_AMOMINU_W_RL = 44
RISCV_INS_AMOMIN_D = 45
RISCV_INS_AMOMIN_D_AQ = 46
RISCV_INS_AMOMIN_D_AQ_RL = 47
RISCV_INS_AMOMIN_D_RL = 48
RISCV_INS_AMOMIN_W = 49
RISCV_INS_AMOMIN_W_AQ = 50
RISCV_INS_AMOMIN_W_AQ_RL = 51
RISCV_INS_AMOMIN_W_RL = 52
RISCV_INS_AMOOR_D = 53
RISCV_INS_AMOOR_D_AQ = 54
RISCV_INS_AMOOR_D_AQ_RL = 55
RISCV_INS_AMOOR_D_RL = 56
RISCV_INS_AMOOR_W = 57
RISCV_INS_AMOOR_W_AQ = 58
RISCV_INS_AMOOR_W_AQ_RL = 59
RISCV_INS_AMOOR_W_RL = 60
RISCV_INS_AMOSWAP_D = 61
RISCV_INS_AMOSWAP_D_AQ = 62
RISCV_INS_AMOSWAP_D_AQ_RL = 63
RISCV_INS_AMOSWAP_D_RL = 64
RISCV_INS_AMOSWAP_W = 65
RISCV_INS_AMOSWAP_W_AQ = 66
RISCV_INS_AMOSWAP_W_AQ_RL = 67
RISCV_INS_AMOSWAP_W_RL = 68
RISCV_INS_AMOXOR_D = 69
RISCV_INS_AMOXOR_D_AQ = 70
RISCV_INS_AMOXOR_D_AQ_RL = 71
RISCV_INS_AMOXOR_D_RL = 72
RISCV_INS_AMOXOR_W = 73
RISCV_INS_AMOXOR_W_AQ = 74
RISCV_INS_AMOXOR_W_AQ_RL = 75
RISCV_INS_AMOXOR_W_RL = 76
RISCV_INS_AND = 77
RISCV_INS_ANDI = 78
RISCV_INS_AUIPC = 79
RISCV_INS_BEQ = 80
RISCV_INS_BGE = 81
RISCV_INS_BGEU = 82
RISCV_INS_BLT = 83
RISCV_INS_BLTU = 84
RISCV_INS_BNE = 85
RISCV_INS_CSRRC = 86
RISCV_INS_CSRRCI = 87
RISCV_INS_CSRRS = 88
RISCV_INS_CSRRSI = 89
RISCV_INS_CSRRW = 90
RISCV_INS_CSRRWI = 91
RISCV_INS_C_ADD = 92
RISCV_INS_C_ADDI = 93
RISCV_INS_C_ADDI16SP = 94
RISCV_INS_C_ADDI4SPN = 95
RISCV_INS_C_ADDIW = 96
RISCV_INS_C_ADDW = 97
RISCV_INS_C_AND = 98
RISCV_INS_C_ANDI = 99
RISCV_INS_C_BEQZ = 100
RISCV_INS_C_BNEZ = 101
RISCV_INS_C_EBREAK = 102
RISCV_INS_C_FLD = 103
RISCV_INS_C_FLDSP = 104
RISCV_INS_C_FLW = 105
RISCV_INS_C_FLWSP = 106
RISCV_INS_C_FSD = 107
RISCV_INS_C_FSDSP = 108
RISCV_INS_C_FSW = 109
RISCV_INS_C_FSWSP = 110
RISCV_INS_C_J = 111
RISCV_INS_C_JAL = 112
RISCV_INS_C_JALR = 113
RISCV_INS_C_JR = 114
RISCV_INS_C_LD = 115
RISCV_INS_C_LDSP = 116
RISCV_INS_C_LI = 117
RISCV_INS_C_LUI = 118
RISCV_INS_C_LW = 119
RISCV_INS_C_LWSP = 120
RISCV_INS_C_MV = 121
RISCV_INS_C_NOP = 122
RISCV_INS_C_OR = 123
RISCV_INS_C_SD = 124
RISCV_INS_C_SDSP = 125
RISCV_INS_C_SLLI = 126
RISCV_INS_C_SRAI = 127
RISCV_INS_C_SRLI = 128
RISCV_INS_C_SUB = 129
RISCV_INS_C_SUBW = 130
RISCV_INS_C_SW = 131
RISCV_INS_C_SWSP = 132
RISCV_INS_C_UNIMP = 133
RISCV_INS_C_XOR = 134
RISCV_INS_DIV = 135
RISCV_INS_DIVU = 136
RISCV_INS_DIVUW = 137
RISCV_INS_DIVW = 138
RISCV_INS_EBREAK = 139
RISCV_INS_ECALL = 140
RISCV_INS_FADD_D = 141
RISCV_INS_FADD_S = 142
RISCV_INS_FCLASS_D = 143
RISCV_INS_FCLASS_S = 144
RISCV_INS_FCVT_D_L = 145
RISCV_INS_FCVT_D_LU = 146
RISCV_INS_FCVT_D_S = 147
RISCV_INS_FCVT_D_W = 148
RISCV_INS_FCVT_D_WU = 149
RISCV_INS_FCVT_LU_D = 150
RISCV_INS_FCVT_LU_S = 151
RISCV_INS_FCVT_L_D = 152
RISCV_INS_FCVT_L_S = 153
RISCV_INS_FCVT_S_D = 154
RISCV_INS_FCVT_S_L = 155
RISCV_INS_FCVT_S_LU = 156
RISCV_INS_FCVT_S_W = 157
RISCV_INS_FCVT_S_WU = 158
RISCV_INS_FCVT_WU_D = 159
RISCV_INS_FCVT_WU_S = 160
RISCV_INS_FCVT_W_D = 161
RISCV_INS_FCVT_W_S = 162
RISCV_INS_FDIV_D = 163
RISCV_INS_FDIV_S = 164
RISCV_INS_FENCE = 165
RISCV_INS_FENCE_I = 166
RISCV_INS_FENCE_TSO = 167
RISCV_INS_FEQ_D = 168
RISCV_INS_FEQ_S = 169
RISCV_INS_FLD = 170
RISCV_INS_FLE_D = 171
RISCV_INS_FLE_S = 172
RISCV_INS_FLT_D = 173
RISCV_INS_FLT_S = 174
RISCV_INS_FLW = 175
RISCV_INS_FMADD_D = 176
RISCV_INS_FMADD_S = 177
RISCV_INS_FMAX_D = 178
RISCV_INS_FMAX_S = 179
RISCV_INS_FMIN_D = 180
RISCV_INS_FMIN_S = 181
RISCV_INS_FMSUB_D = 182
RISCV_INS_FMSUB_S = 183
RISCV_INS_FMUL_D = 184
RISCV_INS_FMUL_S = 185
RISCV_INS_FMV_D_X = 186
RISCV_INS_FMV_W_X = 187
RISCV_INS_FMV_X_D = 188
RISCV_INS_FMV_X_W = 189
RISCV_INS_FNMADD_D = 190
RISCV_INS_FNMADD_S = 191
RISCV_INS_FNMSUB_D = 192
RISCV_INS_FNMSUB_S = 193
RISCV_INS_FSD = 194
RISCV_INS_FSGNJN_D = 195
RISCV_INS_FSGNJN_S = 196
RISCV_INS_FSGNJX_D = 197
RISCV_INS_FSGNJX_S = 198
RISCV_INS_FSGNJ_D = 199
RISCV_INS_FSGNJ_S = 200
RISCV_INS_FSQRT_D = 201
RISCV_INS_FSQRT_S = 202
RISCV_INS_FSUB_D = 203
RISCV_INS_FSUB_S = 204
RISCV_INS_FSW = 205
RISCV_INS_JAL = 206
RISCV_INS_JALR = 207
RISCV_INS_LB = 208
RISCV_INS_LBU = 209
RISCV_INS_LD = 210
RISCV_INS_LH = 211
RISCV_INS_LHU = 212
RISCV_INS_LR_D = 213
RISCV_INS_LR_D_AQ = 214
RISCV_INS_LR_D_AQ_RL = 215
RISCV_INS_LR_D_RL = 216
RISCV_INS_LR_W = 217
RISCV_INS_LR_W_AQ = 218
RISCV_INS_LR_W_AQ_RL = 219
RISCV_INS_LR_W_RL = 220
RISCV_INS_LUI = 221
RISCV_INS_LW = 222
RISCV_INS_LWU = 223
RISCV_INS_MRET = 224
RISCV_INS_MUL = 225
RISCV_INS_MULH = 226
RISCV_INS_MULHSU = 227
RISCV_INS_MULHU = 228
RISCV_INS_MULW = 229
RISCV_INS_OR = 230
RISCV_INS_ORI = 231
RISCV_INS_REM = 232
RISCV_INS_REMU = 233
RISCV_INS_REMUW = 234
RISCV_INS_REMW = 235
RISCV_INS_SB = 236
RISCV_INS_SC_D = 237
RISCV_INS_SC_D_AQ = 238
RISCV_INS_SC_D_AQ_RL = 239
RISCV_INS_SC_D_RL = 240
RISCV_INS_SC_W = 241
RISCV_INS_SC_W_AQ = 242
RISCV_INS_SC_W_AQ_RL = 243
RISCV_INS_SC_W_RL = 244
RISCV_INS_SD = 245
RISCV_INS_SFENCE_VMA = 246
RISCV_INS_SH = 247
RISCV_INS_SLL = 248
RISCV_INS_SLLI = 249
RISCV_INS_SLLIW = 250
RISCV_INS_SLLW = 251
RISCV_INS_SLT = 252
RISCV_INS_SLTI = 253
RISCV_INS_SLTIU = 254
RISCV_INS_SLTU = 255
RISCV_INS_SRA = 256
RISCV_INS_SRAI = 257
RISCV_INS_SRAIW = 258
RISCV_INS_SRAW = 259
RISCV_INS_SRET = 260
RISCV_INS_SRL = 261
RISCV_INS_SRLI = 262
RISCV_INS_SRLIW = 263
RISCV_INS_SRLW = 264
RISCV_INS_SUB = 265
RISCV_INS_SUBW = 266
RISCV_INS_SW = 267
RISCV_INS_UNIMP = 268
RISCV_INS_URET = 269
RISCV_INS_WFI = 270
RISCV_INS_XOR = 271
RISCV_INS_XORI = 272
RISCV_INS_ENDING = 273
# Group of RISCV instructions
RISCV_GRP_INVALID = 0
RISCV_GRP_JUMP = 1
RISCV_GRP_CALL = 2
RISCV_GRP_RET = 3
RISCV_GRP_INT = 4
RISCV_GRP_IRET = 5
RISCV_GRP_PRIVILEGE = 6
RISCV_GRP_BRANCH_RELATIVE = 7
RISCV_GRP_ISRV32 = 128
RISCV_GRP_ISRV64 = 129
RISCV_GRP_HASSTDEXTA = 130
RISCV_GRP_HASSTDEXTC = 131
RISCV_GRP_HASSTDEXTD = 132
RISCV_GRP_HASSTDEXTF = 133
RISCV_GRP_HASSTDEXTM = 134
RISCV_GRP_ISRVA = 135
RISCV_GRP_ISRVC = 136
RISCV_GRP_ISRVD = 137
RISCV_GRP_ISRVCD = 138
RISCV_GRP_ISRVF = 139
RISCV_GRP_ISRV32C = 140
RISCV_GRP_ISRV32CF = 141
RISCV_GRP_ISRVM = 142
RISCV_GRP_ISRV64A = 143
RISCV_GRP_ISRV64C = 144
RISCV_GRP_ISRV64D = 145
RISCV_GRP_ISRV64F = 146
RISCV_GRP_ISRV64M = 147
RISCV_GRP_ENDING = 148

66
thirdparty/capstone/bindings/python/capstone/sh.py vendored Normal file
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# Capstone Python bindings, by Peace-Maker <peacemakerctf@gmail.com>
import ctypes
from . import copy_ctypes_list
from .sh_const import *
# define the API
class SHOpMem(ctypes.Structure):
_fields_ = (
('address', ctypes.c_uint),
('reg', ctypes.c_uint),
('disp', ctypes.c_uint32),
)
class SHOpDsp(ctypes.Structure):
_fields_ = (
('insn', ctypes.c_uint),
('operand', ctypes.c_uint * 2),
('r', ctypes.c_uint * 6),
('cc', ctypes.c_uint),
('imm', ctypes.c_uint8),
('size', ctypes.c_int),
)
class SHOpValue(ctypes.Union):
_fields_ = (
('imm', ctypes.c_int64),
('reg', ctypes.c_uint),
('mem', SHOpMem),
('dsp', SHOpDsp),
)
class SHOp(ctypes.Structure):
_fields_ = (
('type', ctypes.c_uint),
('value', SHOpValue),
)
@property
def imm(self):
return self.value.imm
@property
def reg(self):
return self.value.reg
@property
def mem(self):
return self.value.mem
@property
def dsp(self):
return self.value.dsp
class CsSH(ctypes.Structure):
_fields_ = (
('insn', ctypes.c_uint),
('size', ctypes.c_uint8),
('op_count', ctypes.c_uint8),
('operands', SHOp * 3),
)
def get_arch_info(a):
return (a.insn, a.size, copy_ctypes_list(a.operands[:a.op_count]))

371
thirdparty/capstone/bindings/python/capstone/sh_const.py vendored Normal file
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from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [sh_const.py]
SH_REG_INVALID = 0
SH_REG_R0 = 1
SH_REG_R1 = 2
SH_REG_R2 = 3
SH_REG_R3 = 4
SH_REG_R4 = 5
SH_REG_R5 = 6
SH_REG_R6 = 7
SH_REG_R7 = 8
SH_REG_R8 = 9
SH_REG_R9 = 10
SH_REG_R10 = 11
SH_REG_R11 = 12
SH_REG_R12 = 13
SH_REG_R13 = 14
SH_REG_R14 = 15
SH_REG_R15 = 16
SH_REG_R0_BANK = 17
SH_REG_R1_BANK = 18
SH_REG_R2_BANK = 19
SH_REG_R3_BANK = 20
SH_REG_R4_BANK = 21
SH_REG_R5_BANK = 22
SH_REG_R6_BANK = 23
SH_REG_R7_BANK = 24
SH_REG_FR0 = 25
SH_REG_FR1 = 26
SH_REG_FR2 = 27
SH_REG_FR3 = 28
SH_REG_FR4 = 29
SH_REG_FR5 = 30
SH_REG_FR6 = 31
SH_REG_FR7 = 32
SH_REG_FR8 = 33
SH_REG_FR9 = 34
SH_REG_FR10 = 35
SH_REG_FR11 = 36
SH_REG_FR12 = 37
SH_REG_FR13 = 38
SH_REG_FR14 = 39
SH_REG_FR15 = 40
SH_REG_DR0 = 41
SH_REG_DR2 = 42
SH_REG_DR4 = 43
SH_REG_DR6 = 44
SH_REG_DR8 = 45
SH_REG_DR10 = 46
SH_REG_DR12 = 47
SH_REG_DR14 = 48
SH_REG_XD0 = 49
SH_REG_XD2 = 50
SH_REG_XD4 = 51
SH_REG_XD6 = 52
SH_REG_XD8 = 53
SH_REG_XD10 = 54
SH_REG_XD12 = 55
SH_REG_XD14 = 56
SH_REG_XF0 = 57
SH_REG_XF1 = 58
SH_REG_XF2 = 59
SH_REG_XF3 = 60
SH_REG_XF4 = 61
SH_REG_XF5 = 62
SH_REG_XF6 = 63
SH_REG_XF7 = 64
SH_REG_XF8 = 65
SH_REG_XF9 = 66
SH_REG_XF10 = 67
SH_REG_XF11 = 68
SH_REG_XF12 = 69
SH_REG_XF13 = 70
SH_REG_XF14 = 71
SH_REG_XF15 = 72
SH_REG_FV0 = 73
SH_REG_FV4 = 74
SH_REG_FV8 = 75
SH_REG_FV12 = 76
SH_REG_XMATRX = 77
SH_REG_PC = 78
SH_REG_PR = 79
SH_REG_MACH = 80
SH_REG_MACL = 81
SH_REG_SR = 82
SH_REG_GBR = 83
SH_REG_SSR = 84
SH_REG_SPC = 85
SH_REG_SGR = 86
SH_REG_DBR = 87
SH_REG_VBR = 88
SH_REG_TBR = 89
SH_REG_RS = 90
SH_REG_RE = 91
SH_REG_MOD = 92
SH_REG_FPUL = 93
SH_REG_FPSCR = 94
SH_REG_DSP_X0 = 95
SH_REG_DSP_X1 = 96
SH_REG_DSP_Y0 = 97
SH_REG_DSP_Y1 = 98
SH_REG_DSP_A0 = 99
SH_REG_DSP_A1 = 100
SH_REG_DSP_A0G = 101
SH_REG_DSP_A1G = 102
SH_REG_DSP_M0 = 103
SH_REG_DSP_M1 = 104
SH_REG_DSP_DSR = 105
SH_REG_DSP_RSV0 = 106
SH_REG_DSP_RSV1 = 107
SH_REG_DSP_RSV2 = 108
SH_REG_DSP_RSV3 = 109
SH_REG_DSP_RSV4 = 110
SH_REG_DSP_RSV5 = 111
SH_REG_DSP_RSV6 = 112
SH_REG_DSP_RSV7 = 113
SH_REG_DSP_RSV8 = 114
SH_REG_DSP_RSV9 = 115
SH_REG_DSP_RSVA = 116
SH_REG_DSP_RSVB = 117
SH_REG_DSP_RSVC = 118
SH_REG_DSP_RSVD = 119
SH_REG_DSP_RSVE = 120
SH_REG_DSP_RSVF = 121
SH_REG_ENDING = 122
SH_OP_INVALID = 0
SH_OP_REG = 1
SH_OP_IMM = 2
SH_OP_MEM = 3
SH_OP_MEM_INVALID = 0
SH_OP_MEM_REG_IND = 1
SH_OP_MEM_REG_POST = 2
SH_OP_MEM_REG_PRE = 3
SH_OP_MEM_REG_DISP = 4
SH_OP_MEM_REG_R0 = 5
SH_OP_MEM_GBR_DISP = 6
SH_OP_MEM_GBR_R0 = 7
SH_OP_MEM_PCR = 8
SH_OP_MEM_TBR_DISP = 9
SH_INS_DSP_INVALID = 0
SH_INS_DSP_DOUBLE = 1
SH_INS_DSP_SINGLE = 2
SH_INS_DSP_PARALLEL = 3
SH_INS_DSP_NOP = 1
SH_INS_DSP_MOV = 2
SH_INS_DSP_PSHL = 3
SH_INS_DSP_PSHA = 4
SH_INS_DSP_PMULS = 5
SH_INS_DSP_PCLR_PMULS = 6
SH_INS_DSP_PSUB_PMULS = 7
SH_INS_DSP_PADD_PMULS = 8
SH_INS_DSP_PSUBC = 9
SH_INS_DSP_PADDC = 10
SH_INS_DSP_PCMP = 11
SH_INS_DSP_PABS = 12
SH_INS_DSP_PRND = 13
SH_INS_DSP_PSUB = 14
SH_INS_DSP_PSUBr = 15
SH_INS_DSP_PADD = 16
SH_INS_DSP_PAND = 17
SH_INS_DSP_PXOR = 18
SH_INS_DSP_POR = 19
SH_INS_DSP_PDEC = 20
SH_INS_DSP_PINC = 21
SH_INS_DSP_PCLR = 22
SH_INS_DSP_PDMSB = 23
SH_INS_DSP_PNEG = 24
SH_INS_DSP_PCOPY = 25
SH_INS_DSP_PSTS = 26
SH_INS_DSP_PLDS = 27
SH_INS_DSP_PSWAP = 28
SH_INS_DSP_PWAD = 29
SH_INS_DSP_PWSB = 30
SH_OP_DSP_INVALID = 0
SH_OP_DSP_REG_PRE = 1
SH_OP_DSP_REG_IND = 2
SH_OP_DSP_REG_POST = 3
SH_OP_DSP_REG_INDEX = 4
SH_OP_DSP_REG = 5
SH_OP_DSP_IMM = 6
SH_DSP_CC_INVALID = 0
SH_DSP_CC_NONE = 1
SH_DSP_CC_DCT = 2
SH_DSP_CC_DCF = 3
SH_INS_INVALID = 0
SH_INS_ADD_r = 1
SH_INS_ADD = 2
SH_INS_ADDC = 3
SH_INS_ADDV = 4
SH_INS_AND = 5
SH_INS_BAND = 6
SH_INS_BANDNOT = 7
SH_INS_BCLR = 8
SH_INS_BF = 9
SH_INS_BF_S = 10
SH_INS_BLD = 11
SH_INS_BLDNOT = 12
SH_INS_BOR = 13
SH_INS_BORNOT = 14
SH_INS_BRA = 15
SH_INS_BRAF = 16
SH_INS_BSET = 17
SH_INS_BSR = 18
SH_INS_BSRF = 19
SH_INS_BST = 20
SH_INS_BT = 21
SH_INS_BT_S = 22
SH_INS_BXOR = 23
SH_INS_CLIPS = 24
SH_INS_CLIPU = 25
SH_INS_CLRDMXY = 26
SH_INS_CLRMAC = 27
SH_INS_CLRS = 28
SH_INS_CLRT = 29
SH_INS_CMP_EQ = 30
SH_INS_CMP_GE = 31
SH_INS_CMP_GT = 32
SH_INS_CMP_HI = 33
SH_INS_CMP_HS = 34
SH_INS_CMP_PL = 35
SH_INS_CMP_PZ = 36
SH_INS_CMP_STR = 37
SH_INS_DIV0S = 38
SH_INS_DIV0U = 39
SH_INS_DIV1 = 40
SH_INS_DIVS = 41
SH_INS_DIVU = 42
SH_INS_DMULS_L = 43
SH_INS_DMULU_L = 44
SH_INS_DT = 45
SH_INS_EXTS_B = 46
SH_INS_EXTS_W = 47
SH_INS_EXTU_B = 48
SH_INS_EXTU_W = 49
SH_INS_FABS = 50
SH_INS_FADD = 51
SH_INS_FCMP_EQ = 52
SH_INS_FCMP_GT = 53
SH_INS_FCNVDS = 54
SH_INS_FCNVSD = 55
SH_INS_FDIV = 56
SH_INS_FIPR = 57
SH_INS_FLDI0 = 58
SH_INS_FLDI1 = 59
SH_INS_FLDS = 60
SH_INS_FLOAT = 61
SH_INS_FMAC = 62
SH_INS_FMOV = 63
SH_INS_FMUL = 64
SH_INS_FNEG = 65
SH_INS_FPCHG = 66
SH_INS_FRCHG = 67
SH_INS_FSCA = 68
SH_INS_FSCHG = 69
SH_INS_FSQRT = 70
SH_INS_FSRRA = 71
SH_INS_FSTS = 72
SH_INS_FSUB = 73
SH_INS_FTRC = 74
SH_INS_FTRV = 75
SH_INS_ICBI = 76
SH_INS_JMP = 77
SH_INS_JSR = 78
SH_INS_JSR_N = 79
SH_INS_LDBANK = 80
SH_INS_LDC = 81
SH_INS_LDRC = 82
SH_INS_LDRE = 83
SH_INS_LDRS = 84
SH_INS_LDS = 85
SH_INS_LDTLB = 86
SH_INS_MAC_L = 87
SH_INS_MAC_W = 88
SH_INS_MOV = 89
SH_INS_MOVA = 90
SH_INS_MOVCA = 91
SH_INS_MOVCO = 92
SH_INS_MOVI20 = 93
SH_INS_MOVI20S = 94
SH_INS_MOVLI = 95
SH_INS_MOVML = 96
SH_INS_MOVMU = 97
SH_INS_MOVRT = 98
SH_INS_MOVT = 99
SH_INS_MOVU = 100
SH_INS_MOVUA = 101
SH_INS_MUL_L = 102
SH_INS_MULR = 103
SH_INS_MULS_W = 104
SH_INS_MULU_W = 105
SH_INS_NEG = 106
SH_INS_NEGC = 107
SH_INS_NOP = 108
SH_INS_NOT = 109
SH_INS_NOTT = 110
SH_INS_OCBI = 111
SH_INS_OCBP = 112
SH_INS_OCBWB = 113
SH_INS_OR = 114
SH_INS_PREF = 115
SH_INS_PREFI = 116
SH_INS_RESBANK = 117
SH_INS_ROTCL = 118
SH_INS_ROTCR = 119
SH_INS_ROTL = 120
SH_INS_ROTR = 121
SH_INS_RTE = 122
SH_INS_RTS = 123
SH_INS_RTS_N = 124
SH_INS_RTV_N = 125
SH_INS_SETDMX = 126
SH_INS_SETDMY = 127
SH_INS_SETRC = 128
SH_INS_SETS = 129
SH_INS_SETT = 130
SH_INS_SHAD = 131
SH_INS_SHAL = 132
SH_INS_SHAR = 133
SH_INS_SHLD = 134
SH_INS_SHLL = 135
SH_INS_SHLL16 = 136
SH_INS_SHLL2 = 137
SH_INS_SHLL8 = 138
SH_INS_SHLR = 139
SH_INS_SHLR16 = 140
SH_INS_SHLR2 = 141
SH_INS_SHLR8 = 142
SH_INS_SLEEP = 143
SH_INS_STBANK = 144
SH_INS_STC = 145
SH_INS_STS = 146
SH_INS_SUB = 147
SH_INS_SUBC = 148
SH_INS_SUBV = 149
SH_INS_SWAP_B = 150
SH_INS_SWAP_W = 151
SH_INS_SYNCO = 152
SH_INS_TAS = 153
SH_INS_TRAPA = 154
SH_INS_TST = 155
SH_INS_XOR = 156
SH_INS_XTRCT = 157
SH_INS_DSP = 158
SH_INS_ENDING = 159
SH_GRP_INVALID = 0
SH_GRP_JUMP = 1
SH_GRP_CALL = 2
SH_GRP_INT = 3
SH_GRP_RET = 4
SH_GRP_IRET = 5
SH_GRP_PRIVILEGE = 6
SH_GRP_BRANCH_RELATIVE = 7
SH_GRP_SH1 = 8
SH_GRP_SH2 = 9
SH_GRP_SH2E = 10
SH_GRP_SH2DSP = 11
SH_GRP_SH2A = 12
SH_GRP_SH2AFPU = 13
SH_GRP_SH3 = 14
SH_GRP_SH3DSP = 15
SH_GRP_SH4 = 16
SH_GRP_SH4A = 17
SH_GRP_ENDING = 18

51
thirdparty/capstone/bindings/python/capstone/sparc.py vendored Normal file
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# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
import ctypes
from . import copy_ctypes_list
from .sparc_const import *
# define the API
class SparcOpMem(ctypes.Structure):
_fields_ = (
('base', ctypes.c_uint8),
('index', ctypes.c_uint8),
('disp', ctypes.c_int32),
)
class SparcOpValue(ctypes.Union):
_fields_ = (
('reg', ctypes.c_uint),
('imm', ctypes.c_int64),
('mem', SparcOpMem),
)
class SparcOp(ctypes.Structure):
_fields_ = (
('type', ctypes.c_uint),
('value', SparcOpValue),
)
@property
def imm(self):
return self.value.imm
@property
def reg(self):
return self.value.reg
@property
def mem(self):
return self.value.mem
class CsSparc(ctypes.Structure):
_fields_ = (
('cc', ctypes.c_uint),
('hint', ctypes.c_uint),
('op_count', ctypes.c_uint8),
('operands', SparcOp * 4),
)
def get_arch_info(a):
return (a.cc, a.hint, copy_ctypes_list(a.operands[:a.op_count]))

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thirdparty/capstone/bindings/python/capstone/sparc_const.py vendored Normal file
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from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [sparc_const.py]
SPARC_CC_INVALID = 0
SPARC_CC_ICC_A = 8+256
SPARC_CC_ICC_N = 0+256
SPARC_CC_ICC_NE = 9+256
SPARC_CC_ICC_E = 1+256
SPARC_CC_ICC_G = 10+256
SPARC_CC_ICC_LE = 2+256
SPARC_CC_ICC_GE = 11+256
SPARC_CC_ICC_L = 3+256
SPARC_CC_ICC_GU = 12+256
SPARC_CC_ICC_LEU = 4+256
SPARC_CC_ICC_CC = 13+256
SPARC_CC_ICC_CS = 5+256
SPARC_CC_ICC_POS = 14+256
SPARC_CC_ICC_NEG = 6+256
SPARC_CC_ICC_VC = 15+256
SPARC_CC_ICC_VS = 7+256
SPARC_CC_FCC_A = 8+16+256
SPARC_CC_FCC_N = 0+16+256
SPARC_CC_FCC_U = 7+16+256
SPARC_CC_FCC_G = 6+16+256
SPARC_CC_FCC_UG = 5+16+256
SPARC_CC_FCC_L = 4+16+256
SPARC_CC_FCC_UL = 3+16+256
SPARC_CC_FCC_LG = 2+16+256
SPARC_CC_FCC_NE = 1+16+256
SPARC_CC_FCC_E = 9+16+256
SPARC_CC_FCC_UE = 10+16+256
SPARC_CC_FCC_GE = 11+16+256
SPARC_CC_FCC_UGE = 12+16+256
SPARC_CC_FCC_LE = 13+16+256
SPARC_CC_FCC_ULE = 14+16+256
SPARC_CC_FCC_O = 15+16+256
SPARC_HINT_INVALID = 0
SPARC_HINT_A = 1<<0
SPARC_HINT_PT = 1<<1
SPARC_HINT_PN = 1<<2
SPARC_HINT_A_PN = SPARC_HINT_A|SPARC_HINT_PN
SPARC_HINT_A_PT = SPARC_HINT_A|SPARC_HINT_PT
SPARC_OP_INVALID = 0
SPARC_OP_REG = 1
SPARC_OP_IMM = 2
SPARC_OP_MEM = 3
SPARC_REG_INVALID = 0
SPARC_REG_F0 = 1
SPARC_REG_F1 = 2
SPARC_REG_F2 = 3
SPARC_REG_F3 = 4
SPARC_REG_F4 = 5
SPARC_REG_F5 = 6
SPARC_REG_F6 = 7
SPARC_REG_F7 = 8
SPARC_REG_F8 = 9
SPARC_REG_F9 = 10
SPARC_REG_F10 = 11
SPARC_REG_F11 = 12
SPARC_REG_F12 = 13
SPARC_REG_F13 = 14
SPARC_REG_F14 = 15
SPARC_REG_F15 = 16
SPARC_REG_F16 = 17
SPARC_REG_F17 = 18
SPARC_REG_F18 = 19
SPARC_REG_F19 = 20
SPARC_REG_F20 = 21
SPARC_REG_F21 = 22
SPARC_REG_F22 = 23
SPARC_REG_F23 = 24
SPARC_REG_F24 = 25
SPARC_REG_F25 = 26
SPARC_REG_F26 = 27
SPARC_REG_F27 = 28
SPARC_REG_F28 = 29
SPARC_REG_F29 = 30
SPARC_REG_F30 = 31
SPARC_REG_F31 = 32
SPARC_REG_F32 = 33
SPARC_REG_F34 = 34
SPARC_REG_F36 = 35
SPARC_REG_F38 = 36
SPARC_REG_F40 = 37
SPARC_REG_F42 = 38
SPARC_REG_F44 = 39
SPARC_REG_F46 = 40
SPARC_REG_F48 = 41
SPARC_REG_F50 = 42
SPARC_REG_F52 = 43
SPARC_REG_F54 = 44
SPARC_REG_F56 = 45
SPARC_REG_F58 = 46
SPARC_REG_F60 = 47
SPARC_REG_F62 = 48
SPARC_REG_FCC0 = 49
SPARC_REG_FCC1 = 50
SPARC_REG_FCC2 = 51
SPARC_REG_FCC3 = 52
SPARC_REG_FP = 53
SPARC_REG_G0 = 54
SPARC_REG_G1 = 55
SPARC_REG_G2 = 56
SPARC_REG_G3 = 57
SPARC_REG_G4 = 58
SPARC_REG_G5 = 59
SPARC_REG_G6 = 60
SPARC_REG_G7 = 61
SPARC_REG_I0 = 62
SPARC_REG_I1 = 63
SPARC_REG_I2 = 64
SPARC_REG_I3 = 65
SPARC_REG_I4 = 66
SPARC_REG_I5 = 67
SPARC_REG_I7 = 68
SPARC_REG_ICC = 69
SPARC_REG_L0 = 70
SPARC_REG_L1 = 71
SPARC_REG_L2 = 72
SPARC_REG_L3 = 73
SPARC_REG_L4 = 74
SPARC_REG_L5 = 75
SPARC_REG_L6 = 76
SPARC_REG_L7 = 77
SPARC_REG_O0 = 78
SPARC_REG_O1 = 79
SPARC_REG_O2 = 80
SPARC_REG_O3 = 81
SPARC_REG_O4 = 82
SPARC_REG_O5 = 83
SPARC_REG_O7 = 84
SPARC_REG_SP = 85
SPARC_REG_Y = 86
SPARC_REG_XCC = 87
SPARC_REG_ENDING = 88
SPARC_REG_O6 = SPARC_REG_SP
SPARC_REG_I6 = SPARC_REG_FP
SPARC_INS_INVALID = 0
SPARC_INS_ADDCC = 1
SPARC_INS_ADDX = 2
SPARC_INS_ADDXCC = 3
SPARC_INS_ADDXC = 4
SPARC_INS_ADDXCCC = 5
SPARC_INS_ADD = 6
SPARC_INS_ALIGNADDR = 7
SPARC_INS_ALIGNADDRL = 8
SPARC_INS_ANDCC = 9
SPARC_INS_ANDNCC = 10
SPARC_INS_ANDN = 11
SPARC_INS_AND = 12
SPARC_INS_ARRAY16 = 13
SPARC_INS_ARRAY32 = 14
SPARC_INS_ARRAY8 = 15
SPARC_INS_B = 16
SPARC_INS_JMP = 17
SPARC_INS_BMASK = 18
SPARC_INS_FB = 19
SPARC_INS_BRGEZ = 20
SPARC_INS_BRGZ = 21
SPARC_INS_BRLEZ = 22
SPARC_INS_BRLZ = 23
SPARC_INS_BRNZ = 24
SPARC_INS_BRZ = 25
SPARC_INS_BSHUFFLE = 26
SPARC_INS_CALL = 27
SPARC_INS_CASX = 28
SPARC_INS_CAS = 29
SPARC_INS_CMASK16 = 30
SPARC_INS_CMASK32 = 31
SPARC_INS_CMASK8 = 32
SPARC_INS_CMP = 33
SPARC_INS_EDGE16 = 34
SPARC_INS_EDGE16L = 35
SPARC_INS_EDGE16LN = 36
SPARC_INS_EDGE16N = 37
SPARC_INS_EDGE32 = 38
SPARC_INS_EDGE32L = 39
SPARC_INS_EDGE32LN = 40
SPARC_INS_EDGE32N = 41
SPARC_INS_EDGE8 = 42
SPARC_INS_EDGE8L = 43
SPARC_INS_EDGE8LN = 44
SPARC_INS_EDGE8N = 45
SPARC_INS_FABSD = 46
SPARC_INS_FABSQ = 47
SPARC_INS_FABSS = 48
SPARC_INS_FADDD = 49
SPARC_INS_FADDQ = 50
SPARC_INS_FADDS = 51
SPARC_INS_FALIGNDATA = 52
SPARC_INS_FAND = 53
SPARC_INS_FANDNOT1 = 54
SPARC_INS_FANDNOT1S = 55
SPARC_INS_FANDNOT2 = 56
SPARC_INS_FANDNOT2S = 57
SPARC_INS_FANDS = 58
SPARC_INS_FCHKSM16 = 59
SPARC_INS_FCMPD = 60
SPARC_INS_FCMPEQ16 = 61
SPARC_INS_FCMPEQ32 = 62
SPARC_INS_FCMPGT16 = 63
SPARC_INS_FCMPGT32 = 64
SPARC_INS_FCMPLE16 = 65
SPARC_INS_FCMPLE32 = 66
SPARC_INS_FCMPNE16 = 67
SPARC_INS_FCMPNE32 = 68
SPARC_INS_FCMPQ = 69
SPARC_INS_FCMPS = 70
SPARC_INS_FDIVD = 71
SPARC_INS_FDIVQ = 72
SPARC_INS_FDIVS = 73
SPARC_INS_FDMULQ = 74
SPARC_INS_FDTOI = 75
SPARC_INS_FDTOQ = 76
SPARC_INS_FDTOS = 77
SPARC_INS_FDTOX = 78
SPARC_INS_FEXPAND = 79
SPARC_INS_FHADDD = 80
SPARC_INS_FHADDS = 81
SPARC_INS_FHSUBD = 82
SPARC_INS_FHSUBS = 83
SPARC_INS_FITOD = 84
SPARC_INS_FITOQ = 85
SPARC_INS_FITOS = 86
SPARC_INS_FLCMPD = 87
SPARC_INS_FLCMPS = 88
SPARC_INS_FLUSHW = 89
SPARC_INS_FMEAN16 = 90
SPARC_INS_FMOVD = 91
SPARC_INS_FMOVQ = 92
SPARC_INS_FMOVRDGEZ = 93
SPARC_INS_FMOVRQGEZ = 94
SPARC_INS_FMOVRSGEZ = 95
SPARC_INS_FMOVRDGZ = 96
SPARC_INS_FMOVRQGZ = 97
SPARC_INS_FMOVRSGZ = 98
SPARC_INS_FMOVRDLEZ = 99
SPARC_INS_FMOVRQLEZ = 100
SPARC_INS_FMOVRSLEZ = 101
SPARC_INS_FMOVRDLZ = 102
SPARC_INS_FMOVRQLZ = 103
SPARC_INS_FMOVRSLZ = 104
SPARC_INS_FMOVRDNZ = 105
SPARC_INS_FMOVRQNZ = 106
SPARC_INS_FMOVRSNZ = 107
SPARC_INS_FMOVRDZ = 108
SPARC_INS_FMOVRQZ = 109
SPARC_INS_FMOVRSZ = 110
SPARC_INS_FMOVS = 111
SPARC_INS_FMUL8SUX16 = 112
SPARC_INS_FMUL8ULX16 = 113
SPARC_INS_FMUL8X16 = 114
SPARC_INS_FMUL8X16AL = 115
SPARC_INS_FMUL8X16AU = 116
SPARC_INS_FMULD = 117
SPARC_INS_FMULD8SUX16 = 118
SPARC_INS_FMULD8ULX16 = 119
SPARC_INS_FMULQ = 120
SPARC_INS_FMULS = 121
SPARC_INS_FNADDD = 122
SPARC_INS_FNADDS = 123
SPARC_INS_FNAND = 124
SPARC_INS_FNANDS = 125
SPARC_INS_FNEGD = 126
SPARC_INS_FNEGQ = 127
SPARC_INS_FNEGS = 128
SPARC_INS_FNHADDD = 129
SPARC_INS_FNHADDS = 130
SPARC_INS_FNOR = 131
SPARC_INS_FNORS = 132
SPARC_INS_FNOT1 = 133
SPARC_INS_FNOT1S = 134
SPARC_INS_FNOT2 = 135
SPARC_INS_FNOT2S = 136
SPARC_INS_FONE = 137
SPARC_INS_FONES = 138
SPARC_INS_FOR = 139
SPARC_INS_FORNOT1 = 140
SPARC_INS_FORNOT1S = 141
SPARC_INS_FORNOT2 = 142
SPARC_INS_FORNOT2S = 143
SPARC_INS_FORS = 144
SPARC_INS_FPACK16 = 145
SPARC_INS_FPACK32 = 146
SPARC_INS_FPACKFIX = 147
SPARC_INS_FPADD16 = 148
SPARC_INS_FPADD16S = 149
SPARC_INS_FPADD32 = 150
SPARC_INS_FPADD32S = 151
SPARC_INS_FPADD64 = 152
SPARC_INS_FPMERGE = 153
SPARC_INS_FPSUB16 = 154
SPARC_INS_FPSUB16S = 155
SPARC_INS_FPSUB32 = 156
SPARC_INS_FPSUB32S = 157
SPARC_INS_FQTOD = 158
SPARC_INS_FQTOI = 159
SPARC_INS_FQTOS = 160
SPARC_INS_FQTOX = 161
SPARC_INS_FSLAS16 = 162
SPARC_INS_FSLAS32 = 163
SPARC_INS_FSLL16 = 164
SPARC_INS_FSLL32 = 165
SPARC_INS_FSMULD = 166
SPARC_INS_FSQRTD = 167
SPARC_INS_FSQRTQ = 168
SPARC_INS_FSQRTS = 169
SPARC_INS_FSRA16 = 170
SPARC_INS_FSRA32 = 171
SPARC_INS_FSRC1 = 172
SPARC_INS_FSRC1S = 173
SPARC_INS_FSRC2 = 174
SPARC_INS_FSRC2S = 175
SPARC_INS_FSRL16 = 176
SPARC_INS_FSRL32 = 177
SPARC_INS_FSTOD = 178
SPARC_INS_FSTOI = 179
SPARC_INS_FSTOQ = 180
SPARC_INS_FSTOX = 181
SPARC_INS_FSUBD = 182
SPARC_INS_FSUBQ = 183
SPARC_INS_FSUBS = 184
SPARC_INS_FXNOR = 185
SPARC_INS_FXNORS = 186
SPARC_INS_FXOR = 187
SPARC_INS_FXORS = 188
SPARC_INS_FXTOD = 189
SPARC_INS_FXTOQ = 190
SPARC_INS_FXTOS = 191
SPARC_INS_FZERO = 192
SPARC_INS_FZEROS = 193
SPARC_INS_JMPL = 194
SPARC_INS_LDD = 195
SPARC_INS_LD = 196
SPARC_INS_LDQ = 197
SPARC_INS_LDSB = 198
SPARC_INS_LDSH = 199
SPARC_INS_LDSW = 200
SPARC_INS_LDUB = 201
SPARC_INS_LDUH = 202
SPARC_INS_LDX = 203
SPARC_INS_LZCNT = 204
SPARC_INS_MEMBAR = 205
SPARC_INS_MOVDTOX = 206
SPARC_INS_MOV = 207
SPARC_INS_MOVRGEZ = 208
SPARC_INS_MOVRGZ = 209
SPARC_INS_MOVRLEZ = 210
SPARC_INS_MOVRLZ = 211
SPARC_INS_MOVRNZ = 212
SPARC_INS_MOVRZ = 213
SPARC_INS_MOVSTOSW = 214
SPARC_INS_MOVSTOUW = 215
SPARC_INS_MULX = 216
SPARC_INS_NOP = 217
SPARC_INS_ORCC = 218
SPARC_INS_ORNCC = 219
SPARC_INS_ORN = 220
SPARC_INS_OR = 221
SPARC_INS_PDIST = 222
SPARC_INS_PDISTN = 223
SPARC_INS_POPC = 224
SPARC_INS_RD = 225
SPARC_INS_RESTORE = 226
SPARC_INS_RETT = 227
SPARC_INS_SAVE = 228
SPARC_INS_SDIVCC = 229
SPARC_INS_SDIVX = 230
SPARC_INS_SDIV = 231
SPARC_INS_SETHI = 232
SPARC_INS_SHUTDOWN = 233
SPARC_INS_SIAM = 234
SPARC_INS_SLLX = 235
SPARC_INS_SLL = 236
SPARC_INS_SMULCC = 237
SPARC_INS_SMUL = 238
SPARC_INS_SRAX = 239
SPARC_INS_SRA = 240
SPARC_INS_SRLX = 241
SPARC_INS_SRL = 242
SPARC_INS_STBAR = 243
SPARC_INS_STB = 244
SPARC_INS_STD = 245
SPARC_INS_ST = 246
SPARC_INS_STH = 247
SPARC_INS_STQ = 248
SPARC_INS_STX = 249
SPARC_INS_SUBCC = 250
SPARC_INS_SUBX = 251
SPARC_INS_SUBXCC = 252
SPARC_INS_SUB = 253
SPARC_INS_SWAP = 254
SPARC_INS_TADDCCTV = 255
SPARC_INS_TADDCC = 256
SPARC_INS_T = 257
SPARC_INS_TSUBCCTV = 258
SPARC_INS_TSUBCC = 259
SPARC_INS_UDIVCC = 260
SPARC_INS_UDIVX = 261
SPARC_INS_UDIV = 262
SPARC_INS_UMULCC = 263
SPARC_INS_UMULXHI = 264
SPARC_INS_UMUL = 265
SPARC_INS_UNIMP = 266
SPARC_INS_FCMPED = 267
SPARC_INS_FCMPEQ = 268
SPARC_INS_FCMPES = 269
SPARC_INS_WR = 270
SPARC_INS_XMULX = 271
SPARC_INS_XMULXHI = 272
SPARC_INS_XNORCC = 273
SPARC_INS_XNOR = 274
SPARC_INS_XORCC = 275
SPARC_INS_XOR = 276
SPARC_INS_RET = 277
SPARC_INS_RETL = 278
SPARC_INS_ENDING = 279
SPARC_GRP_INVALID = 0
SPARC_GRP_JUMP = 1
SPARC_GRP_HARDQUAD = 128
SPARC_GRP_V9 = 129
SPARC_GRP_VIS = 130
SPARC_GRP_VIS2 = 131
SPARC_GRP_VIS3 = 132
SPARC_GRP_32BIT = 133
SPARC_GRP_64BIT = 134
SPARC_GRP_ENDING = 135

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thirdparty/capstone/bindings/python/capstone/systemz.py vendored Normal file
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# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
import ctypes
from . import copy_ctypes_list
from .sysz_const import *
# define the API
class SyszOpMem(ctypes.Structure):
_fields_ = (
('base', ctypes.c_uint8),
('index', ctypes.c_uint8),
('length', ctypes.c_uint64),
('disp', ctypes.c_int64),
)
class SyszOpValue(ctypes.Union):
_fields_ = (
('reg', ctypes.c_uint),
('imm', ctypes.c_int64),
('mem', SyszOpMem),
)
class SyszOp(ctypes.Structure):
_fields_ = (
('type', ctypes.c_uint),
('value', SyszOpValue),
)
@property
def imm(self):
return self.value.imm
@property
def reg(self):
return self.value.reg
@property
def mem(self):
return self.value.mem
class CsSysz(ctypes.Structure):
_fields_ = (
('cc', ctypes.c_uint),
('op_count', ctypes.c_uint8),
('operands', SyszOp * 6),
)
def get_arch_info(a):
return (a.cc, copy_ctypes_list(a.operands[:a.op_count]))

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66
thirdparty/capstone/bindings/python/capstone/tms320c64x.py vendored Normal file
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# Capstone Python bindings, by Fotis Loukos <me@fotisl.com>
import ctypes, copy
from .tms320c64x_const import *
# define the API
class TMS320C64xOpMem(ctypes.Structure):
_fields_ = (
('base', ctypes.c_int),
('disp', ctypes.c_int),
('unit', ctypes.c_int),
('scaled', ctypes.c_int),
('disptype', ctypes.c_int),
('direction', ctypes.c_int),
('modify', ctypes.c_int),
)
class TMS320C64xOpValue(ctypes.Union):
_fields_ = (
('reg', ctypes.c_uint),
('imm', ctypes.c_int32),
('mem', TMS320C64xOpMem),
)
class TMS320C64xCondition(ctypes.Structure):
_fields_ = (
('reg', ctypes.c_uint),
('zero', ctypes.c_uint),
)
class TMS320C64xFunctionalUnit(ctypes.Structure):
_fields_ = (
('unit', ctypes.c_uint),
('side', ctypes.c_uint),
('crosspath', ctypes.c_uint),
)
class TMS320C64xOp(ctypes.Structure):
_fields_ = (
('type', ctypes.c_uint),
('value', TMS320C64xOpValue),
)
@property
def imm(self):
return self.value.imm
@property
def reg(self):
return self.value.reg
@property
def mem(self):
return self.value.mem
class CsTMS320C64x(ctypes.Structure):
_fields_ = (
('op_count', ctypes.c_uint8),
('operands', TMS320C64xOp * 8),
('condition', TMS320C64xCondition),
('funit', TMS320C64xFunctionalUnit),
('parallel', ctypes.c_uint),
)
def get_arch_info(a):
return (a.condition, a.funit, a.parallel, copy.deepcopy(a.operands[:a.op_count]))

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thirdparty/capstone/bindings/python/capstone/tms320c64x_const.py vendored Normal file
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from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [tms320c64x_const.py]
TMS320C64X_OP_INVALID = 0
TMS320C64X_OP_REG = 1
TMS320C64X_OP_IMM = 2
TMS320C64X_OP_MEM = 3
TMS320C64X_OP_REGPAIR = 64
TMS320C64X_MEM_DISP_INVALID = 0
TMS320C64X_MEM_DISP_CONSTANT = 1
TMS320C64X_MEM_DISP_REGISTER = 2
TMS320C64X_MEM_DIR_INVALID = 0
TMS320C64X_MEM_DIR_FW = 1
TMS320C64X_MEM_DIR_BW = 2
TMS320C64X_MEM_MOD_INVALID = 0
TMS320C64X_MEM_MOD_NO = 1
TMS320C64X_MEM_MOD_PRE = 2
TMS320C64X_MEM_MOD_POST = 3
TMS320C64X_REG_INVALID = 0
TMS320C64X_REG_AMR = 1
TMS320C64X_REG_CSR = 2
TMS320C64X_REG_DIER = 3
TMS320C64X_REG_DNUM = 4
TMS320C64X_REG_ECR = 5
TMS320C64X_REG_GFPGFR = 6
TMS320C64X_REG_GPLYA = 7
TMS320C64X_REG_GPLYB = 8
TMS320C64X_REG_ICR = 9
TMS320C64X_REG_IER = 10
TMS320C64X_REG_IERR = 11
TMS320C64X_REG_ILC = 12
TMS320C64X_REG_IRP = 13
TMS320C64X_REG_ISR = 14
TMS320C64X_REG_ISTP = 15
TMS320C64X_REG_ITSR = 16
TMS320C64X_REG_NRP = 17
TMS320C64X_REG_NTSR = 18
TMS320C64X_REG_REP = 19
TMS320C64X_REG_RILC = 20
TMS320C64X_REG_SSR = 21
TMS320C64X_REG_TSCH = 22
TMS320C64X_REG_TSCL = 23
TMS320C64X_REG_TSR = 24
TMS320C64X_REG_A0 = 25
TMS320C64X_REG_A1 = 26
TMS320C64X_REG_A2 = 27
TMS320C64X_REG_A3 = 28
TMS320C64X_REG_A4 = 29
TMS320C64X_REG_A5 = 30
TMS320C64X_REG_A6 = 31
TMS320C64X_REG_A7 = 32
TMS320C64X_REG_A8 = 33
TMS320C64X_REG_A9 = 34
TMS320C64X_REG_A10 = 35
TMS320C64X_REG_A11 = 36
TMS320C64X_REG_A12 = 37
TMS320C64X_REG_A13 = 38
TMS320C64X_REG_A14 = 39
TMS320C64X_REG_A15 = 40
TMS320C64X_REG_A16 = 41
TMS320C64X_REG_A17 = 42
TMS320C64X_REG_A18 = 43
TMS320C64X_REG_A19 = 44
TMS320C64X_REG_A20 = 45
TMS320C64X_REG_A21 = 46
TMS320C64X_REG_A22 = 47
TMS320C64X_REG_A23 = 48
TMS320C64X_REG_A24 = 49
TMS320C64X_REG_A25 = 50
TMS320C64X_REG_A26 = 51
TMS320C64X_REG_A27 = 52
TMS320C64X_REG_A28 = 53
TMS320C64X_REG_A29 = 54
TMS320C64X_REG_A30 = 55
TMS320C64X_REG_A31 = 56
TMS320C64X_REG_B0 = 57
TMS320C64X_REG_B1 = 58
TMS320C64X_REG_B2 = 59
TMS320C64X_REG_B3 = 60
TMS320C64X_REG_B4 = 61
TMS320C64X_REG_B5 = 62
TMS320C64X_REG_B6 = 63
TMS320C64X_REG_B7 = 64
TMS320C64X_REG_B8 = 65
TMS320C64X_REG_B9 = 66
TMS320C64X_REG_B10 = 67
TMS320C64X_REG_B11 = 68
TMS320C64X_REG_B12 = 69
TMS320C64X_REG_B13 = 70
TMS320C64X_REG_B14 = 71
TMS320C64X_REG_B15 = 72
TMS320C64X_REG_B16 = 73
TMS320C64X_REG_B17 = 74
TMS320C64X_REG_B18 = 75
TMS320C64X_REG_B19 = 76
TMS320C64X_REG_B20 = 77
TMS320C64X_REG_B21 = 78
TMS320C64X_REG_B22 = 79
TMS320C64X_REG_B23 = 80
TMS320C64X_REG_B24 = 81
TMS320C64X_REG_B25 = 82
TMS320C64X_REG_B26 = 83
TMS320C64X_REG_B27 = 84
TMS320C64X_REG_B28 = 85
TMS320C64X_REG_B29 = 86
TMS320C64X_REG_B30 = 87
TMS320C64X_REG_B31 = 88
TMS320C64X_REG_PCE1 = 89
TMS320C64X_REG_ENDING = 90
TMS320C64X_REG_EFR = TMS320C64X_REG_ECR
TMS320C64X_REG_IFR = TMS320C64X_REG_ISR
TMS320C64X_INS_INVALID = 0
TMS320C64X_INS_ABS = 1
TMS320C64X_INS_ABS2 = 2
TMS320C64X_INS_ADD = 3
TMS320C64X_INS_ADD2 = 4
TMS320C64X_INS_ADD4 = 5
TMS320C64X_INS_ADDAB = 6
TMS320C64X_INS_ADDAD = 7
TMS320C64X_INS_ADDAH = 8
TMS320C64X_INS_ADDAW = 9
TMS320C64X_INS_ADDK = 10
TMS320C64X_INS_ADDKPC = 11
TMS320C64X_INS_ADDU = 12
TMS320C64X_INS_AND = 13
TMS320C64X_INS_ANDN = 14
TMS320C64X_INS_AVG2 = 15
TMS320C64X_INS_AVGU4 = 16
TMS320C64X_INS_B = 17
TMS320C64X_INS_BDEC = 18
TMS320C64X_INS_BITC4 = 19
TMS320C64X_INS_BNOP = 20
TMS320C64X_INS_BPOS = 21
TMS320C64X_INS_CLR = 22
TMS320C64X_INS_CMPEQ = 23
TMS320C64X_INS_CMPEQ2 = 24
TMS320C64X_INS_CMPEQ4 = 25
TMS320C64X_INS_CMPGT = 26
TMS320C64X_INS_CMPGT2 = 27
TMS320C64X_INS_CMPGTU4 = 28
TMS320C64X_INS_CMPLT = 29
TMS320C64X_INS_CMPLTU = 30
TMS320C64X_INS_DEAL = 31
TMS320C64X_INS_DOTP2 = 32
TMS320C64X_INS_DOTPN2 = 33
TMS320C64X_INS_DOTPNRSU2 = 34
TMS320C64X_INS_DOTPRSU2 = 35
TMS320C64X_INS_DOTPSU4 = 36
TMS320C64X_INS_DOTPU4 = 37
TMS320C64X_INS_EXT = 38
TMS320C64X_INS_EXTU = 39
TMS320C64X_INS_GMPGTU = 40
TMS320C64X_INS_GMPY4 = 41
TMS320C64X_INS_LDB = 42
TMS320C64X_INS_LDBU = 43
TMS320C64X_INS_LDDW = 44
TMS320C64X_INS_LDH = 45
TMS320C64X_INS_LDHU = 46
TMS320C64X_INS_LDNDW = 47
TMS320C64X_INS_LDNW = 48
TMS320C64X_INS_LDW = 49
TMS320C64X_INS_LMBD = 50
TMS320C64X_INS_MAX2 = 51
TMS320C64X_INS_MAXU4 = 52
TMS320C64X_INS_MIN2 = 53
TMS320C64X_INS_MINU4 = 54
TMS320C64X_INS_MPY = 55
TMS320C64X_INS_MPY2 = 56
TMS320C64X_INS_MPYH = 57
TMS320C64X_INS_MPYHI = 58
TMS320C64X_INS_MPYHIR = 59
TMS320C64X_INS_MPYHL = 60
TMS320C64X_INS_MPYHLU = 61
TMS320C64X_INS_MPYHSLU = 62
TMS320C64X_INS_MPYHSU = 63
TMS320C64X_INS_MPYHU = 64
TMS320C64X_INS_MPYHULS = 65
TMS320C64X_INS_MPYHUS = 66
TMS320C64X_INS_MPYLH = 67
TMS320C64X_INS_MPYLHU = 68
TMS320C64X_INS_MPYLI = 69
TMS320C64X_INS_MPYLIR = 70
TMS320C64X_INS_MPYLSHU = 71
TMS320C64X_INS_MPYLUHS = 72
TMS320C64X_INS_MPYSU = 73
TMS320C64X_INS_MPYSU4 = 74
TMS320C64X_INS_MPYU = 75
TMS320C64X_INS_MPYU4 = 76
TMS320C64X_INS_MPYUS = 77
TMS320C64X_INS_MVC = 78
TMS320C64X_INS_MVD = 79
TMS320C64X_INS_MVK = 80
TMS320C64X_INS_MVKL = 81
TMS320C64X_INS_MVKLH = 82
TMS320C64X_INS_NOP = 83
TMS320C64X_INS_NORM = 84
TMS320C64X_INS_OR = 85
TMS320C64X_INS_PACK2 = 86
TMS320C64X_INS_PACKH2 = 87
TMS320C64X_INS_PACKH4 = 88
TMS320C64X_INS_PACKHL2 = 89
TMS320C64X_INS_PACKL4 = 90
TMS320C64X_INS_PACKLH2 = 91
TMS320C64X_INS_ROTL = 92
TMS320C64X_INS_SADD = 93
TMS320C64X_INS_SADD2 = 94
TMS320C64X_INS_SADDU4 = 95
TMS320C64X_INS_SADDUS2 = 96
TMS320C64X_INS_SAT = 97
TMS320C64X_INS_SET = 98
TMS320C64X_INS_SHFL = 99
TMS320C64X_INS_SHL = 100
TMS320C64X_INS_SHLMB = 101
TMS320C64X_INS_SHR = 102
TMS320C64X_INS_SHR2 = 103
TMS320C64X_INS_SHRMB = 104
TMS320C64X_INS_SHRU = 105
TMS320C64X_INS_SHRU2 = 106
TMS320C64X_INS_SMPY = 107
TMS320C64X_INS_SMPY2 = 108
TMS320C64X_INS_SMPYH = 109
TMS320C64X_INS_SMPYHL = 110
TMS320C64X_INS_SMPYLH = 111
TMS320C64X_INS_SPACK2 = 112
TMS320C64X_INS_SPACKU4 = 113
TMS320C64X_INS_SSHL = 114
TMS320C64X_INS_SSHVL = 115
TMS320C64X_INS_SSHVR = 116
TMS320C64X_INS_SSUB = 117
TMS320C64X_INS_STB = 118
TMS320C64X_INS_STDW = 119
TMS320C64X_INS_STH = 120
TMS320C64X_INS_STNDW = 121
TMS320C64X_INS_STNW = 122
TMS320C64X_INS_STW = 123
TMS320C64X_INS_SUB = 124
TMS320C64X_INS_SUB2 = 125
TMS320C64X_INS_SUB4 = 126
TMS320C64X_INS_SUBAB = 127
TMS320C64X_INS_SUBABS4 = 128
TMS320C64X_INS_SUBAH = 129
TMS320C64X_INS_SUBAW = 130
TMS320C64X_INS_SUBC = 131
TMS320C64X_INS_SUBU = 132
TMS320C64X_INS_SWAP4 = 133
TMS320C64X_INS_UNPKHU4 = 134
TMS320C64X_INS_UNPKLU4 = 135
TMS320C64X_INS_XOR = 136
TMS320C64X_INS_XPND2 = 137
TMS320C64X_INS_XPND4 = 138
TMS320C64X_INS_IDLE = 139
TMS320C64X_INS_MV = 140
TMS320C64X_INS_NEG = 141
TMS320C64X_INS_NOT = 142
TMS320C64X_INS_SWAP2 = 143
TMS320C64X_INS_ZERO = 144
TMS320C64X_INS_ENDING = 145
TMS320C64X_GRP_INVALID = 0
TMS320C64X_GRP_JUMP = 1
TMS320C64X_GRP_FUNIT_D = 128
TMS320C64X_GRP_FUNIT_L = 129
TMS320C64X_GRP_FUNIT_M = 130
TMS320C64X_GRP_FUNIT_S = 131
TMS320C64X_GRP_FUNIT_NO = 132
TMS320C64X_GRP_ENDING = 133
TMS320C64X_FUNIT_INVALID = 0
TMS320C64X_FUNIT_D = 1
TMS320C64X_FUNIT_L = 2
TMS320C64X_FUNIT_M = 3
TMS320C64X_FUNIT_S = 4
TMS320C64X_FUNIT_NO = 5

51
thirdparty/capstone/bindings/python/capstone/tricore.py vendored Normal file
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@@ -0,0 +1,51 @@
# Capstone Python bindings, by billow <billow.fun@gmail.com>
import ctypes
from . import copy_ctypes_list
from .tricore_const import *
class TriCoreOpMem(ctypes.Structure):
_fields_ = (
('base', ctypes.c_uint8),
('disp', ctypes.c_int64),
)
class TriCoreOpValue(ctypes.Union):
_fields_ = (
('reg', ctypes.c_uint),
('imm', ctypes.c_int64),
('mem', TriCoreOpMem),
)
class TriCoreOp(ctypes.Structure):
_fields_ = (
('type', ctypes.c_uint),
('value', TriCoreOpValue),
('access', ctypes.c_uint8)
)
@property
def imm(self):
return self.value.imm
@property
def reg(self):
return self.value.reg
@property
def mem(self):
return self.value.mem
# Instruction structure
class CsTriCore(ctypes.Structure):
_fields_ = (
('op_count', ctypes.c_uint8),
('operands', TriCoreOp * 8),
('update_flags', ctypes.c_bool),
)
def get_arch_info(a):
return (a.update_flags, copy_ctypes_list(a.operands[:a.op_count]))

480
thirdparty/capstone/bindings/python/capstone/tricore_const.py vendored Normal file
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@@ -0,0 +1,480 @@
from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [tricore_const.py]
TRICORE_OP_INVALID = CS_OP_INVALID
TRICORE_OP_REG = CS_OP_REG
TRICORE_OP_IMM = CS_OP_IMM
TRICORE_OP_MEM = CS_OP_MEM
TRICORE_OP_COUNT = 8
TRICORE_REG_INVALID = 0
TRICORE_REG_FCX = 1
TRICORE_REG_PC = 2
TRICORE_REG_PCXI = 3
TRICORE_REG_PSW = 4
TRICORE_REG_A0 = 5
TRICORE_REG_A1 = 6
TRICORE_REG_A2 = 7
TRICORE_REG_A3 = 8
TRICORE_REG_A4 = 9
TRICORE_REG_A5 = 10
TRICORE_REG_A6 = 11
TRICORE_REG_A7 = 12
TRICORE_REG_A8 = 13
TRICORE_REG_A9 = 14
TRICORE_REG_A10 = 15
TRICORE_REG_A11 = 16
TRICORE_REG_A12 = 17
TRICORE_REG_A13 = 18
TRICORE_REG_A14 = 19
TRICORE_REG_A15 = 20
TRICORE_REG_D0 = 21
TRICORE_REG_D1 = 22
TRICORE_REG_D2 = 23
TRICORE_REG_D3 = 24
TRICORE_REG_D4 = 25
TRICORE_REG_D5 = 26
TRICORE_REG_D6 = 27
TRICORE_REG_D7 = 28
TRICORE_REG_D8 = 29
TRICORE_REG_D9 = 30
TRICORE_REG_D10 = 31
TRICORE_REG_D11 = 32
TRICORE_REG_D12 = 33
TRICORE_REG_D13 = 34
TRICORE_REG_D14 = 35
TRICORE_REG_D15 = 36
TRICORE_REG_E0 = 37
TRICORE_REG_E2 = 38
TRICORE_REG_E4 = 39
TRICORE_REG_E6 = 40
TRICORE_REG_E8 = 41
TRICORE_REG_E10 = 42
TRICORE_REG_E12 = 43
TRICORE_REG_E14 = 44
TRICORE_REG_P0 = 45
TRICORE_REG_P2 = 46
TRICORE_REG_P4 = 47
TRICORE_REG_P6 = 48
TRICORE_REG_P8 = 49
TRICORE_REG_P10 = 50
TRICORE_REG_P12 = 51
TRICORE_REG_P14 = 52
TRICORE_REG_A0_A1 = 53
TRICORE_REG_A2_A3 = 54
TRICORE_REG_A4_A5 = 55
TRICORE_REG_A6_A7 = 56
TRICORE_REG_A8_A9 = 57
TRICORE_REG_A10_A11 = 58
TRICORE_REG_A12_A13 = 59
TRICORE_REG_A14_A15 = 60
TRICORE_REG_ENDING = 61
TRICORE_INS_INVALID = 0
TRICORE_INS_XOR_T = 1
TRICORE_INS_ABSDIFS_B = 2
TRICORE_INS_ABSDIFS_H = 3
TRICORE_INS_ABSDIFS = 4
TRICORE_INS_ABSDIF_B = 5
TRICORE_INS_ABSDIF_H = 6
TRICORE_INS_ABSDIF = 7
TRICORE_INS_ABSS_B = 8
TRICORE_INS_ABSS_H = 9
TRICORE_INS_ABSS = 10
TRICORE_INS_ABS_B = 11
TRICORE_INS_ABS_H = 12
TRICORE_INS_ABS = 13
TRICORE_INS_ADDC = 14
TRICORE_INS_ADDIH_A = 15
TRICORE_INS_ADDIH = 16
TRICORE_INS_ADDI = 17
TRICORE_INS_ADDSC_AT = 18
TRICORE_INS_ADDSC_A = 19
TRICORE_INS_ADDS_BU = 20
TRICORE_INS_ADDS_B = 21
TRICORE_INS_ADDS_H = 22
TRICORE_INS_ADDS_HU = 23
TRICORE_INS_ADDS_U = 24
TRICORE_INS_ADDS = 25
TRICORE_INS_ADDX = 26
TRICORE_INS_ADD_A = 27
TRICORE_INS_ADD_B = 28
TRICORE_INS_ADD_F = 29
TRICORE_INS_ADD_H = 30
TRICORE_INS_ADD = 31
TRICORE_INS_ANDN_T = 32
TRICORE_INS_ANDN = 33
TRICORE_INS_AND_ANDN_T = 34
TRICORE_INS_AND_AND_T = 35
TRICORE_INS_AND_EQ = 36
TRICORE_INS_AND_GE_U = 37
TRICORE_INS_AND_GE = 38
TRICORE_INS_AND_LT_U = 39
TRICORE_INS_AND_LT = 40
TRICORE_INS_AND_NE = 41
TRICORE_INS_AND_NOR_T = 42
TRICORE_INS_AND_OR_T = 43
TRICORE_INS_AND_T = 44
TRICORE_INS_AND = 45
TRICORE_INS_BISR = 46
TRICORE_INS_BMERGE = 47
TRICORE_INS_BSPLIT = 48
TRICORE_INS_CACHEA_I = 49
TRICORE_INS_CACHEA_WI = 50
TRICORE_INS_CACHEA_W = 51
TRICORE_INS_CACHEI_I = 52
TRICORE_INS_CACHEI_WI = 53
TRICORE_INS_CACHEI_W = 54
TRICORE_INS_CADDN_A = 55
TRICORE_INS_CADDN = 56
TRICORE_INS_CADD_A = 57
TRICORE_INS_CADD = 58
TRICORE_INS_CALLA = 59
TRICORE_INS_CALLI = 60
TRICORE_INS_CALL = 61
TRICORE_INS_CLO_B = 62
TRICORE_INS_CLO_H = 63
TRICORE_INS_CLO = 64
TRICORE_INS_CLS_B = 65
TRICORE_INS_CLS_H = 66
TRICORE_INS_CLS = 67
TRICORE_INS_CLZ_B = 68
TRICORE_INS_CLZ_H = 69
TRICORE_INS_CLZ = 70
TRICORE_INS_CMOVN = 71
TRICORE_INS_CMOV = 72
TRICORE_INS_CMPSWAP_W = 73
TRICORE_INS_CMP_F = 74
TRICORE_INS_CRC32B_W = 75
TRICORE_INS_CRC32L_W = 76
TRICORE_INS_CRC32_B = 77
TRICORE_INS_CRCN = 78
TRICORE_INS_CSUBN_A = 79
TRICORE_INS_CSUBN = 80
TRICORE_INS_CSUB_A = 81
TRICORE_INS_CSUB = 82
TRICORE_INS_DEBUG = 83
TRICORE_INS_DEXTR = 84
TRICORE_INS_DIFSC_A = 85
TRICORE_INS_DISABLE = 86
TRICORE_INS_DIV_F = 87
TRICORE_INS_DIV_U = 88
TRICORE_INS_DIV = 89
TRICORE_INS_DSYNC = 90
TRICORE_INS_DVADJ = 91
TRICORE_INS_DVINIT_BU = 92
TRICORE_INS_DVINIT_B = 93
TRICORE_INS_DVINIT_HU = 94
TRICORE_INS_DVINIT_H = 95
TRICORE_INS_DVINIT_U = 96
TRICORE_INS_DVINIT = 97
TRICORE_INS_DVSTEP_U = 98
TRICORE_INS_DVSTEP = 99
TRICORE_INS_ENABLE = 100
TRICORE_INS_EQANY_B = 101
TRICORE_INS_EQANY_H = 102
TRICORE_INS_EQZ_A = 103
TRICORE_INS_EQ_A = 104
TRICORE_INS_EQ_B = 105
TRICORE_INS_EQ_H = 106
TRICORE_INS_EQ_W = 107
TRICORE_INS_EQ = 108
TRICORE_INS_EXTR_U = 109
TRICORE_INS_EXTR = 110
TRICORE_INS_FCALLA = 111
TRICORE_INS_FCALLI = 112
TRICORE_INS_FCALL = 113
TRICORE_INS_FRET = 114
TRICORE_INS_FTOHP = 115
TRICORE_INS_FTOIZ = 116
TRICORE_INS_FTOI = 117
TRICORE_INS_FTOQ31Z = 118
TRICORE_INS_FTOQ31 = 119
TRICORE_INS_FTOUZ = 120
TRICORE_INS_FTOU = 121
TRICORE_INS_GE_A = 122
TRICORE_INS_GE_U = 123
TRICORE_INS_GE = 124
TRICORE_INS_HPTOF = 125
TRICORE_INS_IMASK = 126
TRICORE_INS_INSERT = 127
TRICORE_INS_INSN_T = 128
TRICORE_INS_INS_T = 129
TRICORE_INS_ISYNC = 130
TRICORE_INS_ITOF = 131
TRICORE_INS_IXMAX_U = 132
TRICORE_INS_IXMAX = 133
TRICORE_INS_IXMIN_U = 134
TRICORE_INS_IXMIN = 135
TRICORE_INS_JA = 136
TRICORE_INS_JEQ_A = 137
TRICORE_INS_JEQ = 138
TRICORE_INS_JGEZ = 139
TRICORE_INS_JGE_U = 140
TRICORE_INS_JGE = 141
TRICORE_INS_JGTZ = 142
TRICORE_INS_JI = 143
TRICORE_INS_JLA = 144
TRICORE_INS_JLEZ = 145
TRICORE_INS_JLI = 146
TRICORE_INS_JLTZ = 147
TRICORE_INS_JLT_U = 148
TRICORE_INS_JLT = 149
TRICORE_INS_JL = 150
TRICORE_INS_JNED = 151
TRICORE_INS_JNEI = 152
TRICORE_INS_JNE_A = 153
TRICORE_INS_JNE = 154
TRICORE_INS_JNZ_A = 155
TRICORE_INS_JNZ_T = 156
TRICORE_INS_JNZ = 157
TRICORE_INS_JZ_A = 158
TRICORE_INS_JZ_T = 159
TRICORE_INS_JZ = 160
TRICORE_INS_J = 161
TRICORE_INS_LDLCX = 162
TRICORE_INS_LDMST = 163
TRICORE_INS_LDUCX = 164
TRICORE_INS_LD_A = 165
TRICORE_INS_LD_BU = 166
TRICORE_INS_LD_B = 167
TRICORE_INS_LD_DA = 168
TRICORE_INS_LD_D = 169
TRICORE_INS_LD_HU = 170
TRICORE_INS_LD_H = 171
TRICORE_INS_LD_Q = 172
TRICORE_INS_LD_W = 173
TRICORE_INS_LEA = 174
TRICORE_INS_LHA = 175
TRICORE_INS_LOOPU = 176
TRICORE_INS_LOOP = 177
TRICORE_INS_LT_A = 178
TRICORE_INS_LT_B = 179
TRICORE_INS_LT_BU = 180
TRICORE_INS_LT_H = 181
TRICORE_INS_LT_HU = 182
TRICORE_INS_LT_U = 183
TRICORE_INS_LT_W = 184
TRICORE_INS_LT_WU = 185
TRICORE_INS_LT = 186
TRICORE_INS_MADDMS_H = 187
TRICORE_INS_MADDMS_U = 188
TRICORE_INS_MADDMS = 189
TRICORE_INS_MADDM_H = 190
TRICORE_INS_MADDM_Q = 191
TRICORE_INS_MADDM_U = 192
TRICORE_INS_MADDM = 193
TRICORE_INS_MADDRS_H = 194
TRICORE_INS_MADDRS_Q = 195
TRICORE_INS_MADDR_H = 196
TRICORE_INS_MADDR_Q = 197
TRICORE_INS_MADDSUMS_H = 198
TRICORE_INS_MADDSUM_H = 199
TRICORE_INS_MADDSURS_H = 200
TRICORE_INS_MADDSUR_H = 201
TRICORE_INS_MADDSUS_H = 202
TRICORE_INS_MADDSU_H = 203
TRICORE_INS_MADDS_H = 204
TRICORE_INS_MADDS_Q = 205
TRICORE_INS_MADDS_U = 206
TRICORE_INS_MADDS = 207
TRICORE_INS_MADD_F = 208
TRICORE_INS_MADD_H = 209
TRICORE_INS_MADD_Q = 210
TRICORE_INS_MADD_U = 211
TRICORE_INS_MADD = 212
TRICORE_INS_MAX_B = 213
TRICORE_INS_MAX_BU = 214
TRICORE_INS_MAX_H = 215
TRICORE_INS_MAX_HU = 216
TRICORE_INS_MAX_U = 217
TRICORE_INS_MAX = 218
TRICORE_INS_MFCR = 219
TRICORE_INS_MIN_B = 220
TRICORE_INS_MIN_BU = 221
TRICORE_INS_MIN_H = 222
TRICORE_INS_MIN_HU = 223
TRICORE_INS_MIN_U = 224
TRICORE_INS_MIN = 225
TRICORE_INS_MOVH_A = 226
TRICORE_INS_MOVH = 227
TRICORE_INS_MOVZ_A = 228
TRICORE_INS_MOV_AA = 229
TRICORE_INS_MOV_A = 230
TRICORE_INS_MOV_D = 231
TRICORE_INS_MOV_U = 232
TRICORE_INS_MOV = 233
TRICORE_INS_MSUBADMS_H = 234
TRICORE_INS_MSUBADM_H = 235
TRICORE_INS_MSUBADRS_H = 236
TRICORE_INS_MSUBADR_H = 237
TRICORE_INS_MSUBADS_H = 238
TRICORE_INS_MSUBAD_H = 239
TRICORE_INS_MSUBMS_H = 240
TRICORE_INS_MSUBMS_U = 241
TRICORE_INS_MSUBMS = 242
TRICORE_INS_MSUBM_H = 243
TRICORE_INS_MSUBM_Q = 244
TRICORE_INS_MSUBM_U = 245
TRICORE_INS_MSUBM = 246
TRICORE_INS_MSUBRS_H = 247
TRICORE_INS_MSUBRS_Q = 248
TRICORE_INS_MSUBR_H = 249
TRICORE_INS_MSUBR_Q = 250
TRICORE_INS_MSUBS_H = 251
TRICORE_INS_MSUBS_Q = 252
TRICORE_INS_MSUBS_U = 253
TRICORE_INS_MSUBS = 254
TRICORE_INS_MSUB_F = 255
TRICORE_INS_MSUB_H = 256
TRICORE_INS_MSUB_Q = 257
TRICORE_INS_MSUB_U = 258
TRICORE_INS_MSUB = 259
TRICORE_INS_MTCR = 260
TRICORE_INS_MULMS_H = 261
TRICORE_INS_MULM_H = 262
TRICORE_INS_MULM_U = 263
TRICORE_INS_MULM = 264
TRICORE_INS_MULR_H = 265
TRICORE_INS_MULR_Q = 266
TRICORE_INS_MULS_U = 267
TRICORE_INS_MULS = 268
TRICORE_INS_MUL_F = 269
TRICORE_INS_MUL_H = 270
TRICORE_INS_MUL_Q = 271
TRICORE_INS_MUL_U = 272
TRICORE_INS_MUL = 273
TRICORE_INS_NAND_T = 274
TRICORE_INS_NAND = 275
TRICORE_INS_NEZ_A = 276
TRICORE_INS_NE_A = 277
TRICORE_INS_NE = 278
TRICORE_INS_NOP = 279
TRICORE_INS_NOR_T = 280
TRICORE_INS_NOR = 281
TRICORE_INS_NOT = 282
TRICORE_INS_ORN_T = 283
TRICORE_INS_ORN = 284
TRICORE_INS_OR_ANDN_T = 285
TRICORE_INS_OR_AND_T = 286
TRICORE_INS_OR_EQ = 287
TRICORE_INS_OR_GE_U = 288
TRICORE_INS_OR_GE = 289
TRICORE_INS_OR_LT_U = 290
TRICORE_INS_OR_LT = 291
TRICORE_INS_OR_NE = 292
TRICORE_INS_OR_NOR_T = 293
TRICORE_INS_OR_OR_T = 294
TRICORE_INS_OR_T = 295
TRICORE_INS_OR = 296
TRICORE_INS_PACK = 297
TRICORE_INS_PARITY = 298
TRICORE_INS_POPCNT_W = 299
TRICORE_INS_Q31TOF = 300
TRICORE_INS_QSEED_F = 301
TRICORE_INS_RESTORE = 302
TRICORE_INS_RET = 303
TRICORE_INS_RFE = 304
TRICORE_INS_RFM = 305
TRICORE_INS_RSLCX = 306
TRICORE_INS_RSTV = 307
TRICORE_INS_RSUBS_U = 308
TRICORE_INS_RSUBS = 309
TRICORE_INS_RSUB = 310
TRICORE_INS_SAT_BU = 311
TRICORE_INS_SAT_B = 312
TRICORE_INS_SAT_HU = 313
TRICORE_INS_SAT_H = 314
TRICORE_INS_SELN_A = 315
TRICORE_INS_SELN = 316
TRICORE_INS_SEL_A = 317
TRICORE_INS_SEL = 318
TRICORE_INS_SHAS = 319
TRICORE_INS_SHA_B = 320
TRICORE_INS_SHA_H = 321
TRICORE_INS_SHA = 322
TRICORE_INS_SHUFFLE = 323
TRICORE_INS_SH_ANDN_T = 324
TRICORE_INS_SH_AND_T = 325
TRICORE_INS_SH_B = 326
TRICORE_INS_SH_EQ = 327
TRICORE_INS_SH_GE_U = 328
TRICORE_INS_SH_GE = 329
TRICORE_INS_SH_H = 330
TRICORE_INS_SH_LT_U = 331
TRICORE_INS_SH_LT = 332
TRICORE_INS_SH_NAND_T = 333
TRICORE_INS_SH_NE = 334
TRICORE_INS_SH_NOR_T = 335
TRICORE_INS_SH_ORN_T = 336
TRICORE_INS_SH_OR_T = 337
TRICORE_INS_SH_XNOR_T = 338
TRICORE_INS_SH_XOR_T = 339
TRICORE_INS_SH = 340
TRICORE_INS_STLCX = 341
TRICORE_INS_STUCX = 342
TRICORE_INS_ST_A = 343
TRICORE_INS_ST_B = 344
TRICORE_INS_ST_DA = 345
TRICORE_INS_ST_D = 346
TRICORE_INS_ST_H = 347
TRICORE_INS_ST_Q = 348
TRICORE_INS_ST_T = 349
TRICORE_INS_ST_W = 350
TRICORE_INS_SUBC = 351
TRICORE_INS_SUBSC_A = 352
TRICORE_INS_SUBS_BU = 353
TRICORE_INS_SUBS_B = 354
TRICORE_INS_SUBS_HU = 355
TRICORE_INS_SUBS_H = 356
TRICORE_INS_SUBS_U = 357
TRICORE_INS_SUBS = 358
TRICORE_INS_SUBX = 359
TRICORE_INS_SUB_A = 360
TRICORE_INS_SUB_B = 361
TRICORE_INS_SUB_F = 362
TRICORE_INS_SUB_H = 363
TRICORE_INS_SUB = 364
TRICORE_INS_SVLCX = 365
TRICORE_INS_SWAPMSK_W = 366
TRICORE_INS_SWAP_A = 367
TRICORE_INS_SWAP_W = 368
TRICORE_INS_SYSCALL = 369
TRICORE_INS_TLBDEMAP = 370
TRICORE_INS_TLBFLUSH_A = 371
TRICORE_INS_TLBFLUSH_B = 372
TRICORE_INS_TLBMAP = 373
TRICORE_INS_TLBPROBE_A = 374
TRICORE_INS_TLBPROBE_I = 375
TRICORE_INS_TRAPSV = 376
TRICORE_INS_TRAPV = 377
TRICORE_INS_UNPACK = 378
TRICORE_INS_UPDFL = 379
TRICORE_INS_UTOF = 380
TRICORE_INS_WAIT = 381
TRICORE_INS_XNOR_T = 382
TRICORE_INS_XNOR = 383
TRICORE_INS_XOR_EQ = 384
TRICORE_INS_XOR_GE_U = 385
TRICORE_INS_XOR_GE = 386
TRICORE_INS_XOR_LT_U = 387
TRICORE_INS_XOR_LT = 388
TRICORE_INS_XOR_NE = 389
TRICORE_INS_XOR = 390
TRICORE_INS_ENDING = 391
TRICORE_GRP_INVALID = 0
TRICORE_GRP_CALL = 1
TRICORE_GRP_JUMP = 2
TRICORE_GRP_ENDING = 3
TRICORE_FEATURE_INVALID = 0
TRICORE_FEATURE_HasV110 = 128
TRICORE_FEATURE_HasV120_UP = 129
TRICORE_FEATURE_HasV130_UP = 130
TRICORE_FEATURE_HasV161 = 131
TRICORE_FEATURE_HasV160_UP = 132
TRICORE_FEATURE_HasV131_UP = 133
TRICORE_FEATURE_HasV161_UP = 134
TRICORE_FEATURE_HasV162 = 135
TRICORE_FEATURE_HasV162_UP = 136
TRICORE_FEATURE_ENDING = 137

71
thirdparty/capstone/bindings/python/capstone/wasm.py vendored Normal file
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# Capstone Python bindings, by Peace-Maker <peacemakerctf@gmail.com>
import ctypes
from . import copy_ctypes_list
from .wasm_const import *
# define the API
class WASMBrTable(ctypes.Structure):
_fields_ = (
('length', ctypes.c_uint32),
('address', ctypes.c_uint64),
('default_target', ctypes.c_uint32),
)
class WASMOpValue(ctypes.Union):
_fields_ = (
('int7', ctypes.c_int8),
('varuint32', ctypes.c_uint32),
('varuint64', ctypes.c_uint64),
('uint32', ctypes.c_uint32),
('uint64', ctypes.c_uint64),
('immediate', ctypes.c_uint32 * 2),
('brtable', WASMBrTable),
)
class WASMOp(ctypes.Structure):
_fields_ = (
('type', ctypes.c_uint),
('size', ctypes.c_uint32),
('value', WASMOpValue),
)
@property
def int7(self):
return self.value.int7
@property
def varuint32(self):
return self.value.varuint32
@property
def varuint64(self):
return self.value.varuint64
@property
def uint32(self):
return self.value.uint32
@property
def uint64(self):
return self.value.uint64
@property
def immediate(self):
return self.value.immediate
@property
def brtable(self):
return self.value.brtable
class CsWasm(ctypes.Structure):
_fields_ = (
('op_count', ctypes.c_uint8),
('operands', WASMOp * 2),
)
def get_arch_info(a):
return (copy_ctypes_list(a.operands[:a.op_count]))

192
thirdparty/capstone/bindings/python/capstone/wasm_const.py vendored Normal file
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from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [wasm_const.py]
WASM_OP_INVALID = 0
WASM_OP_NONE = 1
WASM_OP_INT7 = 2
WASM_OP_VARUINT32 = 3
WASM_OP_VARUINT64 = 4
WASM_OP_UINT32 = 5
WASM_OP_UINT64 = 6
WASM_OP_IMM = 7
WASM_OP_BRTABLE = 8
WASM_INS_UNREACHABLE = 0x0
WASM_INS_NOP = 0x1
WASM_INS_BLOCK = 0x2
WASM_INS_LOOP = 0x3
WASM_INS_IF = 0x4
WASM_INS_ELSE = 0x5
WASM_INS_END = 0xb
WASM_INS_BR = 0xc
WASM_INS_BR_IF = 0xd
WASM_INS_BR_TABLE = 0xe
WASM_INS_RETURN = 0xf
WASM_INS_CALL = 0x10
WASM_INS_CALL_INDIRECT = 0x11
WASM_INS_DROP = 0x1a
WASM_INS_SELECT = 0x1b
WASM_INS_GET_LOCAL = 0x20
WASM_INS_SET_LOCAL = 0x21
WASM_INS_TEE_LOCAL = 0x22
WASM_INS_GET_GLOBAL = 0x23
WASM_INS_SET_GLOBAL = 0x24
WASM_INS_I32_LOAD = 0x28
WASM_INS_I64_LOAD = 0x29
WASM_INS_F32_LOAD = 0x2a
WASM_INS_F64_LOAD = 0x2b
WASM_INS_I32_LOAD8_S = 0x2c
WASM_INS_I32_LOAD8_U = 0x2d
WASM_INS_I32_LOAD16_S = 0x2e
WASM_INS_I32_LOAD16_U = 0x2f
WASM_INS_I64_LOAD8_S = 0x30
WASM_INS_I64_LOAD8_U = 0x31
WASM_INS_I64_LOAD16_S = 0x32
WASM_INS_I64_LOAD16_U = 0x33
WASM_INS_I64_LOAD32_S = 0x34
WASM_INS_I64_LOAD32_U = 0x35
WASM_INS_I32_STORE = 0x36
WASM_INS_I64_STORE = 0x37
WASM_INS_F32_STORE = 0x38
WASM_INS_F64_STORE = 0x39
WASM_INS_I32_STORE8 = 0x3a
WASM_INS_I32_STORE16 = 0x3b
WASM_INS_I64_STORE8 = 0x3c
WASM_INS_I64_STORE16 = 0x3d
WASM_INS_I64_STORE32 = 0x3e
WASM_INS_CURRENT_MEMORY = 0x3f
WASM_INS_GROW_MEMORY = 0x40
WASM_INS_I32_CONST = 0x41
WASM_INS_I64_CONST = 0x42
WASM_INS_F32_CONST = 0x43
WASM_INS_F64_CONST = 0x44
WASM_INS_I32_EQZ = 0x45
WASM_INS_I32_EQ = 0x46
WASM_INS_I32_NE = 0x47
WASM_INS_I32_LT_S = 0x48
WASM_INS_I32_LT_U = 0x49
WASM_INS_I32_GT_S = 0x4a
WASM_INS_I32_GT_U = 0x4b
WASM_INS_I32_LE_S = 0x4c
WASM_INS_I32_LE_U = 0x4d
WASM_INS_I32_GE_S = 0x4e
WASM_INS_I32_GE_U = 0x4f
WASM_INS_I64_EQZ = 0x50
WASM_INS_I64_EQ = 0x51
WASM_INS_I64_NE = 0x52
WASM_INS_I64_LT_S = 0x53
WASM_INS_I64_LT_U = 0x54
WASM_INS_I64_GT_U = 0x56
WASM_INS_I64_LE_S = 0x57
WASM_INS_I64_LE_U = 0x58
WASM_INS_I64_GE_S = 0x59
WASM_INS_I64_GE_U = 0x5a
WASM_INS_F32_EQ = 0x5b
WASM_INS_F32_NE = 0x5c
WASM_INS_F32_LT = 0x5d
WASM_INS_F32_GT = 0x5e
WASM_INS_F32_LE = 0x5f
WASM_INS_F32_GE = 0x60
WASM_INS_F64_EQ = 0x61
WASM_INS_F64_NE = 0x62
WASM_INS_F64_LT = 0x63
WASM_INS_F64_GT = 0x64
WASM_INS_F64_LE = 0x65
WASM_INS_F64_GE = 0x66
WASM_INS_I32_CLZ = 0x67
WASM_INS_I32_CTZ = 0x68
WASM_INS_I32_POPCNT = 0x69
WASM_INS_I32_ADD = 0x6a
WASM_INS_I32_SUB = 0x6b
WASM_INS_I32_MUL = 0x6c
WASM_INS_I32_DIV_S = 0x6d
WASM_INS_I32_DIV_U = 0x6e
WASM_INS_I32_REM_S = 0x6f
WASM_INS_I32_REM_U = 0x70
WASM_INS_I32_AND = 0x71
WASM_INS_I32_OR = 0x72
WASM_INS_I32_XOR = 0x73
WASM_INS_I32_SHL = 0x74
WASM_INS_I32_SHR_S = 0x75
WASM_INS_I32_SHR_U = 0x76
WASM_INS_I32_ROTL = 0x77
WASM_INS_I32_ROTR = 0x78
WASM_INS_I64_CLZ = 0x79
WASM_INS_I64_CTZ = 0x7a
WASM_INS_I64_POPCNT = 0x7b
WASM_INS_I64_ADD = 0x7c
WASM_INS_I64_SUB = 0x7d
WASM_INS_I64_MUL = 0x7e
WASM_INS_I64_DIV_S = 0x7f
WASM_INS_I64_DIV_U = 0x80
WASM_INS_I64_REM_S = 0x81
WASM_INS_I64_REM_U = 0x82
WASM_INS_I64_AND = 0x83
WASM_INS_I64_OR = 0x84
WASM_INS_I64_XOR = 0x85
WASM_INS_I64_SHL = 0x86
WASM_INS_I64_SHR_S = 0x87
WASM_INS_I64_SHR_U = 0x88
WASM_INS_I64_ROTL = 0x89
WASM_INS_I64_ROTR = 0x8a
WASM_INS_F32_ABS = 0x8b
WASM_INS_F32_NEG = 0x8c
WASM_INS_F32_CEIL = 0x8d
WASM_INS_F32_FLOOR = 0x8e
WASM_INS_F32_TRUNC = 0x8f
WASM_INS_F32_NEAREST = 0x90
WASM_INS_F32_SQRT = 0x91
WASM_INS_F32_ADD = 0x92
WASM_INS_F32_SUB = 0x93
WASM_INS_F32_MUL = 0x94
WASM_INS_F32_DIV = 0x95
WASM_INS_F32_MIN = 0x96
WASM_INS_F32_MAX = 0x97
WASM_INS_F32_COPYSIGN = 0x98
WASM_INS_F64_ABS = 0x99
WASM_INS_F64_NEG = 0x9a
WASM_INS_F64_CEIL = 0x9b
WASM_INS_F64_FLOOR = 0x9c
WASM_INS_F64_TRUNC = 0x9d
WASM_INS_F64_NEAREST = 0x9e
WASM_INS_F64_SQRT = 0x9f
WASM_INS_F64_ADD = 0xa0
WASM_INS_F64_SUB = 0xa1
WASM_INS_F64_MUL = 0xa2
WASM_INS_F64_DIV = 0xa3
WASM_INS_F64_MIN = 0xa4
WASM_INS_F64_MAX = 0xa5
WASM_INS_F64_COPYSIGN = 0xa6
WASM_INS_I32_WARP_I64 = 0xa7
WASM_INS_I32_TRUNC_U_F32 = 0xa9
WASM_INS_I32_TRUNC_S_F64 = 0xaa
WASM_INS_I32_TRUNC_U_F64 = 0xab
WASM_INS_I64_EXTEND_S_I32 = 0xac
WASM_INS_I64_EXTEND_U_I32 = 0xad
WASM_INS_I64_TRUNC_S_F32 = 0xae
WASM_INS_I64_TRUNC_U_F32 = 0xaf
WASM_INS_I64_TRUNC_S_F64 = 0xb0
WASM_INS_I64_TRUNC_U_F64 = 0xb1
WASM_INS_F32_CONVERT_S_I32 = 0xb2
WASM_INS_F32_CONVERT_U_I32 = 0xb3
WASM_INS_F32_CONVERT_S_I64 = 0xb4
WASM_INS_F32_CONVERT_U_I64 = 0xb5
WASM_INS_F32_DEMOTE_F64 = 0xb6
WASM_INS_F64_CONVERT_S_I32 = 0xb7
WASM_INS_F64_CONVERT_U_I32 = 0xb8
WASM_INS_F64_CONVERT_S_I64 = 0xb9
WASM_INS_F64_CONVERT_U_I64 = 0xba
WASM_INS_F64_PROMOTE_F32 = 0xbb
WASM_INS_I32_REINTERPRET_F32 = 0xbc
WASM_INS_I64_REINTERPRET_F64 = 0xbd
WASM_INS_F32_REINTERPRET_I32 = 0xbe
WASM_INS_F64_REINTERPRET_I64 = 0xbf
WASM_INS_INVALID = 512
WASM_INS_ENDING = 513
WASM_GRP_INVALID = 0
WASM_GRP_NUMBERIC = 8
WASM_GRP_PARAMETRIC = 9
WASM_GRP_VARIABLE = 10
WASM_GRP_MEMORY = 11
WASM_GRP_CONTROL = 12
WASM_GRP_ENDING = 13

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thirdparty/capstone/bindings/python/capstone/x86.py vendored Normal file
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# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
import ctypes
from . import copy_ctypes_list
from .x86_const import *
# define the API
class X86OpMem(ctypes.Structure):
_fields_ = (
('segment', ctypes.c_uint),
('base', ctypes.c_uint),
('index', ctypes.c_uint),
('scale', ctypes.c_int),
('disp', ctypes.c_int64),
)
class X86OpValue(ctypes.Union):
_fields_ = (
('reg', ctypes.c_uint),
('imm', ctypes.c_int64),
('mem', X86OpMem),
)
class X86Op(ctypes.Structure):
_fields_ = (
('type', ctypes.c_uint),
('value', X86OpValue),
('size', ctypes.c_uint8),
('access', ctypes.c_uint8),
('avx_bcast', ctypes.c_uint),
('avx_zero_opmask', ctypes.c_bool),
)
@property
def imm(self):
return self.value.imm
@property
def reg(self):
return self.value.reg
@property
def mem(self):
return self.value.mem
class X86Flags(ctypes.Union):
_fields_ = (
('eflags', ctypes.c_uint64),
('fpu_flags', ctypes.c_uint64),
)
class CsX86Encoding(ctypes.Structure):
_fields_ = (
('modrm_offset', ctypes.c_uint8),
('disp_offset', ctypes.c_uint8),
('disp_size', ctypes.c_uint8),
('imm_offset', ctypes.c_uint8),
('imm_size', ctypes.c_uint8),
)
class CsX86(ctypes.Structure):
_fields_ = (
('prefix', ctypes.c_uint8 * 4),
('opcode', ctypes.c_uint8 * 4),
('rex', ctypes.c_uint8),
('addr_size', ctypes.c_uint8),
('modrm', ctypes.c_uint8),
('sib', ctypes.c_uint8),
('disp', ctypes.c_int64),
('sib_index', ctypes.c_uint),
('sib_scale', ctypes.c_int8),
('sib_base', ctypes.c_uint),
('xop_cc', ctypes.c_uint),
('sse_cc', ctypes.c_uint),
('avx_cc', ctypes.c_uint),
('avx_sae', ctypes.c_bool),
('avx_rm', ctypes.c_uint),
('flags', X86Flags),
('op_count', ctypes.c_uint8),
('operands', X86Op * 8),
('encoding', CsX86Encoding),
)
@property
def eflags(self):
return self.flags.eflags
@property
def fpu_flags(self):
return self.flags.fpu_flags
def get_arch_info(a):
return (a.prefix[:], a.opcode[:], a.rex, a.addr_size, \
a.modrm, a.sib, a.disp, a.sib_index, a.sib_scale, \
a.sib_base, a.xop_cc, a.sse_cc, a.avx_cc, a.avx_sae, a.avx_rm, a.eflags, a.fpu_flags, \
a.encoding, a.encoding.modrm_offset, a.encoding.disp_offset, a.encoding.disp_size, a.encoding.imm_offset, a.encoding.imm_size, \
copy_ctypes_list(a.operands[:a.op_count]))

1991
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50
thirdparty/capstone/bindings/python/capstone/xcore.py vendored Normal file
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# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
import ctypes
from . import copy_ctypes_list
from .xcore_const import *
# define the API
class XcoreOpMem(ctypes.Structure):
_fields_ = (
('base', ctypes.c_uint8),
('index', ctypes.c_uint8),
('disp', ctypes.c_int32),
('direct', ctypes.c_int),
)
class XcoreOpValue(ctypes.Union):
_fields_ = (
('reg', ctypes.c_uint),
('imm', ctypes.c_int32),
('mem', XcoreOpMem),
)
class XcoreOp(ctypes.Structure):
_fields_ = (
('type', ctypes.c_uint),
('value', XcoreOpValue),
)
@property
def imm(self):
return self.value.imm
@property
def reg(self):
return self.value.reg
@property
def mem(self):
return self.value.mem
class CsXcore(ctypes.Structure):
_fields_ = (
('op_count', ctypes.c_uint8),
('operands', XcoreOp * 8),
)
def get_arch_info(a):
return (copy_ctypes_list(a.operands[:a.op_count]))

162
thirdparty/capstone/bindings/python/capstone/xcore_const.py vendored Normal file
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from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [xcore_const.py]
XCORE_OP_INVALID = 0
XCORE_OP_REG = 1
XCORE_OP_IMM = 2
XCORE_OP_MEM = 3
XCORE_REG_INVALID = 0
XCORE_REG_CP = 1
XCORE_REG_DP = 2
XCORE_REG_LR = 3
XCORE_REG_SP = 4
XCORE_REG_R0 = 5
XCORE_REG_R1 = 6
XCORE_REG_R2 = 7
XCORE_REG_R3 = 8
XCORE_REG_R4 = 9
XCORE_REG_R5 = 10
XCORE_REG_R6 = 11
XCORE_REG_R7 = 12
XCORE_REG_R8 = 13
XCORE_REG_R9 = 14
XCORE_REG_R10 = 15
XCORE_REG_R11 = 16
XCORE_REG_PC = 17
XCORE_REG_SCP = 18
XCORE_REG_SSR = 19
XCORE_REG_ET = 20
XCORE_REG_ED = 21
XCORE_REG_SED = 22
XCORE_REG_KEP = 23
XCORE_REG_KSP = 24
XCORE_REG_ID = 25
XCORE_REG_ENDING = 26
XCORE_INS_INVALID = 0
XCORE_INS_ADD = 1
XCORE_INS_ANDNOT = 2
XCORE_INS_AND = 3
XCORE_INS_ASHR = 4
XCORE_INS_BAU = 5
XCORE_INS_BITREV = 6
XCORE_INS_BLA = 7
XCORE_INS_BLAT = 8
XCORE_INS_BL = 9
XCORE_INS_BF = 10
XCORE_INS_BT = 11
XCORE_INS_BU = 12
XCORE_INS_BRU = 13
XCORE_INS_BYTEREV = 14
XCORE_INS_CHKCT = 15
XCORE_INS_CLRE = 16
XCORE_INS_CLRPT = 17
XCORE_INS_CLRSR = 18
XCORE_INS_CLZ = 19
XCORE_INS_CRC8 = 20
XCORE_INS_CRC32 = 21
XCORE_INS_DCALL = 22
XCORE_INS_DENTSP = 23
XCORE_INS_DGETREG = 24
XCORE_INS_DIVS = 25
XCORE_INS_DIVU = 26
XCORE_INS_DRESTSP = 27
XCORE_INS_DRET = 28
XCORE_INS_ECALLF = 29
XCORE_INS_ECALLT = 30
XCORE_INS_EDU = 31
XCORE_INS_EEF = 32
XCORE_INS_EET = 33
XCORE_INS_EEU = 34
XCORE_INS_ENDIN = 35
XCORE_INS_ENTSP = 36
XCORE_INS_EQ = 37
XCORE_INS_EXTDP = 38
XCORE_INS_EXTSP = 39
XCORE_INS_FREER = 40
XCORE_INS_FREET = 41
XCORE_INS_GETD = 42
XCORE_INS_GET = 43
XCORE_INS_GETN = 44
XCORE_INS_GETR = 45
XCORE_INS_GETSR = 46
XCORE_INS_GETST = 47
XCORE_INS_GETTS = 48
XCORE_INS_INCT = 49
XCORE_INS_INIT = 50
XCORE_INS_INPW = 51
XCORE_INS_INSHR = 52
XCORE_INS_INT = 53
XCORE_INS_IN = 54
XCORE_INS_KCALL = 55
XCORE_INS_KENTSP = 56
XCORE_INS_KRESTSP = 57
XCORE_INS_KRET = 58
XCORE_INS_LADD = 59
XCORE_INS_LD16S = 60
XCORE_INS_LD8U = 61
XCORE_INS_LDA16 = 62
XCORE_INS_LDAP = 63
XCORE_INS_LDAW = 64
XCORE_INS_LDC = 65
XCORE_INS_LDW = 66
XCORE_INS_LDIVU = 67
XCORE_INS_LMUL = 68
XCORE_INS_LSS = 69
XCORE_INS_LSUB = 70
XCORE_INS_LSU = 71
XCORE_INS_MACCS = 72
XCORE_INS_MACCU = 73
XCORE_INS_MJOIN = 74
XCORE_INS_MKMSK = 75
XCORE_INS_MSYNC = 76
XCORE_INS_MUL = 77
XCORE_INS_NEG = 78
XCORE_INS_NOT = 79
XCORE_INS_OR = 80
XCORE_INS_OUTCT = 81
XCORE_INS_OUTPW = 82
XCORE_INS_OUTSHR = 83
XCORE_INS_OUTT = 84
XCORE_INS_OUT = 85
XCORE_INS_PEEK = 86
XCORE_INS_REMS = 87
XCORE_INS_REMU = 88
XCORE_INS_RETSP = 89
XCORE_INS_SETCLK = 90
XCORE_INS_SET = 91
XCORE_INS_SETC = 92
XCORE_INS_SETD = 93
XCORE_INS_SETEV = 94
XCORE_INS_SETN = 95
XCORE_INS_SETPSC = 96
XCORE_INS_SETPT = 97
XCORE_INS_SETRDY = 98
XCORE_INS_SETSR = 99
XCORE_INS_SETTW = 100
XCORE_INS_SETV = 101
XCORE_INS_SEXT = 102
XCORE_INS_SHL = 103
XCORE_INS_SHR = 104
XCORE_INS_SSYNC = 105
XCORE_INS_ST16 = 106
XCORE_INS_ST8 = 107
XCORE_INS_STW = 108
XCORE_INS_SUB = 109
XCORE_INS_SYNCR = 110
XCORE_INS_TESTCT = 111
XCORE_INS_TESTLCL = 112
XCORE_INS_TESTWCT = 113
XCORE_INS_TSETMR = 114
XCORE_INS_START = 115
XCORE_INS_WAITEF = 116
XCORE_INS_WAITET = 117
XCORE_INS_WAITEU = 118
XCORE_INS_XOR = 119
XCORE_INS_ZEXT = 120
XCORE_INS_ENDING = 121
XCORE_GRP_INVALID = 0
XCORE_GRP_JUMP = 1
XCORE_GRP_ENDING = 2

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## Python cstest
This is the equivalent testing tool to `suite/cstest/`. It consumes the `yaml` test files
in `<repo-root>/tests/` and reports the results.

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# Copyright © 2024 Rot127 <unisono@quyllur.org>
# SPDX-License-Identifier: BSD-3
[project]
name = "cstest_py"
version = "0.1.0"
dependencies = [
"pyyaml >= 6.0.2",
"capstone >= 5.0.0",
]
requires-python = ">= 3.8"
[tool.setuptools]
packages = ["cstest_py"]
package-dir = {"" = "src"}
[project.scripts]
cstest_py = "cstest_py.cstest:main"

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# Copyright © 2024 Rot127 <unisono@quyllur.org>
# SPDX-License-Identifier: BSD-3
# Typing for Python3.8
from __future__ import annotations
import struct
import capstone
import re
from capstone import arm_const
from capstone import aarch64_const
from capstone import m68k_const
from capstone import mips_const
from capstone import ppc_const
from capstone import sparc_const
from capstone import sysz_const
from capstone import x86_const
from capstone import xcore_const
from capstone import tms320c64x_const
from capstone import m680x_const
from capstone import evm_const
from capstone import mos65xx_const
from capstone import wasm_const
from capstone import bpf_const
from capstone import riscv_const
from capstone import sh_const
from capstone import tricore_const
from capstone import alpha_const
from capstone import hppa_const
from capstone import loongarch_const
def cs_const_getattr(identifier: str):
attr = getattr(capstone, identifier, None)
if attr is not None:
return attr
attr = getattr(arm_const, identifier, None)
if attr is not None:
return attr
attr = getattr(aarch64_const, identifier, None)
if attr is not None:
return attr
attr = getattr(m68k_const, identifier, None)
if attr is not None:
return attr
attr = getattr(mips_const, identifier, None)
if attr is not None:
return attr
attr = getattr(ppc_const, identifier, None)
if attr is not None:
return attr
attr = getattr(sparc_const, identifier, None)
if attr is not None:
return attr
attr = getattr(sysz_const, identifier, None)
if attr is not None:
return attr
attr = getattr(x86_const, identifier, None)
if attr is not None:
return attr
attr = getattr(xcore_const, identifier, None)
if attr is not None:
return attr
attr = getattr(tms320c64x_const, identifier, None)
if attr is not None:
return attr
attr = getattr(m680x_const, identifier, None)
if attr is not None:
return attr
attr = getattr(evm_const, identifier, None)
if attr is not None:
return attr
attr = getattr(mos65xx_const, identifier, None)
if attr is not None:
return attr
attr = getattr(wasm_const, identifier, None)
if attr is not None:
return attr
attr = getattr(bpf_const, identifier, None)
if attr is not None:
return attr
attr = getattr(riscv_const, identifier, None)
if attr is not None:
return attr
attr = getattr(sh_const, identifier, None)
if attr is not None:
return attr
attr = getattr(tricore_const, identifier, None)
if attr is not None:
return attr
attr = getattr(alpha_const, identifier, None)
if attr is not None:
return attr
attr = getattr(hppa_const, identifier, None)
if attr is not None:
return attr
attr = getattr(loongarch_const, identifier, None)
if attr is not None:
return attr
raise ValueError(f"Python capstone doesn't have the constant: {identifier}")
def twos_complement(val, bits):
if (val & (1 << (bits - 1))) != 0:
val = val - (1 << bits)
return val & ((1 << bits) - 1)
def normalize_asm_text(text: str, arch_bits: int) -> str:
text = text.strip()
text = re.sub(r"\s+", " ", text)
# Replace hex numbers with decimals
for hex_num in re.findall(r"0x[0-9a-fA-F]+", text):
text = re.sub(hex_num, f"{int(hex_num, base=16)}", text, count=1)
# Replace negatives with twos-complement
for num in re.findall(r"-\d+", text):
n = twos_complement(int(num, base=10), arch_bits)
text = re.sub(num, f"{n}", text)
text = text.lower()
return text
def compare_asm_text(
a_insn: capstone.CsInsn, expected: None | str, arch_bits: int
) -> bool:
if expected is None:
return True
from cstest_py.cstest import log
actual = f"{a_insn.mnemonic} {a_insn.op_str}"
actual = normalize_asm_text(actual, arch_bits)
expected = normalize_asm_text(expected, arch_bits)
if actual != expected:
log.error(
"Normalized asm-text doesn't match:\n"
f"decoded: '{actual}'\n"
f"expected: '{expected}'\n"
)
return False
return True
def compare_str(actual: str, expected: None | str, msg: str) -> bool:
if expected is None:
return True
from cstest_py.cstest import log
if actual != expected:
log.error(f"{msg}: {actual} != {expected}")
return False
return True
def compare_tbool(actual: bool, expected: None | int, msg: str) -> bool:
if expected is None:
return True
from cstest_py.cstest import log
if expected == 0:
# Unset
return True
if (expected < 0 and actual) or (expected > 0 and not actual):
log.error(f"{msg}: {actual} != {expected}")
return False
return True
def compare_uint8(actual: int, expected: None | int, msg: str) -> bool:
if expected is None:
return True
from cstest_py.cstest import log
actual = actual & 0xFF
expected = expected & 0xFF
if actual != expected:
log.error(f"{msg}: {actual} != {expected}")
return False
return True
def compare_int8(actual: int, expected: None | int, msg: str) -> bool:
if expected is None:
return True
from cstest_py.cstest import log
actual = actual & 0xFF
expected = expected & 0xFF
if actual != expected:
log.error(f"{msg}: {actual} != {expected}")
return False
return True
def compare_uint16(actual: int, expected: None | int, msg: str) -> bool:
if expected is None:
return True
from cstest_py.cstest import log
actual = actual & 0xFFFF
expected = expected & 0xFFFF
if actual != expected:
log.error(f"{msg}: {actual} != {expected}")
return False
return True
def compare_int16(actual: int, expected: None | int, msg: str) -> bool:
if expected is None:
return True
from cstest_py.cstest import log
actual = actual & 0xFFFF
expected = expected & 0xFFFF
if actual != expected:
log.error(f"{msg}: {actual} != {expected}")
return False
return True
def compare_uint32(actual: int, expected: None | int, msg: str) -> bool:
if expected is None:
return True
from cstest_py.cstest import log
actual = actual & 0xFFFFFFFF
expected = expected & 0xFFFFFFFF
if actual != expected:
log.error(f"{msg}: {actual} != {expected}")
return False
return True
def compare_int32(actual: int, expected: None | int, msg: str) -> bool:
if expected is None:
return True
from cstest_py.cstest import log
actual = actual & 0xFFFFFFFF
expected = expected & 0xFFFFFFFF
if actual != expected:
log.error(f"{msg}: {actual} != {expected}")
return False
return True
def compare_uint64(actual: int, expected: None | int, msg: str) -> bool:
if expected is None:
return True
from cstest_py.cstest import log
actual = actual & 0xFFFFFFFFFFFFFFFF
expected = expected & 0xFFFFFFFFFFFFFFFF
if actual != expected:
log.error(f"{msg}: {actual} != {expected}")
return False
return True
def compare_int64(actual: int, expected: None | int, msg: str) -> bool:
if expected is None:
return True
from cstest_py.cstest import log
actual = actual & 0xFFFFFFFFFFFFFFFF
expected = expected & 0xFFFFFFFFFFFFFFFF
if actual != expected:
log.error(f"{msg}: {actual} != {expected}")
return False
return True
def compare_fp(actual: float, expected: None | float, msg: str) -> bool:
if expected is None:
return True
from cstest_py.cstest import log
def floatToBits(f):
return struct.unpack("=L", struct.pack("=f", f))[0]
if floatToBits(actual) != floatToBits(expected):
log.error(f"{msg}: {actual} != {expected}")
return False
return True
def compare_dp(actual: float, expected: None | float, msg: str) -> bool:
if expected is None:
return True
from cstest_py.cstest import log
def doubleToBits(f):
return struct.unpack("=Q", struct.pack("=d", f))[0]
if doubleToBits(actual) != doubleToBits(expected):
log.error(f"{msg}: {actual} != {expected}")
return False
return True
def compare_enum(actual, expected: None | str, msg: str) -> bool:
if expected is None:
return True
from cstest_py.cstest import log
enum_val = cs_const_getattr(expected)
if actual != enum_val:
log.error(f"{msg}: {actual} != {expected} ({enum_val})")
return False
return True
def compare_bit_flags(actual: int, expected: None | list[str], msg: str) -> bool:
if expected is None:
return True
from cstest_py.cstest import log
for flag in expected:
enum_val = cs_const_getattr(flag)
if not actual & enum_val:
log.error(f"{msg}: In {actual:x} the flag {expected} isn't set.")
return False
return True
def compare_reg(
insn: capstone.CsInsn, actual: int, expected: None | str, msg: str
) -> bool:
if expected is None:
return True
from cstest_py.cstest import log
if insn.reg_name(actual) != expected:
log.error(f"{msg}: {actual} != {expected}")
return False
return True

41
thirdparty/capstone/bindings/python/cstest_py/src/cstest_py/cs_modes.py vendored Normal file
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# Copyright © 2024 Rot127 <unisono@quyllur.org>
# SPDX-License-Identifier: BSD-3
import capstone as cs
configs = {
"CS_OPT_DETAIL": {"type": cs.CS_OPT_DETAIL, "val": cs.CS_OPT_ON},
"CS_OPT_DETAIL_REAL": {
"type": cs.CS_OPT_DETAIL,
"val": cs.CS_OPT_DETAIL_REAL | cs.CS_OPT_ON,
},
"CS_OPT_SKIPDATA": {"type": cs.CS_OPT_SKIPDATA, "val": cs.CS_OPT_ON},
"CS_OPT_UNSIGNED": {"type": cs.CS_OPT_UNSIGNED, "val": cs.CS_OPT_ON},
"CS_OPT_NO_BRANCH_OFFSET": {
"type": cs.CS_OPT_NO_BRANCH_OFFSET,
"val": cs.CS_OPT_ON,
},
"CS_OPT_SYNTAX_DEFAULT": {
"type": cs.CS_OPT_SYNTAX,
"val": cs.CS_OPT_SYNTAX_DEFAULT,
},
"CS_OPT_SYNTAX_INTEL": {"type": cs.CS_OPT_SYNTAX, "val": cs.CS_OPT_SYNTAX_INTEL},
"CS_OPT_SYNTAX_ATT": {"type": cs.CS_OPT_SYNTAX, "val": cs.CS_OPT_SYNTAX_ATT},
"CS_OPT_SYNTAX_NOREGNAME": {
"type": cs.CS_OPT_SYNTAX,
"val": cs.CS_OPT_SYNTAX_NOREGNAME,
},
"CS_OPT_SYNTAX_MASM": {"type": cs.CS_OPT_SYNTAX, "val": cs.CS_OPT_SYNTAX_MASM},
"CS_OPT_SYNTAX_MOTOROLA": {
"type": cs.CS_OPT_SYNTAX,
"val": cs.CS_OPT_SYNTAX_MOTOROLA,
},
"CS_OPT_SYNTAX_CS_REG_ALIAS": {
"type": cs.CS_OPT_SYNTAX,
"val": cs.CS_OPT_SYNTAX_CS_REG_ALIAS,
},
"CS_OPT_SYNTAX_PERCENT": {
"type": cs.CS_OPT_SYNTAX,
"val": cs.CS_OPT_SYNTAX_PERCENT,
},
}

493
thirdparty/capstone/bindings/python/cstest_py/src/cstest_py/cstest.py vendored Normal file
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#!/usr/bin/env python3
# Copyright © 2024 Rot127 <unisono@quyllur.org>
# SPDX-License-Identifier: BSD-3
# Typing for Python3.8
from __future__ import annotations
import argparse
import logging
import subprocess as sp
import sys
import os
import yaml
import capstone
import traceback
from capstone import CsInsn, Cs, CS_ARCH_AARCH64, CS_MODE_64, CS_MODE_16
from cstest_py.cs_modes import configs
from cstest_py.details import compare_details
from cstest_py.compare import (
compare_asm_text,
compare_str,
compare_tbool,
compare_uint32,
)
from enum import Enum
from pathlib import Path
log = logging.getLogger("__name__")
def get_cs_int_attr(cs, attr: str, err_msg_pre: str):
try:
attr_int = getattr(cs, attr)
if not isinstance(attr_int, int):
raise AttributeError(f"{attr} not found")
return attr_int
except AttributeError:
log.warning(f"{err_msg_pre}: Capstone doesn't have the attribute '{attr}'")
return None
def arch_bits(arch: int, mode: int) -> int:
if arch == CS_ARCH_AARCH64 or mode & CS_MODE_64:
return 64
elif mode & CS_MODE_16:
return 16
return 32
class TestResult(Enum):
SUCCESS = 0
FAILED = 1
SKIPPED = 2
ERROR = 3
class TestStats:
def __init__(self, total_file_count: int):
self.total_file_count = total_file_count
self.valid_test_files = 0
self.test_case_count = 0
self.success = 0
self.failed = 0
self.skipped = 0
self.errors = 0
self.invalid_files = 0
self.total_valid_files = 0
self.err_msgs: list[str] = list()
self.failing_files = set()
def add_failing_file(self, test_file: Path):
self.failing_files.add(test_file)
def add_error_msg(self, msg: str):
self.err_msgs.append(msg)
def add_invalid_file_dp(self, tfile: Path):
self.invalid_files += 1
self.errors += 1
self.add_failing_file(tfile)
def add_test_case_data_point(self, dp: TestResult):
if dp == TestResult.SUCCESS:
self.success += 1
elif dp == TestResult.FAILED:
self.failed += 1
elif dp == TestResult.SKIPPED:
self.skipped += 1
elif dp == TestResult.ERROR:
self.errors += 1
self.failed += 1
else:
raise ValueError(f"Unhandled TestResult: {dp}")
def set_total_valid_files(self, total_valid_files: int):
self.total_valid_files = total_valid_files
def set_total_test_cases(self, total_test_cases: int):
self.test_case_count = total_test_cases
def get_test_case_count(self) -> int:
return self.test_case_count
def print_evaluate(self):
if self.total_file_count == 0:
log.error("No test files found!")
exit(-1)
if self.test_case_count == 0:
log.error("No test cases found!")
exit(-1)
if self.failing_files:
print("Test files with failures:")
for tf in self.failing_files:
print(f" - {tf}")
print()
if self.err_msgs:
print("Error messages:")
for error in self.err_msgs:
print(f" - {error}")
print("\n-----------------------------------------")
print("Test run statistics\n")
print(f"Valid files: {self.total_valid_files}")
print(f"Invalid files: {self.invalid_files}")
print(f"Errors: {self.errors}\n")
print("Test cases:")
print(f"\tTotal: {self.test_case_count}")
print(f"\tSuccessful: {self.success}")
print(f"\tSkipped: {self.skipped}")
print(f"\tFailed: {self.failed}")
print("-----------------------------------------")
print("")
if self.test_case_count != self.success + self.failed + self.skipped:
log.error(
"Inconsistent statistics: total != successful + failed + skipped\n"
)
if self.errors != 0:
log.error("Failed with errors\n")
exit(-1)
elif self.failed != 0:
log.warning("Not all tests succeeded\n")
exit(-1)
log.info("All tests succeeded.\n")
exit(0)
class TestInput:
def __init__(self, input_dict: dict):
self.input_dict = input_dict
if "bytes" not in self.input_dict:
raise ValueError("Error: 'Missing required mapping field'\nField: 'bytes'.")
if "options" not in self.input_dict:
raise ValueError(
"Error: 'Missing required mapping field'\nField: 'options'."
)
if "arch" not in self.input_dict:
raise ValueError("Error: 'Missing required mapping field'\nField: 'arch'.")
self.in_bytes = bytes(self.input_dict["bytes"])
self.options = self.input_dict["options"]
self.arch = self.input_dict["arch"]
self.name = "" if "name" not in self.input_dict else self.input_dict["name"]
if "address" not in self.input_dict:
self.address: int = 0
else:
assert isinstance(self.input_dict["address"], int)
self.address = self.input_dict["address"]
self.handle = None
self.arch_bits = 0
def setup(self):
log.debug(f"Init {self}")
arch = get_cs_int_attr(capstone, self.arch, "CS_ARCH")
if arch is None:
cs_name = f"CS_ARCH_{self.arch.upper()}"
arch = get_cs_int_attr(capstone, cs_name, "CS_ARCH")
if arch is None:
raise ValueError(
f"Couldn't init architecture as '{self.arch}' or '{cs_name}'.\n"
f"'{self.arch}' is not mapped to a capstone architecture."
)
new_mode = 0
for opt in self.options:
if "CS_MODE_" in opt:
mode = get_cs_int_attr(capstone, opt, "CS_OPT")
if mode is not None:
new_mode |= mode
continue
self.handle = Cs(arch, new_mode)
for opt in self.options:
if "CS_MODE_" in opt:
continue
if "CS_OPT_" in opt and opt in configs:
mtype = configs[opt]["type"]
val = configs[opt]["val"]
self.handle.option(mtype, val)
continue
log.warning(f"Option: '{opt}' not used")
self.arch_bits = arch_bits(self.handle.arch, self.handle.mode)
log.debug("Init done")
def decode(self) -> list[CsInsn]:
if not self.handle:
raise ValueError("self.handle is None. Must be setup before.")
return [i for i in self.handle.disasm(self.in_bytes, self.address)]
def __str__(self):
default = (
f"TestInput {{ arch: {self.arch}, options: {self.options}, "
f"addr: {self.address:x}, bytes: [ {','.join([f'{b:#04x}' for b in self.in_bytes])} ] }}"
)
if self.name:
return f"{self.name} -- {default}"
return default
class TestExpected:
def __init__(self, expected_dict: dict):
self.expected_dict = expected_dict
self.insns = (
list() if "insns" not in self.expected_dict else self.expected_dict["insns"]
)
def compare(self, actual_insns: list[CsInsn], bits: int) -> TestResult:
if len(actual_insns) != len(self.insns):
log.error(
"Number of decoded instructions don't match (actual != expected): "
f"{len(actual_insns)} != {len(self.insns):#x}"
)
return TestResult.FAILED
for a_insn, e_insn in zip(actual_insns, self.insns):
if not compare_asm_text(
a_insn,
e_insn.get("asm_text"),
bits,
):
return TestResult.FAILED
if not compare_str(a_insn.mnemonic, e_insn.get("mnemonic"), "mnemonic"):
return TestResult.FAILED
if not compare_str(a_insn.op_str, e_insn.get("op_str"), "op_str"):
return TestResult.FAILED
if not compare_uint32(a_insn.id, e_insn.get("id"), "id"):
return TestResult.FAILED
if not compare_tbool(a_insn.is_alias, e_insn.get("is_alias"), "is_alias"):
return TestResult.FAILED
if not compare_uint32(a_insn.alias_id, e_insn.get("alias_id"), "alias_id"):
return TestResult.FAILED
if not compare_details(a_insn, e_insn.get("details")):
return TestResult.FAILED
return TestResult.SUCCESS
class TestCase:
def __init__(self, test_case_dict: dict):
self.tc_dict = test_case_dict
if "input" not in self.tc_dict:
raise ValueError("Mandatory field 'input' missing")
if "expected" not in self.tc_dict:
raise ValueError("Mandatory field 'expected' missing")
self.input = TestInput(self.tc_dict["input"])
self.expected = TestExpected(self.tc_dict["expected"])
self.skip = "skip" in self.tc_dict
if self.skip and "skip_reason" not in self.tc_dict:
raise ValueError(
"If 'skip' field is set a 'skip_reason' field must be set as well."
)
self.skip_reason = (
self.tc_dict["skip_reason"] if "skip_reason" in self.tc_dict else ""
)
def __str__(self) -> str:
return f"{self.input}"
def test(self) -> TestResult:
if self.skip:
log.info(f"Skip {self}\nReason: {self.skip_reason}")
return TestResult.SKIPPED
try:
self.input.setup()
except Exception as e:
log.error(f"Setup failed at with: {e}")
traceback.print_exc()
return TestResult.ERROR
try:
insns = self.input.decode()
except Exception as e:
log.error(f"Decode failed with: {e}")
traceback.print_exc()
return TestResult.ERROR
try:
return self.expected.compare(insns, self.input.arch_bits)
except Exception as e:
log.error(f"Compare expected failed with: {e}")
traceback.print_exc()
return TestResult.ERROR
class TestFile:
def __init__(self, tfile_path: Path):
self.path = tfile_path
with open(tfile_path) as f:
try:
self.content = yaml.safe_load(f)
except yaml.YAMLError as e:
raise e
self.test_cases = list()
if not self.content:
raise ValueError("Empty file")
for tc_dict in self.content["test_cases"]:
tc = TestCase(tc_dict)
self.test_cases.append(tc)
def num_test_cases(self) -> int:
return len(self.test_cases)
def __str__(self) -> str:
return f"{self.path}"
class CSTest:
def __init__(self, path: Path, exclude: list[Path], include: list[Path]):
self.yaml_paths: list[Path] = list()
log.info(f"Search test files in {path}")
if path.is_file():
self.yaml_paths.append(path)
else:
for root, dirs, files in os.walk(path, onerror=print):
for file in files:
f = Path(root).joinpath(file)
if f.suffix not in [".yaml", ".yml"]:
continue
if f.name in exclude:
continue
if not include or f.name in include:
log.debug(f"Add: {f}")
self.yaml_paths.append(f)
log.info(f"Test files found: {len(self.yaml_paths)}")
self.stats = TestStats(len(self.yaml_paths))
self.test_files: list[TestFile] = list()
def parse_files(self):
total_test_cases = 0
total_files = len(self.yaml_paths)
count = 1
for tfile in self.yaml_paths:
print(
f"Parse {count}/{total_files}: {tfile.name}",
end=f"{' ' * 20}\r",
flush=True,
)
try:
tf = TestFile(tfile)
total_test_cases += tf.num_test_cases()
self.test_files.append(tf)
except yaml.YAMLError as e:
self.stats.add_error_msg(str(e))
self.stats.add_invalid_file_dp(tfile)
log.error("Error: 'libyaml parser error'")
log.error(f"{e}")
log.error(f"Failed to parse test file '{tfile}'")
except ValueError as e:
self.stats.add_error_msg(str(e))
self.stats.add_invalid_file_dp(tfile)
log.error(f"Error: ValueError: {e}")
log.error(f"Failed to parse test file '{tfile}'")
finally:
count += 1
self.stats.set_total_valid_files(len(self.test_files))
self.stats.set_total_test_cases(total_test_cases)
log.info(f"Found {self.stats.get_test_case_count()} test cases.{' ' * 20}")
def run_tests(self):
self.parse_files()
for tf in self.test_files:
log.info(f"Test file: {tf}\n")
for tc in tf.test_cases:
log.info(f"Run test: {tc}")
try:
result = tc.test()
except Exception as e:
result = TestResult.ERROR
self.stats.add_error_msg(str(e))
if result == TestResult.FAILED or result == TestResult.ERROR:
self.stats.add_failing_file(tf.path)
self.stats.add_test_case_data_point(result)
log.info(result)
print()
self.stats.print_evaluate()
def get_repo_root() -> str | None:
res = sp.run(["git", "rev-parse", "--show-toplevel"], capture_output=True)
if res.stderr:
log.error("Could not get repository root directory.")
return None
return res.stdout.decode("utf8").strip()
def parse_args() -> argparse.Namespace:
parser = argparse.ArgumentParser(
prog="Python CSTest",
description="Pyton binding cstest implementation.",
)
repo_root = get_repo_root()
if repo_root:
parser.add_argument(
dest="search_dir",
help="Directory to search for .yaml test files.",
default=Path(f"{repo_root}/tests/"),
type=Path,
)
else:
parser.add_argument(
dest="search_dir",
help="Directory to search for .yaml test files.",
required=True,
type=Path,
)
parser.add_argument(
"-e",
dest="exclude",
help="List of file names to exclude.",
nargs="+",
required=False,
default=list(),
)
parser.add_argument(
"-i",
dest="include",
help="List of file names to include.",
nargs="+",
required=False,
default=list(),
)
parser.add_argument(
"-v",
dest="verbosity",
help="Verbosity of the log messages.",
choices=["debug", "info", "warning", "error", "fatal", "critical"],
default="info",
)
arguments = parser.parse_args()
return arguments
def main():
log_levels = {
"debug": logging.DEBUG,
"info": logging.INFO,
"warning": logging.WARNING,
"error": logging.ERROR,
"fatal": logging.FATAL,
"critical": logging.CRITICAL,
}
args = parse_args()
format = logging.Formatter("%(levelname)-5s - %(message)s", None, "%")
log.setLevel(log_levels[args.verbosity])
h1 = logging.StreamHandler(sys.stdout)
h1.addFilter(
lambda record: record.levelno >= log_levels[args.verbosity]
and record.levelno < logging.WARNING
)
h1.setFormatter(format)
h2 = logging.StreamHandler(sys.stderr)
h2.setLevel(logging.WARNING)
h2.setFormatter(format)
log.addHandler(h1)
log.addHandler(h2)
CSTest(args.search_dir, args.exclude, args.include).run_tests()
if __name__ == "__main__":
main()

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[build-system]
requires = ["setuptools"]
build-backend = "setuptools.build_meta"

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#!/usr/bin/env python3
import glob
import os
import shutil
import sys
import platform
import logging
from setuptools import setup
from sysconfig import get_platform
from setuptools.command.build import build
from setuptools.command.sdist import sdist
from setuptools.command.bdist_egg import bdist_egg
logger = logging.getLogger(__name__)
logging.basicConfig(level=logging.INFO)
SYSTEM = sys.platform
# adapted from commit e504b81 of Nguyen Tan Cong
# Reference: https://docs.python.org/2/library/platform.html#cross-platform
IS_64BITS = sys.maxsize > 2**32
# are we building from the repository or from a source distribution?
ROOT_DIR = os.path.dirname(os.path.realpath(__file__))
LIBS_DIR = os.path.join(ROOT_DIR, 'capstone', 'lib')
HEADERS_DIR = os.path.join(ROOT_DIR, 'capstone', 'include')
SRC_DIR = os.path.join(ROOT_DIR, 'src')
BUILD_DIR = SRC_DIR if os.path.exists(SRC_DIR) else os.path.join(ROOT_DIR, '../..')
# Parse version from pkgconfig.mk
VERSION_DATA = {}
with open(os.path.join(BUILD_DIR, 'pkgconfig.mk')) as fp:
lines = fp.readlines()
for line in lines:
line = line.strip()
if len(line) == 0:
continue
if line.startswith('#'):
continue
if '=' not in line:
continue
k, v = line.split('=', 1)
k = k.strip()
v = v.strip()
if len(k) == 0 or len(v) == 0:
continue
VERSION_DATA[k] = v
if 'PKG_MAJOR' not in VERSION_DATA or \
'PKG_MINOR' not in VERSION_DATA or \
'PKG_EXTRA' not in VERSION_DATA:
raise Exception("Malformed pkgconfig.mk")
if 'PKG_TAG' in VERSION_DATA:
VERSION = '{PKG_MAJOR}.{PKG_MINOR}.{PKG_EXTRA}{PKG_TAG}'.format(**VERSION_DATA)
else:
VERSION = '{PKG_MAJOR}.{PKG_MINOR}.{PKG_EXTRA}'.format(**VERSION_DATA)
if SYSTEM == 'darwin':
VERSIONED_LIBRARY_FILE = "libcapstone.{PKG_MAJOR}.dylib".format(**VERSION_DATA)
LIBRARY_FILE = "libcapstone.dylib"
STATIC_LIBRARY_FILE = 'libcapstone.a'
elif SYSTEM in ('win32', 'cygwin'):
VERSIONED_LIBRARY_FILE = "capstone.dll"
LIBRARY_FILE = "capstone.dll"
STATIC_LIBRARY_FILE = None
else:
VERSIONED_LIBRARY_FILE = "libcapstone.so.{PKG_MAJOR}".format(**VERSION_DATA)
LIBRARY_FILE = "libcapstone.so"
STATIC_LIBRARY_FILE = 'libcapstone.a'
def clean_bins():
shutil.rmtree(LIBS_DIR, ignore_errors=True)
shutil.rmtree(HEADERS_DIR, ignore_errors=True)
def copy_sources():
"""Copy the C sources into the source directory.
This rearranges the source files under the python distribution
directory.
"""
src = []
try:
shutil.rmtree("src/")
except (IOError, OSError):
pass
shutil.copytree(os.path.join(BUILD_DIR, "arch"), os.path.join(SRC_DIR, "arch"))
shutil.copytree(os.path.join(BUILD_DIR, "include"), os.path.join(SRC_DIR, "include"))
src.extend(glob.glob(os.path.join(BUILD_DIR, "*.[ch]")))
src.extend(glob.glob(os.path.join(BUILD_DIR, "LICENSES/*")))
src.extend(glob.glob(os.path.join(BUILD_DIR, "README")))
src.extend(glob.glob(os.path.join(BUILD_DIR, "*.TXT")))
src.extend(glob.glob(os.path.join(BUILD_DIR, "RELEASE_NOTES")))
src.extend(glob.glob(os.path.join(BUILD_DIR, "CMakeLists.txt")))
for filename in src:
outpath = os.path.join(SRC_DIR, os.path.basename(filename))
logger.info("%s -> %s" % (filename, outpath))
shutil.copy(filename, outpath)
def build_libraries():
"""
Prepare the capstone directory for a binary distribution or installation.
Builds shared libraries and copies header files.
Will use a src/ dir if one exists in the current directory, otherwise assumes it's in the repo
"""
cwd = os.getcwd()
clean_bins()
os.mkdir(HEADERS_DIR)
os.mkdir(LIBS_DIR)
# copy public headers
shutil.copytree(os.path.join(BUILD_DIR, 'include', 'capstone'), os.path.join(HEADERS_DIR, 'capstone'))
# if prebuilt libraries are available, use those and cancel build
if os.path.exists(os.path.join(ROOT_DIR, 'prebuilt', LIBRARY_FILE)) and \
(not STATIC_LIBRARY_FILE or os.path.exists(os.path.join(ROOT_DIR, 'prebuilt', STATIC_LIBRARY_FILE))):
logger.info('Using prebuilt libraries')
shutil.copy(os.path.join(ROOT_DIR, 'prebuilt', LIBRARY_FILE), LIBS_DIR)
if STATIC_LIBRARY_FILE is not None:
shutil.copy(os.path.join(ROOT_DIR, 'prebuilt', STATIC_LIBRARY_FILE), LIBS_DIR)
return
os.chdir(BUILD_DIR)
# Windows build: this process requires few things:
# - MSVC installed
# - Run this command in an environment setup for MSVC
if not os.path.exists("build_py"):
os.mkdir("build_py")
os.chdir("build_py")
print("Build Directory: {}\n".format(os.getcwd()))
# Only build capstone.dll / libcapstone.dylib
if SYSTEM == "win32":
os.system('cmake -DCMAKE_BUILD_TYPE=Release -DBUILD_SHARED_LIBS=ON -DCAPSTONE_BUILD_LEGACY_TESTS=OFF -DCAPSTONE_BUILD_CSTOOL=OFF -G "NMake Makefiles" ..')
elif 'AFL_NOOPT' in os.environ:
# build for test_corpus
os.system('cmake -DBUILD_SHARED_LIBS=ON -DCAPSTONE_BUILD_LEGACY_TESTS=OFF -DCAPSTONE_BUILD_CSTOOL=OFF ..')
else:
os.system('cmake -DCMAKE_BUILD_TYPE=Release -DBUILD_SHARED_LIBS=ON -DCAPSTONE_BUILD_LEGACY_TESTS=OFF -DCAPSTONE_BUILD_CSTOOL=OFF -G "Unix Makefiles" ..')
os.system("cmake --build .")
shutil.copy(VERSIONED_LIBRARY_FILE, os.path.join(LIBS_DIR, LIBRARY_FILE))
# only copy static library if it exists (it's a build option)
if STATIC_LIBRARY_FILE and os.path.exists(STATIC_LIBRARY_FILE):
shutil.copy(STATIC_LIBRARY_FILE, LIBS_DIR)
os.chdir(cwd)
class custom_sdist(sdist):
def run(self):
clean_bins()
copy_sources()
return sdist.run(self)
class custom_build(build):
def run(self):
if 'LIBCAPSTONE_PATH' in os.environ:
logger.info('Skipping building C extensions since LIBCAPSTONE_PATH is set')
else:
logger.info('Building C extensions')
build_libraries()
return build.run(self)
class custom_bdist_egg(bdist_egg):
def run(self):
self.run_command('build')
return bdist_egg.run(self)
cmdclass = {}
cmdclass['build'] = custom_build
cmdclass['sdist'] = custom_sdist
cmdclass['bdist_egg'] = custom_bdist_egg
try:
from setuptools.command.develop import develop
class custom_develop(develop):
def run(self):
logger.info("Building C extensions")
build_libraries()
return develop.run(self)
cmdclass['develop'] = custom_develop
except ImportError:
print("Proper 'develop' support unavailable.")
if 'bdist_wheel' in sys.argv and '--plat-name' not in sys.argv:
# Inject the platform identifier into argv.
# Platform tags are described here:
# https://packaging.python.org/en/latest/specifications/platform-compatibility-tags
#
# I couldn't really find out in time why we need to inject the platform here?
# The cibuildwheel doesn't need it for the Windows job. But for Mac and Linux.
# This here is very dirty and will maybe break in the future.
# Sorry if this is the case and you read this.
# See: https://github.com/capstone-engine/capstone/issues/2445
idx = sys.argv.index('bdist_wheel') + 1
sys.argv.insert(idx, '--plat-name')
name = get_platform()
sys.argv.insert(idx + 1, name.replace('.', '_').replace('-', '_'))
setup(
provides=['capstone'],
packages=['capstone'],
name='capstone',
version=VERSION,
author='Nguyen Anh Quynh',
author_email='aquynh@gmail.com',
description='Capstone disassembly engine',
url='https://www.capstone-engine.org',
long_description=open('README.txt', encoding="utf8").read(),
long_description_content_type='text/markdown',
python_requires='>=3.8',
classifiers=[
'License :: OSI Approved :: BSD License',
'Programming Language :: Python :: 3',
],
cmdclass=cmdclass,
zip_safe=False,
include_package_data=True,
package_data={
"capstone": ["lib/*", "include/capstone/*"],
},
install_requires=[
"importlib_resources;python_version<'3.9'",
],
)

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#!/usr/bin/env python3
import test_lite
import test_skipdata
import test_customized_mnem
test_lite.test_class()
test_skipdata.test_class()
test_customized_mnem.test()

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#!/usr/bin/env python3
# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
from capstone import *
from capstone.x86 import *
from xprint import to_hex
X86_CODE32 = b"\x75\x01"
def print_insn(md, code):
print("%s\t" % to_hex(code, False), end="")
for insn in md.disasm(code, 0x1000):
print("\t%s\t%s" % (insn.mnemonic, insn.op_str))
def test():
try:
md = Cs(CS_ARCH_X86, CS_MODE_32)
print("Disassemble X86 code with default instruction mnemonic")
print_insn(md, X86_CODE32)
print("\nNow customize engine to change mnemonic from 'JNE' to 'JNZ'")
md.mnemonic_setup(X86_INS_JNE, "jnz")
print_insn(md, X86_CODE32)
print("\nReset engine to use the default mnemonic")
md.mnemonic_setup(X86_INS_JNE, None)
print_insn(md, X86_CODE32)
except CsError as e:
print("ERROR: %s" % e)
if __name__ == '__main__':
test()

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#!/usr/bin/env python3
# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
from capstone import *
from xprint import to_hex
X86_CODE16 = b"\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
X86_CODE32 = b"\xba\xcd\xab\x00\x00\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
X86_CODE64 = b"\x55\x48\x8b\x05\xb8\x13\x00\x00"
ARM_CODE = b"\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3"
ARM_CODE2 = b"\x10\xf1\x10\xe7\x11\xf2\x31\xe7\xdc\xa1\x2e\xf3\xe8\x4e\x62\xf3"
THUMB_CODE = b"\x70\x47\xeb\x46\x83\xb0\xc9\x68"
THUMB_CODE2 = b"\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0"
THUMB_MCLASS = b"\xef\xf3\x02\x80"
ARMV8 = b"\xe0\x3b\xb2\xee\x42\x00\x01\xe1\x51\xf0\x7f\xf5"
MIPS_CODE = b"\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56"
MIPS_CODE2 = b"\x56\x34\x21\x34\xc2\x17\x01\x00"
MIPS_32R6M = b"\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0"
MIPS_32R6 = b"\xec\x80\x00\x19\x7c\x43\x22\xa0"
AARCH64_CODE = b"\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9"
PPC_CODE = b"\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21"
PPC_CODE2 = b"\x10\x60\x2a\x10\x10\x64\x28\x88\x7c\x4a\x5d\x0f"
SPARC_CODE = b"\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03"
SPARCV9_CODE = b"\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0"
SYSZ_CODE = b"\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78"
XCORE_CODE = b"\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10"
M68K_CODE = b"\xd4\x40\x87\x5a\x4e\x71\x02\xb4\xc0\xde\xc0\xde\x5c\x00\x1d\x80\x71\x12\x01\x23\xf2\x3c\x44\x22\x40\x49\x0e\x56\x54\xc5\xf2\x3c\x44\x00\x44\x7a\x00\x00\xf2\x00\x0a\x28\x4E\xB9\x00\x00\x00\x12\x4E\x75"
M680X_CODE = b"\x06\x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa6\x9f\x10\x00\x11\xac\x99\x10\x00\x39"
ALPHA_CODE = b'\x02\x00\xbb\x27\x50\x7a\xbd\x23\xd0\xff\xde\x23\x00\x00\x5e\xb7'
ALPHA_CODE_BE = b'\x27\xbb\x00\x02\x23\xbd\x7a\x50\x23\xde\xff\xd0\xb7\x5e\x00\x00'
HPPA_20_CODE_BE = b'\x00\x20\x50\xa2\x00\x01\x58\x20\x00\x00\x44\xa1\x00\x41\x18\x40\x00\x20\x08\xa2\x01\x60\x48\xa1\x01\x61\x18\xc0\x00\x00\x14\xa1\x00\x0f\x0d\x61\x00\x0f\x0e\x61\x00\x01\x18\x60\x00\x00\x0c\x00\x00\x00\x0c\xa0\x03\xff\xc0\x1f\x00\x00\x04\x00\x00\x10\x04\x00\x04\x22\x51\x83\x04\x22\x51\xc3\x04\x22\x51\x83\x04\x2f\x71\x83\x04\x2f\x71\xc3\x04\x2f\x71\x83\x04\x41\x53\x43\x04\x41\x53\x63\x04\x41\x53\x03\x04\x41\x12\x00\x04\x41\x16\x00\x04\x41\x16\x20\x04\x41\x42\x00\x04\x41\x46\x00\x04\x41\x46\x20\x04\x41\x12\x40\x04\x41\x12\x60\x04\x41\x42\x40\x04\x41\x42\x60\x04\x41\x18\x00\x04\x41\x08\x00\x04\x41\x13\x80\x04\x41\x13\xa0\x04\x41\x52\x80\x04\x41\x52\xa0\x04\x5e\x72\x80\x04\x41\x42\x80\x04\x41\x52\xc0\x04\x41\x52\xe0\x04\x41\x42\xc0\x04\x41\x42\xe0\x14\x00\xde\xad'
HPPA_20_CODE = b'\xa2\x50\x20\x00\x20\x58\x01\x00\xa1\x44\x00\x00\x40\x18\x41\x00\xa2\x08\x20\x00\xa1\x48\x60\x01\xc0\x18\x61\x01\xa1\x14\x00\x00\x61\x0d\x0f\x00\x61\x0e\x0f\x00\x60\x18\x01\x00\x00\x0c\x00\x00\xa0\x0c\x00\x00\x1f\xc0\xff\x03\x00\x04\x00\x00\x00\x04\x10\x00\x83\x51\x22\x04\xc3\x51\x22\x04\x83\x51\x22\x04\x83\x71\x2f\x04\xc3\x71\x2f\x04\x83\x71\x2f\x04\x43\x53\x41\x04\x63\x53\x41\x04\x03\x53\x41\x04\x00\x12\x41\x04\x00\x16\x41\x04\x20\x16\x41\x04\x00\x42\x41\x04\x00\x46\x41\x04\x20\x46\x41\x04\x40\x12\x41\x04\x60\x12\x41\x04\x40\x42\x41\x04\x60\x42\x41\x04\x00\x18\x41\x04\x00\x08\x41\x04\x80\x13\x41\x04\xa0\x13\x41\x04\x80\x52\x41\x04\xa0\x52\x41\x04\x80\x72\x5e\x04\x80\x42\x41\x04\xc0\x52\x41\x04\xe0\x52\x41\x04\xc0\x42\x41\x04\xe0\x42\x41\x04\xad\xde\x00\x14'
HPPA_11_CODE_BE = b'\x24\x41\x40\xc3\x24\x41\x60\xc3\x24\x41\x40\xe3\x24\x41\x60\xe3\x24\x41\x68\xe3\x2c\x41\x40\xc3\x2c\x41\x60\xc3\x2c\x41\x40\xe3\x2c\x41\x60\xe3\x2c\x41\x68\xe3\x24\x62\x42\xc1\x24\x62\x62\xc1\x24\x62\x42\xe1\x24\x62\x46\xe1\x24\x62\x62\xe1\x24\x62\x6a\xe1\x2c\x62\x42\xc1\x2c\x62\x62\xc1\x2c\x62\x42\xe1\x2c\x62\x46\xe1\x2c\x62\x62\xe1\x2c\x62\x6a\xe1\x24\x3e\x50\xc2\x24\x3e\x50\xe2\x24\x3e\x70\xe2\x24\x3e\x78\xe2\x2c\x3e\x50\xc2\x2c\x3e\x50\xe2\x2c\x3e\x70\xe2\x2c\x3e\x78\xe2\x24\x5e\x52\xc1\x24\x5e\x52\xe1\x24\x5e\x56\xe1\x24\x5e\x72\xe1\x24\x5e\x7a\xe1\x2c\x5e\x52\xc1\x2c\x5e\x52\xe1\x2c\x5e\x56\xe1\x2c\x5e\x72\xe1\x2c\x5e\x7a\xe1'
HPPA_11_CODE = b'\xc3\x40\x41\x24\xc3\x60\x41\x24\xe3\x40\x41\x24\xe3\x60\x41\x24\xe3\x68\x41\x24\xc3\x40\x41\x2c\xc3\x60\x41\x2c\xe3\x40\x41\x2c\xe3\x60\x41\x2c\xe3\x68\x41\x2c\xc1\x42\x62\x24\xc1\x62\x62\x24\xe1\x42\x62\x24\xe1\x46\x62\x24\xe1\x62\x62\x24\xe1\x6a\x62\x24\xc1\x42\x62\x2c\xc1\x62\x62\x2c\xe1\x42\x62\x2c\xe1\x46\x62\x2c\xe1\x62\x62\x2c\xe1\x6a\x62\x2c\xc2\x50\x3e\x24\xe2\x50\x3e\x24\xe2\x70\x3e\x24\xe2\x78\x3e\x24\xc2\x50\x3e\x2c\xe2\x50\x3e\x2c\xe2\x70\x3e\x2c\xe2\x78\x3e\x2c\xc1\x52\x5e\x24\xe1\x52\x5e\x24\xe1\x56\x5e\x24\xe1\x72\x5e\x24\xe1\x7a\x5e\x24\xc1\x52\x5e\x2c\xe1\x52\x5e\x2c\xe1\x56\x5e\x2c\xe1\x72\x5e\x2c\xe1\x7a\x5e\x2c'
all_tests = (
(CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)", None),
(CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32bit (ATT syntax)", CS_OPT_SYNTAX_ATT),
(CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (Intel syntax)", None),
(CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (MASM syntax)", CS_OPT_SYNTAX_MASM),
(CS_ARCH_X86, CS_MODE_64, X86_CODE64, "X86 64 (Intel syntax)", None),
(CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE, "ARM", None),
(CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE2, "THUMB-2", None),
(CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE2, "ARM: Cortex-A15 + NEON", None),
(CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE, "THUMB", None),
(CS_ARCH_ARM, CS_MODE_THUMB + CS_MODE_MCLASS, THUMB_MCLASS, "Thumb-MClass", None),
(CS_ARCH_ARM, CS_MODE_ARM + CS_MODE_V8, ARMV8, "Arm-V8", None),
(CS_ARCH_MIPS, CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN, MIPS_CODE, "MIPS-32 (Big-endian)", None),
(CS_ARCH_MIPS, CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)", None),
(CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN, MIPS_32R6M, "MIPS-32R6 | Micro (Big-endian)", None),
(CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN, MIPS_32R6, "MIPS-32R6 (Big-endian)", None),
(CS_ARCH_AARCH64, CS_MODE_ARM, AARCH64_CODE, "AARCH64", None),
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64", None),
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64, print register with number only", CS_OPT_SYNTAX_NOREGNAME),
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN + CS_MODE_QPX, PPC_CODE2, "PPC-64 + QPX", CS_OPT_SYNTAX_NOREGNAME),
(CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, SPARC_CODE, "Sparc", None),
(CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN + CS_MODE_V9, SPARCV9_CODE, "SparcV9", None),
(CS_ARCH_SYSZ, 0, SYSZ_CODE, "SystemZ", None),
(CS_ARCH_XCORE, 0, XCORE_CODE, "XCore", None),
(CS_ARCH_M68K, CS_MODE_BIG_ENDIAN | CS_MODE_M68K_040, M68K_CODE, "M68K (68040)", None),
(CS_ARCH_M680X, CS_MODE_M680X_6809, M680X_CODE, "M680X_M6809", None),
(CS_ARCH_ALPHA, CS_MODE_LITTLE_ENDIAN, ALPHA_CODE, "Alpha (Little-endian)", None),
(CS_ARCH_ALPHA, CS_MODE_BIG_ENDIAN, ALPHA_CODE_BE, "Alpha (Big-endian)", None),
(CS_ARCH_HPPA, CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_20, HPPA_20_CODE_BE, "HPPA 2.0 (Big-endian)", None),
(CS_ARCH_HPPA, CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_20, HPPA_20_CODE, "HPPA 2.0 (Little-endian)", None),
(CS_ARCH_HPPA, CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_11, HPPA_11_CODE_BE, "HPPA 1.1 (Big-endian)", None),
(CS_ARCH_HPPA, CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_11, HPPA_11_CODE, "HPPA 1.1 (Little-endian)", None),
)
# ## Test class Cs
def test_class():
for (arch, mode, code, comment, syntax) in all_tests:
print('*' * 16)
print("Platform: %s" % comment)
print("Code: %s" % to_hex(code))
print("Disasm:")
try:
md = Cs(arch, mode)
if syntax is not None:
md.syntax = syntax
for (addr, size, mnemonic, op_str) in md.disasm_iter(code, 0x1000):
print("0x%x:\t%s\t%s" % (addr, mnemonic, op_str))
print("0x%x:" % (addr + size))
print()
except CsError as e:
print("ERROR: %s" % e)
if __name__ == '__main__':
test_class()

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#!/usr/bin/env python3
# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
from capstone import *
from xprint import to_hex
X86_CODE16 = b"\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
X86_CODE32 = b"\xba\xcd\xab\x00\x00\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
X86_CODE64 = b"\x55\x48\x8b\x05\xb8\x13\x00\x00"
ARM_CODE = b"\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3"
ARM_CODE2 = b"\x10\xf1\x10\xe7\x11\xf2\x31\xe7\xdc\xa1\x2e\xf3\xe8\x4e\x62\xf3"
THUMB_CODE = b"\x70\x47\xeb\x46\x83\xb0\xc9\x68"
THUMB_CODE2 = b"\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0"
THUMB_MCLASS = b"\xef\xf3\x02\x80"
ARMV8 = b"\xe0\x3b\xb2\xee\x42\x00\x01\xe1\x51\xf0\x7f\xf5"
MIPS_CODE = b"\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56"
MIPS_CODE2 = b"\x56\x34\x21\x34\xc2\x17\x01\x00"
MIPS_32R6M = b"\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0"
MIPS_32R6 = b"\xec\x80\x00\x19\x7c\x43\x22\xa0"
AARCH64_CODE = b"\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9"
PPC_CODE = b"\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21"
PPC_CODE2 = b"\x10\x60\x2a\x10\x10\x64\x28\x88\x7c\x4a\x5d\x0f"
SPARC_CODE = b"\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03"
SPARCV9_CODE = b"\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0"
SYSZ_CODE = b"\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78"
XCORE_CODE = b"\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10"
M68K_CODE = b"\xd4\x40\x87\x5a\x4e\x71\x02\xb4\xc0\xde\xc0\xde\x5c\x00\x1d\x80\x71\x12\x01\x23\xf2\x3c\x44\x22\x40\x49\x0e\x56\x54\xc5\xf2\x3c\x44\x00\x44\x7a\x00\x00\xf2\x00\x0a\x28\x4E\xB9\x00\x00\x00\x12\x4E\x75"
M680X_CODE = b"\x06\x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa6\x9f\x10\x00\x11\xac\x99\x10\x00\x39"
all_tests = (
(CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)", None),
(CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32bit (ATT syntax)", CS_OPT_SYNTAX_ATT),
(CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (Intel syntax)", None),
(CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (MASM syntax)", CS_OPT_SYNTAX_MASM),
(CS_ARCH_X86, CS_MODE_64, X86_CODE64, "X86 64 (Intel syntax)", None),
(CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE, "ARM", None),
(CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE2, "THUMB-2", None),
(CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE2, "ARM: Cortex-A15 + NEON", None),
(CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE, "THUMB", None),
(CS_ARCH_ARM, CS_MODE_THUMB + CS_MODE_MCLASS, THUMB_MCLASS, "Thumb-MClass", None),
(CS_ARCH_ARM, CS_MODE_ARM + CS_MODE_V8, ARMV8, "Arm-V8", None),
(CS_ARCH_MIPS, CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN, MIPS_CODE, "MIPS-32 (Big-endian)", None),
(CS_ARCH_MIPS, CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)", None),
(CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN, MIPS_32R6M, "MIPS-32R6 | Micro (Big-endian)", None),
(CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN, MIPS_32R6, "MIPS-32R6 (Big-endian)", None),
(CS_ARCH_AARCH64, CS_MODE_ARM, AARCH64_CODE, "AARCH64", None),
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64", None),
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64, print register with number only", CS_OPT_SYNTAX_NOREGNAME),
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN + CS_MODE_QPX, PPC_CODE2, "PPC-64 + QPX", CS_OPT_SYNTAX_NOREGNAME),
(CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, SPARC_CODE, "Sparc", None),
(CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN + CS_MODE_V9, SPARCV9_CODE, "SparcV9", None),
(CS_ARCH_SYSZ, 0, SYSZ_CODE, "SystemZ", None),
(CS_ARCH_XCORE, 0, XCORE_CODE, "XCore", None),
(CS_ARCH_M68K, CS_MODE_BIG_ENDIAN | CS_MODE_M68K_040, M68K_CODE, "M68K (68040)", None),
(CS_ARCH_M680X, CS_MODE_M680X_6809, M680X_CODE, "M680X_M6809", None),
)
# ## Test cs_disasm_quick()
def test_cs_disasm_quick():
for (arch, mode, code, comment, syntax) in all_tests:
print('*' * 40)
print("Platform: %s" % comment)
print("Disasm:"),
print(to_hex(code))
for (addr, size, mnemonic, op_str) in cs_disasm_lite(arch, mode, code, 0x1000):
print("0x%x:\t%s\t%s" % (addr, mnemonic, op_str))
print()
# ## Test class Cs
def test_class():
for (arch, mode, code, comment, syntax) in all_tests:
print('*' * 16)
print("Platform: %s" % comment)
print("Code: %s" % to_hex(code))
print("Disasm:")
try:
md = Cs(arch, mode)
if syntax is not None:
md.syntax = syntax
for (addr, size, mnemonic, op_str) in md.disasm_lite(code, 0x1000):
print("0x%x:\t%s\t%s" % (addr, mnemonic, op_str))
print("0x%x:" % (addr + size))
print()
except CsError as e:
print("ERROR: %s" % e)
# test_cs_disasm_quick()
# print "*" * 40
if __name__ == '__main__':
test_class()

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#!/usr/bin/env python3
# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
from capstone import *
from xprint import to_hex
X86_CODE32 = b"\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x00\x91\x92"
RANDOM_CODE = b"\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78"
all_tests = (
(CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (Intel syntax)", None),
(CS_ARCH_ARM, CS_MODE_ARM, RANDOM_CODE, "Arm", None),
)
# Sample callback for SKIPDATA option
def testcb(buffer, size, offset, userdata):
# always skip 2 bytes of data
return 2
# ## Test class Cs
def test_class():
for (arch, mode, code, comment, syntax) in all_tests:
print('*' * 16)
print("Platform: %s" %comment)
print("Code: %s" % to_hex(code))
print("Disasm:")
try:
md = Cs(arch, mode)
if syntax is not None:
md.syntax = syntax
md.skipdata = True
# Default "data" instruction's name is ".byte". To rename it to "db", just use
# the code below.
md.skipdata_setup = ("db", None, None)
# NOTE: This example ignores SKIPDATA's callback (first None) & user_data (second None)
# Can also use dedicated setter
#md.skipdata_mnem = 'db'
# To customize the SKIPDATA callback, use the line below.
#md.skipdata_setup = (".db", testcb, None)
# Or use dedicated setter with custom parameter
#md.skipdata_callback = (testcb, 42)
# Or provide just a function
#md.skipdata_callback = testcb
# Note that reading this property will always return a tuple
#assert md.skipdata_callback == (testcb, None)
for insn in md.disasm(code, 0x1000):
#bytes = binascii.hexlify(insn.bytes)
#print("0x%x:\t%s\t%s\t// hex-code: %s" %(insn.address, insn.mnemonic, insn.op_str, bytes))
print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
print("0x%x:" % (insn.address + insn.size))
print
except CsError as e:
print("ERROR: %s" % e)
if __name__ == '__main__':
test_class()

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#!/usr/bin/env python
# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
def to_hex(s, prefix_0x = True):
if prefix_0x:
return " ".join("0x{0:02x}".format(c) for c in s) # <-- Python 3 is OK
else:
return " ".join("{0:02x}".format(c) for c in s) # <-- Python 3 is OK
def to_hex2(s):
r = "".join("{0:02x}".format(c) for c in s) # <-- Python 3 is OK
while r[0] == '0': r = r[1:]
return r
def to_x(s):
from struct import pack
if not s: return '0'
x = pack(">q", s)
while x[0] in ('\0', 0): x = x[1:]
return to_hex2(x)
def to_x_32(s):
from struct import pack
if not s: return '0'
x = pack(">i", s)
while x[0] in ('\0', 0): x = x[1:]
return to_hex2(x)