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Sajid
2024-09-07 18:00:09 +06:00
commit 0f9a53f75a
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174
thirdparty/capstone/contrib/sysz_update/0006-capstone-generate-MappingInsn.inc.patch vendored Normal file
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@@ -0,0 +1,174 @@
From 7a436110ef15c803dc8524af2fb5612bcacbb126 Mon Sep 17 00:00:00 2001
From: mephi42 <mephi42@gmail.com>
Date: Tue, 7 Aug 2018 20:55:32 +0200
Subject: [PATCH 6/7] capstone: generate *MappingInsn.inc
---
lib/Target/SystemZ/CMakeLists.txt | 1 +
utils/TableGen/InstrInfoEmitter.cpp | 95 +++++++++++++++++++++++++++++
utils/TableGen/TableGen.cpp | 6 ++
utils/TableGen/TableGenBackends.h | 1 +
4 files changed, 103 insertions(+)
diff --git a/lib/Target/SystemZ/CMakeLists.txt b/lib/Target/SystemZ/CMakeLists.txt
index f83b4242fb4..4b5d9c4a3b2 100644
--- a/lib/Target/SystemZ/CMakeLists.txt
+++ b/lib/Target/SystemZ/CMakeLists.txt
@@ -6,6 +6,7 @@ tablegen(LLVM SystemZGenCallingConv.inc -gen-callingconv)
tablegen(LLVM SystemZGenDAGISel.inc -gen-dag-isel)
tablegen(LLVM SystemZGenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM SystemZGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM SystemZMappingInsn.inc -mapping-insn)
tablegen(LLVM SystemZGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM SystemZGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM SystemZGenSubtargetInfo.inc -gen-subtarget)
diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp
index 2f3a2729262..14ab1ea8a72 100644
--- a/utils/TableGen/InstrInfoEmitter.cpp
+++ b/utils/TableGen/InstrInfoEmitter.cpp
@@ -744,4 +744,99 @@ void EmitInstrInfo(RecordKeeper &RK, raw_ostream &OS) {
#endif
}
+#ifdef CAPSTONE
+std::string GetPublicName(const CodeGenInstruction *Inst) {
+ std::string Name = Inst->TheDef->getName();
+ // Apply backward compatibility fixups.
+ // BRNLE -> BNLER.
+ if (Name.length() >= 5 && Name.substr(0, 5) == "BRAsm") {
+ Name = "B" + Name.substr(5, Name.length() - 5) + "R";
+ }
+ // SSKEOpt -> SSKE.
+ while (Name.length() >= 3 && Name.substr(Name.length() - 3, 3) == "Opt") {
+ Name = Name.substr(0, Name.length() - 3);
+ }
+ // BRCLAsm -> BRCL.
+ while (true) {
+ size_t pos = Name.find("Asm");
+ if (pos == std::string::npos) {
+ break;
+ }
+ Name = Name.substr(0, pos) + Name.substr(pos + 3);
+ }
+ // CPSDRxx -> CPSDR.
+ if (Name.length() >= 2) {
+ std::string Suffix2 = Name.substr(Name.length() - 2, 2);
+ if (Suffix2 == "dd" || Suffix2 == "ds" ||
+ Suffix2 == "sd" || Suffix2 == "ss") {
+ Name = Name.substr(0, Name.length() - 2);
+ }
+ }
+ return "SYSZ_INS_" + Name;
+}
+
+std::string GetRegisterName(Record *Reg) {
+ std::string Name = Reg->getName();
+ for (char& c : Name) {
+ c = toupper(c);
+ }
+ // R0L, R0D -> R0.
+ if (Name.length() >= 3 &&
+ Name[Name.length() - 3] == 'R' &&
+ (Name[Name.length() - 1] == 'L' ||
+ Name[Name.length() - 1] == 'D')) {
+ Name = Name.substr(0, Name.length() - 3) + Name[Name.length() - 2];
+ }
+ return "SYSZ_REG_" + Name;
+}
+
+std::string GetGroupName(Record *Pred) {
+ std::string Name = Pred->getName();
+ for (char& c : Name) {
+ c = toupper(c);
+ }
+ if (Name.length() >= 7 && Name.substr(0, 7) == "FEATURE") {
+ Name = Name.substr(7);
+ }
+ return "SYSZ_GRP_" + Name;
+}
+
+void EmitMappingInsn(RecordKeeper &RK, raw_ostream &OS) {
+ OS << "// This is auto-gen data for Capstone engine (www.capstone-engine.org)\n"
+ "// By Nguyen Anh Quynh <aquynh@gmail.com>\n"
+ "\n";
+ CodeGenTarget Target(RK);
+ for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
+ if (Inst->TheDef->getValueAsBit("isPseudo") ||
+ Inst->TheDef->getValueAsBit("isCodeGenOnly")) {
+ continue;
+ }
+ OS << "{\n"
+ << "\t" << Target.getName() << "_" << Inst->TheDef->getName() << ", "
+ << GetPublicName(Inst) << ",\n"
+ << "#ifndef CAPSTONE_DIET\n"
+ << "\t{ ";
+ for (Record *Use : Inst->TheDef->getValueAsListOfDefs("Uses")) {
+ OS << GetRegisterName(Use) << ", ";
+ }
+ OS << "0 }, { ";
+ for (Record *Def : Inst->TheDef->getValueAsListOfDefs("Defs")) {
+ OS << GetRegisterName(Def) << ", ";
+ }
+ OS << "0 }, { ";
+ ListInit *Predicates = Inst->TheDef->getValueAsListInit("Predicates");
+ for (unsigned i = 0; i < Predicates->size(); ++i) {
+ OS << GetGroupName(Predicates->getElementAsRecord(i)) << ", ";
+ }
+ OS << "0 }, "
+ << Inst->TheDef->getValueAsBit("isBranch")
+ << ", "
+ << Inst->TheDef->getValueAsBit("isIndirectBranch")
+ << "\n"
+ << "#endif\n"
+ << "},\n";
+ }
+}
+#endif
+
} // end llvm namespace
diff --git a/utils/TableGen/TableGen.cpp b/utils/TableGen/TableGen.cpp
index cf1404d8769..bbb4e860536 100644
--- a/utils/TableGen/TableGen.cpp
+++ b/utils/TableGen/TableGen.cpp
@@ -27,6 +27,7 @@ enum ActionType {
GenEmitter,
GenRegisterInfo,
GenInstrInfo,
+ MappingInsn,
GenInstrDocs,
GenAsmWriter,
GenAsmMatcher,
@@ -65,6 +66,8 @@ namespace {
"Generate registers and register classes info"),
clEnumValN(GenInstrInfo, "gen-instr-info",
"Generate instruction descriptions"),
+ clEnumValN(MappingInsn, "mapping-insn",
+ ""),
clEnumValN(GenInstrDocs, "gen-instr-docs",
"Generate instruction documentation"),
clEnumValN(GenCallingConv, "gen-callingconv",
@@ -135,6 +138,9 @@ bool LLVMTableGenMain(raw_ostream &OS, RecordKeeper &Records) {
case GenInstrInfo:
EmitInstrInfo(Records, OS);
break;
+ case MappingInsn:
+ EmitMappingInsn(Records, OS);
+ break;
case GenInstrDocs:
EmitInstrDocs(Records, OS);
break;
diff --git a/utils/TableGen/TableGenBackends.h b/utils/TableGen/TableGenBackends.h
index 1329a6d833f..a41e46b1db0 100644
--- a/utils/TableGen/TableGenBackends.h
+++ b/utils/TableGen/TableGenBackends.h
@@ -75,6 +75,7 @@ void EmitDFAPacketizer(RecordKeeper &RK, raw_ostream &OS);
void EmitDisassembler(RecordKeeper &RK, raw_ostream &OS);
void EmitFastISel(RecordKeeper &RK, raw_ostream &OS);
void EmitInstrInfo(RecordKeeper &RK, raw_ostream &OS);
+void EmitMappingInsn(RecordKeeper &RK, raw_ostream &OS);
void EmitInstrDocs(RecordKeeper &RK, raw_ostream &OS);
void EmitPseudoLowering(RecordKeeper &RK, raw_ostream &OS);
void EmitCompressInst(RecordKeeper &RK, raw_ostream &OS);
--
2.19.1