mirror of
https://github.com/hedge-dev/XenonRecomp.git
synced 2025-07-24 22:13:57 +00:00
Initial Commit
This commit is contained in:
Sajid
3
thirdparty/capstone/suite/MC/AArch64/a64-ignored-fields.txt.cs
vendored
Normal file
3
thirdparty/capstone/suite/MC/AArch64/a64-ignored-fields.txt.cs
vendored
Normal file
@@ -0,0 +1,3 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0xe8,0x23,0x20,0x1e == fcmp s31, #0.0
|
||||
346
thirdparty/capstone/suite/MC/AArch64/add.s.cs
vendored
Normal file
346
thirdparty/capstone/suite/MC/AArch64/add.s.cs
vendored
Normal file
@@ -0,0 +1,346 @@
|
||||
# CS_ARCH_AARCH64, None, None
|
||||
0xc160a300 == {z0.h, z1.h}, {z0.h, z1.h}, z0.h
|
||||
0xc165a314 == {z20.h, z21.h}, {z20.h, z21.h}, z5.h
|
||||
0xc168a316 == {z22.h, z23.h}, {z22.h, z23.h}, z8.h
|
||||
0xc16fa31e == {z30.h, z31.h}, {z30.h, z31.h}, z15.h
|
||||
0xc1a01c10 == za.s[w8, 0, vgx2], {z0.s, z1.s}
|
||||
0xc1a01c10 == za.s[w8, 0], {z0.s, z1.s}
|
||||
0xc1a05d55 == za.s[w10, 5, vgx2], {z10.s, z11.s}
|
||||
0xc1a05d55 == za.s[w10, 5], {z10.s, z11.s}
|
||||
0xc1a07d97 == za.s[w11, 7, vgx2], {z12.s, z13.s}
|
||||
0xc1a07d97 == za.s[w11, 7], {z12.s, z13.s}
|
||||
0xc1a07fd7 == za.s[w11, 7, vgx2], {z30.s, z31.s}
|
||||
0xc1a07fd7 == za.s[w11, 7], {z30.s, z31.s}
|
||||
0xc1a01e15 == za.s[w8, 5, vgx2], {z16.s, z17.s}
|
||||
0xc1a01e15 == za.s[w8, 5], {z16.s, z17.s}
|
||||
0xc1a01c11 == za.s[w8, 1, vgx2], {z0.s, z1.s}
|
||||
0xc1a01c11 == za.s[w8, 1], {z0.s, z1.s}
|
||||
0xc1a05e50 == za.s[w10, 0, vgx2], {z18.s, z19.s}
|
||||
0xc1a05e50 == za.s[w10, 0], {z18.s, z19.s}
|
||||
0xc1a01d90 == za.s[w8, 0], {z12.s, z13.s}
|
||||
0xc1a05c11 == za.s[w10, 1, vgx2], {z0.s, z1.s}
|
||||
0xc1a05c11 == za.s[w10, 1], {z0.s, z1.s}
|
||||
0xc1a01ed5 == za.s[w8, 5, vgx2], {z22.s, z23.s}
|
||||
0xc1a01ed5 == za.s[w8, 5], {z22.s, z23.s}
|
||||
0xc1a07d12 == za.s[w11, 2, vgx2], {z8.s, z9.s}
|
||||
0xc1a07d12 == za.s[w11, 2], {z8.s, z9.s}
|
||||
0xc1a03d97 == za.s[w9, 7, vgx2], {z12.s, z13.s}
|
||||
0xc1a03d97 == za.s[w9, 7], {z12.s, z13.s}
|
||||
0xc1201810 == za.s[w8, 0, vgx2], {z0.s, z1.s}, z0.s
|
||||
0xc1201810 == za.s[w8, 0], {z0.s - z1.s}, z0.s
|
||||
0xc1255955 == za.s[w10, 5, vgx2], {z10.s, z11.s}, z5.s
|
||||
0xc1255955 == za.s[w10, 5], {z10.s - z11.s}, z5.s
|
||||
0xc12879b7 == za.s[w11, 7, vgx2], {z13.s, z14.s}, z8.s
|
||||
0xc12879b7 == za.s[w11, 7], {z13.s - z14.s}, z8.s
|
||||
0x1825ebbf7 == (faulty numer in LLVM. 1 or 0?) za.s[w11, 7, vgx2], {z31.s, z0.s}, z15.s
|
||||
0x1825efbf7 == (faulty numer in LLVM. 1 or 0?) za.s[w11, 7, vgx2], {z31.s, z0.s}, z15.s
|
||||
0xc12f7bf7 == za.s[w11, 7], {z31.s - z0.s}, z15.s
|
||||
0xc1201a35 == za.s[w8, 5, vgx2], {z17.s, z18.s}, z0.s
|
||||
0xc1201a35 == za.s[w8, 5], {z17.s - z18.s}, z0.s
|
||||
0xc12e1831 == za.s[w8, 1, vgx2], {z1.s, z2.s}, z14.s
|
||||
0xc12e1831 == za.s[w8, 1], {z1.s - z2.s}, z14.s
|
||||
0xc1245a70 == za.s[w10, 0, vgx2], {z19.s, z20.s}, z4.s
|
||||
0xc1245a70 == za.s[w10, 0], {z19.s - z20.s}, z4.s
|
||||
0xc1221990 == za.s[w8, 0, vgx2], {z12.s, z13.s}, z2.s
|
||||
0xc1221990 == za.s[w8, 0], {z12.s - z13.s}, z2.s
|
||||
0xc12a5831 == za.s[w10, 1, vgx2], {z1.s, z2.s}, z10.s
|
||||
0xc12a5831 == za.s[w10, 1], {z1.s - z2.s}, z10.s
|
||||
0xc12e1ad5 == za.s[w8, 5, vgx2], {z22.s, z23.s}, z14.s
|
||||
0xc12e1ad5 == za.s[w8, 5], {z22.s - z23.s}, z14.s
|
||||
0xc1217932 == za.s[w11, 2, vgx2], {z9.s, z10.s}, z1.s
|
||||
0xc1217932 == za.s[w11, 2], {z9.s - z10.s}, z1.s
|
||||
0xc12b3997 == za.s[w9, 7, vgx2], {z12.s, z13.s}, z11.s
|
||||
0xc12b3997 == za.s[w9, 7], {z12.s - z13.s}, z11.s
|
||||
0xc1a0a300 == {z0.s-z1.s}, {z0.s-z1.s}, z0.s
|
||||
0xc1a5a314 == {z20.s-z21.s}, {z20.s-z21.s}, z5.s
|
||||
0xc1a8a316 == {z22.s-z23.s}, {z22.s-z23.s}, z8.s
|
||||
0xc1afa31e == {z30.s-z31.s}, {z30.s-z31.s}, z15.s
|
||||
0xc1a01810 == za.s[w8, 0, vgx2], {z0.s, z1.s}, {z0.s, z1.s}
|
||||
0xc1a01810 == za.s[w8, 0], {z0.s - z1.s}, {z0.s - z1.s}
|
||||
0xc1b45955 == za.s[w10, 5, vgx2], {z10.s, z11.s}, {z20.s, z21.s}
|
||||
0xc1b45955 == za.s[w10, 5], {z10.s - z11.s}, {z20.s - z21.s}
|
||||
0xc1a87997 == za.s[w11, 7, vgx2], {z12.s, z13.s}, {z8.s, z9.s}
|
||||
0xc1a87997 == za.s[w11, 7], {z12.s - z13.s}, {z8.s - z9.s}
|
||||
0xc1be7bd7 == za.s[w11, 7, vgx2], {z30.s, z31.s}, {z30.s, z31.s}
|
||||
0xc1be7bd7 == za.s[w11, 7], {z30.s - z31.s}, {z30.s - z31.s}
|
||||
0xc1b01a15 == za.s[w8, 5, vgx2], {z16.s, z17.s}, {z16.s, z17.s}
|
||||
0xc1b01a15 == za.s[w8, 5], {z16.s - z17.s}, {z16.s - z17.s}
|
||||
0xc1be1811 == za.s[w8, 1, vgx2], {z0.s, z1.s}, {z30.s, z31.s}
|
||||
0xc1be1811 == za.s[w8, 1], {z0.s - z1.s}, {z30.s - z31.s}
|
||||
0xc1b45a50 == za.s[w10, 0, vgx2], {z18.s, z19.s}, {z20.s, z21.s}
|
||||
0xc1b45a50 == za.s[w10, 0], {z18.s - z19.s}, {z20.s - z21.s}
|
||||
0xc1a21990 == za.s[w8, 0, vgx2], {z12.s, z13.s}, {z2.s, z3.s}
|
||||
0xc1a21990 == za.s[w8, 0], {z12.s - z13.s}, {z2.s - z3.s}
|
||||
0xc1ba5811 == za.s[w10, 1, vgx2], {z0.s, z1.s}, {z26.s, z27.s}
|
||||
0xc1ba5811 == za.s[w10, 1], {z0.s - z1.s}, {z26.s - z27.s}
|
||||
0xc1be1ad5 == za.s[w8, 5, vgx2], {z22.s, z23.s}, {z30.s, z31.s}
|
||||
0xc1be1ad5 == za.s[w8, 5], {z22.s - z23.s}, {z30.s - z31.s}
|
||||
0xc1a07912 == za.s[w11, 2, vgx2], {z8.s, z9.s}, {z0.s, z1.s}
|
||||
0xc1a07912 == za.s[w11, 2], {z8.s - z9.s}, {z0.s - z1.s}
|
||||
0xc1aa3997 == za.s[w9, 7, vgx2], {z12.s, z13.s}, {z10.s, z11.s}
|
||||
0xc1aa3997 == za.s[w9, 7], {z12.s - z13.s}, {z10.s - z11.s}
|
||||
0xc1e01c10 == za.d[w8, 0, vgx2], {z0.d, z1.d}
|
||||
0xc1e01c10 == za.d[w8, 0], {z0.d, z1.d}
|
||||
0xc1e05d55 == za.d[w10, 5, vgx2], {z10.d, z11.d}
|
||||
0xc1e05d55 == za.d[w10, 5], {z10.d, z11.d}
|
||||
0xc1e07d97 == za.d[w11, 7, vgx2], {z12.d, z13.d}
|
||||
0xc1e07d97 == za.d[w11, 7], {z12.d, z13.d}
|
||||
0xc1e07fd7 == za.d[w11, 7, vgx2], {z30.d, z31.d}
|
||||
0xc1e07fd7 == za.d[w11, 7], {z30.d, z31.d}
|
||||
0xc1e01e15 == za.d[w8, 5, vgx2], {z16.d, z17.d}
|
||||
0xc1e01e15 == za.d[w8, 5], {z16.d, z17.d}
|
||||
0xc1e01c11 == za.d[w8, 1, vgx2], {z0.d, z1.d}
|
||||
0xc1e01c11 == za.d[w8, 1], {z0.d, z1.d}
|
||||
0xc1e05e50 == za.d[w10, 0, vgx2], {z18.d, z19.d}
|
||||
0xc1e05e50 == za.d[w10, 0], {z18.d, z19.d}
|
||||
0xc1e01d90 == za.d[w8, 0, vgx2], {z12.d, z13.d}
|
||||
0xc1e01d90 == za.d[w8, 0], {z12.d, z13.d}
|
||||
0xc1e05c11 == za.d[w10, 1, vgx2], {z0.d, z1.d}
|
||||
0xc1e05c11 == za.d[w10, 1], {z0.d, z1.d}
|
||||
0xc1e01ed5 == za.d[w8, 5, vgx2], {z22.d, z23.d}
|
||||
0xc1e01ed5 == za.d[w8, 5], {z22.d, z23.d}
|
||||
0xc1e07d12 == za.d[w11, 2, vgx2], {z8.d, z9.d}
|
||||
0xc1e07d12 == za.d[w11, 2], {z8.d, z9.d}
|
||||
0xc1e03d97 == za.d[w9, 7, vgx2], {z12.d, z13.d}
|
||||
0xc1e03d97 == za.d[w9, 7], {z12.d, z13.d}
|
||||
0xc1601810 == za.d[w8, 0, vgx2], {z0.d, z1.d}, z0.d
|
||||
0xc1601810 == za.d[w8, 0], {z0.d - z1.d}, z0.d
|
||||
0xc1655955 == za.d[w10, 5, vgx2], {z10.d, z11.d}, z5.d
|
||||
0xc1655955 == za.d[w10, 5], {z10.d - z11.d}, z5.d
|
||||
0xc16879b7 == za.d[w11, 7, vgx2], {z13.d, z14.d}, z8.d
|
||||
0xc16879b7 == (1 or 0?) za.d[w11, 7], {z13.d - z14.d}, z8.d
|
||||
0x182debbf7 == (1 or 0?) za.d[w11, 7, vgx2], {z31.d, z0.d}, z15.d
|
||||
0x182defbf7 == za.d[w11, 7, vgx2], {z31.d, z0.d}, z15.d
|
||||
0xc16f7bf7 == za.d[w11, 7], {z31.d - z0.d}, z15.d
|
||||
0xc1601a35 == za.d[w8, 5, vgx2], {z17.d, z18.d}, z0.d
|
||||
0xc1601a35 == za.d[w8, 5], {z17.d - z18.d}, z0.d
|
||||
0xc16e1831 == za.d[w8, 1, vgx2], {z1.d, z2.d}, z14.d
|
||||
0xc16e1831 == za.d[w8, 1], {z1.d - z2.d}, z14.d
|
||||
0xc1645a70 == za.d[w10, 0, vgx2], {z19.d, z20.d}, z4.d
|
||||
0xc1645a70 == za.d[w10, 0], {z19.d - z20.d}, z4.d
|
||||
0xc1621990 == za.d[w8, 0, vgx2], {z12.d, z13.d}, z2.d
|
||||
0xc1621990 == za.d[w8, 0], {z12.d - z13.d}, z2.d
|
||||
0xc16a5831 == za.d[w10, 1, vgx2], {z1.d, z2.d}, z10.d
|
||||
0xc16a5831 == za.d[w10, 1], {z1.d - z2.d}, z10.d
|
||||
0xc16e1ad5 == za.d[w8, 5, vgx2], {z22.d, z23.d}, z14.d
|
||||
0xc16e1ad5 == za.d[w8, 5], {z22.d - z23.d}, z14.d
|
||||
0xc1617932 == za.d[w11, 2, vgx2], {z9.d, z10.d}, z1.d
|
||||
0xc1617932 == za.d[w11, 2], {z9.d - z10.d}, z1.d
|
||||
0xc16b3997 == za.d[w9, 7, vgx2], {z12.d, z13.d}, z11.d
|
||||
0xc16b3997 == za.d[w9, 7], {z12.d - z13.d}, z11.d
|
||||
0xc1e0a300 == {z0.d-z1.d}, {z0.d-z1.d}, z0.d
|
||||
0xc1e5a314 == {z20.d-z21.d}, {z20.d-z21.d}, z5.d
|
||||
0xc1e8a316 == {z22.d-z23.d}, {z22.d-z23.d}, z8.d
|
||||
0xc1efa31e == {z30.d-z31.d}, {z30.d-z31.d}, z15.d
|
||||
0xc1e01810 == za.d[w8, 0, vgx2], {z0.d, z1.d}, {z0.d, z1.d}
|
||||
0xc1e01810 == za.d[w8, 0], {z0.d - z1.d}, {z0.d - z1.d}
|
||||
0xc1f45955 == za.d[w10, 5, vgx2], {z10.d, z11.d}, {z20.d, z21.d}
|
||||
0xc1f45955 == za.d[w10, 5], {z10.d - z11.d}, {z20.d - z21.d}
|
||||
0xc1e87997 == za.d[w11, 7, vgx2], {z12.d, z13.d}, {z8.d, z9.d}
|
||||
0xc1e87997 == za.d[w11, 7], {z12.d - z13.d}, {z8.d - z9.d}
|
||||
0xc1fe7bd7 == za.d[w11, 7, vgx2], {z30.d, z31.d}, {z30.d, z31.d}
|
||||
0xc1fe7bd7 == za.d[w11, 7], {z30.d - z31.d}, {z30.d - z31.d}
|
||||
0xc1f01a15 == za.d[w8, 5, vgx2], {z16.d, z17.d}, {z16.d, z17.d}
|
||||
0xc1f01a15 == za.d[w8, 5], {z16.d - z17.d}, {z16.d - z17.d}
|
||||
0xc1fe1811 == za.d[w8, 1, vgx2], {z0.d, z1.d}, {z30.d, z31.d}
|
||||
0xc1fe1811 == za.d[w8, 1], {z0.d - z1.d}, {z30.d - z31.d}
|
||||
0xc1f45a50 == za.d[w10, 0, vgx2], {z18.d, z19.d}, {z20.d, z21.d}
|
||||
0xc1f45a50 == za.d[w10, 0], {z18.d - z19.d}, {z20.d - z21.d}
|
||||
0xc1e21990 == za.d[w8, 0, vgx2], {z12.d, z13.d}, {z2.d, z3.d}
|
||||
0xc1e21990 == za.d[w8, 0], {z12.d - z13.d}, {z2.d - z3.d}
|
||||
0xc1fa5811 == za.d[w10, 1, vgx2], {z0.d, z1.d}, {z26.d, z27.d}
|
||||
0xc1fa5811 == za.d[w10, 1], {z0.d - z1.d}, {z26.d - z27.d}
|
||||
0xc1fe1ad5 == za.d[w8, 5, vgx2], {z22.d, z23.d}, {z30.d, z31.d}
|
||||
0xc1fe1ad5 == za.d[w8, 5], {z22.d - z23.d}, {z30.d - z31.d}
|
||||
0xc1e07912 == za.d[w11, 2, vgx2], {z8.d, z9.d}, {z0.d, z1.d}
|
||||
0xc1e07912 == za.d[w11, 2], {z8.d - z9.d}, {z0.d - z1.d}
|
||||
0xc1ea3997 == za.d[w9, 7, vgx2], {z12.d, z13.d}, {z10.d, z11.d}
|
||||
0xc1ea3997 == za.d[w9, 7], {z12.d - z13.d}, {z10.d - z11.d}
|
||||
0xc120a300 == {z0.b-z1.b}, {z0.b-z1.b}, z0.b
|
||||
0xc125a314 == {z20.b-z21.b}, {z20.b-z21.b}, z5.b
|
||||
0xc128a316 == {z22.b-z23.b}, {z22.b-z23.b}, z8.b
|
||||
0xc12fa31e == {z30.b-z31.b}, {z30.b-z31.b}, z15.b
|
||||
0xc160ab00 == {z0.h - z3.h}, {z0.h - z3.h}, z0.h
|
||||
0xc165ab14 == {z20.h - z23.h}, {z20.h - z23.h}, z5.h
|
||||
0xc168ab14 == {z20.h - z23.h}, {z20.h - z23.h}, z8.h
|
||||
0xc16fab1c == {z28.h - z31.h}, {z28.h - z31.h}, z15.h
|
||||
0xc1a11c10 == za.s[w8, 0, vgx4], {z0.s - z3.s}
|
||||
0xc1a11c10 == za.s[w8, 0], {z0.s - z3.s}
|
||||
0xc1a15d15 == za.s[w10, 5, vgx4], {z8.s - z11.s}
|
||||
0xc1a15d15 == za.s[w10, 5], {z8.s - z11.s}
|
||||
0xc1a17d97 == za.s[w11, 7, vgx4], {z12.s - z15.s}
|
||||
0xc1a17d97 == za.s[w11, 7], {z12.s - z15.s}
|
||||
0xc1a17f97 == za.s[w11, 7, vgx4], {z28.s - z31.s}
|
||||
0xc1a17f97 == za.s[w11, 7], {z28.s - z31.s}
|
||||
0xc1a11e15 == za.s[w8, 5, vgx4], {z16.s - z19.s}
|
||||
0xc1a11e15 == za.s[w8, 5], {z16.s - z19.s}
|
||||
0xc1a11c11 == za.s[w8, 1, vgx4], {z0.s - z3.s}
|
||||
0xc1a11c11 == za.s[w8, 1], {z0.s - z3.s}
|
||||
0xc1a15e10 == za.s[w10, 0, vgx4], {z16.s - z19.s}
|
||||
0xc1a15e10 == za.s[w10, 0], {z16.s - z19.s}
|
||||
0xc1a11d90 == za.s[w8, 0, vgx4], {z12.s - z15.s}
|
||||
0xc1a11d90 == za.s[w8, 0], {z12.s - z15.s}
|
||||
0xc1a15c11 == za.s[w10, 1, vgx4], {z0.s - z3.s}
|
||||
0xc1a15c11 == za.s[w10, 1], {z0.s - z3.s}
|
||||
0xc1a11e95 == za.s[w8, 5, vgx4], {z20.s - z23.s}
|
||||
0xc1a11e95 == za.s[w8, 5], {z20.s - z23.s}
|
||||
0xc1a17d12 == za.s[w11, 2, vgx4], {z8.s - z11.s}
|
||||
0xc1a17d12 == za.s[w11, 2], {z8.s - z11.s}
|
||||
0xc1a13d97 == za.s[w9, 7, vgx4], {z12.s - z15.s}
|
||||
0xc1a13d97 == za.s[w9, 7], {z12.s - z15.s}
|
||||
0xc1301810 == za.s[w8, 0, vgx4], {z0.s - z3.s}, z0.s
|
||||
0xc1301810 == za.s[w8, 0], {z0.s - z3.s}, z0.s
|
||||
0xc1355955 == za.s[w10, 5, vgx4], {z10.s - z13.s}, z5.s
|
||||
0xc1355955 == za.s[w10, 5], {z10.s - z13.s}, z5.s
|
||||
0xc13879b7 == za.s[w11, 7, vgx4], {z13.s - z16.s}, z8.s
|
||||
0xc13879b7 == za.s[w11, 7], {z13.s - z16.s}, z8.s
|
||||
0xc13f7bf7 == za.s[w11, 7, vgx4], {z31.s - z2.s}, z15.s
|
||||
0xc13f7bf7 == za.s[w11, 7], {z31.s - z2.s}, z15.s
|
||||
0xc1301a35 == za.s[w8, 5, vgx4], {z17.s - z20.s}, z0.s
|
||||
0xc1301a35 == za.s[w8, 5], {z17.s - z20.s}, z0.s
|
||||
0xc13e1831 == za.s[w8, 1, vgx4], {z1.s - z4.s}, z14.s
|
||||
0xc13e1831 == za.s[w8, 1], {z1.s - z4.s}, z14.s
|
||||
0xc1345a70 == za.s[w10, 0, vgx4], {z19.s - z22.s}, z4.s
|
||||
0xc1345a70 == za.s[w10, 0], {z19.s - z22.s}, z4.s
|
||||
0xc1321990 == za.s[w8, 0, vgx4], {z12.s - z15.s}, z2.s
|
||||
0xc1321990 == za.s[w8, 0], {z12.s - z15.s}, z2.s
|
||||
0xc13a5831 == za.s[w10, 1, vgx4], {z1.s - z4.s}, z10.s
|
||||
0xc13a5831 == za.s[w10, 1], {z1.s - z4.s}, z10.s
|
||||
0xc13e1ad5 == za.s[w8, 5, vgx4], {z22.s - z25.s}, z14.s
|
||||
0xc13e1ad5 == za.s[w8, 5], {z22.s - z25.s}, z14.s
|
||||
0xc1317932 == za.s[w11, 2, vgx4], {z9.s - z12.s}, z1.s
|
||||
0xc1317932 == za.s[w11, 2], {z9.s - z12.s}, z1.s
|
||||
0xc13b3997 == za.s[w9, 7, vgx4], {z12.s - z15.s}, z11.s
|
||||
0xc13b3997 == za.s[w9, 7], {z12.s - z15.s}, z11.s
|
||||
0xc1a0ab00 == {z0.s-z3.s}, {z0.s-z3.s}, z0.s
|
||||
0xc1a5ab14 == {z20.s-z23.s}, {z20.s-z23.s}, z5.s
|
||||
0xc1a8ab14 == {z20.s-z23.s}, {z20.s-z23.s}, z8.s
|
||||
0xc1afab1c == {z28.s-z31.s}, {z28.s-z31.s}, z15.s
|
||||
0xc1a11810 == za.s[w8, 0, vgx4], {z0.s-z3.s}, {z0.s-z3.s}
|
||||
0xc1a11810 == za.s[w8, 0], {z0.s-z3.s}, {z0.s-z3.s}
|
||||
0xc1b55915 == za.s[w10, 5, vgx4], {z8.s - z11.s}, {z20.s - z23.s}
|
||||
0xc1b55915 == za.s[w10, 5], {z8.s - z11.s}, {z20.s - z23.s}
|
||||
0xc1a97997 == za.s[w11, 7, vgx4], {z12.s - z15.s}, {z8.s - z11.s}
|
||||
0xc1a97997 == za.s[w11, 7], {z12.s - z15.s}, {z8.s - z11.s}
|
||||
0xc1bd7b97 == za.s[w11, 7, vgx4], {z28.s - z31.s}, {z28.s - z31.s}
|
||||
0xc1bd7b97 == za.s[w11, 7], {z28.s - z31.s}, {z28.s - z31.s}
|
||||
0xc1b11a15 == za.s[w8, 5, vgx4], {z16.s - z19.s}, {z16.s - z19.s}
|
||||
0xc1b11a15 == za.s[w8, 5], {z16.s - z19.s}, {z16.s - z19.s}
|
||||
0xc1bd1811 == za.s[w8, 1, vgx4], {z0.s - z3.s}, {z28.s - z31.s}
|
||||
0xc1bd1811 == za.s[w8, 1], {z0.s - z3.s}, {z28.s - z31.s}
|
||||
0xc1b55a10 == za.s[w10, 0, vgx4], {z16.s - z19.s}, {z20.s - z23.s}
|
||||
0xc1b55a10 == za.s[w10, 0], {z16.s - z19.s}, {z20.s - z23.s}
|
||||
0xc1a11990 == za.s[w8, 0, vgx4], {z12.s - z15.s}, {z0.s - z3.s}
|
||||
0xc1a11990 == za.s[w8, 0], {z12.s - z15.s}, {z0.s - z3.s}
|
||||
0xc1b95811 == za.s[w10, 1, vgx4], {z0.s - z3.s}, {z24.s - z27.s}
|
||||
0xc1b95811 == za.s[w10, 1], {z0.s - z3.s}, {z24.s - z27.s}
|
||||
0xc1bd1a95 == za.s[w8, 5, vgx4], {z20.s - z23.s}, {z28.s - z31.s}
|
||||
0xc1bd1a95 == za.s[w8, 5], {z20.s - z23.s}, {z28.s - z31.s}
|
||||
0xc1a17912 == za.s[w11, 2, vgx4], {z8.s - z11.s}, {z0.s - z3.s}
|
||||
0xc1a17912 == za.s[w11, 2], {z8.s - z11.s}, {z0.s - z3.s}
|
||||
0xc1a93997 == za.s[w9, 7, vgx4], {z12.s - z15.s}, {z8.s - z11.s}
|
||||
0xc1a93997 == za.s[w9, 7], {z12.s - z15.s}, {z8.s - z11.s}
|
||||
0xc1e11c10 == za.d[w8, 0, vgx4], {z0.d - z3.d}
|
||||
0xc1e11c10 == za.d[w8, 0], {z0.d - z3.d}
|
||||
0xc1e15d15 == za.d[w10, 5, vgx4], {z8.d - z11.d}
|
||||
0xc1e15d15 == za.d[w10, 5], {z8.d - z11.d}
|
||||
0xc1e17d97 == za.d[w11, 7, vgx4], {z12.d - z15.d}
|
||||
0xc1e17d97 == za.d[w11, 7], {z12.d - z15.d}
|
||||
0xc1e17f97 == za.d[w11, 7, vgx4], {z28.d - z31.d}
|
||||
0xc1e17f97 == za.d[w11, 7], {z28.d - z31.d}
|
||||
0xc1e11e15 == za.d[w8, 5, vgx4], {z16.d - z19.d}
|
||||
0xc1e11e15 == za.d[w8, 5], {z16.d - z19.d}
|
||||
0xc1e11c11 == za.d[w8, 1, vgx4], {z0.d - z3.d}
|
||||
0xc1e11c11 == za.d[w8, 1], {z0.d - z3.d}
|
||||
0xc1e15e10 == za.d[w10, 0, vgx4], {z16.d - z19.d}
|
||||
0xc1e15e10 == za.d[w10, 0], {z16.d - z19.d}
|
||||
0xc1e11d90 == za.d[w8, 0, vgx4], {z12.d - z15.d}
|
||||
0xc1e11d90 == za.d[w8, 0], {z12.d - z15.d}
|
||||
0xc1e15c11 == za.d[w10, 1, vgx4], {z0.d - z3.d}
|
||||
0xc1e15c11 == za.d[w10, 1], {z0.d - z3.d}
|
||||
0xc1e11e95 == za.d[w8, 5, vgx4], {z20.d - z23.d}
|
||||
0xc1e11e95 == za.d[w8, 5], {z20.d - z23.d}
|
||||
0xc1e17d12 == za.d[w11, 2, vgx4], {z8.d - z11.d}
|
||||
0xc1e17d12 == za.d[w11, 2], {z8.d - z11.d}
|
||||
0xc1e13d97 == za.d[w9, 7, vgx4], {z12.d - z15.d}
|
||||
0xc1e13d97 == za.d[w9, 7], {z12.d - z15.d}
|
||||
0xc1701810 == za.d[w8, 0, vgx4], {z0.d - z3.d}, z0.d
|
||||
0xc1701810 == za.d[w8, 0], {z0.d - z3.d}, z0.d
|
||||
0xc1755955 == za.d[w10, 5, vgx4], {z10.d - z13.d}, z5.d
|
||||
0xc1755955 == za.d[w10, 5], {z10.d - z13.d}, z5.d
|
||||
0xc17879b7 == za.d[w11, 7, vgx4], {z13.d - z16.d}, z8.d
|
||||
0xc17879b7 == za.d[w11, 7], {z13.d - z16.d}, z8.d
|
||||
0xc17f7bf7 == za.d[w11, 7, vgx4], {z31.d - z2.d}, z15.d
|
||||
0xc17f7bf7 == za.d[w11, 7], {z31.d - z2.d}, z15.d
|
||||
0xc1701a35 == za.d[w8, 5, vgx4], {z17.d - z20.d}, z0.d
|
||||
0xc1701a35 == za.d[w8, 5], {z17.d - z20.d}, z0.d
|
||||
0xc17e1831 == za.d[w8, 1, vgx4], {z1.d - z4.d}, z14.d
|
||||
0xc17e1831 == za.d[w8, 1], {z1.d - z4.d}, z14.d
|
||||
0xc1745a70 == za.d[w10, 0, vgx4], {z19.d - z22.d}, z4.d
|
||||
0xc1745a70 == za.d[w10, 0], {z19.d - z22.d}, z4.d
|
||||
0xc1721990 == za.d[w8, 0, vgx4], {z12.d - z15.d}, z2.d
|
||||
0xc1721990 == za.d[w8, 0], {z12.d - z15.d}, z2.d
|
||||
0xc17a5831 == za.d[w10, 1, vgx4], {z1.d - z4.d}, z10.d
|
||||
0xc17a5831 == za.d[w10, 1], {z1.d - z4.d}, z10.d
|
||||
0xc17e1ad5 == za.d[w8, 5, vgx4], {z22.d - z25.d}, z14.d
|
||||
0xc17e1ad5 == za.d[w8, 5], {z22.d - z25.d}, z14.d
|
||||
0xc1717932 == za.d[w11, 2, vgx4], {z9.d - z12.d}, z1.d
|
||||
0xc1717932 == za.d[w11, 2], {z9.d - z12.d}, z1.d
|
||||
0xc17b3997 == za.d[w9, 7, vgx4], {z12.d - z15.d}, z11.d
|
||||
0xc17b3997 == za.d[w9, 7], {z12.d - z15.d}, z11.d
|
||||
0xc1e11810 == za.d[w8, 0, vgx4], {z0.d - z3.d}, {z0.d - z3.d}
|
||||
0xc1e11810 == za.d[w8, 0], {z0.d - z3.d}, {z0.d - z3.d}
|
||||
0xc1f55915 == za.d[w10, 5, vgx4], {z8.d - z11.d}, {z20.d - z23.d}
|
||||
0xc1f55915 == za.d[w10, 5], {z8.d - z11.d}, {z20.d - z23.d}
|
||||
0xc1e97997 == za.d[w11, 7, vgx4], {z12.d - z15.d}, {z8.d - z11.d}
|
||||
0xc1e97997 == za.d[w11, 7], {z12.d - z15.d}, {z8.d - z11.d}
|
||||
0xc1fd7b97 == za.d[w11, 7, vgx4], {z28.d - z31.d}, {z28.d - z31.d}
|
||||
0xc1fd7b97 == za.d[w11, 7], {z28.d - z31.d}, {z28.d - z31.d}
|
||||
0xc1f11a15 == za.d[w8, 5, vgx4], {z16.d - z19.d}, {z16.d - z19.d}
|
||||
0xc1f11a15 == za.d[w8, 5], {z16.d - z19.d}, {z16.d - z19.d}
|
||||
0xc1fd1811 == za.d[w8, 1, vgx4], {z0.d - z3.d}, {z28.d - z31.d}
|
||||
0xc1fd1811 == za.d[w8, 1], {z0.d - z3.d}, {z28.d - z31.d}
|
||||
0xc1f55a10 == za.d[w10, 0, vgx4], {z16.d - z19.d}, {z20.d - z23.d}
|
||||
0xc1f55a10 == za.d[w10, 0], {z16.d - z19.d}, {z20.d - z23.d}
|
||||
0xc1e11990 == za.d[w8, 0, vgx4], {z12.d - z15.d}, {z0.d - z3.d}
|
||||
0xc1e11990 == za.d[w8, 0], {z12.d - z15.d}, {z0.d - z3.d}
|
||||
0xc1f95811 == za.d[w10, 1, vgx4], {z0.d - z3.d}, {z24.d - z27.d}
|
||||
0xc1f95811 == za.d[w10, 1], {z0.d - z3.d}, {z24.d - z27.d}
|
||||
0xc1fd1a95 == za.d[w8, 5, vgx4], {z20.d - z23.d}, {z28.d - z31.d}
|
||||
0xc1fd1a95 == za.d[w8, 5], {z20.d - z23.d}, {z28.d - z31.d}
|
||||
0xc1e17912 == za.d[w11, 2, vgx4], {z8.d - z11.d}, {z0.d - z3.d}
|
||||
0xc1e17912 == za.d[w11, 2], {z8.d - z11.d}, {z0.d - z3.d}
|
||||
0xc1e93997 == za.d[w9, 7, vgx4], {z12.d - z15.d}, {z8.d - z11.d}
|
||||
0xc1e93997 == za.d[w9, 7], {z12.d - z15.d}, {z8.d - z11.d}
|
||||
0xc1e0ab00 == {z0.d-z3.d}, {z0.d-z3.d}, z0.d
|
||||
0xc1e5ab14 == {z20.d-z23.d}, {z20.d-z23.d}, z5.d
|
||||
0xc1e8ab14 == {z20.d-z23.d}, {z20.d-z23.d}, z8.d
|
||||
0xc1efab1c == {z28.d-z31.d}, {z28.d-z31.d}, z15.d
|
||||
0xc1e11810 == za.d[w8, 0, vgx4], {z0.d - z3.d}, {z0.d - z3.d}
|
||||
0xc1e11810 == za.d[w8, 0], {z0.d - z3.d}, {z0.d - z3.d}
|
||||
0xc1f55915 == za.d[w10, 5, vgx4], {z8.d - z11.d}, {z20.d - z23.d}
|
||||
0xc1f55915 == za.d[w10, 5], {z8.d - z11.d}, {z20.d - z23.d}
|
||||
0xc1e97997 == za.d[w11, 7, vgx4], {z12.d - z15.d}, {z8.d - z11.d}
|
||||
0xc1e97997 == za.d[w11, 7], {z12.d - z15.d}, {z8.d - z11.d}
|
||||
0xc1fd7b97 == za.d[w11, 7, vgx4], {z28.d - z31.d}, {z28.d - z31.d}
|
||||
0xc1fd7b97 == za.d[w11, 7], {z28.d - z31.d}, {z28.d - z31.d}
|
||||
0xc1f11a15 == za.d[w8, 5, vgx4], {z16.d - z19.d}, {z16.d - z19.d}
|
||||
0xc1f11a15 == za.d[w8, 5], {z16.d - z19.d}, {z16.d - z19.d}
|
||||
0xc1fd1811 == za.d[w8, 1, vgx4], {z0.d - z3.d}, {z28.d - z31.d}
|
||||
0xc1fd1811 == za.d[w8, 1], {z0.d - z3.d}, {z28.d - z31.d}
|
||||
0xc1f55a10 == za.d[w10, 0, vgx4], {z16.d - z19.d}, {z20.d - z23.d}
|
||||
0xc1f55a10 == za.d[w10, 0], {z16.d - z19.d}, {z20.d - z23.d}
|
||||
0xc1e11990 == za.d[w8, 0, vgx4], {z12.d - z15.d}, {z0.d - z3.d}
|
||||
0xc1e11990 == za.d[w8, 0], {z12.d - z15.d}, {z0.d - z3.d}
|
||||
0xc1f95811 == za.d[w10, 1, vgx4], {z0.d - z3.d}, {z24.d - z27.d}
|
||||
0xc1f95811 == za.d[w10, 1], {z0.d - z3.d}, {z24.d - z27.d}
|
||||
0xc1fd1a95 == za.d[w8, 5, vgx4], {z20.d - z23.d}, {z28.d - z31.d}
|
||||
0xc1fd1a95 == za.d[w8, 5], {z20.d - z23.d}, {z28.d - z31.d}
|
||||
0xc1e17912 == za.d[w11, 2, vgx4], {z8.d - z11.d}, {z0.d - z3.d}
|
||||
0xc1e17912 == za.d[w11, 2], {z8.d - z11.d}, {z0.d - z3.d}
|
||||
0xc1e93997 == za.d[w9, 7, vgx4], {z12.d - z15.d}, {z8.d - z11.d}
|
||||
0xc1e93997 == za.d[w9, 7], {z12.d - z15.d}, {z8.d - z11.d}
|
||||
0xc120ab00 == {z0.b-z3.b}, {z0.b-z3.b}, z0.b
|
||||
0xc125ab14 == {z20.b-z23.b}, {z20.b-z23.b}, z5.b
|
||||
0xc128ab14 == {z20.b-z23.b}, {z20.b-z23.b}, z8.b
|
||||
0xc12fab1c == {z28.b-z31.b}, {z28.b-z31.b}, z15.b
|
||||
17
thirdparty/capstone/suite/MC/AArch64/addqv.s.cs
vendored
Normal file
17
thirdparty/capstone/suite/MC/AArch64/addqv.s.cs
vendored
Normal file
@@ -0,0 +1,17 @@
|
||||
# CS_ARCH_AARCH64, None, None
|
||||
0x4452000 == v0.8h, p0, z0.h
|
||||
0x4453555 == v21.8h, p5, z10.h
|
||||
0x4452db7 == v23.8h, p3, z13.h
|
||||
0x4453fff == v31.8h, p7, z31.h
|
||||
0x4852000 == v0.4s, p0, z0.s
|
||||
0x4853555 == v21.4s, p5, z10.s
|
||||
0x4852db7 == v23.4s, p3, z13.s
|
||||
0x4853fff == v31.4s, p7, z31.s
|
||||
0x4c52000 == v0.2d, p0, z0.d
|
||||
0x4c53555 == v21.2d, p5, z10.d
|
||||
0x4c52db7 == v23.2d, p3, z13.d
|
||||
0x4c53fff == v31.2d, p7, z31.d
|
||||
0x4052000 == v0.16b, p0, z0.b
|
||||
0x4053555 == v21.16b, p5, z10.b
|
||||
0x4052db7 == v23.16b, p3, z13.b
|
||||
0x4053fff == v31.16b, p7, z31.b
|
||||
17
thirdparty/capstone/suite/MC/AArch64/andqv.s.cs
vendored
Normal file
17
thirdparty/capstone/suite/MC/AArch64/andqv.s.cs
vendored
Normal file
@@ -0,0 +1,17 @@
|
||||
# CS_ARCH_AARCH64, None, None
|
||||
0x45e2000 == v0.8h, p0, z0.h
|
||||
0x45e3555 == v21.8h, p5, z10.h
|
||||
0x45e2db7 == v23.8h, p3, z13.h
|
||||
0x45e3fff == v31.8h, p7, z31.h
|
||||
0x49e2000 == v0.4s, p0, z0.s
|
||||
0x49e3555 == v21.4s, p5, z10.s
|
||||
0x49e2db7 == v23.4s, p3, z13.s
|
||||
0x49e3fff == v31.4s, p7, z31.s
|
||||
0x4de2000 == v0.2d, p0, z0.d
|
||||
0x4de3555 == v21.2d, p5, z10.d
|
||||
0x4de2db7 == v23.2d, p3, z13.d
|
||||
0x4de3fff == v31.2d, p7, z31.d
|
||||
0x41e2000 == v0.16b, p0, z0.b
|
||||
0x41e3555 == v21.16b, p5, z10.b
|
||||
0x41e2db7 == v23.16b, p3, z13.b
|
||||
0x41e3fff == v31.16b, p7, z31.b
|
||||
6
thirdparty/capstone/suite/MC/AArch64/arm64-adr.s.cs
vendored
Normal file
6
thirdparty/capstone/suite/MC/AArch64/arm64-adr.s.cs
vendored
Normal file
@@ -0,0 +1,6 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0x00,0x00,0x00,0x10 == adr x0, #0
|
||||
0x00,0x00,0x00,0x30 == adr x0, #1
|
||||
0x00,0x00,0x00,0x90 == adrp x0, #0
|
||||
0x00,0x00,0x00,0xb0 == adrp x0, #4096
|
||||
955
thirdparty/capstone/suite/MC/AArch64/arm64-advsimd.s.cs
vendored
Normal file
955
thirdparty/capstone/suite/MC/AArch64/arm64-advsimd.s.cs
vendored
Normal file
@@ -0,0 +1,955 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
0x00,0xb8,0x20,0x0e = abs v0.8b, v0.8b
|
||||
0x00,0xb8,0x20,0x4e = abs v0.16b, v0.16b
|
||||
0x00,0xb8,0x60,0x0e = abs v0.4h, v0.4h
|
||||
0x00,0xb8,0x60,0x4e = abs v0.8h, v0.8h
|
||||
0x00,0xb8,0xa0,0x0e = abs v0.2s, v0.2s
|
||||
0x00,0xb8,0xa0,0x4e = abs v0.4s, v0.4s
|
||||
0x00,0x84,0x20,0x0e = add v0.8b, v0.8b, v0.8b
|
||||
0x00,0x84,0x20,0x4e = add v0.16b, v0.16b, v0.16b
|
||||
0x00,0x84,0x60,0x0e = add v0.4h, v0.4h, v0.4h
|
||||
0x00,0x84,0x60,0x4e = add v0.8h, v0.8h, v0.8h
|
||||
0x00,0x84,0xa0,0x0e = add v0.2s, v0.2s, v0.2s
|
||||
0x00,0x84,0xa0,0x4e = add v0.4s, v0.4s, v0.4s
|
||||
0x00,0x84,0xe0,0x4e = add v0.2d, v0.2d, v0.2d
|
||||
0x41,0x84,0xe3,0x5e = add d1, d2, d3
|
||||
0x00,0x40,0x20,0x0e = addhn v0.8b, v0.8h, v0.8h
|
||||
0x00,0x40,0x20,0x4e = addhn2 v0.16b, v0.8h, v0.8h
|
||||
0x00,0x40,0x60,0x0e = addhn v0.4h, v0.4s, v0.4s
|
||||
0x00,0x40,0x60,0x4e = addhn2 v0.8h, v0.4s, v0.4s
|
||||
0x00,0x40,0xa0,0x0e = addhn v0.2s, v0.2d, v0.2d
|
||||
0x00,0x40,0xa0,0x4e = addhn2 v0.4s, v0.2d, v0.2d
|
||||
0x00,0xbc,0x20,0x0e = addp v0.8b, v0.8b, v0.8b
|
||||
0x00,0xbc,0x20,0x4e = addp v0.16b, v0.16b, v0.16b
|
||||
0x00,0xbc,0x60,0x0e = addp v0.4h, v0.4h, v0.4h
|
||||
0x00,0xbc,0x60,0x4e = addp v0.8h, v0.8h, v0.8h
|
||||
0x00,0xbc,0xa0,0x0e = addp v0.2s, v0.2s, v0.2s
|
||||
0x00,0xbc,0xa0,0x4e = addp v0.4s, v0.4s, v0.4s
|
||||
0x00,0xbc,0xe0,0x4e = addp v0.2d, v0.2d, v0.2d
|
||||
0x00,0xb8,0xf1,0x5e = addp d0, v0.2d
|
||||
0x00,0xb8,0x31,0x0e = addv b0, v0.8b
|
||||
0x00,0xb8,0x31,0x4e = addv b0, v0.16b
|
||||
0x00,0xb8,0x71,0x0e = addv h0, v0.4h
|
||||
0x00,0xb8,0x71,0x4e = addv h0, v0.8h
|
||||
0x00,0xb8,0xb1,0x4e = addv s0, v0.4s
|
||||
0x60,0x0c,0x08,0x4e = dup v0.2d, x3
|
||||
0x60,0x0c,0x04,0x4e = dup v0.4s, w3
|
||||
0x60,0x0c,0x04,0x0e = dup v0.2s, w3
|
||||
0x60,0x0c,0x02,0x4e = dup v0.8h, w3
|
||||
0x60,0x0c,0x02,0x0e = dup v0.4h, w3
|
||||
0x60,0x0c,0x01,0x4e = dup v0.16b, w3
|
||||
0x60,0x0c,0x01,0x0e = dup v0.8b, w3
|
||||
0x61,0x0c,0x08,0x4e = dup v1.2d, x3
|
||||
0x82,0x0c,0x04,0x4e = dup v2.4s, w4
|
||||
0xa3,0x0c,0x04,0x0e = dup v3.2s, w5
|
||||
0xc4,0x0c,0x02,0x4e = dup v4.8h, w6
|
||||
0xe5,0x0c,0x02,0x0e = dup v5.4h, w7
|
||||
0x06,0x0d,0x01,0x4e = dup v6.16b, w8
|
||||
0x27,0x0d,0x01,0x0e = dup v7.8b, w9
|
||||
0x60,0x04,0x18,0x4e = dup v0.2d, v3.d[1]
|
||||
0x60,0x04,0x0c,0x0e = dup v0.2s, v3.s[1]
|
||||
0x60,0x04,0x0c,0x4e = dup v0.4s, v3.s[1]
|
||||
0x60,0x04,0x06,0x0e = dup v0.4h, v3.h[1]
|
||||
0x60,0x04,0x06,0x4e = dup v0.8h, v3.h[1]
|
||||
0x60,0x04,0x03,0x0e = dup v0.8b, v3.b[1]
|
||||
0x60,0x04,0x03,0x4e = dup v0.16b, v3.b[1]
|
||||
0x27,0x05,0x18,0x4e = dup v7.2d, v9.d[1]
|
||||
0x06,0x05,0x0c,0x0e = dup v6.2s, v8.s[1]
|
||||
0xe5,0x04,0x14,0x4e = dup v5.4s, v7.s[2]
|
||||
0xc4,0x04,0x0e,0x0e = dup v4.4h, v6.h[3]
|
||||
0xa3,0x04,0x12,0x4e = dup v3.8h, v5.h[4]
|
||||
0x82,0x04,0x0b,0x0e = dup v2.8b, v4.b[5]
|
||||
0x61,0x04,0x0d,0x4e = dup v1.16b, v3.b[6]
|
||||
0x83,0x04,0x03,0x5e = mov b3, v4.b[1]
|
||||
0x83,0x04,0x06,0x5e = mov h3, v4.h[1]
|
||||
0x83,0x04,0x0c,0x5e = mov s3, v4.s[1]
|
||||
0x83,0x04,0x18,0x5e = mov d3, v4.d[1]
|
||||
0x83,0x04,0x03,0x5e = mov b3, v4.b[1]
|
||||
0x83,0x04,0x06,0x5e = mov h3, v4.h[1]
|
||||
0x83,0x04,0x0c,0x5e = mov s3, v4.s[1]
|
||||
0x83,0x04,0x18,0x5e = mov d3, v4.d[1]
|
||||
0x83,0x04,0x03,0x5e = mov b3, v4.b[1]
|
||||
0x83,0x04,0x06,0x5e = mov h3, v4.h[1]
|
||||
0x83,0x04,0x0c,0x5e = mov s3, v4.s[1]
|
||||
0x83,0x04,0x18,0x5e = mov d3, v4.d[1]
|
||||
0x83,0x04,0x03,0x5e = mov b3, v4.b[1]
|
||||
0x83,0x04,0x06,0x5e = mov h3, v4.h[1]
|
||||
0x83,0x04,0x0c,0x5e = mov s3, v4.s[1]
|
||||
0x83,0x04,0x18,0x5e = mov d3, v4.d[1]
|
||||
0x43,0x2c,0x14,0x4e = smov x3, v2.s[2]
|
||||
0x43,0x2c,0x14,0x4e = smov x3, v2.s[2]
|
||||
0x43,0x3c,0x14,0x0e = mov w3, v2.s[2]
|
||||
0x43,0x3c,0x14,0x0e = mov w3, v2.s[2]
|
||||
0x43,0x3c,0x18,0x4e = mov x3, v2.d[1]
|
||||
0x43,0x3c,0x18,0x4e = mov x3, v2.d[1]
|
||||
0x62,0x3c,0x1c,0x0e = mov w2, v3.s[3]
|
||||
0xe5,0x3c,0x14,0x0e = mov w5, v7.s[2]
|
||||
0xab,0x3d,0x18,0x4e = mov x11, v13.d[1]
|
||||
0x71,0x3e,0x08,0x4e = mov x17, v19.d[0]
|
||||
0xa2,0x1c,0x18,0x4e = mov v2.d[1], x5
|
||||
0xa2,0x1c,0x0c,0x4e = mov v2.s[1], w5
|
||||
0xa2,0x1c,0x06,0x4e = mov v2.h[1], w5
|
||||
0xa2,0x1c,0x03,0x4e = mov v2.b[1], w5
|
||||
0xa2,0x1c,0x18,0x4e = mov v2.d[1], x5
|
||||
0xa2,0x1c,0x0c,0x4e = mov v2.s[1], w5
|
||||
0xa2,0x1c,0x06,0x4e = mov v2.h[1], w5
|
||||
0xa2,0x1c,0x03,0x4e = mov v2.b[1], w5
|
||||
0xe2,0x45,0x18,0x6e = mov v2.d[1], v15.d[1]
|
||||
0xe2,0x25,0x0c,0x6e = mov v2.s[1], v15.s[1]
|
||||
0xe2,0x15,0x06,0x6e = mov v2.h[1], v15.h[1]
|
||||
0xe2,0x0d,0x03,0x6e = mov v2.b[1], v15.b[1]
|
||||
0xe2,0x05,0x18,0x6e = mov v2.d[1], v15.d[0]
|
||||
0xe2,0x45,0x1c,0x6e = mov v2.s[3], v15.s[2]
|
||||
0xe2,0x35,0x1e,0x6e = mov v2.h[7], v15.h[3]
|
||||
0xe2,0x2d,0x15,0x6e = mov v2.b[10], v15.b[5]
|
||||
0xa2,0x1c,0x18,0x4e = mov v2.d[1], x5
|
||||
0xc3,0x1c,0x0c,0x4e = mov v3.s[1], w6
|
||||
0xe4,0x1c,0x06,0x4e = mov v4.h[1], w7
|
||||
0x05,0x1d,0x03,0x4e = mov v5.b[1], w8
|
||||
0x49,0x1c,0x18,0x4e = mov v9.d[1], x2
|
||||
0x68,0x1c,0x0c,0x4e = mov v8.s[1], w3
|
||||
0x87,0x1c,0x06,0x4e = mov v7.h[1], w4
|
||||
0xa6,0x1c,0x03,0x4e = mov v6.b[1], w5
|
||||
0x41,0x45,0x18,0x6e = mov v1.d[1], v10.d[1]
|
||||
0x62,0x25,0x0c,0x6e = mov v2.s[1], v11.s[1]
|
||||
0x87,0x15,0x06,0x6e = mov v7.h[1], v12.h[1]
|
||||
0xe8,0x0d,0x03,0x6e = mov v8.b[1], v15.b[1]
|
||||
0xe2,0x05,0x18,0x6e = mov v2.d[1], v15.d[0]
|
||||
0x07,0x46,0x1c,0x6e = mov v7.s[3], v16.s[2]
|
||||
0x28,0x36,0x1e,0x6e = mov v8.h[7], v17.h[3]
|
||||
0x49,0x2e,0x15,0x6e = mov v9.b[10], v18.b[5]
|
||||
0x00,0x1c,0x20,0x0e = and v0.8b, v0.8b, v0.8b
|
||||
0x00,0x1c,0x20,0x4e = and v0.16b, v0.16b, v0.16b
|
||||
0x00,0x1c,0x60,0x0e = bic v0.8b, v0.8b, v0.8b
|
||||
0x00,0x8c,0x20,0x2e = cmeq v0.8b, v0.8b, v0.8b
|
||||
0x00,0x3c,0x20,0x0e = cmge v0.8b, v0.8b, v0.8b
|
||||
0x00,0x34,0x20,0x0e = cmgt v0.8b, v0.8b, v0.8b
|
||||
0x00,0x34,0x20,0x2e = cmhi v0.8b, v0.8b, v0.8b
|
||||
0x00,0x3c,0x20,0x2e = cmhs v0.8b, v0.8b, v0.8b
|
||||
0x00,0x8c,0x20,0x0e = cmtst v0.8b, v0.8b, v0.8b
|
||||
0x00,0xd4,0xa0,0x2e = fabd v0.2s, v0.2s, v0.2s
|
||||
0x00,0xec,0x20,0x2e = facge v0.2s, v0.2s, v0.2s
|
||||
0x00,0xec,0xa0,0x2e = facgt v0.2s, v0.2s, v0.2s
|
||||
0x00,0xd4,0x20,0x2e = faddp v0.2s, v0.2s, v0.2s
|
||||
0x00,0xd4,0x20,0x0e = fadd v0.2s, v0.2s, v0.2s
|
||||
0x00,0xe4,0x20,0x0e = fcmeq v0.2s, v0.2s, v0.2s
|
||||
0x00,0xe4,0x20,0x2e = fcmge v0.2s, v0.2s, v0.2s
|
||||
0x00,0xe4,0xa0,0x2e = fcmgt v0.2s, v0.2s, v0.2s
|
||||
0x00,0xfc,0x20,0x2e = fdiv v0.2s, v0.2s, v0.2s
|
||||
0x00,0xc4,0x20,0x2e = fmaxnmp v0.2s, v0.2s, v0.2s
|
||||
0x00,0xc4,0x20,0x0e = fmaxnm v0.2s, v0.2s, v0.2s
|
||||
0x00,0xf4,0x20,0x2e = fmaxp v0.2s, v0.2s, v0.2s
|
||||
0x00,0xf4,0x20,0x0e = fmax v0.2s, v0.2s, v0.2s
|
||||
0x00,0xc4,0xa0,0x2e = fminnmp v0.2s, v0.2s, v0.2s
|
||||
0x00,0xc4,0xa0,0x0e = fminnm v0.2s, v0.2s, v0.2s
|
||||
0x00,0xf4,0xa0,0x2e = fminp v0.2s, v0.2s, v0.2s
|
||||
0x00,0xf4,0xa0,0x0e = fmin v0.2s, v0.2s, v0.2s
|
||||
0x00,0xcc,0x20,0x0e = fmla v0.2s, v0.2s, v0.2s
|
||||
0x00,0xcc,0xa0,0x0e = fmls v0.2s, v0.2s, v0.2s
|
||||
0x00,0xdc,0x20,0x0e = fmulx v0.2s, v0.2s, v0.2s
|
||||
0x00,0xdc,0x20,0x2e = fmul v0.2s, v0.2s, v0.2s
|
||||
0x62,0xdc,0x61,0x5e = fmulx d2, d3, d1
|
||||
0x62,0xdc,0x21,0x5e = fmulx s2, s3, s1
|
||||
0x00,0xfc,0x20,0x0e = frecps v0.2s, v0.2s, v0.2s
|
||||
0x00,0xfc,0xa0,0x0e = frsqrts v0.2s, v0.2s, v0.2s
|
||||
0x00,0xd4,0xa0,0x0e = fsub v0.2s, v0.2s, v0.2s
|
||||
0x00,0x94,0x20,0x0e = mla v0.8b, v0.8b, v0.8b
|
||||
0x00,0x94,0x20,0x2e = mls v0.8b, v0.8b, v0.8b
|
||||
0x00,0x9c,0x20,0x0e = mul v0.8b, v0.8b, v0.8b
|
||||
0x00,0x9c,0x20,0x2e = pmul v0.8b, v0.8b, v0.8b
|
||||
0x00,0x7c,0x20,0x0e = saba v0.8b, v0.8b, v0.8b
|
||||
0x00,0x74,0x20,0x0e = sabd v0.8b, v0.8b, v0.8b
|
||||
0x00,0x04,0x20,0x0e = shadd v0.8b, v0.8b, v0.8b
|
||||
0x00,0x24,0x20,0x0e = shsub v0.8b, v0.8b, v0.8b
|
||||
0x00,0xa4,0x20,0x0e = smaxp v0.8b, v0.8b, v0.8b
|
||||
0x00,0x64,0x20,0x0e = smax v0.8b, v0.8b, v0.8b
|
||||
0x00,0xac,0x20,0x0e = sminp v0.8b, v0.8b, v0.8b
|
||||
0x00,0x6c,0x20,0x0e = smin v0.8b, v0.8b, v0.8b
|
||||
0x00,0x0c,0x20,0x0e = sqadd v0.8b, v0.8b, v0.8b
|
||||
0x00,0xb4,0x60,0x0e = sqdmulh v0.4h, v0.4h, v0.4h
|
||||
0x00,0xb4,0x60,0x2e = sqrdmulh v0.4h, v0.4h, v0.4h
|
||||
0x00,0x5c,0x20,0x0e = sqrshl v0.8b, v0.8b, v0.8b
|
||||
0x00,0x4c,0x20,0x0e = sqshl v0.8b, v0.8b, v0.8b
|
||||
0x00,0x2c,0x20,0x0e = sqsub v0.8b, v0.8b, v0.8b
|
||||
0x00,0x14,0x20,0x0e = srhadd v0.8b, v0.8b, v0.8b
|
||||
0x00,0x54,0x20,0x0e = srshl v0.8b, v0.8b, v0.8b
|
||||
0x00,0x44,0x20,0x0e = sshl v0.8b, v0.8b, v0.8b
|
||||
0x00,0x84,0x20,0x2e = sub v0.8b, v0.8b, v0.8b
|
||||
0x00,0x7c,0x20,0x2e = uaba v0.8b, v0.8b, v0.8b
|
||||
0x00,0x74,0x20,0x2e = uabd v0.8b, v0.8b, v0.8b
|
||||
0x00,0x04,0x20,0x2e = uhadd v0.8b, v0.8b, v0.8b
|
||||
0x00,0x24,0x20,0x2e = uhsub v0.8b, v0.8b, v0.8b
|
||||
0x00,0xa4,0x20,0x2e = umaxp v0.8b, v0.8b, v0.8b
|
||||
0x00,0x64,0x20,0x2e = umax v0.8b, v0.8b, v0.8b
|
||||
0x00,0xac,0x20,0x2e = uminp v0.8b, v0.8b, v0.8b
|
||||
0x00,0x6c,0x20,0x2e = umin v0.8b, v0.8b, v0.8b
|
||||
0x00,0x0c,0x20,0x2e = uqadd v0.8b, v0.8b, v0.8b
|
||||
0x00,0x5c,0x20,0x2e = uqrshl v0.8b, v0.8b, v0.8b
|
||||
0x00,0x4c,0x20,0x2e = uqshl v0.8b, v0.8b, v0.8b
|
||||
0x00,0x2c,0x20,0x2e = uqsub v0.8b, v0.8b, v0.8b
|
||||
0x00,0x14,0x20,0x2e = urhadd v0.8b, v0.8b, v0.8b
|
||||
0x00,0x54,0x20,0x2e = urshl v0.8b, v0.8b, v0.8b
|
||||
0x00,0x44,0x20,0x2e = ushl v0.8b, v0.8b, v0.8b
|
||||
0x00,0x14,0xc0,0x2e = fabd v0.4h, v0.4h, v0.4h
|
||||
0x00,0x2c,0x40,0x2e = facge v0.4h, v0.4h, v0.4h
|
||||
0x00,0x2c,0xc0,0x2e = facgt v0.4h, v0.4h, v0.4h
|
||||
0x00,0x14,0x40,0x2e = faddp v0.4h, v0.4h, v0.4h
|
||||
0x00,0x14,0x40,0x0e = fadd v0.4h, v0.4h, v0.4h
|
||||
0x00,0x24,0x40,0x0e = fcmeq v0.4h, v0.4h, v0.4h
|
||||
0x00,0x24,0x40,0x2e = fcmge v0.4h, v0.4h, v0.4h
|
||||
0x00,0x24,0xc0,0x2e = fcmgt v0.4h, v0.4h, v0.4h
|
||||
0x00,0x3c,0x40,0x2e = fdiv v0.4h, v0.4h, v0.4h
|
||||
0x00,0x04,0x40,0x2e = fmaxnmp v0.4h, v0.4h, v0.4h
|
||||
0x00,0x04,0x40,0x0e = fmaxnm v0.4h, v0.4h, v0.4h
|
||||
0x00,0x34,0x40,0x2e = fmaxp v0.4h, v0.4h, v0.4h
|
||||
0x00,0x34,0x40,0x0e = fmax v0.4h, v0.4h, v0.4h
|
||||
0x00,0x04,0xc0,0x2e = fminnmp v0.4h, v0.4h, v0.4h
|
||||
0x00,0x04,0xc0,0x0e = fminnm v0.4h, v0.4h, v0.4h
|
||||
0x00,0x34,0xc0,0x2e = fminp v0.4h, v0.4h, v0.4h
|
||||
0x00,0x34,0xc0,0x0e = fmin v0.4h, v0.4h, v0.4h
|
||||
0x00,0x0c,0x40,0x0e = fmla v0.4h, v0.4h, v0.4h
|
||||
0x00,0x0c,0xc0,0x0e = fmls v0.4h, v0.4h, v0.4h
|
||||
0x00,0x1c,0x40,0x0e = fmulx v0.4h, v0.4h, v0.4h
|
||||
0x00,0x1c,0x40,0x2e = fmul v0.4h, v0.4h, v0.4h
|
||||
0x00,0x3c,0x40,0x0e = frecps v0.4h, v0.4h, v0.4h
|
||||
0x00,0x3c,0xc0,0x0e = frsqrts v0.4h, v0.4h, v0.4h
|
||||
0x00,0x14,0xc0,0x0e = fsub v0.4h, v0.4h, v0.4h
|
||||
0x00,0x14,0xc0,0x6e = fabd v0.8h, v0.8h, v0.8h
|
||||
0x00,0x2c,0x40,0x6e = facge v0.8h, v0.8h, v0.8h
|
||||
0x00,0x2c,0xc0,0x6e = facgt v0.8h, v0.8h, v0.8h
|
||||
0x00,0x14,0x40,0x6e = faddp v0.8h, v0.8h, v0.8h
|
||||
0x00,0x14,0x40,0x4e = fadd v0.8h, v0.8h, v0.8h
|
||||
0x00,0x24,0x40,0x4e = fcmeq v0.8h, v0.8h, v0.8h
|
||||
0x00,0x24,0x40,0x6e = fcmge v0.8h, v0.8h, v0.8h
|
||||
0x00,0x24,0xc0,0x6e = fcmgt v0.8h, v0.8h, v0.8h
|
||||
0x00,0x3c,0x40,0x6e = fdiv v0.8h, v0.8h, v0.8h
|
||||
0x00,0x04,0x40,0x6e = fmaxnmp v0.8h, v0.8h, v0.8h
|
||||
0x00,0x04,0x40,0x4e = fmaxnm v0.8h, v0.8h, v0.8h
|
||||
0x00,0x34,0x40,0x6e = fmaxp v0.8h, v0.8h, v0.8h
|
||||
0x00,0x34,0x40,0x4e = fmax v0.8h, v0.8h, v0.8h
|
||||
0x00,0x04,0xc0,0x6e = fminnmp v0.8h, v0.8h, v0.8h
|
||||
0x00,0x04,0xc0,0x4e = fminnm v0.8h, v0.8h, v0.8h
|
||||
0x00,0x34,0xc0,0x6e = fminp v0.8h, v0.8h, v0.8h
|
||||
0x00,0x34,0xc0,0x4e = fmin v0.8h, v0.8h, v0.8h
|
||||
0x00,0x0c,0x40,0x4e = fmla v0.8h, v0.8h, v0.8h
|
||||
0x00,0x0c,0xc0,0x4e = fmls v0.8h, v0.8h, v0.8h
|
||||
0x00,0x1c,0x40,0x4e = fmulx v0.8h, v0.8h, v0.8h
|
||||
0x00,0x1c,0x40,0x6e = fmul v0.8h, v0.8h, v0.8h
|
||||
0x00,0x3c,0x40,0x4e = frecps v0.8h, v0.8h, v0.8h
|
||||
0x00,0x3c,0xc0,0x4e = frsqrts v0.8h, v0.8h, v0.8h
|
||||
0x00,0x14,0xc0,0x4e = fsub v0.8h, v0.8h, v0.8h
|
||||
0x00,0x1c,0xe0,0x2e = bif v0.8b, v0.8b, v0.8b
|
||||
0x00,0x1c,0xa0,0x2e = bit v0.8b, v0.8b, v0.8b
|
||||
0x00,0x1c,0x60,0x2e = bsl v0.8b, v0.8b, v0.8b
|
||||
0x00,0x1c,0x20,0x2e = eor v0.8b, v0.8b, v0.8b
|
||||
0x00,0x1c,0xe0,0x0e = orn v0.8b, v0.8b, v0.8b
|
||||
0x00,0x1c,0xa1,0x0e = orr v0.8b, v0.8b, v1.8b
|
||||
0x00,0x68,0x20,0x0e = sadalp v0.4h, v0.8b
|
||||
0x00,0x68,0x20,0x4e = sadalp v0.8h, v0.16b
|
||||
0x00,0x68,0x60,0x0e = sadalp v0.2s, v0.4h
|
||||
0x00,0x68,0x60,0x4e = sadalp v0.4s, v0.8h
|
||||
0x00,0x68,0xa0,0x0e = sadalp v0.1d, v0.2s
|
||||
0x00,0x68,0xa0,0x4e = sadalp v0.2d, v0.4s
|
||||
0x00,0x48,0x20,0x0e = cls v0.8b, v0.8b
|
||||
0x00,0x48,0x20,0x2e = clz v0.8b, v0.8b
|
||||
0x00,0x58,0x20,0x0e = cnt v0.8b, v0.8b
|
||||
0x00,0xf8,0xa0,0x0e = fabs v0.2s, v0.2s
|
||||
0x00,0xf8,0xa0,0x2e = fneg v0.2s, v0.2s
|
||||
0x00,0xd8,0xa1,0x0e = frecpe v0.2s, v0.2s
|
||||
0x00,0x88,0x21,0x2e = frinta v0.2s, v0.2s
|
||||
0x00,0x98,0x21,0x2e = frintx v0.2s, v0.2s
|
||||
0x00,0x98,0xa1,0x2e = frinti v0.2s, v0.2s
|
||||
0x00,0x98,0x21,0x0e = frintm v0.2s, v0.2s
|
||||
0x00,0x88,0x21,0x0e = frintn v0.2s, v0.2s
|
||||
0x00,0x88,0xa1,0x0e = frintp v0.2s, v0.2s
|
||||
0x00,0x98,0xa1,0x0e = frintz v0.2s, v0.2s
|
||||
0x00,0xd8,0xa1,0x2e = frsqrte v0.2s, v0.2s
|
||||
0x00,0xf8,0xa1,0x2e = fsqrt v0.2s, v0.2s
|
||||
0x00,0xb8,0x20,0x2e = neg v0.8b, v0.8b
|
||||
0x00,0x58,0x20,0x2e = mvn v0.8b, v0.8b
|
||||
0x00,0x58,0x60,0x2e = rbit v0.8b, v0.8b
|
||||
0x00,0x18,0x20,0x0e = rev16 v0.8b, v0.8b
|
||||
0x00,0x08,0x20,0x2e = rev32 v0.8b, v0.8b
|
||||
0x00,0x08,0x20,0x0e = rev64 v0.8b, v0.8b
|
||||
0x00,0x68,0x20,0x0e = sadalp v0.4h, v0.8b
|
||||
0x00,0x28,0x20,0x0e = saddlp v0.4h, v0.8b
|
||||
0x00,0xd8,0x21,0x0e = scvtf v0.2s, v0.2s
|
||||
0x00,0x78,0x20,0x0e = sqabs v0.8b, v0.8b
|
||||
0x00,0x78,0x20,0x2e = sqneg v0.8b, v0.8b
|
||||
0x00,0x48,0x21,0x0e = sqxtn v0.8b, v0.8h
|
||||
0x00,0x28,0x21,0x2e = sqxtun v0.8b, v0.8h
|
||||
0x00,0x38,0x20,0x0e = suqadd v0.8b, v0.8b
|
||||
0x00,0x68,0x20,0x2e = uadalp v0.4h, v0.8b
|
||||
0x00,0x28,0x20,0x2e = uaddlp v0.4h, v0.8b
|
||||
0x00,0xd8,0x21,0x2e = ucvtf v0.2s, v0.2s
|
||||
0x00,0x48,0x21,0x2e = uqxtn v0.8b, v0.8h
|
||||
0x00,0xc8,0xa1,0x0e = urecpe v0.2s, v0.2s
|
||||
0x00,0xc8,0xa1,0x2e = ursqrte v0.2s, v0.2s
|
||||
0x00,0x38,0x20,0x2e = usqadd v0.8b, v0.8b
|
||||
0x00,0x28,0x21,0x0e = xtn v0.8b, v0.8h
|
||||
0x41,0x38,0x21,0x2e = shll v1.8h, v2.8b, #8
|
||||
0x83,0x38,0x61,0x2e = shll v3.4s, v4.4h, #16
|
||||
0xc5,0x38,0xa1,0x2e = shll v5.2d, v6.2s, #32
|
||||
0x07,0x39,0x21,0x6e = shll2 v7.8h, v8.16b, #8
|
||||
0x49,0x39,0x61,0x6e = shll2 v9.4s, v10.8h, #16
|
||||
0x8b,0x39,0xa1,0x6e = shll2 v11.2d, v12.4s, #32
|
||||
0x41,0x38,0x21,0x2e = shll v1.8h, v2.8b, #8
|
||||
0x41,0x38,0x61,0x2e = shll v1.4s, v2.4h, #16
|
||||
0x41,0x38,0xa1,0x2e = shll v1.2d, v2.2s, #32
|
||||
0x41,0x38,0x21,0x6e = shll2 v1.8h, v2.16b, #8
|
||||
0x41,0x38,0x61,0x6e = shll2 v1.4s, v2.8h, #16
|
||||
0x41,0x38,0xa1,0x6e = shll2 v1.2d, v2.4s, #32
|
||||
0x00,0xf8,0xf8,0x0e = fabs v0.4h, v0.4h
|
||||
0x00,0xf8,0xf8,0x2e = fneg v0.4h, v0.4h
|
||||
0x00,0xd8,0xf9,0x0e = frecpe v0.4h, v0.4h
|
||||
0x00,0x88,0x79,0x2e = frinta v0.4h, v0.4h
|
||||
0x00,0x98,0x79,0x2e = frintx v0.4h, v0.4h
|
||||
0x00,0x98,0xf9,0x2e = frinti v0.4h, v0.4h
|
||||
0x00,0x98,0x79,0x0e = frintm v0.4h, v0.4h
|
||||
0x00,0x88,0x79,0x0e = frintn v0.4h, v0.4h
|
||||
0x00,0x88,0xf9,0x0e = frintp v0.4h, v0.4h
|
||||
0x00,0x98,0xf9,0x0e = frintz v0.4h, v0.4h
|
||||
0x00,0xd8,0xf9,0x2e = frsqrte v0.4h, v0.4h
|
||||
0x00,0xf8,0xf9,0x2e = fsqrt v0.4h, v0.4h
|
||||
0x00,0xf8,0xf8,0x4e = fabs v0.8h, v0.8h
|
||||
0x00,0xf8,0xf8,0x6e = fneg v0.8h, v0.8h
|
||||
0x00,0xd8,0xf9,0x4e = frecpe v0.8h, v0.8h
|
||||
0x00,0x88,0x79,0x6e = frinta v0.8h, v0.8h
|
||||
0x00,0x98,0x79,0x6e = frintx v0.8h, v0.8h
|
||||
0x00,0x98,0xf9,0x6e = frinti v0.8h, v0.8h
|
||||
0x00,0x98,0x79,0x4e = frintm v0.8h, v0.8h
|
||||
0x00,0x88,0x79,0x4e = frintn v0.8h, v0.8h
|
||||
0x00,0x88,0xf9,0x4e = frintp v0.8h, v0.8h
|
||||
0x00,0x98,0xf9,0x4e = frintz v0.8h, v0.8h
|
||||
0x00,0xd8,0xf9,0x6e = frsqrte v0.8h, v0.8h
|
||||
0x00,0xf8,0xf9,0x6e = fsqrt v0.8h, v0.8h
|
||||
0x00,0x98,0x20,0x0e = cmeq v0.8b, v0.8b, #0
|
||||
0x00,0x98,0x20,0x4e = cmeq v0.16b, v0.16b, #0
|
||||
0x00,0x98,0x60,0x0e = cmeq v0.4h, v0.4h, #0
|
||||
0x00,0x98,0x60,0x4e = cmeq v0.8h, v0.8h, #0
|
||||
0x00,0x98,0xa0,0x0e = cmeq v0.2s, v0.2s, #0
|
||||
0x00,0x98,0xa0,0x4e = cmeq v0.4s, v0.4s, #0
|
||||
0x00,0x98,0xe0,0x4e = cmeq v0.2d, v0.2d, #0
|
||||
0x00,0x88,0x20,0x2e = cmge v0.8b, v0.8b, #0
|
||||
0x00,0x88,0x20,0x0e = cmgt v0.8b, v0.8b, #0
|
||||
0x00,0x98,0x20,0x2e = cmle v0.8b, v0.8b, #0
|
||||
0x00,0xa8,0x20,0x0e = cmlt v0.8b, v0.8b, #0
|
||||
0x00,0xd8,0xa0,0x0e = fcmeq v0.2s, v0.2s, #0.0
|
||||
0x00,0xc8,0xa0,0x2e = fcmge v0.2s, v0.2s, #0.0
|
||||
0x00,0xc8,0xa0,0x0e = fcmgt v0.2s, v0.2s, #0.0
|
||||
0x00,0xd8,0xa0,0x2e = fcmle v0.2s, v0.2s, #0.0
|
||||
0x00,0xe8,0xa0,0x0e = fcmlt v0.2s, v0.2s, #0.0
|
||||
0xc8,0xa9,0x20,0x0e = cmlt v8.8b, v14.8b, #0
|
||||
0xc8,0xa9,0x20,0x4e = cmlt v8.16b, v14.16b, #0
|
||||
0xc8,0xa9,0x60,0x0e = cmlt v8.4h, v14.4h, #0
|
||||
0xc8,0xa9,0x60,0x4e = cmlt v8.8h, v14.8h, #0
|
||||
0xc8,0xa9,0xa0,0x0e = cmlt v8.2s, v14.2s, #0
|
||||
0xc8,0xa9,0xa0,0x4e = cmlt v8.4s, v14.4s, #0
|
||||
0xc8,0xa9,0xe0,0x4e = cmlt v8.2d, v14.2d, #0
|
||||
0x00,0xc8,0x21,0x0e = fcvtas v0.2s, v0.2s
|
||||
0x00,0xc8,0x21,0x4e = fcvtas v0.4s, v0.4s
|
||||
0x00,0xc8,0x61,0x4e = fcvtas v0.2d, v0.2d
|
||||
0x00,0xc8,0x21,0x5e = fcvtas s0, s0
|
||||
0x00,0xc8,0x61,0x5e = fcvtas d0, d0
|
||||
0x00,0xc8,0x21,0x2e = fcvtau v0.2s, v0.2s
|
||||
0x00,0xc8,0x21,0x6e = fcvtau v0.4s, v0.4s
|
||||
0x00,0xc8,0x61,0x6e = fcvtau v0.2d, v0.2d
|
||||
0x00,0xc8,0x21,0x7e = fcvtau s0, s0
|
||||
0x00,0xc8,0x61,0x7e = fcvtau d0, d0
|
||||
0xa1,0x78,0x21,0x0e = fcvtl v1.4s, v5.4h
|
||||
0xc2,0x78,0x61,0x0e = fcvtl v2.2d, v6.2s
|
||||
0xe3,0x78,0x21,0x4e = fcvtl2 v3.4s, v7.8h
|
||||
0x04,0x79,0x61,0x4e = fcvtl2 v4.2d, v8.4s
|
||||
0x00,0xb8,0x21,0x0e = fcvtms v0.2s, v0.2s
|
||||
0x00,0xb8,0x21,0x4e = fcvtms v0.4s, v0.4s
|
||||
0x00,0xb8,0x61,0x4e = fcvtms v0.2d, v0.2d
|
||||
0x00,0xb8,0x21,0x5e = fcvtms s0, s0
|
||||
0x00,0xb8,0x61,0x5e = fcvtms d0, d0
|
||||
0x00,0xb8,0x21,0x2e = fcvtmu v0.2s, v0.2s
|
||||
0x00,0xb8,0x21,0x6e = fcvtmu v0.4s, v0.4s
|
||||
0x00,0xb8,0x61,0x6e = fcvtmu v0.2d, v0.2d
|
||||
0x00,0xb8,0x21,0x7e = fcvtmu s0, s0
|
||||
0x00,0xb8,0x61,0x7e = fcvtmu d0, d0
|
||||
0x00,0xa8,0x21,0x0e = fcvtns v0.2s, v0.2s
|
||||
0x00,0xa8,0x21,0x4e = fcvtns v0.4s, v0.4s
|
||||
0x00,0xa8,0x61,0x4e = fcvtns v0.2d, v0.2d
|
||||
0x00,0xa8,0x21,0x5e = fcvtns s0, s0
|
||||
0x00,0xa8,0x61,0x5e = fcvtns d0, d0
|
||||
0x00,0xa8,0x21,0x2e = fcvtnu v0.2s, v0.2s
|
||||
0x00,0xa8,0x21,0x6e = fcvtnu v0.4s, v0.4s
|
||||
0x00,0xa8,0x61,0x6e = fcvtnu v0.2d, v0.2d
|
||||
0x00,0xa8,0x21,0x7e = fcvtnu s0, s0
|
||||
0x00,0xa8,0x61,0x7e = fcvtnu d0, d0
|
||||
0x82,0x68,0x21,0x0e = fcvtn v2.4h, v4.4s
|
||||
0xa3,0x68,0x61,0x0e = fcvtn v3.2s, v5.2d
|
||||
0xc4,0x68,0x21,0x4e = fcvtn2 v4.8h, v6.4s
|
||||
0xe5,0x68,0x61,0x4e = fcvtn2 v5.4s, v7.2d
|
||||
0x26,0x69,0x61,0x2e = fcvtxn v6.2s, v9.2d
|
||||
0x07,0x69,0x61,0x6e = fcvtxn2 v7.4s, v8.2d
|
||||
0x00,0xa8,0xa1,0x0e = fcvtps v0.2s, v0.2s
|
||||
0x00,0xa8,0xa1,0x4e = fcvtps v0.4s, v0.4s
|
||||
0x00,0xa8,0xe1,0x4e = fcvtps v0.2d, v0.2d
|
||||
0x00,0xa8,0xa1,0x5e = fcvtps s0, s0
|
||||
0x00,0xa8,0xe1,0x5e = fcvtps d0, d0
|
||||
0x00,0xa8,0xa1,0x2e = fcvtpu v0.2s, v0.2s
|
||||
0x00,0xa8,0xa1,0x6e = fcvtpu v0.4s, v0.4s
|
||||
0x00,0xa8,0xe1,0x6e = fcvtpu v0.2d, v0.2d
|
||||
0x00,0xa8,0xa1,0x7e = fcvtpu s0, s0
|
||||
0x00,0xa8,0xe1,0x7e = fcvtpu d0, d0
|
||||
0x00,0xb8,0xa1,0x0e = fcvtzs v0.2s, v0.2s
|
||||
0x00,0xb8,0xa1,0x4e = fcvtzs v0.4s, v0.4s
|
||||
0x00,0xb8,0xe1,0x4e = fcvtzs v0.2d, v0.2d
|
||||
0x00,0xb8,0xa1,0x5e = fcvtzs s0, s0
|
||||
0x00,0xb8,0xe1,0x5e = fcvtzs d0, d0
|
||||
0x00,0xb8,0xa1,0x2e = fcvtzu v0.2s, v0.2s
|
||||
0x00,0xb8,0xa1,0x6e = fcvtzu v0.4s, v0.4s
|
||||
0x00,0xb8,0xe1,0x6e = fcvtzu v0.2d, v0.2d
|
||||
0x00,0xb8,0xa1,0x7e = fcvtzu s0, s0
|
||||
0x00,0xb8,0xe1,0x7e = fcvtzu d0, d0
|
||||
0x20,0x14,0x00,0x2f = bic v0.2s, #1
|
||||
0x20,0x14,0x00,0x2f = bic v0.2s, #1
|
||||
0x20,0x34,0x00,0x2f = bic v0.2s, #1, lsl #8
|
||||
0x20,0x54,0x00,0x2f = bic v0.2s, #1, lsl #16
|
||||
0x20,0x74,0x00,0x2f = bic v0.2s, #1, lsl #24
|
||||
0x20,0x94,0x00,0x2f = bic v0.4h, #1
|
||||
0x20,0x94,0x00,0x2f = bic v0.4h, #1
|
||||
0x20,0xb4,0x00,0x2f = bic v0.4h, #1, lsl #8
|
||||
0x20,0x14,0x00,0x6f = bic v0.4s, #1
|
||||
0x20,0x14,0x00,0x6f = bic v0.4s, #1
|
||||
0x20,0x34,0x00,0x6f = bic v0.4s, #1, lsl #8
|
||||
0x20,0x54,0x00,0x6f = bic v0.4s, #1, lsl #16
|
||||
0x20,0x74,0x00,0x6f = bic v0.4s, #1, lsl #24
|
||||
0x20,0x94,0x00,0x6f = bic v0.8h, #1
|
||||
0x20,0x94,0x00,0x6f = bic v0.8h, #1
|
||||
0x20,0xb4,0x00,0x6f = bic v0.8h, #1, lsl #8
|
||||
0x00,0xf4,0x02,0x6f = fmov v0.2d, #0.12500000
|
||||
0x00,0xf4,0x02,0x0f = fmov v0.2s, #0.12500000
|
||||
0x00,0xf4,0x02,0x4f = fmov v0.4s, #0.12500000
|
||||
0x20,0x14,0x00,0x0f = orr v0.2s, #1
|
||||
0x20,0x14,0x00,0x0f = orr v0.2s, #1
|
||||
0x20,0x34,0x00,0x0f = orr v0.2s, #1, lsl #8
|
||||
0x20,0x54,0x00,0x0f = orr v0.2s, #1, lsl #16
|
||||
0x20,0x74,0x00,0x0f = orr v0.2s, #1, lsl #24
|
||||
0x20,0x94,0x00,0x0f = orr v0.4h, #1
|
||||
0x20,0x94,0x00,0x0f = orr v0.4h, #1
|
||||
0x20,0xb4,0x00,0x0f = orr v0.4h, #1, lsl #8
|
||||
0x20,0x14,0x00,0x4f = orr v0.4s, #1
|
||||
0x20,0x14,0x00,0x4f = orr v0.4s, #1
|
||||
0x20,0x34,0x00,0x4f = orr v0.4s, #1, lsl #8
|
||||
0x20,0x54,0x00,0x4f = orr v0.4s, #1, lsl #16
|
||||
0x20,0x74,0x00,0x4f = orr v0.4s, #1, lsl #24
|
||||
0x20,0x94,0x00,0x4f = orr v0.8h, #1
|
||||
0x20,0x94,0x00,0x4f = orr v0.8h, #1
|
||||
0x20,0xb4,0x00,0x4f = orr v0.8h, #1, lsl #8
|
||||
0x20,0xe4,0x00,0x2f = movi d0, #0x000000000000ff
|
||||
0x20,0xe4,0x00,0x6f = movi v0.2d, #0x000000000000ff
|
||||
0x20,0x04,0x00,0x0f = movi v0.2s, #1
|
||||
0x20,0x04,0x00,0x0f = movi v0.2s, #1
|
||||
0x20,0x24,0x00,0x0f = movi v0.2s, #1, lsl #8
|
||||
0x20,0x44,0x00,0x0f = movi v0.2s, #1, lsl #16
|
||||
0x20,0x64,0x00,0x0f = movi v0.2s, #1, lsl #24
|
||||
0x20,0x04,0x00,0x4f = movi v0.4s, #1
|
||||
0x20,0x04,0x00,0x4f = movi v0.4s, #1
|
||||
0x20,0x24,0x00,0x4f = movi v0.4s, #1, lsl #8
|
||||
0x20,0x44,0x00,0x4f = movi v0.4s, #1, lsl #16
|
||||
0x20,0x64,0x00,0x4f = movi v0.4s, #1, lsl #24
|
||||
0x20,0x84,0x00,0x0f = movi v0.4h, #1
|
||||
0x20,0x84,0x00,0x0f = movi v0.4h, #1
|
||||
0x20,0xa4,0x00,0x0f = movi v0.4h, #1, lsl #8
|
||||
0x20,0x84,0x00,0x4f = movi v0.8h, #1
|
||||
0x20,0x84,0x00,0x4f = movi v0.8h, #1
|
||||
0x20,0xa4,0x00,0x4f = movi v0.8h, #1, lsl #8
|
||||
0x20,0xc4,0x00,0x0f = movi v0.2s, #1, msl #8
|
||||
0x20,0xd4,0x00,0x0f = movi v0.2s, #1, msl #16
|
||||
0x20,0xc4,0x00,0x4f = movi v0.4s, #1, msl #8
|
||||
0x20,0xd4,0x00,0x4f = movi v0.4s, #1, msl #16
|
||||
0x20,0xe4,0x00,0x0f = movi v0.8b, #1
|
||||
0x20,0xe4,0x00,0x4f = movi v0.16b, #1
|
||||
0x20,0x04,0x00,0x2f = mvni v0.2s, #1
|
||||
0x20,0x04,0x00,0x2f = mvni v0.2s, #1
|
||||
0x20,0x24,0x00,0x2f = mvni v0.2s, #1, lsl #8
|
||||
0x20,0x44,0x00,0x2f = mvni v0.2s, #1, lsl #16
|
||||
0x20,0x64,0x00,0x2f = mvni v0.2s, #1, lsl #24
|
||||
0x20,0x04,0x00,0x6f = mvni v0.4s, #1
|
||||
0x20,0x04,0x00,0x6f = mvni v0.4s, #1
|
||||
0x20,0x24,0x00,0x6f = mvni v0.4s, #1, lsl #8
|
||||
0x20,0x44,0x00,0x6f = mvni v0.4s, #1, lsl #16
|
||||
0x20,0x64,0x00,0x6f = mvni v0.4s, #1, lsl #24
|
||||
0x20,0x84,0x00,0x2f = mvni v0.4h, #1
|
||||
0x20,0x84,0x00,0x2f = mvni v0.4h, #1
|
||||
0x20,0xa4,0x00,0x2f = mvni v0.4h, #1, lsl #8
|
||||
0x20,0x84,0x00,0x6f = mvni v0.8h, #1
|
||||
0x20,0x84,0x00,0x6f = mvni v0.8h, #1
|
||||
0x20,0xa4,0x00,0x6f = mvni v0.8h, #1, lsl #8
|
||||
0x20,0xc4,0x00,0x2f = mvni v0.2s, #1, msl #8
|
||||
0x20,0xd4,0x00,0x2f = mvni v0.2s, #1, msl #16
|
||||
0x20,0xc4,0x00,0x6f = mvni v0.4s, #1, msl #8
|
||||
0x20,0xd4,0x00,0x6f = mvni v0.4s, #1, msl #16
|
||||
0x00,0x18,0xa0,0x5f = fmla s0, s0, v0.s[3]
|
||||
0x00,0x18,0xc0,0x5f = fmla d0, d0, v0.d[1]
|
||||
0x00,0x58,0xa0,0x5f = fmls s0, s0, v0.s[3]
|
||||
0x00,0x58,0xc0,0x5f = fmls d0, d0, v0.d[1]
|
||||
0x00,0x98,0xa0,0x7f = fmulx s0, s0, v0.s[3]
|
||||
0x00,0x98,0xc0,0x7f = fmulx d0, d0, v0.d[1]
|
||||
0x00,0x98,0xa0,0x5f = fmul s0, s0, v0.s[3]
|
||||
0x00,0x98,0xc0,0x5f = fmul d0, d0, v0.d[1]
|
||||
0x00,0x38,0x70,0x5f = sqdmlal s0, h0, v0.h[7]
|
||||
0x00,0x38,0xa0,0x5f = sqdmlal d0, s0, v0.s[3]
|
||||
0x00,0x78,0x70,0x5f = sqdmlsl s0, h0, v0.h[7]
|
||||
0x00,0xc8,0x70,0x5f = sqdmulh h0, h0, v0.h[7]
|
||||
0x00,0xc8,0xa0,0x5f = sqdmulh s0, s0, v0.s[3]
|
||||
0x00,0xb8,0x70,0x5f = sqdmull s0, h0, v0.h[7]
|
||||
0x00,0xb8,0xa0,0x5f = sqdmull d0, s0, v0.s[3]
|
||||
0x00,0xd8,0x70,0x5f = sqrdmulh h0, h0, v0.h[7]
|
||||
0x00,0xd8,0xa0,0x5f = sqrdmulh s0, s0, v0.s[3]
|
||||
0x41,0x80,0x23,0x0e = smlal v1.8h, v2.8b, v3.8b
|
||||
0x41,0x80,0x63,0x0e = smlal v1.4s, v2.4h, v3.4h
|
||||
0x41,0x80,0xa3,0x0e = smlal v1.2d, v2.2s, v3.2s
|
||||
0x41,0x80,0x23,0x4e = smlal2 v1.8h, v2.16b, v3.16b
|
||||
0x41,0x80,0x63,0x4e = smlal2 v1.4s, v2.8h, v3.8h
|
||||
0x41,0x80,0xa3,0x4e = smlal2 v1.2d, v2.4s, v3.4s
|
||||
0x0d,0x81,0x20,0x0e = smlal v13.8h, v8.8b, v0.8b
|
||||
0x0d,0x81,0x60,0x0e = smlal v13.4s, v8.4h, v0.4h
|
||||
0x0d,0x81,0xa0,0x0e = smlal v13.2d, v8.2s, v0.2s
|
||||
0x0d,0x81,0x20,0x4e = smlal2 v13.8h, v8.16b, v0.16b
|
||||
0x0d,0x81,0x60,0x4e = smlal2 v13.4s, v8.8h, v0.8h
|
||||
0x0d,0x81,0xa0,0x4e = smlal2 v13.2d, v8.4s, v0.4s
|
||||
0x00,0x10,0x80,0x0f = fmla v0.2s, v0.2s, v0.s[0]
|
||||
0x00,0x10,0xa0,0x4f = fmla v0.4s, v0.4s, v0.s[1]
|
||||
0x00,0x18,0xc0,0x4f = fmla v0.2d, v0.2d, v0.d[1]
|
||||
0x00,0x50,0x80,0x0f = fmls v0.2s, v0.2s, v0.s[0]
|
||||
0x00,0x50,0xa0,0x4f = fmls v0.4s, v0.4s, v0.s[1]
|
||||
0x00,0x58,0xc0,0x4f = fmls v0.2d, v0.2d, v0.d[1]
|
||||
0x00,0x90,0x80,0x2f = fmulx v0.2s, v0.2s, v0.s[0]
|
||||
0x00,0x90,0xa0,0x6f = fmulx v0.4s, v0.4s, v0.s[1]
|
||||
0x00,0x98,0xc0,0x6f = fmulx v0.2d, v0.2d, v0.d[1]
|
||||
0x00,0x90,0x80,0x0f = fmul v0.2s, v0.2s, v0.s[0]
|
||||
0x00,0x90,0xa0,0x4f = fmul v0.4s, v0.4s, v0.s[1]
|
||||
0x00,0x98,0xc0,0x4f = fmul v0.2d, v0.2d, v0.d[1]
|
||||
0x00,0x00,0x40,0x2f = mla v0.4h, v0.4h, v0.h[0]
|
||||
0x00,0x00,0x50,0x6f = mla v0.8h, v0.8h, v0.h[1]
|
||||
0x00,0x08,0x80,0x2f = mla v0.2s, v0.2s, v0.s[2]
|
||||
0x00,0x08,0xa0,0x6f = mla v0.4s, v0.4s, v0.s[3]
|
||||
0x00,0x40,0x40,0x2f = mls v0.4h, v0.4h, v0.h[0]
|
||||
0x00,0x40,0x50,0x6f = mls v0.8h, v0.8h, v0.h[1]
|
||||
0x00,0x48,0x80,0x2f = mls v0.2s, v0.2s, v0.s[2]
|
||||
0x00,0x48,0xa0,0x6f = mls v0.4s, v0.4s, v0.s[3]
|
||||
0x00,0x80,0x40,0x0f = mul v0.4h, v0.4h, v0.h[0]
|
||||
0x00,0x80,0x50,0x4f = mul v0.8h, v0.8h, v0.h[1]
|
||||
0x00,0x88,0x80,0x0f = mul v0.2s, v0.2s, v0.s[2]
|
||||
0x00,0x88,0xa0,0x4f = mul v0.4s, v0.4s, v0.s[3]
|
||||
0x00,0x20,0x40,0x0f = smlal v0.4s, v0.4h, v0.h[0]
|
||||
0x00,0x20,0x50,0x4f = smlal2 v0.4s, v0.8h, v0.h[1]
|
||||
0x00,0x28,0x80,0x0f = smlal v0.2d, v0.2s, v0.s[2]
|
||||
0x00,0x28,0xa0,0x4f = smlal2 v0.2d, v0.4s, v0.s[3]
|
||||
0x00,0x60,0x40,0x0f = smlsl v0.4s, v0.4h, v0.h[0]
|
||||
0x00,0x60,0x50,0x4f = smlsl2 v0.4s, v0.8h, v0.h[1]
|
||||
0x00,0x68,0x80,0x0f = smlsl v0.2d, v0.2s, v0.s[2]
|
||||
0x00,0x68,0xa0,0x4f = smlsl2 v0.2d, v0.4s, v0.s[3]
|
||||
0x00,0xa0,0x40,0x0f = smull v0.4s, v0.4h, v0.h[0]
|
||||
0x00,0xa0,0x50,0x4f = smull2 v0.4s, v0.8h, v0.h[1]
|
||||
0x00,0xa8,0x80,0x0f = smull v0.2d, v0.2s, v0.s[2]
|
||||
0x00,0xa8,0xa0,0x4f = smull2 v0.2d, v0.4s, v0.s[3]
|
||||
0x00,0x30,0x40,0x0f = sqdmlal v0.4s, v0.4h, v0.h[0]
|
||||
0x00,0x30,0x50,0x4f = sqdmlal2 v0.4s, v0.8h, v0.h[1]
|
||||
0x00,0x38,0x80,0x0f = sqdmlal v0.2d, v0.2s, v0.s[2]
|
||||
0x00,0x38,0xa0,0x4f = sqdmlal2 v0.2d, v0.4s, v0.s[3]
|
||||
0x00,0x70,0x40,0x0f = sqdmlsl v0.4s, v0.4h, v0.h[0]
|
||||
0x00,0x70,0x50,0x4f = sqdmlsl2 v0.4s, v0.8h, v0.h[1]
|
||||
0x00,0x78,0x80,0x0f = sqdmlsl v0.2d, v0.2s, v0.s[2]
|
||||
0x00,0x78,0xa0,0x4f = sqdmlsl2 v0.2d, v0.4s, v0.s[3]
|
||||
0x00,0xc0,0x40,0x0f = sqdmulh v0.4h, v0.4h, v0.h[0]
|
||||
0x00,0xc0,0x50,0x4f = sqdmulh v0.8h, v0.8h, v0.h[1]
|
||||
0x00,0xc8,0x80,0x0f = sqdmulh v0.2s, v0.2s, v0.s[2]
|
||||
0x00,0xc8,0xa0,0x4f = sqdmulh v0.4s, v0.4s, v0.s[3]
|
||||
0x00,0xb0,0x40,0x0f = sqdmull v0.4s, v0.4h, v0.h[0]
|
||||
0x00,0xb0,0x50,0x4f = sqdmull2 v0.4s, v0.8h, v0.h[1]
|
||||
0x00,0xb8,0x80,0x0f = sqdmull v0.2d, v0.2s, v0.s[2]
|
||||
0x00,0xb8,0xa0,0x4f = sqdmull2 v0.2d, v0.4s, v0.s[3]
|
||||
0x00,0xd0,0x40,0x0f = sqrdmulh v0.4h, v0.4h, v0.h[0]
|
||||
0x00,0xd0,0x50,0x4f = sqrdmulh v0.8h, v0.8h, v0.h[1]
|
||||
0x00,0xd8,0x80,0x0f = sqrdmulh v0.2s, v0.2s, v0.s[2]
|
||||
0x00,0xd8,0xa0,0x4f = sqrdmulh v0.4s, v0.4s, v0.s[3]
|
||||
0x00,0x20,0x40,0x2f = umlal v0.4s, v0.4h, v0.h[0]
|
||||
0x00,0x20,0x50,0x6f = umlal2 v0.4s, v0.8h, v0.h[1]
|
||||
0x00,0x28,0x80,0x2f = umlal v0.2d, v0.2s, v0.s[2]
|
||||
0x00,0x28,0xa0,0x6f = umlal2 v0.2d, v0.4s, v0.s[3]
|
||||
0x00,0x60,0x40,0x2f = umlsl v0.4s, v0.4h, v0.h[0]
|
||||
0x00,0x60,0x50,0x6f = umlsl2 v0.4s, v0.8h, v0.h[1]
|
||||
0x00,0x68,0x80,0x2f = umlsl v0.2d, v0.2s, v0.s[2]
|
||||
0x00,0x68,0xa0,0x6f = umlsl2 v0.2d, v0.4s, v0.s[3]
|
||||
0x00,0xa0,0x40,0x2f = umull v0.4s, v0.4h, v0.h[0]
|
||||
0x00,0xa0,0x50,0x6f = umull2 v0.4s, v0.8h, v0.h[1]
|
||||
0x00,0xa8,0x80,0x2f = umull v0.2d, v0.2s, v0.s[2]
|
||||
0x00,0xa8,0xa0,0x6f = umull2 v0.2d, v0.4s, v0.s[3]
|
||||
0x00,0xfc,0x3f,0x5f = fcvtzs s0, s0, #1
|
||||
0x00,0xfc,0x7e,0x5f = fcvtzs d0, d0, #2
|
||||
0x00,0xfc,0x3f,0x7f = fcvtzu s0, s0, #1
|
||||
0x00,0xfc,0x7e,0x7f = fcvtzu d0, d0, #2
|
||||
0x00,0x54,0x41,0x5f = shl d0, d0, #1
|
||||
0x00,0x54,0x41,0x7f = sli d0, d0, #1
|
||||
0x00,0x9c,0x0f,0x5f = sqrshrn b0, h0, #1
|
||||
0x00,0x9c,0x1e,0x5f = sqrshrn h0, s0, #2
|
||||
0x00,0x9c,0x3d,0x5f = sqrshrn s0, d0, #3
|
||||
0x00,0x8c,0x0f,0x7f = sqrshrun b0, h0, #1
|
||||
0x00,0x8c,0x1e,0x7f = sqrshrun h0, s0, #2
|
||||
0x00,0x8c,0x3d,0x7f = sqrshrun s0, d0, #3
|
||||
0x00,0x64,0x09,0x7f = sqshlu b0, b0, #1
|
||||
0x00,0x64,0x12,0x7f = sqshlu h0, h0, #2
|
||||
0x00,0x64,0x23,0x7f = sqshlu s0, s0, #3
|
||||
0x00,0x64,0x44,0x7f = sqshlu d0, d0, #4
|
||||
0x00,0x74,0x09,0x5f = sqshl b0, b0, #1
|
||||
0x00,0x74,0x12,0x5f = sqshl h0, h0, #2
|
||||
0x00,0x74,0x23,0x5f = sqshl s0, s0, #3
|
||||
0x00,0x74,0x44,0x5f = sqshl d0, d0, #4
|
||||
0x00,0x94,0x0f,0x5f = sqshrn b0, h0, #1
|
||||
0x00,0x94,0x1e,0x5f = sqshrn h0, s0, #2
|
||||
0x00,0x94,0x3d,0x5f = sqshrn s0, d0, #3
|
||||
0x00,0x84,0x0f,0x7f = sqshrun b0, h0, #1
|
||||
0x00,0x84,0x1e,0x7f = sqshrun h0, s0, #2
|
||||
0x00,0x84,0x3d,0x7f = sqshrun s0, d0, #3
|
||||
0x00,0x44,0x7f,0x7f = sri d0, d0, #1
|
||||
0x00,0x24,0x7f,0x5f = srshr d0, d0, #1
|
||||
0x00,0x34,0x7f,0x5f = srsra d0, d0, #1
|
||||
0x00,0x04,0x7f,0x5f = sshr d0, d0, #1
|
||||
0x00,0xe4,0x3f,0x7f = ucvtf s0, s0, #1
|
||||
0x00,0xe4,0x7e,0x7f = ucvtf d0, d0, #2
|
||||
0x00,0xe4,0x3f,0x5f = scvtf s0, s0, #1
|
||||
0x00,0xe4,0x7e,0x5f = scvtf d0, d0, #2
|
||||
0x00,0x9c,0x0f,0x7f = uqrshrn b0, h0, #1
|
||||
0x00,0x9c,0x1e,0x7f = uqrshrn h0, s0, #2
|
||||
0x00,0x9c,0x3d,0x7f = uqrshrn s0, d0, #3
|
||||
0x00,0x74,0x09,0x7f = uqshl b0, b0, #1
|
||||
0x00,0x74,0x12,0x7f = uqshl h0, h0, #2
|
||||
0x00,0x74,0x23,0x7f = uqshl s0, s0, #3
|
||||
0x00,0x74,0x44,0x7f = uqshl d0, d0, #4
|
||||
0x00,0x94,0x0f,0x7f = uqshrn b0, h0, #1
|
||||
0x00,0x94,0x1e,0x7f = uqshrn h0, s0, #2
|
||||
0x00,0x94,0x3d,0x7f = uqshrn s0, d0, #3
|
||||
0x00,0x24,0x7f,0x7f = urshr d0, d0, #1
|
||||
0x00,0x34,0x7f,0x7f = ursra d0, d0, #1
|
||||
0x00,0x04,0x7f,0x7f = ushr d0, d0, #1
|
||||
0x00,0x14,0x7f,0x7f = usra d0, d0, #1
|
||||
0x00,0xfc,0x3f,0x0f = fcvtzs v0.2s, v0.2s, #1
|
||||
0x00,0xfc,0x3e,0x4f = fcvtzs v0.4s, v0.4s, #2
|
||||
0x00,0xfc,0x7d,0x4f = fcvtzs v0.2d, v0.2d, #3
|
||||
0x00,0xfc,0x3f,0x2f = fcvtzu v0.2s, v0.2s, #1
|
||||
0x00,0xfc,0x3e,0x6f = fcvtzu v0.4s, v0.4s, #2
|
||||
0x00,0xfc,0x7d,0x6f = fcvtzu v0.2d, v0.2d, #3
|
||||
0x00,0x8c,0x0f,0x0f = rshrn v0.8b, v0.8h, #1
|
||||
0x00,0x8c,0x0e,0x4f = rshrn2 v0.16b, v0.8h, #2
|
||||
0x00,0x8c,0x1d,0x0f = rshrn v0.4h, v0.4s, #3
|
||||
0x00,0x8c,0x1c,0x4f = rshrn2 v0.8h, v0.4s, #4
|
||||
0x00,0x8c,0x3b,0x0f = rshrn v0.2s, v0.2d, #5
|
||||
0x00,0x8c,0x3a,0x4f = rshrn2 v0.4s, v0.2d, #6
|
||||
0x00,0xe4,0x3f,0x0f = scvtf v0.2s, v0.2s, #1
|
||||
0x00,0xe4,0x3e,0x4f = scvtf v0.4s, v0.4s, #2
|
||||
0x00,0xe4,0x7d,0x4f = scvtf v0.2d, v0.2d, #3
|
||||
0x00,0x54,0x09,0x0f = shl v0.8b, v0.8b, #1
|
||||
0x00,0x54,0x0a,0x4f = shl v0.16b, v0.16b, #2
|
||||
0x00,0x54,0x13,0x0f = shl v0.4h, v0.4h, #3
|
||||
0x00,0x54,0x14,0x4f = shl v0.8h, v0.8h, #4
|
||||
0x00,0x54,0x25,0x0f = shl v0.2s, v0.2s, #5
|
||||
0x00,0x54,0x26,0x4f = shl v0.4s, v0.4s, #6
|
||||
0x00,0x54,0x47,0x4f = shl v0.2d, v0.2d, #7
|
||||
0x00,0x84,0x0f,0x0f = shrn v0.8b, v0.8h, #1
|
||||
0x00,0x84,0x0e,0x4f = shrn2 v0.16b, v0.8h, #2
|
||||
0x00,0x84,0x1d,0x0f = shrn v0.4h, v0.4s, #3
|
||||
0x00,0x84,0x1c,0x4f = shrn2 v0.8h, v0.4s, #4
|
||||
0x00,0x84,0x3b,0x0f = shrn v0.2s, v0.2d, #5
|
||||
0x00,0x84,0x3a,0x4f = shrn2 v0.4s, v0.2d, #6
|
||||
0x00,0x54,0x09,0x2f = sli v0.8b, v0.8b, #1
|
||||
0x00,0x54,0x0a,0x6f = sli v0.16b, v0.16b, #2
|
||||
0x00,0x54,0x13,0x2f = sli v0.4h, v0.4h, #3
|
||||
0x00,0x54,0x14,0x6f = sli v0.8h, v0.8h, #4
|
||||
0x00,0x54,0x25,0x2f = sli v0.2s, v0.2s, #5
|
||||
0x00,0x54,0x26,0x6f = sli v0.4s, v0.4s, #6
|
||||
0x00,0x54,0x47,0x6f = sli v0.2d, v0.2d, #7
|
||||
0x00,0x9c,0x0f,0x0f = sqrshrn v0.8b, v0.8h, #1
|
||||
0x00,0x9c,0x0e,0x4f = sqrshrn2 v0.16b, v0.8h, #2
|
||||
0x00,0x9c,0x1d,0x0f = sqrshrn v0.4h, v0.4s, #3
|
||||
0x00,0x9c,0x1c,0x4f = sqrshrn2 v0.8h, v0.4s, #4
|
||||
0x00,0x9c,0x3b,0x0f = sqrshrn v0.2s, v0.2d, #5
|
||||
0x00,0x9c,0x3a,0x4f = sqrshrn2 v0.4s, v0.2d, #6
|
||||
0x00,0x8c,0x0f,0x2f = sqrshrun v0.8b, v0.8h, #1
|
||||
0x00,0x8c,0x0e,0x6f = sqrshrun2 v0.16b, v0.8h, #2
|
||||
0x00,0x8c,0x1d,0x2f = sqrshrun v0.4h, v0.4s, #3
|
||||
0x00,0x8c,0x1c,0x6f = sqrshrun2 v0.8h, v0.4s, #4
|
||||
0x00,0x8c,0x3b,0x2f = sqrshrun v0.2s, v0.2d, #5
|
||||
0x00,0x8c,0x3a,0x6f = sqrshrun2 v0.4s, v0.2d, #6
|
||||
0x00,0x64,0x09,0x2f = sqshlu v0.8b, v0.8b, #1
|
||||
0x00,0x64,0x0a,0x6f = sqshlu v0.16b, v0.16b, #2
|
||||
0x00,0x64,0x13,0x2f = sqshlu v0.4h, v0.4h, #3
|
||||
0x00,0x64,0x14,0x6f = sqshlu v0.8h, v0.8h, #4
|
||||
0x00,0x64,0x25,0x2f = sqshlu v0.2s, v0.2s, #5
|
||||
0x00,0x64,0x26,0x6f = sqshlu v0.4s, v0.4s, #6
|
||||
0x00,0x64,0x47,0x6f = sqshlu v0.2d, v0.2d, #7
|
||||
0x00,0x74,0x09,0x0f = sqshl v0.8b, v0.8b, #1
|
||||
0x00,0x74,0x0a,0x4f = sqshl v0.16b, v0.16b, #2
|
||||
0x00,0x74,0x13,0x0f = sqshl v0.4h, v0.4h, #3
|
||||
0x00,0x74,0x14,0x4f = sqshl v0.8h, v0.8h, #4
|
||||
0x00,0x74,0x25,0x0f = sqshl v0.2s, v0.2s, #5
|
||||
0x00,0x74,0x26,0x4f = sqshl v0.4s, v0.4s, #6
|
||||
0x00,0x74,0x47,0x4f = sqshl v0.2d, v0.2d, #7
|
||||
0x00,0x94,0x0f,0x0f = sqshrn v0.8b, v0.8h, #1
|
||||
0x00,0x94,0x0e,0x4f = sqshrn2 v0.16b, v0.8h, #2
|
||||
0x00,0x94,0x1d,0x0f = sqshrn v0.4h, v0.4s, #3
|
||||
0x00,0x94,0x1c,0x4f = sqshrn2 v0.8h, v0.4s, #4
|
||||
0x00,0x94,0x3b,0x0f = sqshrn v0.2s, v0.2d, #5
|
||||
0x00,0x94,0x3a,0x4f = sqshrn2 v0.4s, v0.2d, #6
|
||||
0x00,0x84,0x0f,0x2f = sqshrun v0.8b, v0.8h, #1
|
||||
0x00,0x84,0x0e,0x6f = sqshrun2 v0.16b, v0.8h, #2
|
||||
0x00,0x84,0x1d,0x2f = sqshrun v0.4h, v0.4s, #3
|
||||
0x00,0x84,0x1c,0x6f = sqshrun2 v0.8h, v0.4s, #4
|
||||
0x00,0x84,0x3b,0x2f = sqshrun v0.2s, v0.2d, #5
|
||||
0x00,0x84,0x3a,0x6f = sqshrun2 v0.4s, v0.2d, #6
|
||||
0x00,0x44,0x0f,0x2f = sri v0.8b, v0.8b, #1
|
||||
0x00,0x44,0x0e,0x6f = sri v0.16b, v0.16b, #2
|
||||
0x00,0x44,0x1d,0x2f = sri v0.4h, v0.4h, #3
|
||||
0x00,0x44,0x1c,0x6f = sri v0.8h, v0.8h, #4
|
||||
0x00,0x44,0x3b,0x2f = sri v0.2s, v0.2s, #5
|
||||
0x00,0x44,0x3a,0x6f = sri v0.4s, v0.4s, #6
|
||||
0x00,0x44,0x79,0x6f = sri v0.2d, v0.2d, #7
|
||||
0x00,0x24,0x0f,0x0f = srshr v0.8b, v0.8b, #1
|
||||
0x00,0x24,0x0e,0x4f = srshr v0.16b, v0.16b, #2
|
||||
0x00,0x24,0x1d,0x0f = srshr v0.4h, v0.4h, #3
|
||||
0x00,0x24,0x1c,0x4f = srshr v0.8h, v0.8h, #4
|
||||
0x00,0x24,0x3b,0x0f = srshr v0.2s, v0.2s, #5
|
||||
0x00,0x24,0x3a,0x4f = srshr v0.4s, v0.4s, #6
|
||||
0x00,0x24,0x79,0x4f = srshr v0.2d, v0.2d, #7
|
||||
0x00,0x34,0x0f,0x0f = srsra v0.8b, v0.8b, #1
|
||||
0x00,0x34,0x0e,0x4f = srsra v0.16b, v0.16b, #2
|
||||
0x00,0x34,0x1d,0x0f = srsra v0.4h, v0.4h, #3
|
||||
0x00,0x34,0x1c,0x4f = srsra v0.8h, v0.8h, #4
|
||||
0x00,0x34,0x3b,0x0f = srsra v0.2s, v0.2s, #5
|
||||
0x00,0x34,0x3a,0x4f = srsra v0.4s, v0.4s, #6
|
||||
0x00,0x34,0x79,0x4f = srsra v0.2d, v0.2d, #7
|
||||
0x00,0xa4,0x09,0x0f = sshll v0.8h, v0.8b, #1
|
||||
0x00,0xa4,0x0a,0x4f = sshll2 v0.8h, v0.16b, #2
|
||||
0x00,0xa4,0x13,0x0f = sshll v0.4s, v0.4h, #3
|
||||
0x00,0xa4,0x14,0x4f = sshll2 v0.4s, v0.8h, #4
|
||||
0x00,0xa4,0x25,0x0f = sshll v0.2d, v0.2s, #5
|
||||
0x00,0xa4,0x26,0x4f = sshll2 v0.2d, v0.4s, #6
|
||||
0x00,0x04,0x0f,0x0f = sshr v0.8b, v0.8b, #1
|
||||
0x00,0x04,0x0e,0x4f = sshr v0.16b, v0.16b, #2
|
||||
0x00,0x04,0x1d,0x0f = sshr v0.4h, v0.4h, #3
|
||||
0x00,0x04,0x1c,0x4f = sshr v0.8h, v0.8h, #4
|
||||
0x00,0x04,0x3b,0x0f = sshr v0.2s, v0.2s, #5
|
||||
0x00,0x04,0x3a,0x4f = sshr v0.4s, v0.4s, #6
|
||||
0x00,0x04,0x79,0x4f = sshr v0.2d, v0.2d, #7
|
||||
0x00,0x04,0x0f,0x0f = sshr v0.8b, v0.8b, #1
|
||||
0x00,0x14,0x0e,0x4f = ssra v0.16b, v0.16b, #2
|
||||
0x00,0x14,0x1d,0x0f = ssra v0.4h, v0.4h, #3
|
||||
0x00,0x14,0x1c,0x4f = ssra v0.8h, v0.8h, #4
|
||||
0x00,0x14,0x3b,0x0f = ssra v0.2s, v0.2s, #5
|
||||
0x00,0x14,0x3a,0x4f = ssra v0.4s, v0.4s, #6
|
||||
0x00,0x14,0x79,0x4f = ssra v0.2d, v0.2d, #7
|
||||
0x00,0x14,0x40,0x5f = ssra d0, d0, #64
|
||||
0x00,0xe4,0x3f,0x2f = ucvtf v0.2s, v0.2s, #1
|
||||
0x00,0xe4,0x3e,0x6f = ucvtf v0.4s, v0.4s, #2
|
||||
0x00,0xe4,0x7d,0x6f = ucvtf v0.2d, v0.2d, #3
|
||||
0x00,0x9c,0x0f,0x2f = uqrshrn v0.8b, v0.8h, #1
|
||||
0x00,0x9c,0x0e,0x6f = uqrshrn2 v0.16b, v0.8h, #2
|
||||
0x00,0x9c,0x1d,0x2f = uqrshrn v0.4h, v0.4s, #3
|
||||
0x00,0x9c,0x1c,0x6f = uqrshrn2 v0.8h, v0.4s, #4
|
||||
0x00,0x9c,0x3b,0x2f = uqrshrn v0.2s, v0.2d, #5
|
||||
0x00,0x9c,0x3a,0x6f = uqrshrn2 v0.4s, v0.2d, #6
|
||||
0x00,0x74,0x09,0x2f = uqshl v0.8b, v0.8b, #1
|
||||
0x00,0x74,0x0a,0x6f = uqshl v0.16b, v0.16b, #2
|
||||
0x00,0x74,0x13,0x2f = uqshl v0.4h, v0.4h, #3
|
||||
0x00,0x74,0x14,0x6f = uqshl v0.8h, v0.8h, #4
|
||||
0x00,0x74,0x25,0x2f = uqshl v0.2s, v0.2s, #5
|
||||
0x00,0x74,0x26,0x6f = uqshl v0.4s, v0.4s, #6
|
||||
0x00,0x74,0x47,0x6f = uqshl v0.2d, v0.2d, #7
|
||||
0x00,0x94,0x0f,0x2f = uqshrn v0.8b, v0.8h, #1
|
||||
0x00,0x94,0x0e,0x6f = uqshrn2 v0.16b, v0.8h, #2
|
||||
0x00,0x94,0x1d,0x2f = uqshrn v0.4h, v0.4s, #3
|
||||
0x00,0x94,0x1c,0x6f = uqshrn2 v0.8h, v0.4s, #4
|
||||
0x00,0x94,0x3b,0x2f = uqshrn v0.2s, v0.2d, #5
|
||||
0x00,0x94,0x3a,0x6f = uqshrn2 v0.4s, v0.2d, #6
|
||||
0x00,0x24,0x0f,0x2f = urshr v0.8b, v0.8b, #1
|
||||
0x00,0x24,0x0e,0x6f = urshr v0.16b, v0.16b, #2
|
||||
0x00,0x24,0x1d,0x2f = urshr v0.4h, v0.4h, #3
|
||||
0x00,0x24,0x1c,0x6f = urshr v0.8h, v0.8h, #4
|
||||
0x00,0x24,0x3b,0x2f = urshr v0.2s, v0.2s, #5
|
||||
0x00,0x24,0x3a,0x6f = urshr v0.4s, v0.4s, #6
|
||||
0x00,0x24,0x79,0x6f = urshr v0.2d, v0.2d, #7
|
||||
0x00,0x34,0x0f,0x2f = ursra v0.8b, v0.8b, #1
|
||||
0x00,0x34,0x0e,0x6f = ursra v0.16b, v0.16b, #2
|
||||
0x00,0x34,0x1d,0x2f = ursra v0.4h, v0.4h, #3
|
||||
0x00,0x34,0x1c,0x6f = ursra v0.8h, v0.8h, #4
|
||||
0x00,0x34,0x3b,0x2f = ursra v0.2s, v0.2s, #5
|
||||
0x00,0x34,0x3a,0x6f = ursra v0.4s, v0.4s, #6
|
||||
0x00,0x34,0x79,0x6f = ursra v0.2d, v0.2d, #7
|
||||
0x00,0xa4,0x09,0x2f = ushll v0.8h, v0.8b, #1
|
||||
0x00,0xa4,0x0a,0x6f = ushll2 v0.8h, v0.16b, #2
|
||||
0x00,0xa4,0x13,0x2f = ushll v0.4s, v0.4h, #3
|
||||
0x00,0xa4,0x14,0x6f = ushll2 v0.4s, v0.8h, #4
|
||||
0x00,0xa4,0x25,0x2f = ushll v0.2d, v0.2s, #5
|
||||
0x00,0xa4,0x26,0x6f = ushll2 v0.2d, v0.4s, #6
|
||||
0x00,0x04,0x0f,0x2f = ushr v0.8b, v0.8b, #1
|
||||
0x00,0x04,0x0e,0x6f = ushr v0.16b, v0.16b, #2
|
||||
0x00,0x04,0x1d,0x2f = ushr v0.4h, v0.4h, #3
|
||||
0x00,0x04,0x1c,0x6f = ushr v0.8h, v0.8h, #4
|
||||
0x00,0x04,0x3b,0x2f = ushr v0.2s, v0.2s, #5
|
||||
0x00,0x04,0x3a,0x6f = ushr v0.4s, v0.4s, #6
|
||||
0x00,0x04,0x79,0x6f = ushr v0.2d, v0.2d, #7
|
||||
0x00,0x14,0x0f,0x2f = usra v0.8b, v0.8b, #1
|
||||
0x00,0x14,0x0e,0x6f = usra v0.16b, v0.16b, #2
|
||||
0x00,0x14,0x1d,0x2f = usra v0.4h, v0.4h, #3
|
||||
0x00,0x14,0x1c,0x6f = usra v0.8h, v0.8h, #4
|
||||
0x00,0x14,0x3b,0x2f = usra v0.2s, v0.2s, #5
|
||||
0x00,0x14,0x3a,0x6f = usra v0.4s, v0.4s, #6
|
||||
0x00,0x14,0x79,0x6f = usra v0.2d, v0.2d, #7
|
||||
0x69,0x8d,0x0f,0x0f = rshrn v9.8b, v11.8h, #1
|
||||
0x28,0x8d,0x0e,0x4f = rshrn2 v8.16b, v9.8h, #2
|
||||
0x07,0x8d,0x1d,0x0f = rshrn v7.4h, v8.4s, #3
|
||||
0xe6,0x8c,0x1c,0x4f = rshrn2 v6.8h, v7.4s, #4
|
||||
0xc5,0x8c,0x3b,0x0f = rshrn v5.2s, v6.2d, #5
|
||||
0xa4,0x8c,0x3a,0x4f = rshrn2 v4.4s, v5.2d, #6
|
||||
0x69,0x85,0x0f,0x0f = shrn v9.8b, v11.8h, #1
|
||||
0x28,0x85,0x0e,0x4f = shrn2 v8.16b, v9.8h, #2
|
||||
0x07,0x85,0x1d,0x0f = shrn v7.4h, v8.4s, #3
|
||||
0xe6,0x84,0x1c,0x4f = shrn2 v6.8h, v7.4s, #4
|
||||
0xc5,0x84,0x3b,0x0f = shrn v5.2s, v6.2d, #5
|
||||
0xa4,0x84,0x3a,0x4f = shrn2 v4.4s, v5.2d, #6
|
||||
0x69,0x9d,0x0f,0x0f = sqrshrn v9.8b, v11.8h, #1
|
||||
0x28,0x9d,0x0e,0x4f = sqrshrn2 v8.16b, v9.8h, #2
|
||||
0x07,0x9d,0x1d,0x0f = sqrshrn v7.4h, v8.4s, #3
|
||||
0xe6,0x9c,0x1c,0x4f = sqrshrn2 v6.8h, v7.4s, #4
|
||||
0xc5,0x9c,0x3b,0x0f = sqrshrn v5.2s, v6.2d, #5
|
||||
0xa4,0x9c,0x3a,0x4f = sqrshrn2 v4.4s, v5.2d, #6
|
||||
0x69,0x95,0x0f,0x0f = sqshrn v9.8b, v11.8h, #1
|
||||
0x28,0x95,0x0e,0x4f = sqshrn2 v8.16b, v9.8h, #2
|
||||
0x07,0x95,0x1d,0x0f = sqshrn v7.4h, v8.4s, #3
|
||||
0xe6,0x94,0x1c,0x4f = sqshrn2 v6.8h, v7.4s, #4
|
||||
0xc5,0x94,0x3b,0x0f = sqshrn v5.2s, v6.2d, #5
|
||||
0xa4,0x94,0x3a,0x4f = sqshrn2 v4.4s, v5.2d, #6
|
||||
0x69,0x8d,0x0f,0x2f = sqrshrun v9.8b, v11.8h, #1
|
||||
0x28,0x8d,0x0e,0x6f = sqrshrun2 v8.16b, v9.8h, #2
|
||||
0x07,0x8d,0x1d,0x2f = sqrshrun v7.4h, v8.4s, #3
|
||||
0xe6,0x8c,0x1c,0x6f = sqrshrun2 v6.8h, v7.4s, #4
|
||||
0xc5,0x8c,0x3b,0x2f = sqrshrun v5.2s, v6.2d, #5
|
||||
0xa4,0x8c,0x3a,0x6f = sqrshrun2 v4.4s, v5.2d, #6
|
||||
0x69,0x85,0x0f,0x2f = sqshrun v9.8b, v11.8h, #1
|
||||
0x28,0x85,0x0e,0x6f = sqshrun2 v8.16b, v9.8h, #2
|
||||
0x07,0x85,0x1d,0x2f = sqshrun v7.4h, v8.4s, #3
|
||||
0xe6,0x84,0x1c,0x6f = sqshrun2 v6.8h, v7.4s, #4
|
||||
0xc5,0x84,0x3b,0x2f = sqshrun v5.2s, v6.2d, #5
|
||||
0xa4,0x84,0x3a,0x6f = sqshrun2 v4.4s, v5.2d, #6
|
||||
0x69,0x9d,0x0f,0x2f = uqrshrn v9.8b, v11.8h, #1
|
||||
0x28,0x9d,0x0e,0x6f = uqrshrn2 v8.16b, v9.8h, #2
|
||||
0x07,0x9d,0x1d,0x2f = uqrshrn v7.4h, v8.4s, #3
|
||||
0xe6,0x9c,0x1c,0x6f = uqrshrn2 v6.8h, v7.4s, #4
|
||||
0xc5,0x9c,0x3b,0x2f = uqrshrn v5.2s, v6.2d, #5
|
||||
0xa4,0x9c,0x3a,0x6f = uqrshrn2 v4.4s, v5.2d, #6
|
||||
0x69,0x95,0x0f,0x2f = uqshrn v9.8b, v11.8h, #1
|
||||
0x28,0x95,0x0e,0x6f = uqshrn2 v8.16b, v9.8h, #2
|
||||
0x07,0x95,0x1d,0x2f = uqshrn v7.4h, v8.4s, #3
|
||||
0xe6,0x94,0x1c,0x6f = uqshrn2 v6.8h, v7.4s, #4
|
||||
0xc5,0x94,0x3b,0x2f = uqshrn v5.2s, v6.2d, #5
|
||||
0xa4,0x94,0x3a,0x6f = uqshrn2 v4.4s, v5.2d, #6
|
||||
0x6a,0xa4,0x0e,0x4f = sshll2 v10.8h, v3.16b, #6
|
||||
0x8b,0xa4,0x15,0x4f = sshll2 v11.4s, v4.8h, #5
|
||||
0xac,0xa4,0x24,0x4f = sshll2 v12.2d, v5.4s, #4
|
||||
0xcd,0xa4,0x0b,0x0f = sshll v13.8h, v6.8b, #3
|
||||
0xee,0xa4,0x12,0x0f = sshll v14.4s, v7.4h, #2
|
||||
0x0f,0xa5,0x27,0x0f = sshll v15.2d, v8.2s, #7
|
||||
0x6a,0xa4,0x0e,0x6f = ushll2 v10.8h, v3.16b, #6
|
||||
0x8b,0xa4,0x15,0x6f = ushll2 v11.4s, v4.8h, #5
|
||||
0xac,0xa4,0x24,0x6f = ushll2 v12.2d, v5.4s, #4
|
||||
0xcd,0xa4,0x0b,0x2f = ushll v13.8h, v6.8b, #3
|
||||
0xee,0xa4,0x12,0x2f = ushll v14.4s, v7.4h, #2
|
||||
0x0f,0xa5,0x27,0x2f = ushll v15.2d, v8.2s, #7
|
||||
0x00,0xe0,0x20,0x0e = pmull v0.8h, v0.8b, v0.8b
|
||||
0x00,0xe0,0x20,0x4e = pmull2 v0.8h, v0.16b, v0.16b
|
||||
0x62,0xe0,0xe4,0x0e = pmull v2.1q, v3.1d, v4.1d
|
||||
0x62,0xe0,0xe4,0x4e = pmull2 v2.1q, v3.2d, v4.2d
|
||||
0x62,0xe0,0xe4,0x0e = pmull v2.1q, v3.1d, v4.1d
|
||||
0x62,0xe0,0xe4,0x4e = pmull2 v2.1q, v3.2d, v4.2d
|
||||
0x41,0xd8,0x70,0x7e = faddp d1, v2.2d
|
||||
0x83,0xd8,0x30,0x7e = faddp s3, v4.2s
|
||||
0x82,0x60,0x01,0x4e = tbl v2.16b, { v4.16b, v5.16b, v6.16b, v7.16b }, v1.16b
|
||||
0x80,0x60,0x01,0x0e = tbl v0.8b, { v4.16b, v5.16b, v6.16b, v7.16b }, v1.8b
|
||||
0xa2,0x00,0x01,0x4e = tbl v2.16b, { v5.16b }, v1.16b
|
||||
0xa0,0x00,0x01,0x0e = tbl v0.8b, { v5.16b }, v1.8b
|
||||
0xa2,0x40,0x01,0x4e = tbl v2.16b, { v5.16b, v6.16b, v7.16b }, v1.16b
|
||||
0xa0,0x40,0x01,0x0e = tbl v0.8b, { v5.16b, v6.16b, v7.16b }, v1.8b
|
||||
0xc2,0x20,0x01,0x4e = tbl v2.16b, { v6.16b, v7.16b }, v1.16b
|
||||
0xc0,0x20,0x01,0x0e = tbl v0.8b, { v6.16b, v7.16b }, v1.8b
|
||||
0x82,0x60,0x01,0x4e = tbl v2.16b, { v4.16b, v5.16b, v6.16b, v7.16b }, v1.16b
|
||||
0x80,0x60,0x01,0x0e = tbl v0.8b, { v4.16b, v5.16b, v6.16b, v7.16b }, v1.8b
|
||||
0xa2,0x00,0x01,0x4e = tbl v2.16b, { v5.16b }, v1.16b
|
||||
0xa0,0x00,0x01,0x0e = tbl v0.8b, { v5.16b }, v1.8b
|
||||
0xa2,0x40,0x01,0x4e = tbl v2.16b, { v5.16b, v6.16b, v7.16b }, v1.16b
|
||||
0xa0,0x40,0x01,0x0e = tbl v0.8b, { v5.16b, v6.16b, v7.16b }, v1.8b
|
||||
0xc2,0x20,0x01,0x4e = tbl v2.16b, { v6.16b, v7.16b }, v1.16b
|
||||
0xc0,0x20,0x01,0x0e = tbl v0.8b, { v6.16b, v7.16b }, v1.8b
|
||||
0x00,0xd0,0x60,0x5e = sqdmull s0, h0, h0
|
||||
0x00,0xd0,0xa0,0x5e = sqdmull d0, s0, s0
|
||||
0x00,0xd8,0xa1,0x7e = frsqrte s0, s0
|
||||
0x00,0xd8,0xe1,0x7e = frsqrte d0, d0
|
||||
0x00,0x1c,0xa0,0x4e = mov v0.16b, v0.16b
|
||||
0x00,0x1c,0xa0,0x0e = mov v0.8b, v0.8b
|
||||
0x2e,0x6b,0x20,0x2e = uadalp v14.4h, v25.8b
|
||||
0x0f,0x6b,0x20,0x6e = uadalp v15.8h, v24.16b
|
||||
0xf0,0x6a,0x60,0x2e = uadalp v16.2s, v23.4h
|
||||
0xd1,0x6a,0x60,0x6e = uadalp v17.4s, v22.8h
|
||||
0xb2,0x6a,0xa0,0x2e = uadalp v18.1d, v21.2s
|
||||
0x93,0x6a,0xa0,0x6e = uadalp v19.2d, v20.4s
|
||||
0x61,0x69,0x20,0x0e = sadalp v1.4h, v11.8b
|
||||
0x82,0x69,0x20,0x4e = sadalp v2.8h, v12.16b
|
||||
0xa3,0x69,0x60,0x0e = sadalp v3.2s, v13.4h
|
||||
0xc4,0x69,0x60,0x4e = sadalp v4.4s, v14.8h
|
||||
0xe5,0x69,0xa0,0x0e = sadalp v5.1d, v15.2s
|
||||
0x06,0x6a,0xa0,0x4e = sadalp v6.2d, v16.4s
|
||||
0x81,0x58,0x20,0x2e = mvn v1.8b, v4.8b
|
||||
0x33,0x5a,0x20,0x6e = mvn v19.16b, v17.16b
|
||||
0xca,0x58,0x20,0x2e = mvn v10.8b, v6.8b
|
||||
0xeb,0x58,0x20,0x6e = mvn v11.16b, v7.16b
|
||||
0x8a,0xd1,0x6c,0x0e = sqdmull v10.4s, v12.4h, v12.4h
|
||||
0xaa,0xd1,0x6d,0x4e = sqdmull2 v10.4s, v13.8h, v13.8h
|
||||
0xaa,0xd1,0xad,0x0e = sqdmull v10.2d, v13.2s, v13.2s
|
||||
0xaa,0xd1,0xad,0x4e = sqdmull2 v10.2d, v13.4s, v13.4s
|
||||
0xce,0x29,0x21,0x0e = xtn v14.8b, v14.8h
|
||||
0xce,0x29,0x21,0x4e = xtn2 v14.16b, v14.8h
|
||||
0xce,0x29,0x61,0x0e = xtn v14.4h, v14.4s
|
||||
0xce,0x29,0x61,0x4e = xtn2 v14.8h, v14.4s
|
||||
0xce,0x29,0xa1,0x0e = xtn v14.2s, v14.2d
|
||||
0xce,0x29,0xa1,0x4e = xtn2 v14.4s, v14.2d
|
||||
0xa9,0x01,0x2e,0x2e = uaddl v9.8h, v13.8b, v14.8b
|
||||
0xa9,0x01,0x2e,0x6e = uaddl2 v9.8h, v13.16b, v14.16b
|
||||
0xa9,0x01,0x6e,0x2e = uaddl v9.4s, v13.4h, v14.4h
|
||||
0xa9,0x01,0x6e,0x6e = uaddl2 v9.4s, v13.8h, v14.8h
|
||||
0xa9,0x01,0xae,0x2e = uaddl v9.2d, v13.2s, v14.2s
|
||||
0xa9,0x01,0xae,0x6e = uaddl2 v9.2d, v13.4s, v14.4s
|
||||
0x49,0x1d,0xaa,0x6e = bit v9.16b, v10.16b, v10.16b
|
||||
0x49,0x1d,0xaa,0x2e = bit v9.8b, v10.8b, v10.8b
|
||||
0x08,0xe1,0x28,0x0e = pmull v8.8h, v8.8b, v8.8b
|
||||
0x08,0xe1,0x28,0x4e = pmull2 v8.8h, v8.16b, v8.16b
|
||||
0x08,0xe1,0xe8,0x0e = pmull v8.1q, v8.1d, v8.1d
|
||||
0x08,0xe1,0xe8,0x4e = pmull2 v8.1q, v8.2d, v8.2d
|
||||
0xa9,0x21,0x2e,0x2e = usubl v9.8h, v13.8b, v14.8b
|
||||
0xa9,0x21,0x2e,0x6e = usubl2 v9.8h, v13.16b, v14.16b
|
||||
0xa9,0x21,0x6e,0x2e = usubl v9.4s, v13.4h, v14.4h
|
||||
0xa9,0x21,0x6e,0x6e = usubl2 v9.4s, v13.8h, v14.8h
|
||||
0xa9,0x21,0xae,0x2e = usubl v9.2d, v13.2s, v14.2s
|
||||
0xa9,0x21,0xae,0x6e = usubl2 v9.2d, v13.4s, v14.4s
|
||||
0xa9,0x71,0x2e,0x2e = uabdl v9.8h, v13.8b, v14.8b
|
||||
0xa9,0x71,0x2e,0x6e = uabdl2 v9.8h, v13.16b, v14.16b
|
||||
0xa9,0x71,0x6e,0x2e = uabdl v9.4s, v13.4h, v14.4h
|
||||
0xa9,0x71,0x6e,0x6e = uabdl2 v9.4s, v13.8h, v14.8h
|
||||
0xa9,0x71,0xae,0x2e = uabdl v9.2d, v13.2s, v14.2s
|
||||
0xa9,0x71,0xae,0x6e = uabdl2 v9.2d, v13.4s, v14.4s
|
||||
0xa9,0xc1,0x2e,0x2e = umull v9.8h, v13.8b, v14.8b
|
||||
0xa9,0xc1,0x2e,0x6e = umull2 v9.8h, v13.16b, v14.16b
|
||||
0xa9,0xc1,0x6e,0x2e = umull v9.4s, v13.4h, v14.4h
|
||||
0xa9,0xc1,0x6e,0x6e = umull2 v9.4s, v13.8h, v14.8h
|
||||
0xa9,0xc1,0xae,0x2e = umull v9.2d, v13.2s, v14.2s
|
||||
0xa9,0xc1,0xae,0x6e = umull2 v9.2d, v13.4s, v14.4s
|
||||
0xa9,0xc1,0x2e,0x0e = smull v9.8h, v13.8b, v14.8b
|
||||
0xa9,0xc1,0x2e,0x4e = smull2 v9.8h, v13.16b, v14.16b
|
||||
0xa9,0xc1,0x6e,0x0e = smull v9.4s, v13.4h, v14.4h
|
||||
0xa9,0xc1,0x6e,0x4e = smull2 v9.4s, v13.8h, v14.8h
|
||||
0xa9,0xc1,0xae,0x0e = smull v9.2d, v13.2s, v14.2s
|
||||
0xa9,0xc1,0xae,0x4e = smull2 v9.2d, v13.4s, v14.4s
|
||||
22
thirdparty/capstone/suite/MC/AArch64/arm64-advsimd.txt.cs
vendored
Normal file
22
thirdparty/capstone/suite/MC/AArch64/arm64-advsimd.txt.cs
vendored
Normal file
@@ -0,0 +1,22 @@
|
||||
# CS_ARCH_AARCH64, None, None
|
||||
# This regression test file is new. The option flags could not be determined.
|
||||
# LLVM uses the following mattr = ['mattr=crypto']
|
||||
0x41 0xd8 0x70 0x7e == faddp.2d d1, v2
|
||||
0x83 0xd8 0x30 0x7e == faddp.2s s3, v4
|
||||
0x82 0x70 0x01 0x4e == tbl.16b v2, { v4, v5, v6, v7 }, v1
|
||||
0x80 0x70 0x01 0x0e == tbl.8b v0, { v4, v5, v6, v7 }, v1
|
||||
0xa2 0x10 0x01 0x4e == tbl.16b v2, { v5 }, v1
|
||||
0xa0 0x10 0x01 0x0e == tbl.8b v0, { v5 }, v1
|
||||
0xa2 0x50 0x01 0x4e == tbl.16b v2, { v5, v6, v7 }, v1
|
||||
0xa0 0x50 0x01 0x0e == tbl.8b v0, { v5, v6, v7 }, v1
|
||||
0xc2 0x30 0x01 0x4e == tbl.16b v2, { v6, v7 }, v1
|
||||
0xc0 0x30 0x01 0x0e == tbl.8b v0, { v6, v7 }, v1
|
||||
0x00 0xd0 0x60 0x5e == sqdmull s0, h0, h0
|
||||
0x00 0xd0 0xa0 0x5e == sqdmull d0, s0, s0
|
||||
0xca 0xcd 0xc7 0x4d == ld1r.2d { v10 }, [x14], x7
|
||||
0xea 0xc9 0xe7 0x4d == ld2r.4s { v10, v11 }, [x15], x7
|
||||
0xea 0xe9 0xc7 0x4d == ld3r.4s { v10, v11, v12 }, [x15], x7
|
||||
0xea 0xe9 0xe7 0x4d == ld4r.4s { v10, v11, v12, v13 }, [x15], x7
|
||||
0x62 0xdc 0x21 0x5e == fmulx s2, s3, s1
|
||||
0x62 0xdc 0x61 0x5e == fmulx d2, d3, d1
|
||||
0xe8 0x6b 0xdf 0x4c == ld1.4s { v8, v9, v10 }, [sp], #48
|
||||
95
thirdparty/capstone/suite/MC/AArch64/arm64-aliases.s.cs
vendored
Normal file
95
thirdparty/capstone/suite/MC/AArch64/arm64-aliases.s.cs
vendored
Normal file
@@ -0,0 +1,95 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
0x3f,0x04,0x00,0x72 = tst w1, #0x3
|
||||
0x3f,0x04,0x40,0xf2 = tst x1, #0x3
|
||||
0x3f,0x00,0x02,0x6a = tst w1, w2
|
||||
0x3f,0x00,0x02,0xea = tst x1, x2
|
||||
0x3f,0x08,0x02,0x6a = tst w1, w2, lsl #2
|
||||
0x3f,0x0c,0x02,0xea = tst x1, x2, lsl #3
|
||||
0x7f,0x7c,0x07,0x6a = tst w3, w7, lsl #31
|
||||
0x5f,0x00,0x94,0xea = tst x2, x20, asr #0
|
||||
0x3f,0x0c,0x00,0x31 = cmn w1, #3
|
||||
0x5f,0x00,0x50,0xb1 = cmn x2, #1024, lsl #12
|
||||
0x9f,0x00,0x05,0x2b = cmn w4, w5
|
||||
0xdf,0x00,0x07,0xab = cmn x6, x7
|
||||
0x1f,0x0d,0x89,0x2b = cmn w8, w9, asr #3
|
||||
0x5f,0x10,0x43,0xab = cmn x2, x3, lsr #4
|
||||
0x5f,0x04,0x23,0xab = cmn x2, w3, uxtb #1
|
||||
0x9f,0x64,0x25,0xab = cmn x4, x5, uxtx #1
|
||||
0x3f,0x00,0x50,0x71 = cmp w1, #1024, lsl #12
|
||||
0x5f,0x00,0x10,0xf1 = cmp x2, #1024
|
||||
0x9f,0x00,0x05,0x6b = cmp w4, w5
|
||||
0xdf,0x00,0x07,0xeb = cmp x6, x7
|
||||
0x1f,0x0d,0x89,0x6b = cmp w8, w9, asr #3
|
||||
0x5f,0x10,0x43,0xeb = cmp x2, x3, lsr #4
|
||||
0x5f,0x28,0x23,0xeb = cmp x2, w3, uxth #2
|
||||
0x9f,0x60,0x25,0xeb = cmp x4, x5, uxtx
|
||||
0xff,0x03,0x01,0x6b = cmp wzr, w1
|
||||
0x1f,0x41,0x28,0xeb = cmp x8, w8, uxtw
|
||||
0x3f,0x41,0x28,0x6b = cmp w9, w8, uxtw
|
||||
0xff,0x43,0x29,0x6b = cmp wsp, w9
|
||||
0xe4,0x03,0x29,0x2a = mvn w4, w9
|
||||
0xe2,0x03,0x23,0xaa = mvn x2, x3
|
||||
0xe4,0x03,0x29,0x2a = mvn w4, w9
|
||||
0xe4,0x07,0x29,0x2a = mvn w4, w9, lsl #1
|
||||
0xe2,0x07,0x23,0xaa = mvn x2, x3, lsl #1
|
||||
0xe4,0x07,0x29,0x2a = mvn w4, w9, lsl #1
|
||||
0x1f,0x71,0x08,0xd5 = ic ialluis
|
||||
0x1f,0x75,0x08,0xd5 = ic iallu
|
||||
0x20,0x75,0x0b,0xd5 = ic ivau, x0
|
||||
0x20,0x74,0x0b,0xd5 = dc zva, x0
|
||||
0x20,0x76,0x08,0xd5 = dc ivac, x0
|
||||
0x40,0x76,0x08,0xd5 = dc isw, x0
|
||||
0x20,0x7a,0x0b,0xd5 = dc cvac, x0
|
||||
0x40,0x7a,0x08,0xd5 = dc csw, x0
|
||||
0x20,0x7b,0x0b,0xd5 = dc cvau, x0
|
||||
0x20,0x7e,0x0b,0xd5 = dc civac, x0
|
||||
0x40,0x7e,0x08,0xd5 = dc cisw, x0
|
||||
0x00,0x78,0x08,0xd5 = at s1e1r, x0
|
||||
0x00,0x78,0x0c,0xd5 = at s1e2r, x0
|
||||
0x00,0x78,0x0e,0xd5 = at s1e3r, x0
|
||||
0x20,0x78,0x08,0xd5 = at s1e1w, x0
|
||||
0x20,0x78,0x0c,0xd5 = at s1e2w, x0
|
||||
0x20,0x78,0x0e,0xd5 = at s1e3w, x0
|
||||
0x40,0x78,0x08,0xd5 = at s1e0r, x0
|
||||
0x60,0x78,0x08,0xd5 = at s1e0w, x0
|
||||
0x80,0x78,0x0c,0xd5 = at s12e1r, x0
|
||||
0xa0,0x78,0x0c,0xd5 = at s12e1w, x0
|
||||
0xc0,0x78,0x0c,0xd5 = at s12e0r, x0
|
||||
0xe0,0x78,0x0c,0xd5 = at s12e0w, x0
|
||||
0x1f,0x83,0x08,0xd5 = tlbi vmalle1is
|
||||
0x1f,0x83,0x0c,0xd5 = tlbi alle2is
|
||||
0x1f,0x83,0x0e,0xd5 = tlbi alle3is
|
||||
0x20,0x83,0x08,0xd5 = tlbi vae1is, x0
|
||||
0x20,0x83,0x0c,0xd5 = tlbi vae2is, x0
|
||||
0x20,0x83,0x0e,0xd5 = tlbi vae3is, x0
|
||||
0x40,0x83,0x08,0xd5 = tlbi aside1is, x0
|
||||
0x60,0x83,0x08,0xd5 = tlbi vaae1is, x0
|
||||
0x9f,0x83,0x0c,0xd5 = tlbi alle1is
|
||||
0xa0,0x83,0x08,0xd5 = tlbi vale1is, x0
|
||||
0xe0,0x83,0x08,0xd5 = tlbi vaale1is, x0
|
||||
0x1f,0x87,0x08,0xd5 = tlbi vmalle1
|
||||
0x1f,0x87,0x0c,0xd5 = tlbi alle2
|
||||
0xa0,0x83,0x0c,0xd5 = tlbi vale2is, x0
|
||||
0xa0,0x83,0x0e,0xd5 = tlbi vale3is, x0
|
||||
0x1f,0x87,0x0e,0xd5 = tlbi alle3
|
||||
0x20,0x87,0x08,0xd5 = tlbi vae1, x0
|
||||
0x20,0x87,0x0c,0xd5 = tlbi vae2, x0
|
||||
0x20,0x87,0x0e,0xd5 = tlbi vae3, x0
|
||||
0x40,0x87,0x08,0xd5 = tlbi aside1, x0
|
||||
0x60,0x87,0x08,0xd5 = tlbi vaae1, x0
|
||||
0xa0,0x87,0x08,0xd5 = tlbi vale1, x0
|
||||
0xa0,0x87,0x0c,0xd5 = tlbi vale2, x0
|
||||
0xa0,0x87,0x0e,0xd5 = tlbi vale3, x0
|
||||
0xe0,0x87,0x08,0xd5 = tlbi vaale1, x0
|
||||
0x20,0x84,0x0c,0xd5 = tlbi ipas2e1, x0
|
||||
0xa0,0x84,0x0c,0xd5 = tlbi ipas2le1, x0
|
||||
0x20,0x80,0x0c,0xd5 = tlbi ipas2e1is, x0
|
||||
0xa0,0x80,0x0c,0xd5 = tlbi ipas2le1is, x0
|
||||
0xdf,0x87,0x0c,0xd5 = tlbi vmalls12e1
|
||||
0xdf,0x83,0x0c,0xd5 = tlbi vmalls12e1is
|
||||
0x04,0xe4,0x00,0x4f = movi v4.16b, #0
|
||||
0x24,0xe4,0x00,0x4f = movi v4.16b, #1
|
||||
0x44,0xe4,0x00,0x0f = movi v4.8b, #2
|
||||
0x64,0xe4,0x00,0x0f = movi v4.8b, #3
|
||||
0x21,0xe4,0x00,0x6f = movi v1.2d, #0x000000000000ff
|
||||
0x22,0xe4,0x00,0x6f = movi v2.2d, #0x000000000000ff
|
||||
242
thirdparty/capstone/suite/MC/AArch64/arm64-arithmetic-encoding.s.cs
vendored
Normal file
242
thirdparty/capstone/suite/MC/AArch64/arm64-arithmetic-encoding.s.cs
vendored
Normal file
@@ -0,0 +1,242 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
0x41,0x00,0x03,0x1a = adc w1, w2, w3
|
||||
0x41,0x00,0x03,0x9a = adc x1, x2, x3
|
||||
0x85,0x00,0x03,0x3a = adcs w5, w4, w3
|
||||
0x85,0x00,0x03,0xba = adcs x5, x4, x3
|
||||
0x41,0x00,0x03,0x5a = sbc w1, w2, w3
|
||||
0x41,0x00,0x03,0xda = sbc x1, x2, x3
|
||||
0x41,0x00,0x03,0x7a = sbcs w1, w2, w3
|
||||
0x41,0x00,0x03,0xfa = sbcs x1, x2, x3
|
||||
0x83,0x00,0x10,0x11 = add w3, w4, #1024
|
||||
0x83,0x00,0x10,0x11 = add w3, w4, #1024
|
||||
0x83,0x00,0x10,0x91 = add x3, x4, #1024
|
||||
0x83,0x00,0x10,0x91 = add x3, x4, #1024
|
||||
0x83,0x00,0x50,0x11 = add w3, w4, #1024, lsl #12
|
||||
0x83,0x00,0x50,0x11 = add w3, w4, #1024, lsl #12
|
||||
0x83,0x00,0x40,0x11 = add w3, w4, #0, lsl #12
|
||||
0x83,0x00,0x50,0x91 = add x3, x4, #1024, lsl #12
|
||||
0x83,0x00,0x50,0x91 = add x3, x4, #1024, lsl #12
|
||||
0x83,0x00,0x40,0x91 = add x3, x4, #0, lsl #12
|
||||
0xff,0x83,0x00,0x91 = add sp, sp, #32
|
||||
0x83,0x00,0x10,0x31 = adds w3, w4, #1024
|
||||
0x83,0x00,0x10,0x31 = adds w3, w4, #1024
|
||||
0x83,0x00,0x50,0x31 = adds w3, w4, #1024, lsl #12
|
||||
0x83,0x00,0x10,0xb1 = adds x3, x4, #1024
|
||||
0x83,0x00,0x10,0xb1 = adds x3, x4, #1024
|
||||
0x83,0x00,0x50,0xb1 = adds x3, x4, #1024, lsl #12
|
||||
0x83,0x00,0x10,0x51 = sub w3, w4, #1024
|
||||
0x83,0x00,0x10,0x51 = sub w3, w4, #1024
|
||||
0x83,0x00,0x50,0x51 = sub w3, w4, #1024, lsl #12
|
||||
0x83,0x00,0x10,0xd1 = sub x3, x4, #1024
|
||||
0x83,0x00,0x10,0xd1 = sub x3, x4, #1024
|
||||
0x83,0x00,0x50,0xd1 = sub x3, x4, #1024, lsl #12
|
||||
0xff,0x83,0x00,0xd1 = sub sp, sp, #32
|
||||
0x83,0x00,0x10,0x71 = subs w3, w4, #1024
|
||||
0x83,0x00,0x10,0x71 = subs w3, w4, #1024
|
||||
0x83,0x00,0x50,0x71 = subs w3, w4, #1024, lsl #12
|
||||
0x83,0x00,0x10,0xf1 = subs x3, x4, #1024
|
||||
0x83,0x00,0x10,0xf1 = subs x3, x4, #1024
|
||||
0x83,0x00,0x50,0xf1 = subs x3, x4, #1024, lsl #12
|
||||
0xac,0x01,0x0e,0x0b = add w12, w13, w14
|
||||
0xac,0x01,0x0e,0x8b = add x12, x13, x14
|
||||
0xac,0x31,0x0e,0x0b = add w12, w13, w14, lsl #12
|
||||
0xac,0x31,0x0e,0x8b = add x12, x13, x14, lsl #12
|
||||
0xac,0xa9,0x4e,0x8b = add x12, x13, x14, lsr #42
|
||||
0xac,0x9d,0x8e,0x8b = add x12, x13, x14, asr #39
|
||||
0xac,0x01,0x0e,0x4b = sub w12, w13, w14
|
||||
0xac,0x01,0x0e,0xcb = sub x12, x13, x14
|
||||
0xac,0x31,0x0e,0x4b = sub w12, w13, w14, lsl #12
|
||||
0xac,0x31,0x0e,0xcb = sub x12, x13, x14, lsl #12
|
||||
0xac,0xa9,0x4e,0xcb = sub x12, x13, x14, lsr #42
|
||||
0xac,0x9d,0x8e,0xcb = sub x12, x13, x14, asr #39
|
||||
0xac,0x01,0x0e,0x2b = adds w12, w13, w14
|
||||
0xac,0x01,0x0e,0xab = adds x12, x13, x14
|
||||
0xac,0x31,0x0e,0x2b = adds w12, w13, w14, lsl #12
|
||||
0xac,0x31,0x0e,0xab = adds x12, x13, x14, lsl #12
|
||||
0xac,0xa9,0x4e,0xab = adds x12, x13, x14, lsr #42
|
||||
0xac,0x9d,0x8e,0xab = adds x12, x13, x14, asr #39
|
||||
0xac,0x01,0x0e,0x6b = subs w12, w13, w14
|
||||
0xac,0x01,0x0e,0xeb = subs x12, x13, x14
|
||||
0xac,0x31,0x0e,0x6b = subs w12, w13, w14, lsl #12
|
||||
0xac,0x31,0x0e,0xeb = subs x12, x13, x14, lsl #12
|
||||
0xac,0xa9,0x4e,0xeb = subs x12, x13, x14, lsr #42
|
||||
0xac,0x9d,0x8e,0xeb = subs x12, x13, x14, asr #39
|
||||
0x42,0x00,0x02,0x8b = add x2, x2, x2
|
||||
0x41,0x00,0x23,0x0b = add w1, w2, w3, uxtb
|
||||
0x41,0x20,0x23,0x0b = add w1, w2, w3, uxth
|
||||
0x41,0x40,0x23,0x0b = add w1, w2, w3, uxtw
|
||||
0x41,0x60,0x23,0x0b = add w1, w2, w3, uxtx
|
||||
0x41,0x80,0x23,0x0b = add w1, w2, w3, sxtb
|
||||
0x41,0xa0,0x23,0x0b = add w1, w2, w3, sxth
|
||||
0x41,0xc0,0x23,0x0b = add w1, w2, w3, sxtw
|
||||
0x41,0xe0,0x23,0x0b = add w1, w2, w3, sxtx
|
||||
0x41,0x00,0x23,0x8b = add x1, x2, w3, uxtb
|
||||
0x41,0x20,0x23,0x8b = add x1, x2, w3, uxth
|
||||
0x41,0x40,0x23,0x8b = add x1, x2, w3, uxtw
|
||||
0x41,0x80,0x23,0x8b = add x1, x2, w3, sxtb
|
||||
0x41,0xa0,0x23,0x8b = add x1, x2, w3, sxth
|
||||
0x41,0xc0,0x23,0x8b = add x1, x2, w3, sxtw
|
||||
0xe1,0x43,0x23,0x0b = add w1, wsp, w3
|
||||
0xe1,0x43,0x23,0x0b = add w1, wsp, w3
|
||||
0xe2,0x47,0x23,0x0b = add w2, wsp, w3, lsl #1
|
||||
0x5f,0x60,0x23,0x8b = add sp, x2, x3
|
||||
0x5f,0x60,0x23,0x8b = add sp, x2, x3
|
||||
0x41,0x00,0x23,0x4b = sub w1, w2, w3, uxtb
|
||||
0x41,0x20,0x23,0x4b = sub w1, w2, w3, uxth
|
||||
0x41,0x40,0x23,0x4b = sub w1, w2, w3, uxtw
|
||||
0x41,0x60,0x23,0x4b = sub w1, w2, w3, uxtx
|
||||
0x41,0x80,0x23,0x4b = sub w1, w2, w3, sxtb
|
||||
0x41,0xa0,0x23,0x4b = sub w1, w2, w3, sxth
|
||||
0x41,0xc0,0x23,0x4b = sub w1, w2, w3, sxtw
|
||||
0x41,0xe0,0x23,0x4b = sub w1, w2, w3, sxtx
|
||||
0x41,0x00,0x23,0xcb = sub x1, x2, w3, uxtb
|
||||
0x41,0x20,0x23,0xcb = sub x1, x2, w3, uxth
|
||||
0x41,0x40,0x23,0xcb = sub x1, x2, w3, uxtw
|
||||
0x41,0x80,0x23,0xcb = sub x1, x2, w3, sxtb
|
||||
0x41,0xa0,0x23,0xcb = sub x1, x2, w3, sxth
|
||||
0x41,0xc0,0x23,0xcb = sub x1, x2, w3, sxtw
|
||||
0xe1,0x43,0x23,0x4b = sub w1, wsp, w3
|
||||
0xe1,0x43,0x23,0x4b = sub w1, wsp, w3
|
||||
0x5f,0x60,0x23,0xcb = sub sp, x2, x3
|
||||
0x5f,0x60,0x23,0xcb = sub sp, x2, x3
|
||||
0x7f,0x70,0x27,0xcb = sub sp, x3, x7, lsl #4
|
||||
0x41,0x00,0x23,0x2b = adds w1, w2, w3, uxtb
|
||||
0x41,0x20,0x23,0x2b = adds w1, w2, w3, uxth
|
||||
0x41,0x40,0x23,0x2b = adds w1, w2, w3, uxtw
|
||||
0x41,0x60,0x23,0x2b = adds w1, w2, w3, uxtx
|
||||
0x41,0x80,0x23,0x2b = adds w1, w2, w3, sxtb
|
||||
0x41,0xa0,0x23,0x2b = adds w1, w2, w3, sxth
|
||||
0x41,0xc0,0x23,0x2b = adds w1, w2, w3, sxtw
|
||||
0x41,0xe0,0x23,0x2b = adds w1, w2, w3, sxtx
|
||||
0x41,0x00,0x23,0xab = adds x1, x2, w3, uxtb
|
||||
0x41,0x20,0x23,0xab = adds x1, x2, w3, uxth
|
||||
0x41,0x40,0x23,0xab = adds x1, x2, w3, uxtw
|
||||
0x41,0x60,0x23,0xab = adds x1, x2, x3, uxtx
|
||||
0x41,0x80,0x23,0xab = adds x1, x2, w3, sxtb
|
||||
0x41,0xa0,0x23,0xab = adds x1, x2, w3, sxth
|
||||
0x41,0xc0,0x23,0xab = adds x1, x2, w3, sxtw
|
||||
0x41,0xe0,0x23,0xab = adds x1, x2, x3, sxtx
|
||||
0xe1,0x43,0x23,0x2b = adds w1, wsp, w3
|
||||
0xe1,0x43,0x23,0x2b = adds w1, wsp, w3
|
||||
0xff,0x53,0x23,0x2b = cmn wsp, w3, lsl #4
|
||||
0x41,0x00,0x23,0x6b = subs w1, w2, w3, uxtb
|
||||
0x41,0x20,0x23,0x6b = subs w1, w2, w3, uxth
|
||||
0x41,0x40,0x23,0x6b = subs w1, w2, w3, uxtw
|
||||
0x41,0x60,0x23,0x6b = subs w1, w2, w3, uxtx
|
||||
0x41,0x80,0x23,0x6b = subs w1, w2, w3, sxtb
|
||||
0x41,0xa0,0x23,0x6b = subs w1, w2, w3, sxth
|
||||
0x41,0xc0,0x23,0x6b = subs w1, w2, w3, sxtw
|
||||
0x41,0xe0,0x23,0x6b = subs w1, w2, w3, sxtx
|
||||
0x41,0x00,0x23,0xeb = subs x1, x2, w3, uxtb
|
||||
0x41,0x20,0x23,0xeb = subs x1, x2, w3, uxth
|
||||
0x41,0x40,0x23,0xeb = subs x1, x2, w3, uxtw
|
||||
0x41,0x60,0x23,0xeb = subs x1, x2, x3, uxtx
|
||||
0x41,0x80,0x23,0xeb = subs x1, x2, w3, sxtb
|
||||
0x41,0xa0,0x23,0xeb = subs x1, x2, w3, sxth
|
||||
0x41,0xc0,0x23,0xeb = subs x1, x2, w3, sxtw
|
||||
0x41,0xe0,0x23,0xeb = subs x1, x2, x3, sxtx
|
||||
0xe1,0x43,0x23,0x6b = subs w1, wsp, w3
|
||||
0xe1,0x43,0x23,0x6b = subs w1, wsp, w3
|
||||
0xff,0x43,0x29,0x6b = cmp wsp, w9
|
||||
0xe3,0x6b,0x29,0xeb = subs x3, sp, x9, lsl #2
|
||||
0xff,0x43,0x28,0x6b = cmp wsp, w8
|
||||
0xff,0x43,0x28,0x6b = cmp wsp, w8
|
||||
0xff,0x43,0x28,0xeb = cmp sp, w8, uxtw
|
||||
0xff,0x43,0x28,0xeb = cmp sp, w8, uxtw
|
||||
0x3f,0x41,0x28,0x4b = sub wsp, w9, w8
|
||||
0xe1,0x43,0x28,0x4b = sub w1, wsp, w8
|
||||
0xff,0x43,0x28,0x4b = sub wsp, wsp, w8
|
||||
0x3f,0x41,0x28,0xcb = sub sp, x9, w8, uxtw
|
||||
0xe1,0x43,0x28,0xcb = sub x1, sp, w8, uxtw
|
||||
0xff,0x43,0x28,0xcb = sub sp, sp, w8, uxtw
|
||||
0xe1,0x43,0x28,0x6b = subs w1, wsp, w8
|
||||
0xe1,0x43,0x28,0xeb = subs x1, sp, w8, uxtw
|
||||
0x41,0x0c,0xc3,0x1a = sdiv w1, w2, w3
|
||||
0x41,0x0c,0xc3,0x9a = sdiv x1, x2, x3
|
||||
0x41,0x08,0xc3,0x1a = udiv w1, w2, w3
|
||||
0x41,0x08,0xc3,0x9a = udiv x1, x2, x3
|
||||
0x41,0x28,0xc3,0x1a = asr w1, w2, w3
|
||||
0x41,0x28,0xc3,0x9a = asr x1, x2, x3
|
||||
0x41,0x28,0xc3,0x1a = asr w1, w2, w3
|
||||
0x41,0x28,0xc3,0x9a = asr x1, x2, x3
|
||||
0x41,0x20,0xc3,0x1a = lsl w1, w2, w3
|
||||
0x41,0x20,0xc3,0x9a = lsl x1, x2, x3
|
||||
0x41,0x20,0xc3,0x1a = lsl w1, w2, w3
|
||||
0x41,0x20,0xc3,0x9a = lsl x1, x2, x3
|
||||
0x41,0x24,0xc3,0x1a = lsr w1, w2, w3
|
||||
0x41,0x24,0xc3,0x9a = lsr x1, x2, x3
|
||||
0x41,0x24,0xc3,0x1a = lsr w1, w2, w3
|
||||
0x41,0x24,0xc3,0x9a = lsr x1, x2, x3
|
||||
0x41,0x2c,0xc3,0x1a = ror w1, w2, w3
|
||||
0x41,0x2c,0xc3,0x9a = ror x1, x2, x3
|
||||
0x41,0x2c,0xc3,0x1a = ror w1, w2, w3
|
||||
0x41,0x2c,0xc3,0x9a = ror x1, x2, x3
|
||||
0x41,0x14,0xc0,0x5a = cls w1, w2
|
||||
0x41,0x14,0xc0,0xda = cls x1, x2
|
||||
0x41,0x10,0xc0,0x5a = clz w1, w2
|
||||
0x41,0x10,0xc0,0xda = clz x1, x2
|
||||
0x41,0x00,0xc0,0x5a = rbit w1, w2
|
||||
0x41,0x00,0xc0,0xda = rbit x1, x2
|
||||
0x41,0x08,0xc0,0x5a = rev w1, w2
|
||||
0x41,0x0c,0xc0,0xda = rev x1, x2
|
||||
0x41,0x04,0xc0,0x5a = rev16 w1, w2
|
||||
0x41,0x04,0xc0,0xda = rev16 x1, x2
|
||||
0x41,0x08,0xc0,0xda = rev32 x1, x2
|
||||
0x41,0x10,0x03,0x1b = madd w1, w2, w3, w4
|
||||
0x41,0x10,0x03,0x9b = madd x1, x2, x3, x4
|
||||
0x41,0x90,0x03,0x1b = msub w1, w2, w3, w4
|
||||
0x41,0x90,0x03,0x9b = msub x1, x2, x3, x4
|
||||
0x41,0x10,0x23,0x9b = smaddl x1, w2, w3, x4
|
||||
0x41,0x90,0x23,0x9b = smsubl x1, w2, w3, x4
|
||||
0x41,0x10,0xa3,0x9b = umaddl x1, w2, w3, x4
|
||||
0x41,0x90,0xa3,0x9b = umsubl x1, w2, w3, x4
|
||||
0x41,0x7c,0x43,0x9b = smulh x1, x2, x3
|
||||
0x41,0x7c,0xc3,0x9b = umulh x1, x2, x3
|
||||
0x20,0x00,0x80,0x52 = mov w0, #1
|
||||
0x20,0x00,0x80,0xd2 = mov x0, #1
|
||||
0x20,0x00,0xa0,0x52 = mov w0, #65536
|
||||
0x20,0x00,0xa0,0xd2 = mov x0, #65536
|
||||
0x40,0x00,0x80,0x12 = mov w0, #-3
|
||||
0x40,0x00,0x80,0x92 = mov x0, #-3
|
||||
0x40,0x00,0xa0,0x12 = mov w0, #-131073
|
||||
0x40,0x00,0xa0,0x92 = mov x0, #-131073
|
||||
0x20,0x00,0x80,0x72 = movk w0, #1
|
||||
0x20,0x00,0x80,0xf2 = movk x0, #1
|
||||
0x20,0x00,0xa0,0x72 = movk w0, #1, lsl #16
|
||||
0x20,0x00,0xa0,0xf2 = movk x0, #1, lsl #16
|
||||
0x23,0x08,0x42,0x3a = ccmn w1, #2, #3, eq
|
||||
0x23,0x08,0x42,0xba = ccmn x1, #2, #3, eq
|
||||
0x23,0x08,0x42,0x7a = ccmp w1, #2, #3, eq
|
||||
0x23,0x08,0x42,0xfa = ccmp x1, #2, #3, eq
|
||||
0x23,0x00,0x42,0x3a = ccmn w1, w2, #3, eq
|
||||
0x23,0x00,0x42,0xba = ccmn x1, x2, #3, eq
|
||||
0x23,0x00,0x42,0x7a = ccmp w1, w2, #3, eq
|
||||
0x23,0x00,0x42,0xfa = ccmp x1, x2, #3, eq
|
||||
0x41,0x00,0x83,0x1a = csel w1, w2, w3, eq
|
||||
0x41,0x00,0x83,0x9a = csel x1, x2, x3, eq
|
||||
0x41,0x04,0x83,0x1a = csinc w1, w2, w3, eq
|
||||
0x41,0x04,0x83,0x9a = csinc x1, x2, x3, eq
|
||||
0x41,0x00,0x83,0x5a = csinv w1, w2, w3, eq
|
||||
0x41,0x00,0x83,0xda = csinv x1, x2, x3, eq
|
||||
0x41,0x04,0x83,0x5a = csneg w1, w2, w3, eq
|
||||
0x41,0x04,0x83,0xda = csneg x1, x2, x3, eq
|
||||
0xf0,0x00,0x9b,0x1a = csel w16, w7, w27, eq
|
||||
0xcf,0x10,0x9a,0x1a = csel w15, w6, w26, ne
|
||||
0xae,0x20,0x99,0x1a = csel w14, w5, w25, hs
|
||||
0x8d,0x20,0x98,0x1a = csel w13, w4, w24, hs
|
||||
0x6c,0x30,0x97,0x1a = csel w12, w3, w23, lo
|
||||
0x4b,0x30,0x96,0x1a = csel w11, w2, w22, lo
|
||||
0x2a,0x40,0x95,0x1a = csel w10, w1, w21, mi
|
||||
0x29,0x51,0x81,0x9a = csel x9, x9, x1, pl
|
||||
0x08,0x61,0x82,0x9a = csel x8, x8, x2, vs
|
||||
0xe7,0x70,0x83,0x9a = csel x7, x7, x3, vc
|
||||
0xe6,0x80,0x84,0x9a = csel x6, x7, x4, hi
|
||||
0xc5,0x90,0x85,0x9a = csel x5, x6, x5, ls
|
||||
0xa4,0xa0,0x86,0x9a = csel x4, x5, x6, ge
|
||||
0x83,0xb0,0x87,0x9a = csel x3, x4, x7, lt
|
||||
0x62,0xc0,0x88,0x9a = csel x2, x3, x8, gt
|
||||
0x41,0xd0,0x89,0x9a = csel x1, x2, x9, le
|
||||
0x2a,0xe0,0x94,0x9a = csel x10, x1, x20, al
|
||||
0x44,0x48,0x21,0x7e = uqxtn b4, h2
|
||||
0x62,0x48,0x61,0x7e = uqxtn h2, s3
|
||||
0x49,0x48,0xa1,0x7e = uqxtn s9, d2
|
||||
40
thirdparty/capstone/suite/MC/AArch64/arm64-arithmetic.txt.cs
vendored
Normal file
40
thirdparty/capstone/suite/MC/AArch64/arm64-arithmetic.txt.cs
vendored
Normal file
@@ -0,0 +1,40 @@
|
||||
# CS_ARCH_AARCH64, None, None
|
||||
# This regression test file is new. The option flags could not be determined.
|
||||
# LLVM uses the following mattr = []
|
||||
0x41 0x28 0xc3 0x1a == asr w1, w2, w3
|
||||
0x41 0x28 0xc3 0x9a == asr x1, x2, x3
|
||||
0x41 0x20 0xc3 0x1a == lsl w1, w2, w3
|
||||
0x41 0x20 0xc3 0x9a == lsl x1, x2, x3
|
||||
0x41 0x24 0xc3 0x1a == lsr w1, w2, w3
|
||||
0x41 0x24 0xc3 0x9a == lsr x1, x2, x3
|
||||
0x41 0x2c 0xc3 0x1a == ror w1, w2, w3
|
||||
0x41 0x2c 0xc3 0x9a == ror x1, x2, x3
|
||||
0x41 0x14 0xc0 0x5a == cls w1, w2
|
||||
0x41 0x14 0xc0 0xda == cls x1, x2
|
||||
0x41 0x10 0xc0 0x5a == clz w1, w2
|
||||
0x41 0x10 0xc0 0xda == clz x1, x2
|
||||
0x41 0x00 0xc0 0x5a == rbit w1, w2
|
||||
0x41 0x00 0xc0 0xda == rbit x1, x2
|
||||
0x41 0x08 0xc0 0x5a == rev w1, w2
|
||||
0x41 0x0c 0xc0 0xda == rev x1, x2
|
||||
0x41 0x04 0xc0 0x5a == rev16 w1, w2
|
||||
0x41 0x04 0xc0 0xda == rev16 x1, x2
|
||||
0x41 0x08 0xc0 0xda == rev32 x1, x2
|
||||
0x1f 0x00 0x00 0x31 == cmn w0, #0
|
||||
0x1f 0xfc 0x03 0xb1 == x0, #255
|
||||
0x23 0x08 0x42 0x3a == ccmn w1, #2, #3, eq
|
||||
0x23 0x08 0x42 0xba == ccmn x1, #2, #3, eq
|
||||
0x23 0x08 0x42 0x7a == ccmp w1, #2, #3, eq
|
||||
0x23 0x08 0x42 0xfa == ccmp x1, #2, #3, eq
|
||||
0x23 0x00 0x42 0x3a == ccmn w1, w2, #3, eq
|
||||
0x23 0x00 0x42 0xba == ccmn x1, x2, #3, eq
|
||||
0x23 0x00 0x42 0x7a == ccmp w1, w2, #3, eq
|
||||
0x23 0x00 0x42 0xfa == ccmp x1, x2, #3, eq
|
||||
0x41 0x00 0x83 0x1a == csel w1, w2, w3, eq
|
||||
0x41 0x00 0x83 0x9a == csel x1, x2, x3, eq
|
||||
0x41 0x04 0x83 0x1a == csinc w1, w2, w3, eq
|
||||
0x41 0x04 0x83 0x9a == csinc x1, x2, x3, eq
|
||||
0x41 0x00 0x83 0x5a == csinv w1, w2, w3, eq
|
||||
0x41 0x00 0x83 0xda == csinv x1, x2, x3, eq
|
||||
0x41 0x04 0x83 0x5a == csneg w1, w2, w3, eq
|
||||
0x41 0x04 0x83 0xda == csneg x1, x2, x3, eq
|
||||
10
thirdparty/capstone/suite/MC/AArch64/arm64-basic-a64-instructions.s.cs
vendored
Normal file
10
thirdparty/capstone/suite/MC/AArch64/arm64-basic-a64-instructions.s.cs
vendored
Normal file
@@ -0,0 +1,10 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0xe5,0x40,0xd4,0x1a == crc32b w5, w7, w20
|
||||
0xfc,0x47,0xde,0x1a == crc32h w28, wzr, w30
|
||||
0x20,0x48,0xc2,0x1a == crc32w w0, w1, w2
|
||||
0x27,0x4d,0xd4,0x9a == crc32x w7, w9, x20
|
||||
0xa9,0x50,0xc4,0x1a == crc32cb w9, w5, w4
|
||||
0x2d,0x56,0xd9,0x1a == crc32ch w13, w17, w25
|
||||
0x7f,0x58,0xc5,0x1a == crc32cw wzr, w3, w5
|
||||
0x12,0x5e,0xdf,0x9a == crc32cx w18, w16, xzr
|
||||
13
thirdparty/capstone/suite/MC/AArch64/arm64-bitfield-encoding.s.cs
vendored
Normal file
13
thirdparty/capstone/suite/MC/AArch64/arm64-bitfield-encoding.s.cs
vendored
Normal file
@@ -0,0 +1,13 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
0x41,0x3c,0x01,0x33 = bfxil w1, w2, #1, #15
|
||||
0x41,0x3c,0x41,0xb3 = bfxil x1, x2, #1, #15
|
||||
0x41,0x3c,0x01,0x13 = sbfx w1, w2, #1, #15
|
||||
0x41,0x3c,0x41,0x93 = sbfx x1, x2, #1, #15
|
||||
0x41,0x3c,0x01,0x53 = ubfx w1, w2, #1, #15
|
||||
0x41,0x3c,0x41,0xd3 = ubfx x1, x2, #1, #15
|
||||
0x1f,0x00,0x01,0x13 = sbfiz wzr, w0, #31, #1
|
||||
0x1f,0x00,0x61,0x93 = sbfiz xzr, x0, #31, #1
|
||||
0x1f,0x00,0x01,0x53 = lsl wzr, w0, #31
|
||||
0x1f,0x00,0x61,0xd3 = ubfiz xzr, x0, #31, #1
|
||||
0x41,0x3c,0x83,0x13 = extr w1, w2, w3, #15
|
||||
0x62,0x04,0xc4,0x93 = extr x2, x3, x4, #1
|
||||
25
thirdparty/capstone/suite/MC/AArch64/arm64-branch-encoding.s.cs
vendored
Normal file
25
thirdparty/capstone/suite/MC/AArch64/arm64-branch-encoding.s.cs
vendored
Normal file
@@ -0,0 +1,25 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
0xc0,0x03,0x5f,0xd6 = ret
|
||||
0x20,0x00,0x5f,0xd6 = ret x1
|
||||
0xe0,0x03,0xbf,0xd6 = drps
|
||||
0xe0,0x03,0x9f,0xd6 = eret
|
||||
0xa0,0x00,0x1f,0xd6 = br x5
|
||||
0x20,0x01,0x3f,0xd6 = blr x9
|
||||
0xe3,0xff,0x7f,0x54 = b.lo #1048572
|
||||
0xff,0xff,0xff,0x15 = b #134217724
|
||||
0x00,0x00,0x00,0x16 = b #-134217728
|
||||
0xf4,0xff,0x7f,0x34 = cbz w20, #1048572
|
||||
0x02,0x00,0x80,0xb5 = cbnz x2, #-1048576
|
||||
0xe3,0xff,0x2b,0x36 = tbz w3, #5, #32764
|
||||
0x03,0x00,0x44,0x37 = tbnz w3, #8, #-32768
|
||||
0x20,0x00,0x20,0xd4 = brk #0x1
|
||||
0x41,0x00,0xa0,0xd4 = dcps1 #0x2
|
||||
0x62,0x00,0xa0,0xd4 = dcps2 #0x3
|
||||
0x83,0x00,0xa0,0xd4 = dcps3 #0x4
|
||||
0xa0,0x00,0x40,0xd4 = hlt #0x5
|
||||
0xc2,0x00,0x00,0xd4 = hvc #0x6
|
||||
0xe3,0x00,0x00,0xd4 = smc #0x7
|
||||
0x01,0x01,0x00,0xd4 = svc #0x8
|
||||
0x01,0x00,0xa0,0xd4 = dcps1
|
||||
0x02,0x00,0xa0,0xd4 = dcps2
|
||||
0x03,0x00,0xa0,0xd4 = dcps3
|
||||
32
thirdparty/capstone/suite/MC/AArch64/arm64-branch.txt.cs
vendored
Normal file
32
thirdparty/capstone/suite/MC/AArch64/arm64-branch.txt.cs
vendored
Normal file
@@ -0,0 +1,32 @@
|
||||
# CS_ARCH_AARCH64, None, None
|
||||
# This regression test file is new. The option flags could not be determined.
|
||||
# LLVM uses the following mattr = []
|
||||
0xc0 0x03 0x5f 0xd6 == ret
|
||||
0x20 0x00 0x5f 0xd6 == ret x1
|
||||
0xe0 0x03 0xbf 0xd6 == drps
|
||||
0xe0 0x03 0x9f 0xd6 == eret
|
||||
0xa0 0x00 0x1f 0xd6 == br x5
|
||||
0x20 0x01 0x3f 0xd6 == blr x9
|
||||
0x0B 0x00 0x18 0x37 == tbnz w11, #3, #0
|
||||
0x20 0x00 0x20 0xd4 == brk #0x1
|
||||
0x41 0x00 0xa0 0xd4 == dcps1 #0x2
|
||||
0x62 0x00 0xa0 0xd4 == dcps2 #0x3
|
||||
0x83 0x00 0xa0 0xd4 == dcps3 #0x4
|
||||
0xa0 0x00 0x40 0xd4 == hlt #0x5
|
||||
0xc2 0x00 0x00 0xd4 == hvc #0x6
|
||||
0xe3 0x00 0x00 0xd4 == smc #0x7
|
||||
0x01 0x01 0x00 0xd4 == svc #0x8
|
||||
0x07 0x00 0x00 0x14 == b #28
|
||||
0x06 0x00 0x00 0x94 == bl #24
|
||||
0xa1 0x00 0x00 0x54 == b.ne #20
|
||||
0x80 0x00 0x08 0x36 == tbz w0, #1, #16
|
||||
0xe1 0xff 0xf7 0x36 == tbz w1, #30, #-4
|
||||
0x60 0x00 0x08 0x37 == tbnz w0, #1, #12
|
||||
0x40 0x00 0x00 0xb4 == cbz x0, #8
|
||||
0x20 0x00 0x00 0xb5 == cbnz x0, #4
|
||||
0x1f 0x20 0x03 0xd5 == nop
|
||||
0xff 0xff 0xff 0x17 == b #-4
|
||||
0xc1 0xff 0xff 0x54 == b.ne #-8
|
||||
0xa0 0xff 0x0f 0x36 == tbz w0, #1, #-12
|
||||
0x80 0xff 0xff 0xb4 == cbz x0, #-16
|
||||
0x1f 0x20 0x03 0xd5 == nop
|
||||
7
thirdparty/capstone/suite/MC/AArch64/arm64-compact-unwind-fallback.s.cs
vendored
Normal file
7
thirdparty/capstone/suite/MC/AArch64/arm64-compact-unwind-fallback.s.cs
vendored
Normal file
@@ -0,0 +1,7 @@
|
||||
# CS_ARCH_AARCH64, None, None
|
||||
# This regression test file is new. The option flags could not be determined.
|
||||
# LLVM uses the following mattr = []
|
||||
0x03 == compact encoding: 0x03000000
|
||||
0x03 == compact encoding: 0x03000000
|
||||
0x03 == compact encoding: 0x03000000
|
||||
0x03 == compact encoding: 0x03000000
|
||||
11
thirdparty/capstone/suite/MC/AArch64/arm64-crc32.txt.cs
vendored
Normal file
11
thirdparty/capstone/suite/MC/AArch64/arm64-crc32.txt.cs
vendored
Normal file
@@ -0,0 +1,11 @@
|
||||
# CS_ARCH_AARCH64, None, None
|
||||
# This regression test file is new. The option flags could not be determined.
|
||||
# LLVM uses the following mattr = ['mattr=+crc']
|
||||
0xe5 0x40 0xd4 0x1a == crc32b w5, w7, w20
|
||||
0xfc 0x47 0xde 0x1a == crc32h w28, wzr, w30
|
||||
0x20 0x48 0xc2 0x1a == crc32w w0, w1, w2
|
||||
0x27 0x4d 0xd4 0x9a == crc32x w7, w9, x20
|
||||
0xa9 0x50 0xc4 0x1a == crc32cb w9, w5, w4
|
||||
0x2d 0x56 0xd9 0x1a == crc32ch w13, w17, w25
|
||||
0x7f 0x58 0xc5 0x1a == crc32cw wzr, w3, w5
|
||||
0x12 0x5e 0xdf 0x9a == crc32cx w18, w16, xzr
|
||||
29
thirdparty/capstone/suite/MC/AArch64/arm64-crypto.s.cs
vendored
Normal file
29
thirdparty/capstone/suite/MC/AArch64/arm64-crypto.s.cs
vendored
Normal file
@@ -0,0 +1,29 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
0x20,0x48,0x28,0x4e = aese v0.16b, v1.16b
|
||||
0x20,0x58,0x28,0x4e = aesd v0.16b, v1.16b
|
||||
0x20,0x68,0x28,0x4e = aesmc v0.16b, v1.16b
|
||||
0x20,0x78,0x28,0x4e = aesimc v0.16b, v1.16b
|
||||
0x20,0x00,0x02,0x5e = sha1c q0, s1, v2.4s
|
||||
0x20,0x10,0x02,0x5e = sha1p q0, s1, v2.4s
|
||||
0x20,0x20,0x02,0x5e = sha1m q0, s1, v2.4s
|
||||
0x20,0x30,0x02,0x5e = sha1su0 v0.4s, v1.4s, v2.4s
|
||||
0x20,0x40,0x02,0x5e = sha256h q0, q1, v2.4s
|
||||
0x20,0x50,0x02,0x5e = sha256h2 q0, q1, v2.4s
|
||||
0x20,0x60,0x02,0x5e = sha256su1 v0.4s, v1.4s, v2.4s
|
||||
0x20,0x08,0x28,0x5e = sha1h s0, s1
|
||||
0x20,0x18,0x28,0x5e = sha1su1 v0.4s, v1.4s
|
||||
0x20,0x28,0x28,0x5e = sha256su0 v0.4s, v1.4s
|
||||
0x62,0x48,0x28,0x4e = aese v2.16b, v3.16b
|
||||
0xe5,0x58,0x28,0x4e = aesd v5.16b, v7.16b
|
||||
0xab,0x69,0x28,0x4e = aesmc v11.16b, v13.16b
|
||||
0x71,0x7a,0x28,0x4e = aesimc v17.16b, v19.16b
|
||||
0xb7,0x03,0x03,0x5e = sha1c q23, s29, v3.4s
|
||||
0xee,0x11,0x09,0x5e = sha1p q14, s15, v9.4s
|
||||
0xc2,0x20,0x05,0x5e = sha1m q2, s6, v5.4s
|
||||
0xa3,0x30,0x09,0x5e = sha1su0 v3.4s, v5.4s, v9.4s
|
||||
0xe2,0x40,0x12,0x5e = sha256h q2, q7, v18.4s
|
||||
0x5c,0x52,0x1c,0x5e = sha256h2 q28, q18, v28.4s
|
||||
0xa4,0x60,0x09,0x5e = sha256su1 v4.4s, v5.4s, v9.4s
|
||||
0x1e,0x08,0x28,0x5e = sha1h s30, s0
|
||||
0xaa,0x1a,0x28,0x5e = sha1su1 v10.4s, v21.4s
|
||||
0xe2,0x2b,0x28,0x5e = sha256su0 v2.4s, v31.4s
|
||||
231
thirdparty/capstone/suite/MC/AArch64/arm64-fp-encoding.s.cs
vendored
Normal file
231
thirdparty/capstone/suite/MC/AArch64/arm64-fp-encoding.s.cs
vendored
Normal file
@@ -0,0 +1,231 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
0x41,0xc0,0xe0,0x1e = fabs h1, h2
|
||||
0x41,0xc0,0x20,0x1e = fabs s1, s2
|
||||
0x41,0xc0,0x60,0x1e = fabs d1, d2
|
||||
0x41,0x28,0xe3,0x1e = fadd h1, h2, h3
|
||||
0x41,0x28,0x23,0x1e = fadd s1, s2, s3
|
||||
0x41,0x28,0x63,0x1e = fadd d1, d2, d3
|
||||
0x41,0x18,0xe3,0x1e = fdiv h1, h2, h3
|
||||
0x41,0x18,0x23,0x1e = fdiv s1, s2, s3
|
||||
0x41,0x18,0x63,0x1e = fdiv d1, d2, d3
|
||||
0x41,0x10,0xc3,0x1f = fmadd h1, h2, h3, h4
|
||||
0x41,0x10,0x03,0x1f = fmadd s1, s2, s3, s4
|
||||
0x41,0x10,0x43,0x1f = fmadd d1, d2, d3, d4
|
||||
0x41,0x48,0xe3,0x1e = fmax h1, h2, h3
|
||||
0x41,0x48,0x23,0x1e = fmax s1, s2, s3
|
||||
0x41,0x48,0x63,0x1e = fmax d1, d2, d3
|
||||
0x41,0x68,0xe3,0x1e = fmaxnm h1, h2, h3
|
||||
0x41,0x68,0x23,0x1e = fmaxnm s1, s2, s3
|
||||
0x41,0x68,0x63,0x1e = fmaxnm d1, d2, d3
|
||||
0x41,0x58,0xe3,0x1e = fmin h1, h2, h3
|
||||
0x41,0x58,0x23,0x1e = fmin s1, s2, s3
|
||||
0x41,0x58,0x63,0x1e = fmin d1, d2, d3
|
||||
0x41,0x78,0xe3,0x1e = fminnm h1, h2, h3
|
||||
0x41,0x78,0x23,0x1e = fminnm s1, s2, s3
|
||||
0x41,0x78,0x63,0x1e = fminnm d1, d2, d3
|
||||
0x41,0x90,0xc3,0x1f = fmsub h1, h2, h3, h4
|
||||
0x41,0x90,0x03,0x1f = fmsub s1, s2, s3, s4
|
||||
0x41,0x90,0x43,0x1f = fmsub d1, d2, d3, d4
|
||||
0x41,0x08,0xe3,0x1e = fmul h1, h2, h3
|
||||
0x41,0x08,0x23,0x1e = fmul s1, s2, s3
|
||||
0x41,0x08,0x63,0x1e = fmul d1, d2, d3
|
||||
0x41,0x40,0xe1,0x1e = fneg h1, h2
|
||||
0x41,0x40,0x21,0x1e = fneg s1, s2
|
||||
0x41,0x40,0x61,0x1e = fneg d1, d2
|
||||
0x41,0x10,0xe3,0x1f = fnmadd h1, h2, h3, h4
|
||||
0x41,0x10,0x23,0x1f = fnmadd s1, s2, s3, s4
|
||||
0x41,0x10,0x63,0x1f = fnmadd d1, d2, d3, d4
|
||||
0x41,0x90,0xe3,0x1f = fnmsub h1, h2, h3, h4
|
||||
0x41,0x90,0x23,0x1f = fnmsub s1, s2, s3, s4
|
||||
0x41,0x90,0x63,0x1f = fnmsub d1, d2, d3, d4
|
||||
0x41,0x88,0xe3,0x1e = fnmul h1, h2, h3
|
||||
0x41,0x88,0x23,0x1e = fnmul s1, s2, s3
|
||||
0x41,0x88,0x63,0x1e = fnmul d1, d2, d3
|
||||
0x41,0xc0,0xe1,0x1e = fsqrt h1, h2
|
||||
0x41,0xc0,0x21,0x1e = fsqrt s1, s2
|
||||
0x41,0xc0,0x61,0x1e = fsqrt d1, d2
|
||||
0x41,0x38,0xe3,0x1e = fsub h1, h2, h3
|
||||
0x41,0x38,0x23,0x1e = fsub s1, s2, s3
|
||||
0x41,0x38,0x63,0x1e = fsub d1, d2, d3
|
||||
0x20,0x04,0xe2,0x1e = fccmp h1, h2, #0, eq
|
||||
0x20,0x04,0x22,0x1e = fccmp s1, s2, #0, eq
|
||||
0x20,0x04,0x62,0x1e = fccmp d1, d2, #0, eq
|
||||
0x30,0x04,0xe2,0x1e = fccmpe h1, h2, #0, eq
|
||||
0x30,0x04,0x22,0x1e = fccmpe s1, s2, #0, eq
|
||||
0x30,0x04,0x62,0x1e = fccmpe d1, d2, #0, eq
|
||||
0x20,0x20,0xe2,0x1e = fcmp h1, h2
|
||||
0x20,0x20,0x22,0x1e = fcmp s1, s2
|
||||
0x20,0x20,0x62,0x1e = fcmp d1, d2
|
||||
0x28,0x20,0xe0,0x1e = fcmp h1, #0.0
|
||||
0x28,0x20,0x20,0x1e = fcmp s1, #0.0
|
||||
0x28,0x20,0x60,0x1e = fcmp d1, #0.0
|
||||
0x30,0x20,0xe2,0x1e = fcmpe h1, h2
|
||||
0x30,0x20,0x22,0x1e = fcmpe s1, s2
|
||||
0x30,0x20,0x62,0x1e = fcmpe d1, d2
|
||||
0x38,0x20,0xe0,0x1e = fcmpe h1, #0.0
|
||||
0x38,0x20,0x20,0x1e = fcmpe s1, #0.0
|
||||
0x38,0x20,0x60,0x1e = fcmpe d1, #0.0
|
||||
0x41,0x0c,0xe3,0x1e = fcsel h1, h2, h3, eq
|
||||
0x41,0x0c,0x23,0x1e = fcsel s1, s2, s3, eq
|
||||
0x41,0x0c,0x63,0x1e = fcsel d1, d2, d3, eq
|
||||
0x41,0xc0,0x63,0x1e = fcvt h1, d2
|
||||
0x41,0x40,0x62,0x1e = fcvt s1, d2
|
||||
0x41,0xc0,0xe2,0x1e = fcvt d1, h2
|
||||
0x41,0x40,0xe2,0x1e = fcvt s1, h2
|
||||
0x41,0xc0,0x22,0x1e = fcvt d1, s2
|
||||
0x41,0xc0,0x23,0x1e = fcvt h1, s2
|
||||
0x41,0x00,0x64,0x1e = fcvtas w1, d2
|
||||
0x41,0x00,0x64,0x9e = fcvtas x1, d2
|
||||
0x41,0x00,0x24,0x1e = fcvtas w1, s2
|
||||
0x41,0x00,0x24,0x9e = fcvtas x1, s2
|
||||
0x41,0x00,0xe4,0x1e = fcvtas w1, h2
|
||||
0x41,0x00,0xe4,0x9e = fcvtas x1, h2
|
||||
0x41,0x00,0xe5,0x1e = fcvtau w1, h2
|
||||
0x41,0x00,0x25,0x1e = fcvtau w1, s2
|
||||
0x41,0x00,0x65,0x1e = fcvtau w1, d2
|
||||
0x41,0x00,0xe5,0x9e = fcvtau x1, h2
|
||||
0x41,0x00,0x25,0x9e = fcvtau x1, s2
|
||||
0x41,0x00,0x65,0x9e = fcvtau x1, d2
|
||||
0x41,0x00,0xf0,0x1e = fcvtms w1, h2
|
||||
0x41,0x00,0x30,0x1e = fcvtms w1, s2
|
||||
0x41,0x00,0x70,0x1e = fcvtms w1, d2
|
||||
0x41,0x00,0xf0,0x9e = fcvtms x1, h2
|
||||
0x41,0x00,0x30,0x9e = fcvtms x1, s2
|
||||
0x41,0x00,0x70,0x9e = fcvtms x1, d2
|
||||
0x41,0x00,0xf1,0x1e = fcvtmu w1, h2
|
||||
0x41,0x00,0x31,0x1e = fcvtmu w1, s2
|
||||
0x41,0x00,0x71,0x1e = fcvtmu w1, d2
|
||||
0x41,0x00,0xf1,0x9e = fcvtmu x1, h2
|
||||
0x41,0x00,0x31,0x9e = fcvtmu x1, s2
|
||||
0x41,0x00,0x71,0x9e = fcvtmu x1, d2
|
||||
0x41,0x00,0xe0,0x1e = fcvtns w1, h2
|
||||
0x41,0x00,0x20,0x1e = fcvtns w1, s2
|
||||
0x41,0x00,0x60,0x1e = fcvtns w1, d2
|
||||
0x41,0x00,0xe0,0x9e = fcvtns x1, h2
|
||||
0x41,0x00,0x20,0x9e = fcvtns x1, s2
|
||||
0x41,0x00,0x60,0x9e = fcvtns x1, d2
|
||||
0x41,0x00,0xe1,0x1e = fcvtnu w1, h2
|
||||
0x41,0x00,0x21,0x1e = fcvtnu w1, s2
|
||||
0x41,0x00,0x61,0x1e = fcvtnu w1, d2
|
||||
0x41,0x00,0xe1,0x9e = fcvtnu x1, h2
|
||||
0x41,0x00,0x21,0x9e = fcvtnu x1, s2
|
||||
0x41,0x00,0x61,0x9e = fcvtnu x1, d2
|
||||
0x41,0x00,0xe8,0x1e = fcvtps w1, h2
|
||||
0x41,0x00,0x28,0x1e = fcvtps w1, s2
|
||||
0x41,0x00,0x68,0x1e = fcvtps w1, d2
|
||||
0x41,0x00,0xe8,0x9e = fcvtps x1, h2
|
||||
0x41,0x00,0x28,0x9e = fcvtps x1, s2
|
||||
0x41,0x00,0x68,0x9e = fcvtps x1, d2
|
||||
0x41,0x00,0xe9,0x1e = fcvtpu w1, h2
|
||||
0x41,0x00,0x29,0x1e = fcvtpu w1, s2
|
||||
0x41,0x00,0x69,0x1e = fcvtpu w1, d2
|
||||
0x41,0x00,0xe9,0x9e = fcvtpu x1, h2
|
||||
0x41,0x00,0x29,0x9e = fcvtpu x1, s2
|
||||
0x41,0x00,0x69,0x9e = fcvtpu x1, d2
|
||||
0x41,0x00,0xf8,0x1e = fcvtzs w1, h2
|
||||
0x41,0xfc,0xd8,0x1e = fcvtzs w1, h2, #1
|
||||
0x41,0x00,0x38,0x1e = fcvtzs w1, s2
|
||||
0x41,0xfc,0x18,0x1e = fcvtzs w1, s2, #1
|
||||
0x41,0x00,0x78,0x1e = fcvtzs w1, d2
|
||||
0x41,0xfc,0x58,0x1e = fcvtzs w1, d2, #1
|
||||
0x41,0x00,0xf8,0x9e = fcvtzs x1, h2
|
||||
0x41,0xfc,0xd8,0x9e = fcvtzs x1, h2, #1
|
||||
0x41,0x00,0x38,0x9e = fcvtzs x1, s2
|
||||
0x41,0xfc,0x18,0x9e = fcvtzs x1, s2, #1
|
||||
0x41,0x00,0x78,0x9e = fcvtzs x1, d2
|
||||
0x41,0xfc,0x58,0x9e = fcvtzs x1, d2, #1
|
||||
0x41,0x00,0xf9,0x1e = fcvtzu w1, h2
|
||||
0x41,0xfc,0xd9,0x1e = fcvtzu w1, h2, #1
|
||||
0x41,0x00,0x39,0x1e = fcvtzu w1, s2
|
||||
0x41,0xfc,0x19,0x1e = fcvtzu w1, s2, #1
|
||||
0x41,0x00,0x79,0x1e = fcvtzu w1, d2
|
||||
0x41,0xfc,0x59,0x1e = fcvtzu w1, d2, #1
|
||||
0x41,0x00,0xf9,0x9e = fcvtzu x1, h2
|
||||
0x41,0xfc,0xd9,0x9e = fcvtzu x1, h2, #1
|
||||
0x41,0x00,0x39,0x9e = fcvtzu x1, s2
|
||||
0x41,0xfc,0x19,0x9e = fcvtzu x1, s2, #1
|
||||
0x41,0x00,0x79,0x9e = fcvtzu x1, d2
|
||||
0x41,0xfc,0x59,0x9e = fcvtzu x1, d2, #1
|
||||
0x41,0x00,0xe2,0x1e = scvtf h1, w2
|
||||
0x41,0xfc,0xc2,0x1e = scvtf h1, w2, #1
|
||||
0x41,0x00,0x22,0x1e = scvtf s1, w2
|
||||
0x41,0xfc,0x02,0x1e = scvtf s1, w2, #1
|
||||
0x41,0x00,0x62,0x1e = scvtf d1, w2
|
||||
0x41,0xfc,0x42,0x1e = scvtf d1, w2, #1
|
||||
0x41,0x00,0xe2,0x9e = scvtf h1, x2
|
||||
0x41,0xfc,0xc2,0x9e = scvtf h1, x2, #1
|
||||
0x41,0x00,0x22,0x9e = scvtf s1, x2
|
||||
0x41,0xfc,0x02,0x9e = scvtf s1, x2, #1
|
||||
0x41,0x00,0x62,0x9e = scvtf d1, x2
|
||||
0x41,0xfc,0x42,0x9e = scvtf d1, x2, #1
|
||||
0x41,0x00,0xe3,0x1e = ucvtf h1, w2
|
||||
0x41,0xfc,0xc3,0x1e = ucvtf h1, w2, #1
|
||||
0x41,0x00,0x23,0x1e = ucvtf s1, w2
|
||||
0x41,0xfc,0x03,0x1e = ucvtf s1, w2, #1
|
||||
0x41,0x00,0x63,0x1e = ucvtf d1, w2
|
||||
0x41,0xfc,0x43,0x1e = ucvtf d1, w2, #1
|
||||
0x41,0x00,0xe3,0x9e = ucvtf h1, x2
|
||||
0x41,0xfc,0xc3,0x9e = ucvtf h1, x2, #1
|
||||
0x41,0x00,0x23,0x9e = ucvtf s1, x2
|
||||
0x41,0xfc,0x03,0x9e = ucvtf s1, x2, #1
|
||||
0x41,0x00,0x63,0x9e = ucvtf d1, x2
|
||||
0x41,0xfc,0x43,0x9e = ucvtf d1, x2, #1
|
||||
0x41,0x00,0xe7,0x1e = fmov h1, w2
|
||||
0x41,0x00,0xe6,0x1e = fmov w1, h2
|
||||
0x41,0x00,0xe7,0x9e = fmov h1, x2
|
||||
0x41,0x00,0xe6,0x9e = fmov x1, h2
|
||||
0x41,0x00,0x27,0x1e = fmov s1, w2
|
||||
0x41,0x00,0x26,0x1e = fmov w1, s2
|
||||
0x41,0x00,0x67,0x9e = fmov d1, x2
|
||||
0x41,0x00,0x66,0x9e = fmov x1, d2
|
||||
0x01,0x10,0xe8,0x1e = fmov h1, #0.12500000
|
||||
0x01,0x10,0xe8,0x1e = fmov h1, #0.12500000
|
||||
0x01,0x10,0x28,0x1e = fmov s1, #0.12500000
|
||||
0x01,0x10,0x28,0x1e = fmov s1, #0.12500000
|
||||
0x01,0x10,0x68,0x1e = fmov d1, #0.12500000
|
||||
0x01,0x10,0x68,0x1e = fmov d1, #0.12500000
|
||||
0x01,0xf0,0x7b,0x1e = fmov d1, #-0.48437500
|
||||
0x01,0xf0,0x6b,0x1e = fmov d1, #0.48437500
|
||||
0x03,0x10,0x61,0x1e = fmov d3, #3.00000000
|
||||
0xe2,0x03,0xe7,0x1e = fmov h2, wzr
|
||||
0xe2,0x03,0x27,0x1e = fmov s2, wzr
|
||||
0xe2,0x03,0x67,0x9e = fmov d2, xzr
|
||||
0x41,0x40,0xe0,0x1e = fmov h1, h2
|
||||
0x41,0x40,0x20,0x1e = fmov s1, s2
|
||||
0x41,0x40,0x60,0x1e = fmov d1, d2
|
||||
0xa2,0x00,0xae,0x9e = fmov x2, v5.d[1]
|
||||
0xe9,0x00,0xae,0x9e = fmov x9, v7.d[1]
|
||||
0x21,0x00,0xaf,0x9e = fmov v1.d[1], x1
|
||||
0xc8,0x00,0xaf,0x9e = fmov v8.d[1], x6
|
||||
0x41,0x40,0xe6,0x1e = frinta h1, h2
|
||||
0x41,0x40,0x26,0x1e = frinta s1, s2
|
||||
0x41,0x40,0x66,0x1e = frinta d1, d2
|
||||
0x41,0xc0,0xe7,0x1e = frinti h1, h2
|
||||
0x41,0xc0,0x27,0x1e = frinti s1, s2
|
||||
0x41,0xc0,0x67,0x1e = frinti d1, d2
|
||||
0x41,0x40,0xe5,0x1e = frintm h1, h2
|
||||
0x41,0x40,0x25,0x1e = frintm s1, s2
|
||||
0x41,0x40,0x65,0x1e = frintm d1, d2
|
||||
0x41,0x40,0xe4,0x1e = frintn h1, h2
|
||||
0x41,0x40,0x24,0x1e = frintn s1, s2
|
||||
0x41,0x40,0x64,0x1e = frintn d1, d2
|
||||
0x41,0xc0,0xe4,0x1e = frintp h1, h2
|
||||
0x41,0xc0,0x24,0x1e = frintp s1, s2
|
||||
0x41,0xc0,0x64,0x1e = frintp d1, d2
|
||||
0x41,0x40,0xe7,0x1e = frintx h1, h2
|
||||
0x41,0x40,0x27,0x1e = frintx s1, s2
|
||||
0x41,0x40,0x67,0x1e = frintx d1, d2
|
||||
0x41,0xc0,0xe5,0x1e = frintz h1, h2
|
||||
0x41,0xc0,0x25,0x1e = frintz s1, s2
|
||||
0x41,0xc0,0x65,0x1e = frintz d1, d2
|
||||
0x00,0x3c,0xe0,0x7e = cmhs d0, d0, d0
|
||||
0x00,0x8c,0xe0,0x5e = cmtst d0, d0, d0
|
||||
0x44,0x48,0x21,0x5e = sqxtn b4, h2
|
||||
0x62,0x48,0x61,0x5e = sqxtn h2, s3
|
||||
0x49,0x48,0xa1,0x5e = sqxtn s9, d2
|
||||
0x44,0x28,0x21,0x7e = sqxtun b4, h2
|
||||
0x62,0x28,0x61,0x7e = sqxtun h2, s3
|
||||
0x49,0x28,0xa1,0x7e = sqxtun s9, d2
|
||||
0x44,0x48,0x21,0x7e = uqxtn b4, h2
|
||||
0x62,0x48,0x61,0x7e = uqxtn h2, s3
|
||||
0x49,0x48,0xa1,0x7e = uqxtn s9, d2
|
||||
4
thirdparty/capstone/suite/MC/AArch64/arm64-invalid-logical.txt.cs
vendored
Normal file
4
thirdparty/capstone/suite/MC/AArch64/arm64-invalid-logical.txt.cs
vendored
Normal file
@@ -0,0 +1,4 @@
|
||||
# CS_ARCH_AARCH64, None, None
|
||||
# This regression test file is new. The option flags could not be determined.
|
||||
# LLVM uses the following mattr = []
|
||||
0x7b 0xbf 0x25 0x72 == invalid instruction encoding
|
||||
7
thirdparty/capstone/suite/MC/AArch64/arm64-leaf-compact-unwind.s.cs
vendored
Normal file
7
thirdparty/capstone/suite/MC/AArch64/arm64-leaf-compact-unwind.s.cs
vendored
Normal file
@@ -0,0 +1,7 @@
|
||||
# CS_ARCH_AARCH64, None, None
|
||||
# This regression test file is new. The option flags could not be determined.
|
||||
# LLVM uses the following mattr = []
|
||||
0x02 == compact encoding: 0x02000000
|
||||
0x02 == compact encoding: 0x02009000
|
||||
0x02 == compact encoding: 0x0200400f
|
||||
0x02 == compact encoding: 0x02021010
|
||||
96
thirdparty/capstone/suite/MC/AArch64/arm64-logical-encoding.s.cs
vendored
Normal file
96
thirdparty/capstone/suite/MC/AArch64/arm64-logical-encoding.s.cs
vendored
Normal file
@@ -0,0 +1,96 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
0x00,0x00,0x00,0x12 = and w0, w0, #0x1
|
||||
0x00,0x00,0x40,0x92 = and x0, x0, #0x1
|
||||
0x41,0x0c,0x00,0x12 = and w1, w2, #0xf
|
||||
0x41,0x0c,0x40,0x92 = and x1, x2, #0xf
|
||||
0xbf,0xec,0x7c,0x92 = and sp, x5, #0xfffffffffffffff0
|
||||
0x00,0x00,0x00,0x72 = ands w0, w0, #0x1
|
||||
0x00,0x00,0x40,0xf2 = ands x0, x0, #0x1
|
||||
0x41,0x0c,0x00,0x72 = ands w1, w2, #0xf
|
||||
0x41,0x0c,0x40,0xf2 = ands x1, x2, #0xf
|
||||
0x41,0x00,0x12,0x52 = eor w1, w2, #0x4000
|
||||
0x41,0x00,0x71,0xd2 = eor x1, x2, #0x8000
|
||||
0x41,0x00,0x12,0x32 = orr w1, w2, #0x4000
|
||||
0x41,0x00,0x71,0xb2 = orr x1, x2, #0x8000
|
||||
0xe8,0x03,0x00,0x32 = orr w8, wzr, #0x1
|
||||
0xe8,0x03,0x40,0xb2 = orr x8, xzr, #0x1
|
||||
0x41,0x00,0x03,0x0a = and w1, w2, w3
|
||||
0x41,0x00,0x03,0x8a = and x1, x2, x3
|
||||
0x41,0x08,0x03,0x0a = and w1, w2, w3, lsl #2
|
||||
0x41,0x08,0x03,0x8a = and x1, x2, x3, lsl #2
|
||||
0x41,0x08,0x43,0x0a = and w1, w2, w3, lsr #2
|
||||
0x41,0x08,0x43,0x8a = and x1, x2, x3, lsr #2
|
||||
0x41,0x08,0x83,0x0a = and w1, w2, w3, asr #2
|
||||
0x41,0x08,0x83,0x8a = and x1, x2, x3, asr #2
|
||||
0x41,0x08,0xc3,0x0a = and w1, w2, w3, ror #2
|
||||
0x41,0x08,0xc3,0x8a = and x1, x2, x3, ror #2
|
||||
0x41,0x00,0x03,0x6a = ands w1, w2, w3
|
||||
0x41,0x00,0x03,0xea = ands x1, x2, x3
|
||||
0x41,0x08,0x03,0x6a = ands w1, w2, w3, lsl #2
|
||||
0x41,0x08,0x03,0xea = ands x1, x2, x3, lsl #2
|
||||
0x41,0x08,0x43,0x6a = ands w1, w2, w3, lsr #2
|
||||
0x41,0x08,0x43,0xea = ands x1, x2, x3, lsr #2
|
||||
0x41,0x08,0x83,0x6a = ands w1, w2, w3, asr #2
|
||||
0x41,0x08,0x83,0xea = ands x1, x2, x3, asr #2
|
||||
0x41,0x08,0xc3,0x6a = ands w1, w2, w3, ror #2
|
||||
0x41,0x08,0xc3,0xea = ands x1, x2, x3, ror #2
|
||||
0x41,0x00,0x23,0x0a = bic w1, w2, w3
|
||||
0x41,0x00,0x23,0x8a = bic x1, x2, x3
|
||||
0x41,0x0c,0x23,0x0a = bic w1, w2, w3, lsl #3
|
||||
0x41,0x0c,0x23,0x8a = bic x1, x2, x3, lsl #3
|
||||
0x41,0x0c,0x63,0x0a = bic w1, w2, w3, lsr #3
|
||||
0x41,0x0c,0x63,0x8a = bic x1, x2, x3, lsr #3
|
||||
0x41,0x0c,0xa3,0x0a = bic w1, w2, w3, asr #3
|
||||
0x41,0x0c,0xa3,0x8a = bic x1, x2, x3, asr #3
|
||||
0x41,0x0c,0xe3,0x0a = bic w1, w2, w3, ror #3
|
||||
0x41,0x0c,0xe3,0x8a = bic x1, x2, x3, ror #3
|
||||
0x41,0x00,0x23,0x6a = bics w1, w2, w3
|
||||
0x41,0x00,0x23,0xea = bics x1, x2, x3
|
||||
0x41,0x0c,0x23,0x6a = bics w1, w2, w3, lsl #3
|
||||
0x41,0x0c,0x23,0xea = bics x1, x2, x3, lsl #3
|
||||
0x41,0x0c,0x63,0x6a = bics w1, w2, w3, lsr #3
|
||||
0x41,0x0c,0x63,0xea = bics x1, x2, x3, lsr #3
|
||||
0x41,0x0c,0xa3,0x6a = bics w1, w2, w3, asr #3
|
||||
0x41,0x0c,0xa3,0xea = bics x1, x2, x3, asr #3
|
||||
0x41,0x0c,0xe3,0x6a = bics w1, w2, w3, ror #3
|
||||
0x41,0x0c,0xe3,0xea = bics x1, x2, x3, ror #3
|
||||
0x41,0x00,0x23,0x4a = eon w1, w2, w3
|
||||
0x41,0x00,0x23,0xca = eon x1, x2, x3
|
||||
0x41,0x10,0x23,0x4a = eon w1, w2, w3, lsl #4
|
||||
0x41,0x10,0x23,0xca = eon x1, x2, x3, lsl #4
|
||||
0x41,0x10,0x63,0x4a = eon w1, w2, w3, lsr #4
|
||||
0x41,0x10,0x63,0xca = eon x1, x2, x3, lsr #4
|
||||
0x41,0x10,0xa3,0x4a = eon w1, w2, w3, asr #4
|
||||
0x41,0x10,0xa3,0xca = eon x1, x2, x3, asr #4
|
||||
0x41,0x10,0xe3,0x4a = eon w1, w2, w3, ror #4
|
||||
0x41,0x10,0xe3,0xca = eon x1, x2, x3, ror #4
|
||||
0x41,0x00,0x03,0x4a = eor w1, w2, w3
|
||||
0x41,0x00,0x03,0xca = eor x1, x2, x3
|
||||
0x41,0x14,0x03,0x4a = eor w1, w2, w3, lsl #5
|
||||
0x41,0x14,0x03,0xca = eor x1, x2, x3, lsl #5
|
||||
0x41,0x14,0x43,0x4a = eor w1, w2, w3, lsr #5
|
||||
0x41,0x14,0x43,0xca = eor x1, x2, x3, lsr #5
|
||||
0x41,0x14,0x83,0x4a = eor w1, w2, w3, asr #5
|
||||
0x41,0x14,0x83,0xca = eor x1, x2, x3, asr #5
|
||||
0x41,0x14,0xc3,0x4a = eor w1, w2, w3, ror #5
|
||||
0x41,0x14,0xc3,0xca = eor x1, x2, x3, ror #5
|
||||
0x41,0x00,0x03,0x2a = orr w1, w2, w3
|
||||
0x41,0x00,0x03,0xaa = orr x1, x2, x3
|
||||
0x41,0x18,0x03,0x2a = orr w1, w2, w3, lsl #6
|
||||
0x41,0x18,0x03,0xaa = orr x1, x2, x3, lsl #6
|
||||
0x41,0x18,0x43,0x2a = orr w1, w2, w3, lsr #6
|
||||
0x41,0x18,0x43,0xaa = orr x1, x2, x3, lsr #6
|
||||
0x41,0x18,0x83,0x2a = orr w1, w2, w3, asr #6
|
||||
0x41,0x18,0x83,0xaa = orr x1, x2, x3, asr #6
|
||||
0x41,0x18,0xc3,0x2a = orr w1, w2, w3, ror #6
|
||||
0x41,0x18,0xc3,0xaa = orr x1, x2, x3, ror #6
|
||||
0x41,0x00,0x23,0x2a = orn w1, w2, w3
|
||||
0x41,0x00,0x23,0xaa = orn x1, x2, x3
|
||||
0x41,0x1c,0x23,0x2a = orn w1, w2, w3, lsl #7
|
||||
0x41,0x1c,0x23,0xaa = orn x1, x2, x3, lsl #7
|
||||
0x41,0x1c,0x63,0x2a = orn w1, w2, w3, lsr #7
|
||||
0x41,0x1c,0x63,0xaa = orn x1, x2, x3, lsr #7
|
||||
0x41,0x1c,0xa3,0x2a = orn w1, w2, w3, asr #7
|
||||
0x41,0x1c,0xa3,0xaa = orn x1, x2, x3, asr #7
|
||||
0x41,0x1c,0xe3,0x2a = orn w1, w2, w3, ror #7
|
||||
0x41,0x1c,0xe3,0xaa = orn x1, x2, x3, ror #7
|
||||
248
thirdparty/capstone/suite/MC/AArch64/arm64-memory.s.cs
vendored
Normal file
248
thirdparty/capstone/suite/MC/AArch64/arm64-memory.s.cs
vendored
Normal file
@@ -0,0 +1,248 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
0x85,0x14,0x40,0xb9 = ldr w5, [x4, #20]
|
||||
0x64,0x00,0x40,0xf9 = ldr x4, [x3]
|
||||
0xe2,0x13,0x40,0xf9 = ldr x2, [sp, #32]
|
||||
0xe5,0x07,0x40,0x3d = ldr b5, [sp, #1]
|
||||
0xe6,0x07,0x40,0x7d = ldr h6, [sp, #2]
|
||||
0xe7,0x07,0x40,0xbd = ldr s7, [sp, #4]
|
||||
0xe8,0x07,0x40,0xfd = ldr d8, [sp, #8]
|
||||
0xe9,0x07,0xc0,0x3d = ldr q9, [sp, #16]
|
||||
0x64,0x00,0x40,0x39 = ldrb w4, [x3]
|
||||
0x85,0x50,0x40,0x39 = ldrb w5, [x4, #20]
|
||||
0x69,0x00,0xc0,0x39 = ldrsb w9, [x3]
|
||||
0xe2,0x03,0x82,0x39 = ldrsb x2, [sp, #128]
|
||||
0xe2,0x43,0x40,0x79 = ldrh w2, [sp, #32]
|
||||
0xe3,0x43,0xc0,0x79 = ldrsh w3, [sp, #32]
|
||||
0x25,0x31,0x80,0x79 = ldrsh x5, [x9, #24]
|
||||
0xe9,0x03,0x82,0xb9 = ldrsw x9, [sp, #512]
|
||||
0xe5,0x13,0x80,0xf9 = prfm pldl3strm, [sp, #32]
|
||||
0xff,0x13,0x80,0xf9 = prfm #31, [sp, #32]
|
||||
0x40,0x00,0x80,0xf9 = prfm pldl1keep, [x2]
|
||||
0x41,0x00,0x80,0xf9 = prfm pldl1strm, [x2]
|
||||
0x42,0x00,0x80,0xf9 = prfm pldl2keep, [x2]
|
||||
0x43,0x00,0x80,0xf9 = prfm pldl2strm, [x2]
|
||||
0x44,0x00,0x80,0xf9 = prfm pldl3keep, [x2]
|
||||
0x45,0x00,0x80,0xf9 = prfm pldl3strm, [x2]
|
||||
0x50,0x00,0x80,0xf9 = prfm pstl1keep, [x2]
|
||||
0x51,0x00,0x80,0xf9 = prfm pstl1strm, [x2]
|
||||
0x52,0x00,0x80,0xf9 = prfm pstl2keep, [x2]
|
||||
0x53,0x00,0x80,0xf9 = prfm pstl2strm, [x2]
|
||||
0x54,0x00,0x80,0xf9 = prfm pstl3keep, [x2]
|
||||
0x55,0x00,0x80,0xf9 = prfm pstl3strm, [x2]
|
||||
0x95,0x78,0xa5,0xf8 = prfm pstl3strm, [x4, x5, lsl #3]
|
||||
0x64,0x00,0x00,0xf9 = str x4, [x3]
|
||||
0xe2,0x13,0x00,0xf9 = str x2, [sp, #32]
|
||||
0x85,0x14,0x00,0xb9 = str w5, [x4, #20]
|
||||
0xe5,0x07,0x00,0x3d = str b5, [sp, #1]
|
||||
0xe6,0x07,0x00,0x7d = str h6, [sp, #2]
|
||||
0xe7,0x07,0x00,0xbd = str s7, [sp, #4]
|
||||
0xe8,0x07,0x00,0xfd = str d8, [sp, #8]
|
||||
0xe9,0x07,0x80,0x3d = str q9, [sp, #16]
|
||||
0x64,0x00,0x00,0x39 = strb w4, [x3]
|
||||
0x85,0x50,0x00,0x39 = strb w5, [x4, #20]
|
||||
0xe2,0x43,0x00,0x79 = strh w2, [sp, #32]
|
||||
0x62,0x00,0x40,0xb8 = ldur w2, [x3]
|
||||
0xe2,0x83,0x41,0xb8 = ldur w2, [sp, #24]
|
||||
0x62,0x00,0x40,0xf8 = ldur x2, [x3]
|
||||
0xe2,0x83,0x41,0xf8 = ldur x2, [sp, #24]
|
||||
0xe5,0x13,0x40,0x3c = ldur b5, [sp, #1]
|
||||
0xe6,0x23,0x40,0x7c = ldur h6, [sp, #2]
|
||||
0xe7,0x43,0x40,0xbc = ldur s7, [sp, #4]
|
||||
0xe8,0x83,0x40,0xfc = ldur d8, [sp, #8]
|
||||
0xe9,0x03,0xc1,0x3c = ldur q9, [sp, #16]
|
||||
0x69,0x00,0xc0,0x38 = ldursb w9, [x3]
|
||||
0xe2,0x03,0x88,0x38 = ldursb x2, [sp, #128]
|
||||
0xe3,0x03,0xc2,0x78 = ldursh w3, [sp, #32]
|
||||
0x25,0x81,0x81,0x78 = ldursh x5, [x9, #24]
|
||||
0xe9,0x03,0x98,0xb8 = ldursw x9, [sp, #-128]
|
||||
0x64,0x00,0x00,0xb8 = stur w4, [x3]
|
||||
0xe2,0x03,0x02,0xb8 = stur w2, [sp, #32]
|
||||
0x64,0x00,0x00,0xf8 = stur x4, [x3]
|
||||
0xe2,0x03,0x02,0xf8 = stur x2, [sp, #32]
|
||||
0x85,0x40,0x01,0xb8 = stur w5, [x4, #20]
|
||||
0xe5,0x13,0x00,0x3c = stur b5, [sp, #1]
|
||||
0xe6,0x23,0x00,0x7c = stur h6, [sp, #2]
|
||||
0xe7,0x43,0x00,0xbc = stur s7, [sp, #4]
|
||||
0xe8,0x83,0x00,0xfc = stur d8, [sp, #8]
|
||||
0xe9,0x03,0x81,0x3c = stur q9, [sp, #16]
|
||||
0x64,0x00,0x00,0x38 = sturb w4, [x3]
|
||||
0x85,0x40,0x01,0x38 = sturb w5, [x4, #20]
|
||||
0xe2,0x03,0x02,0x78 = sturh w2, [sp, #32]
|
||||
0xe5,0x03,0x82,0xf8 = prfum pldl3strm, [sp, #32]
|
||||
0x83,0x08,0x41,0xb8 = ldtr w3, [x4, #16]
|
||||
0x83,0x08,0x41,0xf8 = ldtr x3, [x4, #16]
|
||||
0x83,0x08,0x41,0x38 = ldtrb w3, [x4, #16]
|
||||
0x69,0x08,0xc0,0x38 = ldtrsb w9, [x3]
|
||||
0xe2,0x0b,0x88,0x38 = ldtrsb x2, [sp, #128]
|
||||
0x83,0x08,0x41,0x78 = ldtrh w3, [x4, #16]
|
||||
0xe3,0x0b,0xc2,0x78 = ldtrsh w3, [sp, #32]
|
||||
0x25,0x89,0x81,0x78 = ldtrsh x5, [x9, #24]
|
||||
0xe9,0x0b,0x98,0xb8 = ldtrsw x9, [sp, #-128]
|
||||
0x85,0x48,0x01,0xb8 = sttr w5, [x4, #20]
|
||||
0x64,0x08,0x00,0xf8 = sttr x4, [x3]
|
||||
0xe2,0x0b,0x02,0xf8 = sttr x2, [sp, #32]
|
||||
0x64,0x08,0x00,0x38 = sttrb w4, [x3]
|
||||
0x85,0x48,0x01,0x38 = sttrb w5, [x4, #20]
|
||||
0xe2,0x0b,0x02,0x78 = sttrh w2, [sp, #32]
|
||||
0xfd,0x8c,0x40,0xf8 = ldr x29, [x7, #8]!
|
||||
0xfe,0x8c,0x40,0xf8 = ldr x30, [x7, #8]!
|
||||
0x05,0x1c,0x40,0x3c = ldr b5, [x0, #1]!
|
||||
0x06,0x2c,0x40,0x7c = ldr h6, [x0, #2]!
|
||||
0x07,0x4c,0x40,0xbc = ldr s7, [x0, #4]!
|
||||
0x08,0x8c,0x40,0xfc = ldr d8, [x0, #8]!
|
||||
0x09,0x0c,0xc1,0x3c = ldr q9, [x0, #16]!
|
||||
0xfe,0x8c,0x1f,0xf8 = str x30, [x7, #-8]!
|
||||
0xfd,0x8c,0x1f,0xf8 = str x29, [x7, #-8]!
|
||||
0x05,0xfc,0x1f,0x3c = str b5, [x0, #-1]!
|
||||
0x06,0xec,0x1f,0x7c = str h6, [x0, #-2]!
|
||||
0x07,0xcc,0x1f,0xbc = str s7, [x0, #-4]!
|
||||
0x08,0x8c,0x1f,0xfc = str d8, [x0, #-8]!
|
||||
0x09,0x0c,0x9f,0x3c = str q9, [x0, #-16]!
|
||||
0xfe,0x84,0x1f,0xf8 = str x30, [x7], #-8
|
||||
0xfd,0x84,0x1f,0xf8 = str x29, [x7], #-8
|
||||
0x05,0xf4,0x1f,0x3c = str b5, [x0], #-1
|
||||
0x06,0xe4,0x1f,0x7c = str h6, [x0], #-2
|
||||
0x07,0xc4,0x1f,0xbc = str s7, [x0], #-4
|
||||
0x08,0x84,0x1f,0xfc = str d8, [x0], #-8
|
||||
0x09,0x04,0x9f,0x3c = str q9, [x0], #-16
|
||||
0xfd,0x84,0x40,0xf8 = ldr x29, [x7], #8
|
||||
0xfe,0x84,0x40,0xf8 = ldr x30, [x7], #8
|
||||
0x05,0x14,0x40,0x3c = ldr b5, [x0], #1
|
||||
0x06,0x24,0x40,0x7c = ldr h6, [x0], #2
|
||||
0x07,0x44,0x40,0xbc = ldr s7, [x0], #4
|
||||
0x08,0x84,0x40,0xfc = ldr d8, [x0], #8
|
||||
0x09,0x04,0xc1,0x3c = ldr q9, [x0], #16
|
||||
0xe3,0x09,0x42,0x29 = ldp w3, w2, [x15, #16]
|
||||
0xe4,0x27,0x7f,0xa9 = ldp x4, x9, [sp, #-16]
|
||||
0xc2,0x0d,0x42,0x69 = ldpsw x2, x3, [x14, #16]
|
||||
0xe2,0x0f,0x7e,0x69 = ldpsw x2, x3, [sp, #-16]
|
||||
0x4a,0x04,0x48,0x2d = ldp s10, s1, [x2, #64]
|
||||
0x4a,0x04,0x40,0x6d = ldp d10, d1, [x2]
|
||||
0x02,0x0c,0x41,0xad = ldp q2, q3, [x0, #32]
|
||||
0xe3,0x09,0x02,0x29 = stp w3, w2, [x15, #16]
|
||||
0xe4,0x27,0x3f,0xa9 = stp x4, x9, [sp, #-16]
|
||||
0x4a,0x04,0x08,0x2d = stp s10, s1, [x2, #64]
|
||||
0x4a,0x04,0x00,0x6d = stp d10, d1, [x2]
|
||||
0x02,0x0c,0x01,0xad = stp q2, q3, [x0, #32]
|
||||
0xe3,0x09,0xc2,0x29 = ldp w3, w2, [x15, #16]!
|
||||
0xe4,0x27,0xff,0xa9 = ldp x4, x9, [sp, #-16]!
|
||||
0xc2,0x0d,0xc2,0x69 = ldpsw x2, x3, [x14, #16]!
|
||||
0xe2,0x0f,0xfe,0x69 = ldpsw x2, x3, [sp, #-16]!
|
||||
0x4a,0x04,0xc8,0x2d = ldp s10, s1, [x2, #64]!
|
||||
0x4a,0x04,0xc1,0x6d = ldp d10, d1, [x2, #16]!
|
||||
0xe3,0x09,0x82,0x29 = stp w3, w2, [x15, #16]!
|
||||
0xe4,0x27,0xbf,0xa9 = stp x4, x9, [sp, #-16]!
|
||||
0x4a,0x04,0x88,0x2d = stp s10, s1, [x2, #64]!
|
||||
0x4a,0x04,0x81,0x6d = stp d10, d1, [x2, #16]!
|
||||
0xe3,0x09,0xc2,0x28 = ldp w3, w2, [x15], #16
|
||||
0xe4,0x27,0xff,0xa8 = ldp x4, x9, [sp], #-16
|
||||
0xc2,0x0d,0xc2,0x68 = ldpsw x2, x3, [x14], #16
|
||||
0xe2,0x0f,0xfe,0x68 = ldpsw x2, x3, [sp], #-16
|
||||
0x4a,0x04,0xc8,0x2c = ldp s10, s1, [x2], #64
|
||||
0x4a,0x04,0xc1,0x6c = ldp d10, d1, [x2], #16
|
||||
0xe3,0x09,0x82,0x28 = stp w3, w2, [x15], #16
|
||||
0xe4,0x27,0xbf,0xa8 = stp x4, x9, [sp], #-16
|
||||
0x4a,0x04,0x88,0x2c = stp s10, s1, [x2], #64
|
||||
0x4a,0x04,0x81,0x6c = stp d10, d1, [x2], #16
|
||||
0xe3,0x09,0x42,0x28 = ldnp w3, w2, [x15, #16]
|
||||
0xe4,0x27,0x7f,0xa8 = ldnp x4, x9, [sp, #-16]
|
||||
0x4a,0x04,0x48,0x2c = ldnp s10, s1, [x2, #64]
|
||||
0x4a,0x04,0x40,0x6c = ldnp d10, d1, [x2]
|
||||
0xe3,0x09,0x02,0x28 = stnp w3, w2, [x15, #16]
|
||||
0xe4,0x27,0x3f,0xa8 = stnp x4, x9, [sp, #-16]
|
||||
0x4a,0x04,0x08,0x2c = stnp s10, s1, [x2, #64]
|
||||
0x4a,0x04,0x00,0x6c = stnp d10, d1, [x2]
|
||||
0x00,0x68,0x60,0xb8 = ldr w0, [x0, x0]
|
||||
0x00,0x78,0x60,0xb8 = ldr w0, [x0, x0, lsl #2]
|
||||
0x00,0x68,0x60,0xf8 = ldr x0, [x0, x0]
|
||||
0x00,0x78,0x60,0xf8 = ldr x0, [x0, x0, lsl #3]
|
||||
0x00,0xe8,0x60,0xf8 = ldr x0, [x0, x0, sxtx]
|
||||
0x21,0x68,0x62,0x3c = ldr b1, [x1, x2]
|
||||
0x21,0x78,0x62,0x3c = ldr b1, [x1, x2, lsl #0]
|
||||
0x21,0x68,0x62,0x7c = ldr h1, [x1, x2]
|
||||
0x21,0x78,0x62,0x7c = ldr h1, [x1, x2, lsl #1]
|
||||
0x21,0x68,0x62,0xbc = ldr s1, [x1, x2]
|
||||
0x21,0x78,0x62,0xbc = ldr s1, [x1, x2, lsl #2]
|
||||
0x21,0x68,0x62,0xfc = ldr d1, [x1, x2]
|
||||
0x21,0x78,0x62,0xfc = ldr d1, [x1, x2, lsl #3]
|
||||
0x21,0x68,0xe2,0x3c = ldr q1, [x1, x2]
|
||||
0x21,0x78,0xe2,0x3c = ldr q1, [x1, x2, lsl #4]
|
||||
0xe1,0x6b,0x23,0xfc = str d1, [sp, x3]
|
||||
0xe1,0x5b,0x23,0xfc = str d1, [sp, w3, uxtw #3]
|
||||
0xe1,0x6b,0xa3,0x3c = str q1, [sp, x3]
|
||||
0xe1,0x5b,0xa3,0x3c = str q1, [sp, w3, uxtw #4]
|
||||
0x26,0x7c,0x5f,0x08 = ldxrb w6, [x1]
|
||||
0x26,0x7c,0x5f,0x48 = ldxrh w6, [x1]
|
||||
0x27,0x0d,0x7f,0x88 = ldxp w7, w3, [x9]
|
||||
0x27,0x0d,0x7f,0xc8 = ldxp x7, x3, [x9]
|
||||
0x64,0x7c,0x01,0xc8 = stxr w1, x4, [x3]
|
||||
0x64,0x7c,0x01,0x88 = stxr w1, w4, [x3]
|
||||
0x64,0x7c,0x01,0x08 = stxrb w1, w4, [x3]
|
||||
0x64,0x7c,0x01,0x48 = stxrh w1, w4, [x3]
|
||||
0xe2,0x18,0x21,0xc8 = stxp w1, x2, x6, [x7]
|
||||
0x22,0x19,0x21,0x88 = stxp w1, w2, w6, [x9]
|
||||
0xe4,0xff,0xdf,0x88 = ldar w4, [sp]
|
||||
0xe4,0xff,0xdf,0xc8 = ldar x4, [sp]
|
||||
0xe4,0xff,0xdf,0x08 = ldarb w4, [sp]
|
||||
0xe4,0xff,0xdf,0x48 = ldarh w4, [sp]
|
||||
0xc3,0xfc,0x9f,0x88 = stlr w3, [x6]
|
||||
0xc3,0xfc,0x9f,0xc8 = stlr x3, [x6]
|
||||
0xc3,0xfc,0x9f,0x08 = stlrb w3, [x6]
|
||||
0xc3,0xfc,0x9f,0x48 = stlrh w3, [x6]
|
||||
0xc3,0xfc,0x9f,0x88 = stlr w3, [x6]
|
||||
0xc3,0xfc,0x9f,0xc8 = stlr x3, [x6]
|
||||
0xe3,0xff,0x9f,0x08 = stlrb w3, [sp]
|
||||
0xe3,0xff,0x9f,0x08 = stlrb w3, [sp]
|
||||
0xe3,0xff,0x9f,0x08 = stlrb w3, [sp]
|
||||
0x82,0xfc,0x5f,0x88 = ldaxr w2, [x4]
|
||||
0x82,0xfc,0x5f,0xc8 = ldaxr x2, [x4]
|
||||
0x82,0xfc,0x5f,0x08 = ldaxrb w2, [x4]
|
||||
0x82,0xfc,0x5f,0x48 = ldaxrh w2, [x4]
|
||||
0x22,0x98,0x7f,0x88 = ldaxp w2, w6, [x1]
|
||||
0x22,0x98,0x7f,0xc8 = ldaxp x2, x6, [x1]
|
||||
0x27,0xfc,0x08,0xc8 = stlxr w8, x7, [x1]
|
||||
0x27,0xfc,0x08,0x88 = stlxr w8, w7, [x1]
|
||||
0x27,0xfc,0x08,0x08 = stlxrb w8, w7, [x1]
|
||||
0x27,0xfc,0x08,0x48 = stlxrh w8, w7, [x1]
|
||||
0xe2,0x98,0x21,0xc8 = stlxp w1, x2, x6, [x7]
|
||||
0x22,0x99,0x21,0x88 = stlxp w1, w2, w6, [x9]
|
||||
0xab,0x83,0x5f,0xf8 = ldur x11, [x29, #-8]
|
||||
0xab,0x73,0x40,0xf8 = ldur x11, [x29, #7]
|
||||
0x00,0x20,0x40,0xb8 = ldur w0, [x0, #2]
|
||||
0x00,0x00,0x50,0xb8 = ldur w0, [x0, #-256]
|
||||
0x22,0xe0,0x5f,0x3c = ldur b2, [x1, #-2]
|
||||
0x43,0x30,0x40,0x7c = ldur h3, [x2, #3]
|
||||
0x63,0xc0,0x5f,0x7c = ldur h3, [x3, #-4]
|
||||
0x83,0x30,0x40,0xbc = ldur s3, [x4, #3]
|
||||
0xa3,0xc0,0x5f,0xbc = ldur s3, [x5, #-4]
|
||||
0xc4,0x40,0x40,0xfc = ldur d4, [x6, #4]
|
||||
0xe4,0x80,0x5f,0xfc = ldur d4, [x7, #-8]
|
||||
0x05,0x81,0xc0,0x3c = ldur q5, [x8, #8]
|
||||
0x25,0x01,0xdf,0x3c = ldur q5, [x9, #-16]
|
||||
0xab,0x83,0x1f,0xf8 = stur x11, [x29, #-8]
|
||||
0xab,0x73,0x00,0xf8 = stur x11, [x29, #7]
|
||||
0x00,0x20,0x00,0xb8 = stur w0, [x0, #2]
|
||||
0x00,0x00,0x10,0xb8 = stur w0, [x0, #-256]
|
||||
0x22,0xe0,0x1f,0x3c = stur b2, [x1, #-2]
|
||||
0x43,0x30,0x00,0x7c = stur h3, [x2, #3]
|
||||
0x63,0xc0,0x1f,0x7c = stur h3, [x3, #-4]
|
||||
0x83,0x30,0x00,0xbc = stur s3, [x4, #3]
|
||||
0xa3,0xc0,0x1f,0xbc = stur s3, [x5, #-4]
|
||||
0xc4,0x40,0x00,0xfc = stur d4, [x6, #4]
|
||||
0xe4,0x80,0x1f,0xfc = stur d4, [x7, #-8]
|
||||
0x05,0x81,0x80,0x3c = stur q5, [x8, #8]
|
||||
0x25,0x01,0x9f,0x3c = stur q5, [x9, #-16]
|
||||
0x23,0xf0,0x5f,0x38 = ldurb w3, [x1, #-1]
|
||||
0x44,0x10,0x40,0x78 = ldurh w4, [x2, #1]
|
||||
0x65,0xf0,0x5f,0x78 = ldurh w5, [x3, #-1]
|
||||
0x86,0xf0,0xdf,0x38 = ldursb w6, [x4, #-1]
|
||||
0xa7,0xf0,0x9f,0x38 = ldursb x7, [x5, #-1]
|
||||
0xc8,0x10,0xc0,0x78 = ldursh w8, [x6, #1]
|
||||
0xe9,0xf0,0xdf,0x78 = ldursh w9, [x7, #-1]
|
||||
0x01,0x11,0x80,0x78 = ldursh x1, [x8, #1]
|
||||
0x22,0xf1,0x9f,0x78 = ldursh x2, [x9, #-1]
|
||||
0x43,0xa1,0x80,0xb8 = ldursw x3, [x10, #10]
|
||||
0x64,0xf1,0x9f,0xb8 = ldursw x4, [x11, #-1]
|
||||
0x23,0xf0,0x1f,0x38 = sturb w3, [x1, #-1]
|
||||
0x44,0x10,0x00,0x78 = sturh w4, [x2, #1]
|
||||
0x65,0xf0,0x1f,0x78 = sturh w5, [x3, #-1]
|
||||
6
thirdparty/capstone/suite/MC/AArch64/arm64-nv-cond.s.cs
vendored
Normal file
6
thirdparty/capstone/suite/MC/AArch64/arm64-nv-cond.s.cs
vendored
Normal file
@@ -0,0 +1,6 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0xfc,0xff,0x7f,0x1e == fcsel d28, d31, d31, nv
|
||||
0x00,0xf0,0x80,0x9a == csel x0, x0, x0, nv
|
||||
0x00,0xf0,0x40,0xfa == ccmp x0, x0, #0, nv
|
||||
0x0f,0x00,0x00,0x54 == b.nv #0
|
||||
8
thirdparty/capstone/suite/MC/AArch64/arm64-optional-hash.s.cs
vendored
Normal file
8
thirdparty/capstone/suite/MC/AArch64/arm64-optional-hash.s.cs
vendored
Normal file
@@ -0,0 +1,8 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
0xff,0x83,0x00,0x91 = add sp, sp, #32
|
||||
0x83,0x00,0x50,0xb1 = adds x3, x4, #1024, lsl #12
|
||||
0x5f,0x60,0x23,0x8b = add sp, x2, x3
|
||||
0x01,0x10,0x28,0x1e = fmov s1, #0.12500000
|
||||
0xbf,0x33,0x03,0xd5 = dmb osh
|
||||
0xe3,0x09,0x42,0x28 = ldnp w3, w2, [x15, #16]
|
||||
0x95,0x78,0xa5,0xf8 = prfm pstl3strm, [x4, x5, lsl #3]
|
||||
1043
thirdparty/capstone/suite/MC/AArch64/arm64-simd-ldst.s.cs
vendored
Normal file
1043
thirdparty/capstone/suite/MC/AArch64/arm64-simd-ldst.s.cs
vendored
Normal file
File diff suppressed because it is too large
Load Diff
8
thirdparty/capstone/suite/MC/AArch64/arm64-spsel-sysreg.s.cs
vendored
Normal file
8
thirdparty/capstone/suite/MC/AArch64/arm64-spsel-sysreg.s.cs
vendored
Normal file
@@ -0,0 +1,8 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0xbf,0x40,0x00,0xd5 == msr SPSel, #0
|
||||
0x00,0x42,0x18,0xd5 == msr SPSel, x0
|
||||
0xdf,0x40,0x03,0xd5 == msr DAIFSet, #0
|
||||
0x00,0x52,0x18,0xd5 == msr ESR_EL1, x0
|
||||
0x00,0x42,0x38,0xd5 == mrs x0, SPSel
|
||||
0x00,0x52,0x38,0xd5 == mrs x0, ESR_EL1
|
||||
362
thirdparty/capstone/suite/MC/AArch64/arm64-system-encoding.s.cs
vendored
Normal file
362
thirdparty/capstone/suite/MC/AArch64/arm64-system-encoding.s.cs
vendored
Normal file
@@ -0,0 +1,362 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
0x1f,0x20,0x03,0xd5 = nop
|
||||
0x9f,0x20,0x03,0xd5 = sev
|
||||
0xbf,0x20,0x03,0xd5 = sevl
|
||||
0x5f,0x20,0x03,0xd5 = wfe
|
||||
0x7f,0x20,0x03,0xd5 = wfi
|
||||
0x3f,0x20,0x03,0xd5 = yield
|
||||
0x5f,0x3a,0x03,0xd5 = clrex #10
|
||||
0xdf,0x3f,0x03,0xd5 = isb
|
||||
0xdf,0x3f,0x03,0xd5 = isb
|
||||
0xbf,0x33,0x03,0xd5 = dmb osh
|
||||
0xbf,0x33,0x03,0xd5 = dmb osh
|
||||
0x9f,0x37,0x03,0xd5 = dsb nsh
|
||||
0x9f,0x37,0x03,0xd5 = dsb nsh
|
||||
0xff,0x05,0x0a,0xd5 = sys #2, c0, c5, #7
|
||||
0xe7,0x6a,0x0f,0xd5 = sys #7, c6, c10, #7, x7
|
||||
0xf4,0x3f,0x2e,0xd5 = sysl x20, #6, c3, c15, #7
|
||||
0x23,0x10,0x18,0xd5 = msr ACTLR_EL1, x3
|
||||
0x23,0x10,0x1c,0xd5 = msr ACTLR_EL2, x3
|
||||
0x23,0x10,0x1e,0xd5 = msr ACTLR_EL3, x3
|
||||
0x03,0x51,0x18,0xd5 = msr AFSR0_EL1, x3
|
||||
0x03,0x51,0x1c,0xd5 = msr AFSR0_EL2, x3
|
||||
0x03,0x51,0x1e,0xd5 = msr AFSR0_EL3, x3
|
||||
0x23,0x51,0x18,0xd5 = msr AFSR1_EL1, x3
|
||||
0x23,0x51,0x1c,0xd5 = msr AFSR1_EL2, x3
|
||||
0x23,0x51,0x1e,0xd5 = msr AFSR1_EL3, x3
|
||||
0x03,0xa3,0x18,0xd5 = msr AMAIR_EL1, x3
|
||||
0x03,0xa3,0x1c,0xd5 = msr AMAIR_EL2, x3
|
||||
0x03,0xa3,0x1e,0xd5 = msr AMAIR_EL3, x3
|
||||
0x03,0xe0,0x1b,0xd5 = msr CNTFRQ_EL0, x3
|
||||
0x03,0xe1,0x1c,0xd5 = msr CNTHCTL_EL2, x3
|
||||
0x23,0xe2,0x1c,0xd5 = msr CNTHP_CTL_EL2, x3
|
||||
0x43,0xe2,0x1c,0xd5 = msr CNTHP_CVAL_EL2, x3
|
||||
0x03,0xe2,0x1c,0xd5 = msr CNTHP_TVAL_EL2, x3
|
||||
0x03,0xe1,0x18,0xd5 = msr CNTKCTL_EL1, x3
|
||||
0x23,0xe2,0x1b,0xd5 = msr CNTP_CTL_EL0, x3
|
||||
0x43,0xe2,0x1b,0xd5 = msr CNTP_CVAL_EL0, x3
|
||||
0x03,0xe2,0x1b,0xd5 = msr CNTP_TVAL_EL0, x3
|
||||
0x63,0xe0,0x1c,0xd5 = msr CNTVOFF_EL2, x3
|
||||
0x23,0xe3,0x1b,0xd5 = msr CNTV_CTL_EL0, x3
|
||||
0x43,0xe3,0x1b,0xd5 = msr CNTV_CVAL_EL0, x3
|
||||
0x03,0xe3,0x1b,0xd5 = msr CNTV_TVAL_EL0, x3
|
||||
0x23,0xd0,0x18,0xd5 = msr CONTEXTIDR_EL1, x3
|
||||
0x43,0x10,0x18,0xd5 = msr CPACR_EL1, x3
|
||||
0x43,0x11,0x1c,0xd5 = msr CPTR_EL2, x3
|
||||
0x43,0x11,0x1e,0xd5 = msr CPTR_EL3, x3
|
||||
0x03,0x00,0x1a,0xd5 = msr CSSELR_EL1, x3
|
||||
0x03,0x30,0x1c,0xd5 = msr DACR32_EL2, x3
|
||||
0x03,0x52,0x18,0xd5 = msr ESR_EL1, x3
|
||||
0x03,0x52,0x1c,0xd5 = msr ESR_EL2, x3
|
||||
0x03,0x52,0x1e,0xd5 = msr ESR_EL3, x3
|
||||
0x03,0x60,0x18,0xd5 = msr FAR_EL1, x3
|
||||
0x03,0x60,0x1c,0xd5 = msr FAR_EL2, x3
|
||||
0x03,0x60,0x1e,0xd5 = msr FAR_EL3, x3
|
||||
0x03,0x53,0x1c,0xd5 = msr FPEXC32_EL2, x3
|
||||
0xe3,0x11,0x1c,0xd5 = msr HACR_EL2, x3
|
||||
0x03,0x11,0x1c,0xd5 = msr HCR_EL2, x3
|
||||
0x83,0x60,0x1c,0xd5 = msr HPFAR_EL2, x3
|
||||
0x63,0x11,0x1c,0xd5 = msr HSTR_EL2, x3
|
||||
0x23,0x50,0x1c,0xd5 = msr IFSR32_EL2, x3
|
||||
0x03,0xa2,0x18,0xd5 = msr MAIR_EL1, x3
|
||||
0x03,0xa2,0x1c,0xd5 = msr MAIR_EL2, x3
|
||||
0x03,0xa2,0x1e,0xd5 = msr MAIR_EL3, x3
|
||||
0x23,0x11,0x1c,0xd5 = msr MDCR_EL2, x3
|
||||
0x23,0x13,0x1e,0xd5 = msr MDCR_EL3, x3
|
||||
0x03,0x74,0x18,0xd5 = msr PAR_EL1, x3
|
||||
0x03,0x11,0x1e,0xd5 = msr SCR_EL3, x3
|
||||
0x03,0x10,0x18,0xd5 = msr SCTLR_EL1, x3
|
||||
0x03,0x10,0x1c,0xd5 = msr SCTLR_EL2, x3
|
||||
0x03,0x10,0x1e,0xd5 = msr SCTLR_EL3, x3
|
||||
0x23,0x11,0x1e,0xd5 = msr SDER32_EL3, x3
|
||||
0x43,0x20,0x18,0xd5 = msr TCR_EL1, x3
|
||||
0x43,0x20,0x1c,0xd5 = msr TCR_EL2, x3
|
||||
0x43,0x20,0x1e,0xd5 = msr TCR_EL3, x3
|
||||
0x03,0x00,0x12,0xd5 = msr TEECR32_EL1, x3
|
||||
0x03,0x10,0x12,0xd5 = msr TEEHBR32_EL1, x3
|
||||
0x63,0xd0,0x1b,0xd5 = msr TPIDRRO_EL0, x3
|
||||
0x43,0xd0,0x1b,0xd5 = msr TPIDR_EL0, x3
|
||||
0x83,0xd0,0x18,0xd5 = msr TPIDR_EL1, x3
|
||||
0x43,0xd0,0x1c,0xd5 = msr TPIDR_EL2, x3
|
||||
0x43,0xd0,0x1e,0xd5 = msr TPIDR_EL3, x3
|
||||
0x03,0x20,0x18,0xd5 = msr TTBR0_EL1, x3
|
||||
0x03,0x20,0x1c,0xd5 = msr TTBR0_EL2, x3
|
||||
0x03,0x20,0x1e,0xd5 = msr TTBR0_EL3, x3
|
||||
0x23,0x20,0x18,0xd5 = msr TTBR1_EL1, x3
|
||||
0x03,0xc0,0x18,0xd5 = msr VBAR_EL1, x3
|
||||
0x03,0xc0,0x1c,0xd5 = msr VBAR_EL2, x3
|
||||
0x03,0xc0,0x1e,0xd5 = msr VBAR_EL3, x3
|
||||
0xa3,0x00,0x1c,0xd5 = msr VMPIDR_EL2, x3
|
||||
0x03,0x00,0x1c,0xd5 = msr VPIDR_EL2, x3
|
||||
0x43,0x21,0x1c,0xd5 = msr VTCR_EL2, x3
|
||||
0x03,0x21,0x1c,0xd5 = msr VTTBR_EL2, x3
|
||||
0x03,0x42,0x18,0xd5 = msr SPSel, x3
|
||||
0x23,0xa3,0x18,0xd5 = msr AMAIR2_EL1, x3
|
||||
0x23,0xa3,0x1d,0xd5 = msr AMAIR2_EL12, x3
|
||||
0x23,0xa3,0x1c,0xd5 = msr AMAIR2_EL2, x3
|
||||
0x23,0xa3,0x1e,0xd5 = msr AMAIR2_EL3, x3
|
||||
0x23,0xa2,0x18,0xd5 = msr MAIR2_EL1, x3
|
||||
0x23,0xa2,0x1d,0xd5 = msr MAIR2_EL12, x3
|
||||
0x23,0xa1,0x1c,0xd5 = msr MAIR2_EL2, x3
|
||||
0x23,0xa1,0x1e,0xd5 = msr MAIR2_EL3, x3
|
||||
0x43,0xa2,0x18,0xd5 = msr PIRE0_EL1, x3
|
||||
0x43,0xa2,0x1d,0xd5 = msr PIRE0_EL12, x3
|
||||
0x43,0xa2,0x1c,0xd5 = msr PIRE0_EL2, x3
|
||||
0x63,0xa2,0x18,0xd5 = msr PIR_EL1, x3
|
||||
0x63,0xa2,0x1d,0xd5 = msr PIR_EL12, x3
|
||||
0x63,0xa2,0x1c,0xd5 = msr PIR_EL2, x3
|
||||
0x63,0xa2,0x1e,0xd5 = msr PIR_EL3, x3
|
||||
0xa3,0xa2,0x1c,0xd5 = msr S2PIR_EL2, x3
|
||||
0x83,0xa2,0x1b,0xd5 = msr POR_EL0, x3
|
||||
0x83,0xa2,0x18,0xd5 = msr POR_EL1, x3
|
||||
0x83,0xa2,0x1d,0xd5 = msr POR_EL12, x3
|
||||
0x83,0xa2,0x1c,0xd5 = msr POR_EL2, x3
|
||||
0x83,0xa2,0x1e,0xd5 = msr POR_EL3, x3
|
||||
0xa3,0xa2,0x18,0xd5 = msr S2POR_EL1, x3
|
||||
0x63,0x10,0x18,0xd5 = msr SCTLR2_EL1, x3
|
||||
0x63,0x10,0x1d,0xd5 = msr SCTLR2_EL12, x3
|
||||
0x63,0x10,0x1c,0xd5 = msr SCTLR2_EL2, x3
|
||||
0x63,0x10,0x1e,0xd5 = msr SCTLR2_EL3, x3
|
||||
0x63,0x20,0x18,0xd5 = msr TCR2_EL1, x3
|
||||
0x63,0x20,0x1d,0xd5 = msr TCR2_EL12, x3
|
||||
0x63,0x20,0x1c,0xd5 = msr TCR2_EL2, x3
|
||||
0x81,0xb6,0x1a,0xd5 = msr S3_2_C11_C6_4, x1
|
||||
0x00,0x00,0x00,0xd5 = msr S0_0_C0_C0_0, x0
|
||||
0xa2,0x34,0x0a,0xd5 = sys #2, c3, c4, #5, x2
|
||||
0x23,0x10,0x38,0xd5 = mrs x3, ACTLR_EL1
|
||||
0x23,0x10,0x3c,0xd5 = mrs x3, ACTLR_EL2
|
||||
0x23,0x10,0x3e,0xd5 = mrs x3, ACTLR_EL3
|
||||
0x03,0x51,0x38,0xd5 = mrs x3, AFSR0_EL1
|
||||
0x03,0x51,0x3c,0xd5 = mrs x3, AFSR0_EL2
|
||||
0x03,0x51,0x3e,0xd5 = mrs x3, AFSR0_EL3
|
||||
0xe3,0x00,0x39,0xd5 = mrs x3, AIDR_EL1
|
||||
0x23,0x51,0x38,0xd5 = mrs x3, AFSR1_EL1
|
||||
0x23,0x51,0x3c,0xd5 = mrs x3, AFSR1_EL2
|
||||
0x23,0x51,0x3e,0xd5 = mrs x3, AFSR1_EL3
|
||||
0x03,0xa3,0x38,0xd5 = mrs x3, AMAIR_EL1
|
||||
0x03,0xa3,0x3c,0xd5 = mrs x3, AMAIR_EL2
|
||||
0x03,0xa3,0x3e,0xd5 = mrs x3, AMAIR_EL3
|
||||
0x03,0x00,0x39,0xd5 = mrs x3, CCSIDR_EL1
|
||||
0x23,0x00,0x39,0xd5 = mrs x3, CLIDR_EL1
|
||||
0x43,0x00,0x39,0xd5 = mrs x3, CCSIDR2_EL1
|
||||
0x03,0xe0,0x3b,0xd5 = mrs x3, CNTFRQ_EL0
|
||||
0x03,0xe1,0x3c,0xd5 = mrs x3, CNTHCTL_EL2
|
||||
0x23,0xe2,0x3c,0xd5 = mrs x3, CNTHP_CTL_EL2
|
||||
0x43,0xe2,0x3c,0xd5 = mrs x3, CNTHP_CVAL_EL2
|
||||
0x03,0xe2,0x3c,0xd5 = mrs x3, CNTHP_TVAL_EL2
|
||||
0x03,0xe1,0x38,0xd5 = mrs x3, CNTKCTL_EL1
|
||||
0x23,0xe0,0x3b,0xd5 = mrs x3, CNTPCT_EL0
|
||||
0x23,0xe2,0x3b,0xd5 = mrs x3, CNTP_CTL_EL0
|
||||
0x43,0xe2,0x3b,0xd5 = mrs x3, CNTP_CVAL_EL0
|
||||
0x03,0xe2,0x3b,0xd5 = mrs x3, CNTP_TVAL_EL0
|
||||
0x43,0xe0,0x3b,0xd5 = mrs x3, CNTVCT_EL0
|
||||
0x63,0xe0,0x3c,0xd5 = mrs x3, CNTVOFF_EL2
|
||||
0x23,0xe3,0x3b,0xd5 = mrs x3, CNTV_CTL_EL0
|
||||
0x43,0xe3,0x3b,0xd5 = mrs x3, CNTV_CVAL_EL0
|
||||
0x03,0xe3,0x3b,0xd5 = mrs x3, CNTV_TVAL_EL0
|
||||
0x23,0xd0,0x38,0xd5 = mrs x3, CONTEXTIDR_EL1
|
||||
0x43,0x10,0x38,0xd5 = mrs x3, CPACR_EL1
|
||||
0x43,0x11,0x3c,0xd5 = mrs x3, CPTR_EL2
|
||||
0x43,0x11,0x3e,0xd5 = mrs x3, CPTR_EL3
|
||||
0x03,0x00,0x3a,0xd5 = mrs x3, CSSELR_EL1
|
||||
0x23,0x00,0x3b,0xd5 = mrs x3, CTR_EL0
|
||||
0x43,0x42,0x38,0xd5 = mrs x3, CurrentEL
|
||||
0x03,0x30,0x3c,0xd5 = mrs x3, DACR32_EL2
|
||||
0xe3,0x00,0x3b,0xd5 = mrs x3, DCZID_EL0
|
||||
0xc3,0x00,0x38,0xd5 = mrs x3, REVIDR_EL1
|
||||
0x03,0x52,0x38,0xd5 = mrs x3, ESR_EL1
|
||||
0x03,0x52,0x3c,0xd5 = mrs x3, ESR_EL2
|
||||
0x03,0x52,0x3e,0xd5 = mrs x3, ESR_EL3
|
||||
0x03,0x60,0x38,0xd5 = mrs x3, FAR_EL1
|
||||
0x03,0x60,0x3c,0xd5 = mrs x3, FAR_EL2
|
||||
0x03,0x60,0x3e,0xd5 = mrs x3, FAR_EL3
|
||||
0x03,0x53,0x3c,0xd5 = mrs x3, FPEXC32_EL2
|
||||
0xe3,0x11,0x3c,0xd5 = mrs x3, HACR_EL2
|
||||
0x03,0x11,0x3c,0xd5 = mrs x3, HCR_EL2
|
||||
0x83,0x60,0x3c,0xd5 = mrs x3, HPFAR_EL2
|
||||
0x63,0x11,0x3c,0xd5 = mrs x3, HSTR_EL2
|
||||
0x03,0x05,0x38,0xd5 = mrs x3, ID_AA64DFR0_EL1
|
||||
0x23,0x05,0x38,0xd5 = mrs x3, ID_AA64DFR1_EL1
|
||||
0x03,0x06,0x38,0xd5 = mrs x3, ID_AA64ISAR0_EL1
|
||||
0x23,0x06,0x38,0xd5 = mrs x3, ID_AA64ISAR1_EL1
|
||||
0x43,0x06,0x38,0xd5 = mrs x3, ID_AA64ISAR2_EL1
|
||||
0x03,0x07,0x38,0xd5 = mrs x3, ID_AA64MMFR0_EL1
|
||||
0x23,0x07,0x38,0xd5 = mrs x3, ID_AA64MMFR1_EL1
|
||||
0x43,0x07,0x38,0xd5 = mrs x3, ID_AA64MMFR2_EL1
|
||||
0x63,0x07,0x38,0xd5 = mrs x3, ID_AA64MMFR3_EL1
|
||||
0x83,0x07,0x38,0xd5 = mrs x3, ID_AA64MMFR4_EL1
|
||||
0x03,0x04,0x38,0xd5 = mrs x3, ID_AA64PFR0_EL1
|
||||
0x23,0x04,0x38,0xd5 = mrs x3, ID_AA64PFR1_EL1
|
||||
0x43,0x04,0x38,0xd5 = mrs x3, ID_AA64PFR2_EL1
|
||||
0x23,0x50,0x3c,0xd5 = mrs x3, IFSR32_EL2
|
||||
0x03,0xc1,0x38,0xd5 = mrs x3, ISR_EL1
|
||||
0x03,0xa2,0x38,0xd5 = mrs x3, MAIR_EL1
|
||||
0x03,0xa2,0x3c,0xd5 = mrs x3, MAIR_EL2
|
||||
0x03,0xa2,0x3e,0xd5 = mrs x3, MAIR_EL3
|
||||
0x23,0x11,0x3c,0xd5 = mrs x3, MDCR_EL2
|
||||
0x23,0x13,0x3e,0xd5 = mrs x3, MDCR_EL3
|
||||
0x03,0x00,0x38,0xd5 = mrs x3, MIDR_EL1
|
||||
0xa3,0x00,0x38,0xd5 = mrs x3, MPIDR_EL1
|
||||
0x03,0x03,0x38,0xd5 = mrs x3, MVFR0_EL1
|
||||
0x23,0x03,0x38,0xd5 = mrs x3, MVFR1_EL1
|
||||
0x03,0x74,0x38,0xd5 = mrs x3, PAR_EL1
|
||||
0x23,0xc0,0x38,0xd5 = mrs x3, RVBAR_EL1
|
||||
0x23,0xc0,0x3c,0xd5 = mrs x3, RVBAR_EL2
|
||||
0x23,0xc0,0x3e,0xd5 = mrs x3, RVBAR_EL3
|
||||
0x03,0x11,0x3e,0xd5 = mrs x3, SCR_EL3
|
||||
0x03,0x10,0x38,0xd5 = mrs x3, SCTLR_EL1
|
||||
0x03,0x10,0x3c,0xd5 = mrs x3, SCTLR_EL2
|
||||
0x03,0x10,0x3e,0xd5 = mrs x3, SCTLR_EL3
|
||||
0x23,0x11,0x3e,0xd5 = mrs x3, SDER32_EL3
|
||||
0x43,0x20,0x38,0xd5 = mrs x3, TCR_EL1
|
||||
0x43,0x20,0x3c,0xd5 = mrs x3, TCR_EL2
|
||||
0x43,0x20,0x3e,0xd5 = mrs x3, TCR_EL3
|
||||
0x03,0x00,0x32,0xd5 = mrs x3, TEECR32_EL1
|
||||
0x03,0x10,0x32,0xd5 = mrs x3, TEEHBR32_EL1
|
||||
0x63,0xd0,0x3b,0xd5 = mrs x3, TPIDRRO_EL0
|
||||
0x43,0xd0,0x3b,0xd5 = mrs x3, TPIDR_EL0
|
||||
0x83,0xd0,0x38,0xd5 = mrs x3, TPIDR_EL1
|
||||
0x43,0xd0,0x3c,0xd5 = mrs x3, TPIDR_EL2
|
||||
0x43,0xd0,0x3e,0xd5 = mrs x3, TPIDR_EL3
|
||||
0x03,0x20,0x38,0xd5 = mrs x3, TTBR0_EL1
|
||||
0x03,0x20,0x3c,0xd5 = mrs x3, TTBR0_EL2
|
||||
0x03,0x20,0x3e,0xd5 = mrs x3, TTBR0_EL3
|
||||
0x23,0x20,0x38,0xd5 = mrs x3, TTBR1_EL1
|
||||
0x03,0xc0,0x38,0xd5 = mrs x3, VBAR_EL1
|
||||
0x03,0xc0,0x3c,0xd5 = mrs x3, VBAR_EL2
|
||||
0x03,0xc0,0x3e,0xd5 = mrs x3, VBAR_EL3
|
||||
0xa3,0x00,0x3c,0xd5 = mrs x3, VMPIDR_EL2
|
||||
0x03,0x00,0x3c,0xd5 = mrs x3, VPIDR_EL2
|
||||
0x43,0x21,0x3c,0xd5 = mrs x3, VTCR_EL2
|
||||
0x03,0x21,0x3c,0xd5 = mrs x3, VTTBR_EL2
|
||||
0x03,0x01,0x33,0xd5 = mrs x3, MDCCSR_EL0
|
||||
0x03,0x02,0x30,0xd5 = mrs x3, MDCCINT_EL1
|
||||
0x03,0x04,0x33,0xd5 = mrs x3, DBGDTR_EL0
|
||||
0x03,0x05,0x33,0xd5 = mrs x3, DBGDTRRX_EL0
|
||||
0x03,0x07,0x34,0xd5 = mrs x3, DBGVCR32_EL2
|
||||
0x43,0x00,0x30,0xd5 = mrs x3, OSDTRRX_EL1
|
||||
0x43,0x02,0x30,0xd5 = mrs x3, MDSCR_EL1
|
||||
0x43,0x03,0x30,0xd5 = mrs x3, OSDTRTX_EL1
|
||||
0x43,0x06,0x30,0xd5 = mrs x3, OSECCR_EL1
|
||||
0x83,0x00,0x30,0xd5 = mrs x3, DBGBVR0_EL1
|
||||
0x83,0x01,0x30,0xd5 = mrs x3, DBGBVR1_EL1
|
||||
0x83,0x02,0x30,0xd5 = mrs x3, DBGBVR2_EL1
|
||||
0x83,0x03,0x30,0xd5 = mrs x3, DBGBVR3_EL1
|
||||
0x83,0x04,0x30,0xd5 = mrs x3, DBGBVR4_EL1
|
||||
0x83,0x05,0x30,0xd5 = mrs x3, DBGBVR5_EL1
|
||||
0x83,0x06,0x30,0xd5 = mrs x3, DBGBVR6_EL1
|
||||
0x83,0x07,0x30,0xd5 = mrs x3, DBGBVR7_EL1
|
||||
0x83,0x08,0x30,0xd5 = mrs x3, DBGBVR8_EL1
|
||||
0x83,0x09,0x30,0xd5 = mrs x3, DBGBVR9_EL1
|
||||
0x83,0x0a,0x30,0xd5 = mrs x3, DBGBVR10_EL1
|
||||
0x83,0x0b,0x30,0xd5 = mrs x3, DBGBVR11_EL1
|
||||
0x83,0x0c,0x30,0xd5 = mrs x3, DBGBVR12_EL1
|
||||
0x83,0x0d,0x30,0xd5 = mrs x3, DBGBVR13_EL1
|
||||
0x83,0x0e,0x30,0xd5 = mrs x3, DBGBVR14_EL1
|
||||
0x83,0x0f,0x30,0xd5 = mrs x3, DBGBVR15_EL1
|
||||
0xa3,0x00,0x30,0xd5 = mrs x3, DBGBCR0_EL1
|
||||
0xa3,0x01,0x30,0xd5 = mrs x3, DBGBCR1_EL1
|
||||
0xa3,0x02,0x30,0xd5 = mrs x3, DBGBCR2_EL1
|
||||
0xa3,0x03,0x30,0xd5 = mrs x3, DBGBCR3_EL1
|
||||
0xa3,0x04,0x30,0xd5 = mrs x3, DBGBCR4_EL1
|
||||
0xa3,0x05,0x30,0xd5 = mrs x3, DBGBCR5_EL1
|
||||
0xa3,0x06,0x30,0xd5 = mrs x3, DBGBCR6_EL1
|
||||
0xa3,0x07,0x30,0xd5 = mrs x3, DBGBCR7_EL1
|
||||
0xa3,0x08,0x30,0xd5 = mrs x3, DBGBCR8_EL1
|
||||
0xa3,0x09,0x30,0xd5 = mrs x3, DBGBCR9_EL1
|
||||
0xa3,0x0a,0x30,0xd5 = mrs x3, DBGBCR10_EL1
|
||||
0xa3,0x0b,0x30,0xd5 = mrs x3, DBGBCR11_EL1
|
||||
0xa3,0x0c,0x30,0xd5 = mrs x3, DBGBCR12_EL1
|
||||
0xa3,0x0d,0x30,0xd5 = mrs x3, DBGBCR13_EL1
|
||||
0xa3,0x0e,0x30,0xd5 = mrs x3, DBGBCR14_EL1
|
||||
0xa3,0x0f,0x30,0xd5 = mrs x3, DBGBCR15_EL1
|
||||
0xc3,0x00,0x30,0xd5 = mrs x3, DBGWVR0_EL1
|
||||
0xc3,0x01,0x30,0xd5 = mrs x3, DBGWVR1_EL1
|
||||
0xc3,0x02,0x30,0xd5 = mrs x3, DBGWVR2_EL1
|
||||
0xc3,0x03,0x30,0xd5 = mrs x3, DBGWVR3_EL1
|
||||
0xc3,0x04,0x30,0xd5 = mrs x3, DBGWVR4_EL1
|
||||
0xc3,0x05,0x30,0xd5 = mrs x3, DBGWVR5_EL1
|
||||
0xc3,0x06,0x30,0xd5 = mrs x3, DBGWVR6_EL1
|
||||
0xc3,0x07,0x30,0xd5 = mrs x3, DBGWVR7_EL1
|
||||
0xc3,0x08,0x30,0xd5 = mrs x3, DBGWVR8_EL1
|
||||
0xc3,0x09,0x30,0xd5 = mrs x3, DBGWVR9_EL1
|
||||
0xc3,0x0a,0x30,0xd5 = mrs x3, DBGWVR10_EL1
|
||||
0xc3,0x0b,0x30,0xd5 = mrs x3, DBGWVR11_EL1
|
||||
0xc3,0x0c,0x30,0xd5 = mrs x3, DBGWVR12_EL1
|
||||
0xc3,0x0d,0x30,0xd5 = mrs x3, DBGWVR13_EL1
|
||||
0xc3,0x0e,0x30,0xd5 = mrs x3, DBGWVR14_EL1
|
||||
0xc3,0x0f,0x30,0xd5 = mrs x3, DBGWVR15_EL1
|
||||
0xe3,0x00,0x30,0xd5 = mrs x3, DBGWCR0_EL1
|
||||
0xe3,0x01,0x30,0xd5 = mrs x3, DBGWCR1_EL1
|
||||
0xe3,0x02,0x30,0xd5 = mrs x3, DBGWCR2_EL1
|
||||
0xe3,0x03,0x30,0xd5 = mrs x3, DBGWCR3_EL1
|
||||
0xe3,0x04,0x30,0xd5 = mrs x3, DBGWCR4_EL1
|
||||
0xe3,0x05,0x30,0xd5 = mrs x3, DBGWCR5_EL1
|
||||
0xe3,0x06,0x30,0xd5 = mrs x3, DBGWCR6_EL1
|
||||
0xe3,0x07,0x30,0xd5 = mrs x3, DBGWCR7_EL1
|
||||
0xe3,0x08,0x30,0xd5 = mrs x3, DBGWCR8_EL1
|
||||
0xe3,0x09,0x30,0xd5 = mrs x3, DBGWCR9_EL1
|
||||
0xe3,0x0a,0x30,0xd5 = mrs x3, DBGWCR10_EL1
|
||||
0xe3,0x0b,0x30,0xd5 = mrs x3, DBGWCR11_EL1
|
||||
0xe3,0x0c,0x30,0xd5 = mrs x3, DBGWCR12_EL1
|
||||
0xe3,0x0d,0x30,0xd5 = mrs x3, DBGWCR13_EL1
|
||||
0xe3,0x0e,0x30,0xd5 = mrs x3, DBGWCR14_EL1
|
||||
0xe3,0x0f,0x30,0xd5 = mrs x3, DBGWCR15_EL1
|
||||
0x03,0x10,0x30,0xd5 = mrs x3, MDRAR_EL1
|
||||
0x83,0x11,0x30,0xd5 = mrs x3, OSLSR_EL1
|
||||
0x83,0x13,0x30,0xd5 = mrs x3, OSDLR_EL1
|
||||
0x83,0x14,0x30,0xd5 = mrs x3, DBGPRCR_EL1
|
||||
0xc3,0x78,0x30,0xd5 = mrs x3, DBGCLAIMSET_EL1
|
||||
0xc3,0x79,0x30,0xd5 = mrs x3, DBGCLAIMCLR_EL1
|
||||
0xc3,0x7e,0x30,0xd5 = mrs x3, DBGAUTHSTATUS_EL1
|
||||
0x23,0xa3,0x38,0xd5 = mrs x3, AMAIR2_EL1
|
||||
0x23,0xa3,0x3d,0xd5 = mrs x3, AMAIR2_EL12
|
||||
0x23,0xa3,0x3c,0xd5 = mrs x3, AMAIR2_EL2
|
||||
0x23,0xa3,0x3e,0xd5 = mrs x3, AMAIR2_EL3
|
||||
0x23,0xa2,0x38,0xd5 = mrs x3, MAIR2_EL1
|
||||
0x23,0xa2,0x3d,0xd5 = mrs x3, MAIR2_EL12
|
||||
0x23,0xa1,0x3c,0xd5 = mrs x3, MAIR2_EL2
|
||||
0x23,0xa1,0x3e,0xd5 = mrs x3, MAIR2_EL3
|
||||
0x43,0xa2,0x38,0xd5 = mrs x3, PIRE0_EL1
|
||||
0x43,0xa2,0x3d,0xd5 = mrs x3, PIRE0_EL12
|
||||
0x43,0xa2,0x3c,0xd5 = mrs x3, PIRE0_EL2
|
||||
0x63,0xa2,0x38,0xd5 = mrs x3, PIR_EL1
|
||||
0x63,0xa2,0x3d,0xd5 = mrs x3, PIR_EL12
|
||||
0x63,0xa2,0x3c,0xd5 = mrs x3, PIR_EL2
|
||||
0x63,0xa2,0x3e,0xd5 = mrs x3, PIR_EL3
|
||||
0xa3,0xa2,0x3c,0xd5 = mrs x3, S2PIR_EL2
|
||||
0x83,0xa2,0x3b,0xd5 = mrs x3, POR_EL0
|
||||
0x83,0xa2,0x38,0xd5 = mrs x3, POR_EL1
|
||||
0x83,0xa2,0x3d,0xd5 = mrs x3, POR_EL12
|
||||
0x83,0xa2,0x3c,0xd5 = mrs x3, POR_EL2
|
||||
0x83,0xa2,0x3e,0xd5 = mrs x3, POR_EL3
|
||||
0xa3,0xa2,0x38,0xd5 = mrs x3, S2POR_EL1
|
||||
0x63,0x10,0x38,0xd5 = mrs x3, SCTLR2_EL1
|
||||
0x63,0x10,0x3d,0xd5 = mrs x3, SCTLR2_EL12
|
||||
0x63,0x10,0x3c,0xd5 = mrs x3, SCTLR2_EL2
|
||||
0x63,0x10,0x3e,0xd5 = mrs x3, SCTLR2_EL3
|
||||
0x63,0x20,0x38,0xd5 = mrs x3, TCR2_EL1
|
||||
0x63,0x20,0x3d,0xd5 = mrs x3, TCR2_EL12
|
||||
0x63,0x20,0x3c,0xd5 = mrs x3, TCR2_EL2
|
||||
0x81,0xf6,0x3a,0xd5 = mrs x1, S3_2_C15_C6_4
|
||||
0x83,0xb1,0x3b,0xd5 = mrs x3, S3_3_C11_C1_4
|
||||
0x83,0xb1,0x3b,0xd5 = mrs x3, S3_3_C11_C1_4
|
||||
0x40,0xc0,0x1e,0xd5 = msr RMR_EL3, x0
|
||||
0x40,0xc0,0x1c,0xd5 = msr RMR_EL2, x0
|
||||
0x40,0xc0,0x18,0xd5 = msr RMR_EL1, x0
|
||||
0x83,0x10,0x10,0xd5 = msr OSLAR_EL1, x3
|
||||
0x03,0x05,0x13,0xd5 = msr DBGDTRTX_EL0, x3
|
||||
0x00,0x01,0x38,0xd5 = mrs x0, ID_PFR0_EL1
|
||||
0x20,0x01,0x38,0xd5 = mrs x0, ID_PFR1_EL1
|
||||
0x40,0x01,0x38,0xd5 = mrs x0, ID_DFR0_EL1
|
||||
0xa0,0x03,0x38,0xd5 = mrs x0, ID_DFR1_EL1
|
||||
0x60,0x01,0x38,0xd5 = mrs x0, ID_AFR0_EL1
|
||||
0x00,0x02,0x38,0xd5 = mrs x0, ID_ISAR0_EL1
|
||||
0x20,0x02,0x38,0xd5 = mrs x0, ID_ISAR1_EL1
|
||||
0x40,0x02,0x38,0xd5 = mrs x0, ID_ISAR2_EL1
|
||||
0x60,0x02,0x38,0xd5 = mrs x0, ID_ISAR3_EL1
|
||||
0x80,0x02,0x38,0xd5 = mrs x0, ID_ISAR4_EL1
|
||||
0xa0,0x02,0x38,0xd5 = mrs x0, ID_ISAR5_EL1
|
||||
0x20,0x51,0x38,0xd5 = mrs x0, AFSR1_EL1
|
||||
0x00,0x51,0x38,0xd5 = mrs x0, AFSR0_EL1
|
||||
0xc0,0x00,0x38,0xd5 = mrs x0, REVIDR_EL1
|
||||
15
thirdparty/capstone/suite/MC/AArch64/arm64-system.txt.cs
vendored
Normal file
15
thirdparty/capstone/suite/MC/AArch64/arm64-system.txt.cs
vendored
Normal file
@@ -0,0 +1,15 @@
|
||||
# CS_ARCH_AARCH64, None, None
|
||||
# This regression test file is new. The option flags could not be determined.
|
||||
# LLVM uses the following mattr = []
|
||||
0x1f 0x20 0x03 0xd5 == nop
|
||||
0x9f 0x20 0x03 0xd5 == sev
|
||||
0xbf 0x20 0x03 0xd5 == sevl
|
||||
0x5f 0x20 0x03 0xd5 == wfe
|
||||
0x7f 0x20 0x03 0xd5 == wfi
|
||||
0x3f 0x20 0x03 0xd5 == yield
|
||||
0x5f 0x3a 0x03 0xd5 == clrex #10
|
||||
0xdf 0x3f 0x03 0xd5 == isb{{$}}
|
||||
0xdf 0x31 0x03 0xd5 == isb #1
|
||||
0xbf 0x33 0x03 0xd5 == dmb osh
|
||||
0x9f 0x37 0x03 0xd5 == dsb nsh
|
||||
0x3f 0x76 0x08 0xd5 == dc ivac
|
||||
2
thirdparty/capstone/suite/MC/AArch64/arm64-target-specific-sysreg.s.cs
vendored
Normal file
2
thirdparty/capstone/suite/MC/AArch64/arm64-target-specific-sysreg.s.cs
vendored
Normal file
@@ -0,0 +1,2 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
0x00,0xf2,0x1f,0xd5 = msr CPM_IOACC_CTL_EL3, x0
|
||||
4
thirdparty/capstone/suite/MC/AArch64/arm64-vector-lists.s.cs
vendored
Normal file
4
thirdparty/capstone/suite/MC/AArch64/arm64-vector-lists.s.cs
vendored
Normal file
@@ -0,0 +1,4 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0x00,0x00,0x00,0x0c == st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0]
|
||||
0x00,0x04,0x00,0x0c == st4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x0]
|
||||
10
thirdparty/capstone/suite/MC/AArch64/arm64-verbose-vector-case.s.cs
vendored
Normal file
10
thirdparty/capstone/suite/MC/AArch64/arm64-verbose-vector-case.s.cs
vendored
Normal file
@@ -0,0 +1,10 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0x08,0xe1,0x28,0x0e == pmull v8.8h, v8.8b, v8.8b
|
||||
0x08,0xe1,0x28,0x4e == pmull2 v8.8h, v8.16b, v8.16b
|
||||
0x08,0xe1,0xe8,0x0e == pmull v8.1q, v8.1d, v8.1d
|
||||
0x08,0xe1,0xe8,0x4e == pmull2 v8.1q, v8.2d, v8.2d
|
||||
0x08,0xe1,0x28,0x0e == pmull v8.8h, v8.8b, v8.8b
|
||||
0x08,0xe1,0x28,0x4e == pmull2 v8.8h, v8.16b, v8.16b
|
||||
0x08,0xe1,0xe8,0x0e == pmull v8.1q, v8.1d, v8.1d
|
||||
0x08,0xe1,0xe8,0x4e == pmull2 v8.1q, v8.2d, v8.2d
|
||||
2
thirdparty/capstone/suite/MC/AArch64/arm64e.s.cs
vendored
Normal file
2
thirdparty/capstone/suite/MC/AArch64/arm64e.s.cs
vendored
Normal file
@@ -0,0 +1,2 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
0x20,0x00,0xc1,0xda = pacia x0, x1
|
||||
42
thirdparty/capstone/suite/MC/AArch64/armv8.1a-atomic.s.cs
vendored
Normal file
42
thirdparty/capstone/suite/MC/AArch64/armv8.1a-atomic.s.cs
vendored
Normal file
@@ -0,0 +1,42 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0x41,0x7c,0xa0,0x08 == casb w0, w1, [x2]
|
||||
0x41,0x7c,0xe0,0x08 == casab w0, w1, [x2]
|
||||
0x41,0xfc,0xa0,0x08 == caslb w0, w1, [x2]
|
||||
0x41,0xfc,0xe0,0x08 == casalb w0, w1, [x2]
|
||||
0x41,0x7c,0xa0,0x48 == cash w0, w1, [x2]
|
||||
0x41,0x7c,0xe0,0x48 == casah w0, w1, [x2]
|
||||
0x41,0xfc,0xa0,0x48 == caslh w0, w1, [x2]
|
||||
0x41,0xfc,0xe0,0x48 == casalh w0, w1, [x2]
|
||||
0x41,0x7c,0xa0,0x88 == cas w0, w1, [x2]
|
||||
0x41,0x7c,0xe0,0x88 == casa w0, w1, [x2]
|
||||
0x41,0xfc,0xa0,0x88 == casl w0, w1, [x2]
|
||||
0x41,0xfc,0xe0,0x88 == casal w0, w1, [x2]
|
||||
0x41,0x7c,0xa0,0xc8 == cas x0, x1, [x2]
|
||||
0x41,0x7c,0xe0,0xc8 == casa x0, x1, [x2]
|
||||
0x41,0xfc,0xa0,0xc8 == casl x0, x1, [x2]
|
||||
0x41,0xfc,0xe0,0xc8 == casal x0, x1, [x2]
|
||||
0x41,0x00,0xa0,0xf8 == ldadda x0, x1, [x2]
|
||||
0x41,0x10,0x60,0xf8 == ldclrl x0, x1, [x2]
|
||||
0x41,0x20,0xe0,0xf8 == ldeoral x0, x1, [x2]
|
||||
0x41,0x30,0x20,0xf8 == ldset x0, x1, [x2]
|
||||
0x41,0x40,0xa0,0xb8 == ldsmaxa w0, w1, [x2]
|
||||
0x41,0x50,0x60,0x38 == ldsminlb w0, w1, [x2]
|
||||
0x41,0x60,0xe0,0x78 == ldumaxalh w0, w1, [x2]
|
||||
0x41,0x70,0x20,0xb8 == ldumin w0, w1, [x2]
|
||||
0xa3,0x50,0x22,0x38 == ldsminb w2, w3, [x5]
|
||||
0x5f,0x00,0x60,0x38 == staddlb w0, [x2]
|
||||
0x5f,0x10,0x60,0x78 == stclrlh w0, [x2]
|
||||
0x5f,0x20,0x60,0xb8 == steorl w0, [x2]
|
||||
0x5f,0x30,0x60,0xf8 == stsetl x0, [x2]
|
||||
0x5f,0x40,0x20,0x38 == stsmaxb w0, [x2]
|
||||
0x5f,0x50,0x20,0x78 == stsminh w0, [x2]
|
||||
0x5f,0x60,0x20,0xb8 == stumax w0, [x2]
|
||||
0x5f,0x70,0x20,0xf8 == stumin x0, [x2]
|
||||
0xff,0x53,0x7d,0xf8 == stsminl x29, [sp]
|
||||
0x41,0x80,0x20,0xf8 == swp x0, x1, [x2]
|
||||
0x41,0x80,0x20,0x38 == swpb w0, w1, [x2]
|
||||
0x41,0x80,0x60,0x78 == swplh w0, w1, [x2]
|
||||
0xe1,0x83,0xe0,0xf8 == swpal x0, x1, [sp]
|
||||
0x82,0x7c,0x20,0x48 == casp x0, x1, x2, x3, [x4]
|
||||
0x82,0x7c,0x20,0x08 == casp w0, w1, w2, w3, [x4]
|
||||
43
thirdparty/capstone/suite/MC/AArch64/armv8.1a-atomic.txt.cs
vendored
Normal file
43
thirdparty/capstone/suite/MC/AArch64/armv8.1a-atomic.txt.cs
vendored
Normal file
@@ -0,0 +1,43 @@
|
||||
# CS_ARCH_AARCH64, None, None
|
||||
# This regression test file is new. The option flags could not be determined.
|
||||
# LLVM uses the following mattr = ['mattr=+v8.1a']
|
||||
0x41,0x7c,0xa0,0x08 == casb w0, w1, [x2]
|
||||
0x41,0x7c,0xe0,0x08 == casab w0, w1, [x2]
|
||||
0x41,0xfc,0xa0,0x08 == caslb w0, w1, [x2]
|
||||
0x41,0xfc,0xe0,0x08 == casalb w0, w1, [x2]
|
||||
0x41,0x7c,0xa0,0x48 == cash w0, w1, [x2]
|
||||
0x41,0x7c,0xe0,0x48 == casah w0, w1, [x2]
|
||||
0x41,0xfc,0xa0,0x48 == caslh w0, w1, [x2]
|
||||
0x41,0xfc,0xe0,0x48 == casalh w0, w1, [x2]
|
||||
0x41,0x7c,0xa0,0x88 == cas w0, w1, [x2]
|
||||
0x41,0x7c,0xe0,0x88 == casa w0, w1, [x2]
|
||||
0x41,0xfc,0xa0,0x88 == casl w0, w1, [x2]
|
||||
0x41,0xfc,0xe0,0x88 == casal w0, w1, [x2]
|
||||
0x41,0x7c,0xa0,0xc8 == cas x0, x1, [x2]
|
||||
0x41,0x7c,0xe0,0xc8 == casa x0, x1, [x2]
|
||||
0x41,0xfc,0xa0,0xc8 == casl x0, x1, [x2]
|
||||
0x41,0xfc,0xe0,0xc8 == casal x0, x1, [x2]
|
||||
0x41,0x80,0x20,0xf8 == swp x0, x1, [x2]
|
||||
0x41,0x80,0x20,0x38 == swpb w0, w1, [x2]
|
||||
0x41,0x80,0x60,0x78 == swplh w0, w1, [x2]
|
||||
0xe1,0x83,0xe0,0xf8 == swpal x0, x1, [sp]
|
||||
0x41,0x00,0xa0,0xf8 == ldadda x0, x1, [x2]
|
||||
0x41,0x10,0x60,0xf8 == ldclrl x0, x1, [x2]
|
||||
0x41,0x20,0xe0,0xf8 == ldeoral x0, x1, [x2]
|
||||
0x41,0x30,0x20,0xf8 == ldset x0, x1, [x2]
|
||||
0x41,0x40,0xa0,0xb8 == ldsmaxa w0, w1, [x2]
|
||||
0x41,0x50,0x60,0x38 == ldsminlb w0, w1, [x2]
|
||||
0x41,0x60,0xe0,0x78 == ldumaxalh w0, w1, [x2]
|
||||
0x41,0x70,0x20,0xb8 == ldumin w0, w1, [x2]
|
||||
0xab,0x51,0xe7,0x78 == ldsminalh w7, w11, [x13]
|
||||
0x5f,0x00,0x60,0x38 == staddlb w0, [x2]
|
||||
0x5f,0x10,0x60,0x78 == stclrlh w0, [x2]
|
||||
0x5f,0x20,0x60,0xb8 == steorl w0, [x2]
|
||||
0x5f,0x30,0x60,0xf8 == stsetl x0, [x2]
|
||||
0x5f,0x40,0x20,0x38 == stsmaxb w0, [x2]
|
||||
0x5f,0x50,0x20,0x78 == stsminh w0, [x2]
|
||||
0x5f,0x60,0x20,0xb8 == stumax w0, [x2]
|
||||
0x5f,0x70,0x20,0xf8 == stumin x0, [x2]
|
||||
0xff,0x53,0x7d,0xf8 == stsminl x29, [sp]
|
||||
0x82,0x7c,0x20,0x48 == casp x0, x1, x2, x3, [x4]
|
||||
0x82,0x7c,0x20,0x08 == casp w0, w1, w2, w3, [x4]
|
||||
15
thirdparty/capstone/suite/MC/AArch64/armv8.1a-lor.s.cs
vendored
Normal file
15
thirdparty/capstone/suite/MC/AArch64/armv8.1a-lor.s.cs
vendored
Normal file
@@ -0,0 +1,15 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0x20,0x7c,0xdf,0x08 == ldlarb w0, [x1]
|
||||
0x20,0x7c,0xdf,0x48 == ldlarh w0, [x1]
|
||||
0x20,0x7c,0xdf,0x88 == ldlar w0, [x1]
|
||||
0x20,0x7c,0xdf,0xc8 == ldlar x0, [x1]
|
||||
0x20,0x7c,0x9f,0x08 == stllrb w0, [x1]
|
||||
0x20,0x7c,0x9f,0x48 == stllrh w0, [x1]
|
||||
0x20,0x7c,0x9f,0x88 == stllr w0, [x1]
|
||||
0x20,0x7c,0x9f,0xc8 == stllr x0, [x1]
|
||||
0x00,0xa4,0x18,0xd5 == msr LORSA_EL1, x0
|
||||
0x20,0xa4,0x18,0xd5 == msr LOREA_EL1, x0
|
||||
0x40,0xa4,0x18,0xd5 == msr LORN_EL1, x0
|
||||
0x60,0xa4,0x18,0xd5 == msr LORC_EL1, x0
|
||||
0xe0,0xa4,0x38,0xd5 == mrs x0, LORID_EL1
|
||||
21
thirdparty/capstone/suite/MC/AArch64/armv8.1a-lor.txt.cs
vendored
Normal file
21
thirdparty/capstone/suite/MC/AArch64/armv8.1a-lor.txt.cs
vendored
Normal file
@@ -0,0 +1,21 @@
|
||||
# CS_ARCH_AARCH64, None, None
|
||||
# This regression test file is new. The option flags could not be determined.
|
||||
# LLVM uses the following mattr = ['mattr=+v8.1a']
|
||||
0x20,0x7c,0xdf,0x08 == ldlarb w0, [x1]
|
||||
0x20,0x7c,0xdf,0x48 == ldlarh w0, [x1]
|
||||
0x20,0x7c,0xdf,0x88 == ldlar w0, [x1]
|
||||
0x20,0x7c,0xdf,0xc8 == ldlar x0, [x1]
|
||||
0x20,0x7c,0x9f,0x08 == stllrb w0, [x1]
|
||||
0x20,0x7c,0x9f,0x48 == stllrh w0, [x1]
|
||||
0x20,0x7c,0x9f,0x88 == stllr w0, [x1]
|
||||
0x20,0x7c,0x9f,0xc8 == stllr x0, [x1]
|
||||
0x00,0xa4,0x18,0xd5 == msr LORSA_EL1, x0
|
||||
0x20,0xa4,0x18,0xd5 == msr LOREA_EL1, x0
|
||||
0x40,0xa4,0x18,0xd5 == msr LORN_EL1, x0
|
||||
0x60,0xa4,0x18,0xd5 == msr LORC_EL1, x0
|
||||
0xe0,0xa4,0x18,0xd5 == msr S3_0_C10_C4_7, x0
|
||||
0x00,0xa4,0x38,0xd5 == mrs x0, LORSA_EL1
|
||||
0x20,0xa4,0x38,0xd5 == mrs x0, LOREA_EL1
|
||||
0x40,0xa4,0x38,0xd5 == mrs x0, LORN_EL1
|
||||
0x60,0xa4,0x38,0xd5 == mrs x0, LORC_EL1
|
||||
0xe0,0xa4,0x38,0xd5 == mrs x0, LORID_EL1
|
||||
458
thirdparty/capstone/suite/MC/AArch64/armv8.1a-lse.s.cs
vendored
Normal file
458
thirdparty/capstone/suite/MC/AArch64/armv8.1a-lse.s.cs
vendored
Normal file
@@ -0,0 +1,458 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0x41,0x7c,0xa0,0x88 == cas w0, w1, [x2]
|
||||
0xe3,0x7f,0xa2,0x88 == cas w2, w3, [sp]
|
||||
0x41,0x7c,0xe0,0x88 == casa w0, w1, [x2]
|
||||
0xe3,0x7f,0xe2,0x88 == casa w2, w3, [sp]
|
||||
0x41,0xfc,0xa0,0x88 == casl w0, w1, [x2]
|
||||
0xe3,0xff,0xa2,0x88 == casl w2, w3, [sp]
|
||||
0x41,0xfc,0xe0,0x88 == casal w0, w1, [x2]
|
||||
0xe3,0xff,0xe2,0x88 == casal w2, w3, [sp]
|
||||
0x41,0x7c,0xa0,0x08 == casb w0, w1, [x2]
|
||||
0xe3,0x7f,0xa2,0x08 == casb w2, w3, [sp]
|
||||
0x41,0x7c,0xa0,0x48 == cash w0, w1, [x2]
|
||||
0xe3,0x7f,0xa2,0x48 == cash w2, w3, [sp]
|
||||
0x41,0x7c,0xe0,0x08 == casab w0, w1, [x2]
|
||||
0xe3,0x7f,0xe2,0x08 == casab w2, w3, [sp]
|
||||
0x41,0xfc,0xa0,0x08 == caslb w0, w1, [x2]
|
||||
0xe3,0xff,0xa2,0x08 == caslb w2, w3, [sp]
|
||||
0x41,0xfc,0xe0,0x08 == casalb w0, w1, [x2]
|
||||
0xe3,0xff,0xe2,0x08 == casalb w2, w3, [sp]
|
||||
0x41,0x7c,0xe0,0x48 == casah w0, w1, [x2]
|
||||
0xe3,0x7f,0xe2,0x48 == casah w2, w3, [sp]
|
||||
0x41,0xfc,0xa0,0x48 == caslh w0, w1, [x2]
|
||||
0xe3,0xff,0xa2,0x48 == caslh w2, w3, [sp]
|
||||
0x41,0xfc,0xe0,0x48 == casalh w0, w1, [x2]
|
||||
0xe3,0xff,0xe2,0x48 == casalh w2, w3, [sp]
|
||||
0x41,0x7c,0xa0,0xc8 == cas x0, x1, [x2]
|
||||
0xe3,0x7f,0xa2,0xc8 == cas x2, x3, [sp]
|
||||
0x41,0x7c,0xe0,0xc8 == casa x0, x1, [x2]
|
||||
0xe3,0x7f,0xe2,0xc8 == casa x2, x3, [sp]
|
||||
0x41,0xfc,0xa0,0xc8 == casl x0, x1, [x2]
|
||||
0xe3,0xff,0xa2,0xc8 == casl x2, x3, [sp]
|
||||
0x41,0xfc,0xe0,0xc8 == casal x0, x1, [x2]
|
||||
0xe3,0xff,0xe2,0xc8 == casal x2, x3, [sp]
|
||||
0x41,0x80,0x20,0xb8 == swp w0, w1, [x2]
|
||||
0xe3,0x83,0x22,0xb8 == swp w2, w3, [sp]
|
||||
0x41,0x80,0xa0,0xb8 == swpa w0, w1, [x2]
|
||||
0xe3,0x83,0xa2,0xb8 == swpa w2, w3, [sp]
|
||||
0x41,0x80,0x60,0xb8 == swpl w0, w1, [x2]
|
||||
0xe3,0x83,0x62,0xb8 == swpl w2, w3, [sp]
|
||||
0x41,0x80,0xe0,0xb8 == swpal w0, w1, [x2]
|
||||
0xe3,0x83,0xe2,0xb8 == swpal w2, w3, [sp]
|
||||
0x41,0x80,0x20,0x38 == swpb w0, w1, [x2]
|
||||
0xe3,0x83,0x22,0x38 == swpb w2, w3, [sp]
|
||||
0x41,0x80,0x20,0x78 == swph w0, w1, [x2]
|
||||
0xe3,0x83,0x22,0x78 == swph w2, w3, [sp]
|
||||
0x41,0x80,0xa0,0x38 == swpab w0, w1, [x2]
|
||||
0xe3,0x83,0xa2,0x38 == swpab w2, w3, [sp]
|
||||
0x41,0x80,0x60,0x38 == swplb w0, w1, [x2]
|
||||
0xe3,0x83,0x62,0x38 == swplb w2, w3, [sp]
|
||||
0x41,0x80,0xe0,0x38 == swpalb w0, w1, [x2]
|
||||
0xe3,0x83,0xe2,0x38 == swpalb w2, w3, [sp]
|
||||
0x41,0x80,0xa0,0x78 == swpah w0, w1, [x2]
|
||||
0xe3,0x83,0xa2,0x78 == swpah w2, w3, [sp]
|
||||
0x41,0x80,0x60,0x78 == swplh w0, w1, [x2]
|
||||
0xe3,0x83,0x62,0x78 == swplh w2, w3, [sp]
|
||||
0x41,0x80,0xe0,0x78 == swpalh w0, w1, [x2]
|
||||
0xe3,0x83,0xe2,0x78 == swpalh w2, w3, [sp]
|
||||
0x41,0x80,0x20,0xf8 == swp x0, x1, [x2]
|
||||
0xe3,0x83,0x22,0xf8 == swp x2, x3, [sp]
|
||||
0x41,0x80,0xa0,0xf8 == swpa x0, x1, [x2]
|
||||
0xe3,0x83,0xa2,0xf8 == swpa x2, x3, [sp]
|
||||
0x41,0x80,0x60,0xf8 == swpl x0, x1, [x2]
|
||||
0xe3,0x83,0x62,0xf8 == swpl x2, x3, [sp]
|
||||
0x41,0x80,0xe0,0xf8 == swpal x0, x1, [x2]
|
||||
0xe3,0x83,0xe2,0xf8 == swpal x2, x3, [sp]
|
||||
0xa2,0x7c,0x20,0x08 == casp w0, w1, w2, w3, [x5]
|
||||
0xe6,0x7f,0x24,0x08 == casp w4, w5, w6, w7, [sp]
|
||||
0x42,0x7c,0x20,0x48 == casp x0, x1, x2, x3, [x2]
|
||||
0xe6,0x7f,0x24,0x48 == casp x4, x5, x6, x7, [sp]
|
||||
0xa2,0x7c,0x60,0x08 == caspa w0, w1, w2, w3, [x5]
|
||||
0xe6,0x7f,0x64,0x08 == caspa w4, w5, w6, w7, [sp]
|
||||
0x42,0x7c,0x60,0x48 == caspa x0, x1, x2, x3, [x2]
|
||||
0xe6,0x7f,0x64,0x48 == caspa x4, x5, x6, x7, [sp]
|
||||
0xa2,0xfc,0x20,0x08 == caspl w0, w1, w2, w3, [x5]
|
||||
0xe6,0xff,0x24,0x08 == caspl w4, w5, w6, w7, [sp]
|
||||
0x42,0xfc,0x20,0x48 == caspl x0, x1, x2, x3, [x2]
|
||||
0xe6,0xff,0x24,0x48 == caspl x4, x5, x6, x7, [sp]
|
||||
0xa2,0xfc,0x60,0x08 == caspal w0, w1, w2, w3, [x5]
|
||||
0xe6,0xff,0x64,0x08 == caspal w4, w5, w6, w7, [sp]
|
||||
0x42,0xfc,0x60,0x48 == caspal x0, x1, x2, x3, [x2]
|
||||
0xe6,0xff,0x64,0x48 == caspal x4, x5, x6, x7, [sp]
|
||||
0x41,0x00,0x20,0xb8 == ldadd w0, w1, [x2]
|
||||
0xe3,0x03,0x22,0xb8 == ldadd w2, w3, [sp]
|
||||
0x41,0x00,0xa0,0xb8 == ldadda w0, w1, [x2]
|
||||
0xe3,0x03,0xa2,0xb8 == ldadda w2, w3, [sp]
|
||||
0x41,0x00,0x60,0xb8 == ldaddl w0, w1, [x2]
|
||||
0xe3,0x03,0x62,0xb8 == ldaddl w2, w3, [sp]
|
||||
0x41,0x00,0xe0,0xb8 == ldaddal w0, w1, [x2]
|
||||
0xe3,0x03,0xe2,0xb8 == ldaddal w2, w3, [sp]
|
||||
0x41,0x00,0x20,0x38 == ldaddb w0, w1, [x2]
|
||||
0xe3,0x03,0x22,0x38 == ldaddb w2, w3, [sp]
|
||||
0x41,0x00,0x20,0x78 == ldaddh w0, w1, [x2]
|
||||
0xe3,0x03,0x22,0x78 == ldaddh w2, w3, [sp]
|
||||
0x41,0x00,0xa0,0x38 == ldaddab w0, w1, [x2]
|
||||
0xe3,0x03,0xa2,0x38 == ldaddab w2, w3, [sp]
|
||||
0x41,0x00,0x60,0x38 == ldaddlb w0, w1, [x2]
|
||||
0xe3,0x03,0x62,0x38 == ldaddlb w2, w3, [sp]
|
||||
0x41,0x00,0xe0,0x38 == ldaddalb w0, w1, [x2]
|
||||
0xe3,0x03,0xe2,0x38 == ldaddalb w2, w3, [sp]
|
||||
0x41,0x00,0xa0,0x78 == ldaddah w0, w1, [x2]
|
||||
0xe3,0x03,0xa2,0x78 == ldaddah w2, w3, [sp]
|
||||
0x41,0x00,0x60,0x78 == ldaddlh w0, w1, [x2]
|
||||
0xe3,0x03,0x62,0x78 == ldaddlh w2, w3, [sp]
|
||||
0x41,0x00,0xe0,0x78 == ldaddalh w0, w1, [x2]
|
||||
0xe3,0x03,0xe2,0x78 == ldaddalh w2, w3, [sp]
|
||||
0x41,0x00,0x20,0xf8 == ldadd x0, x1, [x2]
|
||||
0xe3,0x03,0x22,0xf8 == ldadd x2, x3, [sp]
|
||||
0x41,0x00,0xa0,0xf8 == ldadda x0, x1, [x2]
|
||||
0xe3,0x03,0xa2,0xf8 == ldadda x2, x3, [sp]
|
||||
0x41,0x00,0x60,0xf8 == ldaddl x0, x1, [x2]
|
||||
0xe3,0x03,0x62,0xf8 == ldaddl x2, x3, [sp]
|
||||
0x41,0x00,0xe0,0xf8 == ldaddal x0, x1, [x2]
|
||||
0xe3,0x03,0xe2,0xf8 == ldaddal x2, x3, [sp]
|
||||
0x41,0x10,0x20,0xb8 == ldclr w0, w1, [x2]
|
||||
0xe3,0x13,0x22,0xb8 == ldclr w2, w3, [sp]
|
||||
0x41,0x10,0xa0,0xb8 == ldclra w0, w1, [x2]
|
||||
0xe3,0x13,0xa2,0xb8 == ldclra w2, w3, [sp]
|
||||
0x41,0x10,0x60,0xb8 == ldclrl w0, w1, [x2]
|
||||
0xe3,0x13,0x62,0xb8 == ldclrl w2, w3, [sp]
|
||||
0x41,0x10,0xe0,0xb8 == ldclral w0, w1, [x2]
|
||||
0xe3,0x13,0xe2,0xb8 == ldclral w2, w3, [sp]
|
||||
0x41,0x10,0x20,0x38 == ldclrb w0, w1, [x2]
|
||||
0xe3,0x13,0x22,0x38 == ldclrb w2, w3, [sp]
|
||||
0x41,0x10,0x20,0x78 == ldclrh w0, w1, [x2]
|
||||
0xe3,0x13,0x22,0x78 == ldclrh w2, w3, [sp]
|
||||
0x41,0x10,0xa0,0x38 == ldclrab w0, w1, [x2]
|
||||
0xe3,0x13,0xa2,0x38 == ldclrab w2, w3, [sp]
|
||||
0x41,0x10,0x60,0x38 == ldclrlb w0, w1, [x2]
|
||||
0xe3,0x13,0x62,0x38 == ldclrlb w2, w3, [sp]
|
||||
0x41,0x10,0xe0,0x38 == ldclralb w0, w1, [x2]
|
||||
0xe3,0x13,0xe2,0x38 == ldclralb w2, w3, [sp]
|
||||
0x41,0x10,0xa0,0x78 == ldclrah w0, w1, [x2]
|
||||
0xe3,0x13,0xa2,0x78 == ldclrah w2, w3, [sp]
|
||||
0x41,0x10,0x60,0x78 == ldclrlh w0, w1, [x2]
|
||||
0xe3,0x13,0x62,0x78 == ldclrlh w2, w3, [sp]
|
||||
0x41,0x10,0xe0,0x78 == ldclralh w0, w1, [x2]
|
||||
0xe3,0x13,0xe2,0x78 == ldclralh w2, w3, [sp]
|
||||
0x41,0x10,0x20,0xf8 == ldclr x0, x1, [x2]
|
||||
0xe3,0x13,0x22,0xf8 == ldclr x2, x3, [sp]
|
||||
0x41,0x10,0xa0,0xf8 == ldclra x0, x1, [x2]
|
||||
0xe3,0x13,0xa2,0xf8 == ldclra x2, x3, [sp]
|
||||
0x41,0x10,0x60,0xf8 == ldclrl x0, x1, [x2]
|
||||
0xe3,0x13,0x62,0xf8 == ldclrl x2, x3, [sp]
|
||||
0x41,0x10,0xe0,0xf8 == ldclral x0, x1, [x2]
|
||||
0xe3,0x13,0xe2,0xf8 == ldclral x2, x3, [sp]
|
||||
0x41,0x20,0x20,0xb8 == ldeor w0, w1, [x2]
|
||||
0xe3,0x23,0x22,0xb8 == ldeor w2, w3, [sp]
|
||||
0x41,0x20,0xa0,0xb8 == ldeora w0, w1, [x2]
|
||||
0xe3,0x23,0xa2,0xb8 == ldeora w2, w3, [sp]
|
||||
0x41,0x20,0x60,0xb8 == ldeorl w0, w1, [x2]
|
||||
0xe3,0x23,0x62,0xb8 == ldeorl w2, w3, [sp]
|
||||
0x41,0x20,0xe0,0xb8 == ldeoral w0, w1, [x2]
|
||||
0xe3,0x23,0xe2,0xb8 == ldeoral w2, w3, [sp]
|
||||
0x41,0x20,0x20,0x38 == ldeorb w0, w1, [x2]
|
||||
0xe3,0x23,0x22,0x38 == ldeorb w2, w3, [sp]
|
||||
0x41,0x20,0x20,0x78 == ldeorh w0, w1, [x2]
|
||||
0xe3,0x23,0x22,0x78 == ldeorh w2, w3, [sp]
|
||||
0x41,0x20,0xa0,0x38 == ldeorab w0, w1, [x2]
|
||||
0xe3,0x23,0xa2,0x38 == ldeorab w2, w3, [sp]
|
||||
0x41,0x20,0x60,0x38 == ldeorlb w0, w1, [x2]
|
||||
0xe3,0x23,0x62,0x38 == ldeorlb w2, w3, [sp]
|
||||
0x41,0x20,0xe0,0x38 == ldeoralb w0, w1, [x2]
|
||||
0xe3,0x23,0xe2,0x38 == ldeoralb w2, w3, [sp]
|
||||
0x41,0x20,0xa0,0x78 == ldeorah w0, w1, [x2]
|
||||
0xe3,0x23,0xa2,0x78 == ldeorah w2, w3, [sp]
|
||||
0x41,0x20,0x60,0x78 == ldeorlh w0, w1, [x2]
|
||||
0xe3,0x23,0x62,0x78 == ldeorlh w2, w3, [sp]
|
||||
0x41,0x20,0xe0,0x78 == ldeoralh w0, w1, [x2]
|
||||
0xe3,0x23,0xe2,0x78 == ldeoralh w2, w3, [sp]
|
||||
0x41,0x20,0x20,0xf8 == ldeor x0, x1, [x2]
|
||||
0xe3,0x23,0x22,0xf8 == ldeor x2, x3, [sp]
|
||||
0x41,0x20,0xa0,0xf8 == ldeora x0, x1, [x2]
|
||||
0xe3,0x23,0xa2,0xf8 == ldeora x2, x3, [sp]
|
||||
0x41,0x20,0x60,0xf8 == ldeorl x0, x1, [x2]
|
||||
0xe3,0x23,0x62,0xf8 == ldeorl x2, x3, [sp]
|
||||
0x41,0x20,0xe0,0xf8 == ldeoral x0, x1, [x2]
|
||||
0xe3,0x23,0xe2,0xf8 == ldeoral x2, x3, [sp]
|
||||
0x41,0x30,0x20,0xb8 == ldset w0, w1, [x2]
|
||||
0xe3,0x33,0x22,0xb8 == ldset w2, w3, [sp]
|
||||
0x41,0x30,0xa0,0xb8 == ldseta w0, w1, [x2]
|
||||
0xe3,0x33,0xa2,0xb8 == ldseta w2, w3, [sp]
|
||||
0x41,0x30,0x60,0xb8 == ldsetl w0, w1, [x2]
|
||||
0xe3,0x33,0x62,0xb8 == ldsetl w2, w3, [sp]
|
||||
0x41,0x30,0xe0,0xb8 == ldsetal w0, w1, [x2]
|
||||
0xe3,0x33,0xe2,0xb8 == ldsetal w2, w3, [sp]
|
||||
0x41,0x30,0x20,0x38 == ldsetb w0, w1, [x2]
|
||||
0xe3,0x33,0x22,0x38 == ldsetb w2, w3, [sp]
|
||||
0x41,0x30,0x20,0x78 == ldseth w0, w1, [x2]
|
||||
0xe3,0x33,0x22,0x78 == ldseth w2, w3, [sp]
|
||||
0x41,0x30,0xa0,0x38 == ldsetab w0, w1, [x2]
|
||||
0xe3,0x33,0xa2,0x38 == ldsetab w2, w3, [sp]
|
||||
0x41,0x30,0x60,0x38 == ldsetlb w0, w1, [x2]
|
||||
0xe3,0x33,0x62,0x38 == ldsetlb w2, w3, [sp]
|
||||
0x41,0x30,0xe0,0x38 == ldsetalb w0, w1, [x2]
|
||||
0xe3,0x33,0xe2,0x38 == ldsetalb w2, w3, [sp]
|
||||
0x41,0x30,0xa0,0x78 == ldsetah w0, w1, [x2]
|
||||
0xe3,0x33,0xa2,0x78 == ldsetah w2, w3, [sp]
|
||||
0x41,0x30,0x60,0x78 == ldsetlh w0, w1, [x2]
|
||||
0xe3,0x33,0x62,0x78 == ldsetlh w2, w3, [sp]
|
||||
0x41,0x30,0xe0,0x78 == ldsetalh w0, w1, [x2]
|
||||
0xe3,0x33,0xe2,0x78 == ldsetalh w2, w3, [sp]
|
||||
0x41,0x30,0x20,0xf8 == ldset x0, x1, [x2]
|
||||
0xe3,0x33,0x22,0xf8 == ldset x2, x3, [sp]
|
||||
0x41,0x30,0xa0,0xf8 == ldseta x0, x1, [x2]
|
||||
0xe3,0x33,0xa2,0xf8 == ldseta x2, x3, [sp]
|
||||
0x41,0x30,0x60,0xf8 == ldsetl x0, x1, [x2]
|
||||
0xe3,0x33,0x62,0xf8 == ldsetl x2, x3, [sp]
|
||||
0x41,0x30,0xe0,0xf8 == ldsetal x0, x1, [x2]
|
||||
0xe3,0x33,0xe2,0xf8 == ldsetal x2, x3, [sp]
|
||||
0x41,0x40,0x20,0xb8 == ldsmax w0, w1, [x2]
|
||||
0xe3,0x43,0x22,0xb8 == ldsmax w2, w3, [sp]
|
||||
0x41,0x40,0xa0,0xb8 == ldsmaxa w0, w1, [x2]
|
||||
0xe3,0x43,0xa2,0xb8 == ldsmaxa w2, w3, [sp]
|
||||
0x41,0x40,0x60,0xb8 == ldsmaxl w0, w1, [x2]
|
||||
0xe3,0x43,0x62,0xb8 == ldsmaxl w2, w3, [sp]
|
||||
0x41,0x40,0xe0,0xb8 == ldsmaxal w0, w1, [x2]
|
||||
0xe3,0x43,0xe2,0xb8 == ldsmaxal w2, w3, [sp]
|
||||
0x41,0x40,0x20,0x38 == ldsmaxb w0, w1, [x2]
|
||||
0xe3,0x43,0x22,0x38 == ldsmaxb w2, w3, [sp]
|
||||
0x41,0x40,0x20,0x78 == ldsmaxh w0, w1, [x2]
|
||||
0xe3,0x43,0x22,0x78 == ldsmaxh w2, w3, [sp]
|
||||
0x41,0x40,0xa0,0x38 == ldsmaxab w0, w1, [x2]
|
||||
0xe3,0x43,0xa2,0x38 == ldsmaxab w2, w3, [sp]
|
||||
0x41,0x40,0x60,0x38 == ldsmaxlb w0, w1, [x2]
|
||||
0xe3,0x43,0x62,0x38 == ldsmaxlb w2, w3, [sp]
|
||||
0x41,0x40,0xe0,0x38 == ldsmaxalb w0, w1, [x2]
|
||||
0xe3,0x43,0xe2,0x38 == ldsmaxalb w2, w3, [sp]
|
||||
0x41,0x40,0xa0,0x78 == ldsmaxah w0, w1, [x2]
|
||||
0xe3,0x43,0xa2,0x78 == ldsmaxah w2, w3, [sp]
|
||||
0x41,0x40,0x60,0x78 == ldsmaxlh w0, w1, [x2]
|
||||
0xe3,0x43,0x62,0x78 == ldsmaxlh w2, w3, [sp]
|
||||
0x41,0x40,0xe0,0x78 == ldsmaxalh w0, w1, [x2]
|
||||
0xe3,0x43,0xe2,0x78 == ldsmaxalh w2, w3, [sp]
|
||||
0x41,0x40,0x20,0xf8 == ldsmax x0, x1, [x2]
|
||||
0xe3,0x43,0x22,0xf8 == ldsmax x2, x3, [sp]
|
||||
0x41,0x40,0xa0,0xf8 == ldsmaxa x0, x1, [x2]
|
||||
0xe3,0x43,0xa2,0xf8 == ldsmaxa x2, x3, [sp]
|
||||
0x41,0x40,0x60,0xf8 == ldsmaxl x0, x1, [x2]
|
||||
0xe3,0x43,0x62,0xf8 == ldsmaxl x2, x3, [sp]
|
||||
0x41,0x40,0xe0,0xf8 == ldsmaxal x0, x1, [x2]
|
||||
0xe3,0x43,0xe2,0xf8 == ldsmaxal x2, x3, [sp]
|
||||
0x41,0x50,0x20,0xb8 == ldsmin w0, w1, [x2]
|
||||
0xe3,0x53,0x22,0xb8 == ldsmin w2, w3, [sp]
|
||||
0x41,0x50,0xa0,0xb8 == ldsmina w0, w1, [x2]
|
||||
0xe3,0x53,0xa2,0xb8 == ldsmina w2, w3, [sp]
|
||||
0x41,0x50,0x60,0xb8 == ldsminl w0, w1, [x2]
|
||||
0xe3,0x53,0x62,0xb8 == ldsminl w2, w3, [sp]
|
||||
0x41,0x50,0xe0,0xb8 == ldsminal w0, w1, [x2]
|
||||
0xe3,0x53,0xe2,0xb8 == ldsminal w2, w3, [sp]
|
||||
0x41,0x50,0x20,0x38 == ldsminb w0, w1, [x2]
|
||||
0xe3,0x53,0x22,0x38 == ldsminb w2, w3, [sp]
|
||||
0x41,0x50,0x20,0x78 == ldsminh w0, w1, [x2]
|
||||
0xe3,0x53,0x22,0x78 == ldsminh w2, w3, [sp]
|
||||
0x41,0x50,0xa0,0x38 == ldsminab w0, w1, [x2]
|
||||
0xe3,0x53,0xa2,0x38 == ldsminab w2, w3, [sp]
|
||||
0x41,0x50,0x60,0x38 == ldsminlb w0, w1, [x2]
|
||||
0xe3,0x53,0x62,0x38 == ldsminlb w2, w3, [sp]
|
||||
0x41,0x50,0xe0,0x38 == ldsminalb w0, w1, [x2]
|
||||
0xe3,0x53,0xe2,0x38 == ldsminalb w2, w3, [sp]
|
||||
0x41,0x50,0xa0,0x78 == ldsminah w0, w1, [x2]
|
||||
0xe3,0x53,0xa2,0x78 == ldsminah w2, w3, [sp]
|
||||
0x41,0x50,0x60,0x78 == ldsminlh w0, w1, [x2]
|
||||
0xe3,0x53,0x62,0x78 == ldsminlh w2, w3, [sp]
|
||||
0x41,0x50,0xe0,0x78 == ldsminalh w0, w1, [x2]
|
||||
0xe3,0x53,0xe2,0x78 == ldsminalh w2, w3, [sp]
|
||||
0x41,0x50,0x20,0xf8 == ldsmin x0, x1, [x2]
|
||||
0xe3,0x53,0x22,0xf8 == ldsmin x2, x3, [sp]
|
||||
0x41,0x50,0xa0,0xf8 == ldsmina x0, x1, [x2]
|
||||
0xe3,0x53,0xa2,0xf8 == ldsmina x2, x3, [sp]
|
||||
0x41,0x50,0x60,0xf8 == ldsminl x0, x1, [x2]
|
||||
0xe3,0x53,0x62,0xf8 == ldsminl x2, x3, [sp]
|
||||
0x41,0x50,0xe0,0xf8 == ldsminal x0, x1, [x2]
|
||||
0xe3,0x53,0xe2,0xf8 == ldsminal x2, x3, [sp]
|
||||
0x41,0x60,0x20,0xb8 == ldumax w0, w1, [x2]
|
||||
0xe3,0x63,0x22,0xb8 == ldumax w2, w3, [sp]
|
||||
0x41,0x60,0xa0,0xb8 == ldumaxa w0, w1, [x2]
|
||||
0xe3,0x63,0xa2,0xb8 == ldumaxa w2, w3, [sp]
|
||||
0x41,0x60,0x60,0xb8 == ldumaxl w0, w1, [x2]
|
||||
0xe3,0x63,0x62,0xb8 == ldumaxl w2, w3, [sp]
|
||||
0x41,0x60,0xe0,0xb8 == ldumaxal w0, w1, [x2]
|
||||
0xe3,0x63,0xe2,0xb8 == ldumaxal w2, w3, [sp]
|
||||
0x41,0x60,0x20,0x38 == ldumaxb w0, w1, [x2]
|
||||
0xe3,0x63,0x22,0x38 == ldumaxb w2, w3, [sp]
|
||||
0x41,0x60,0x20,0x78 == ldumaxh w0, w1, [x2]
|
||||
0xe3,0x63,0x22,0x78 == ldumaxh w2, w3, [sp]
|
||||
0x41,0x60,0xa0,0x38 == ldumaxab w0, w1, [x2]
|
||||
0xe3,0x63,0xa2,0x38 == ldumaxab w2, w3, [sp]
|
||||
0x41,0x60,0x60,0x38 == ldumaxlb w0, w1, [x2]
|
||||
0xe3,0x63,0x62,0x38 == ldumaxlb w2, w3, [sp]
|
||||
0x41,0x60,0xe0,0x38 == ldumaxalb w0, w1, [x2]
|
||||
0xe3,0x63,0xe2,0x38 == ldumaxalb w2, w3, [sp]
|
||||
0x41,0x60,0xa0,0x78 == ldumaxah w0, w1, [x2]
|
||||
0xe3,0x63,0xa2,0x78 == ldumaxah w2, w3, [sp]
|
||||
0x41,0x60,0x60,0x78 == ldumaxlh w0, w1, [x2]
|
||||
0xe3,0x63,0x62,0x78 == ldumaxlh w2, w3, [sp]
|
||||
0x41,0x60,0xe0,0x78 == ldumaxalh w0, w1, [x2]
|
||||
0xe3,0x63,0xe2,0x78 == ldumaxalh w2, w3, [sp]
|
||||
0x41,0x60,0x20,0xf8 == ldumax x0, x1, [x2]
|
||||
0xe3,0x63,0x22,0xf8 == ldumax x2, x3, [sp]
|
||||
0x41,0x60,0xa0,0xf8 == ldumaxa x0, x1, [x2]
|
||||
0xe3,0x63,0xa2,0xf8 == ldumaxa x2, x3, [sp]
|
||||
0x41,0x60,0x60,0xf8 == ldumaxl x0, x1, [x2]
|
||||
0xe3,0x63,0x62,0xf8 == ldumaxl x2, x3, [sp]
|
||||
0x41,0x60,0xe0,0xf8 == ldumaxal x0, x1, [x2]
|
||||
0xe3,0x63,0xe2,0xf8 == ldumaxal x2, x3, [sp]
|
||||
0x41,0x70,0x20,0xb8 == ldumin w0, w1, [x2]
|
||||
0xe3,0x73,0x22,0xb8 == ldumin w2, w3, [sp]
|
||||
0x41,0x70,0xa0,0xb8 == ldumina w0, w1, [x2]
|
||||
0xe3,0x73,0xa2,0xb8 == ldumina w2, w3, [sp]
|
||||
0x41,0x70,0x60,0xb8 == lduminl w0, w1, [x2]
|
||||
0xe3,0x73,0x62,0xb8 == lduminl w2, w3, [sp]
|
||||
0x41,0x70,0xe0,0xb8 == lduminal w0, w1, [x2]
|
||||
0xe3,0x73,0xe2,0xb8 == lduminal w2, w3, [sp]
|
||||
0x41,0x70,0x20,0x38 == lduminb w0, w1, [x2]
|
||||
0xe3,0x73,0x22,0x38 == lduminb w2, w3, [sp]
|
||||
0x41,0x70,0x20,0x78 == lduminh w0, w1, [x2]
|
||||
0xe3,0x73,0x22,0x78 == lduminh w2, w3, [sp]
|
||||
0x41,0x70,0xa0,0x38 == lduminab w0, w1, [x2]
|
||||
0xe3,0x73,0xa2,0x38 == lduminab w2, w3, [sp]
|
||||
0x41,0x70,0x60,0x38 == lduminlb w0, w1, [x2]
|
||||
0xe3,0x73,0x62,0x38 == lduminlb w2, w3, [sp]
|
||||
0x41,0x70,0xe0,0x38 == lduminalb w0, w1, [x2]
|
||||
0xe3,0x73,0xe2,0x38 == lduminalb w2, w3, [sp]
|
||||
0x41,0x70,0xa0,0x78 == lduminah w0, w1, [x2]
|
||||
0xe3,0x73,0xa2,0x78 == lduminah w2, w3, [sp]
|
||||
0x41,0x70,0x60,0x78 == lduminlh w0, w1, [x2]
|
||||
0xe3,0x73,0x62,0x78 == lduminlh w2, w3, [sp]
|
||||
0x41,0x70,0xe0,0x78 == lduminalh w0, w1, [x2]
|
||||
0xe3,0x73,0xe2,0x78 == lduminalh w2, w3, [sp]
|
||||
0x41,0x70,0x20,0xf8 == ldumin x0, x1, [x2]
|
||||
0xe3,0x73,0x22,0xf8 == ldumin x2, x3, [sp]
|
||||
0x41,0x70,0xa0,0xf8 == ldumina x0, x1, [x2]
|
||||
0xe3,0x73,0xa2,0xf8 == ldumina x2, x3, [sp]
|
||||
0x41,0x70,0x60,0xf8 == lduminl x0, x1, [x2]
|
||||
0xe3,0x73,0x62,0xf8 == lduminl x2, x3, [sp]
|
||||
0x41,0x70,0xe0,0xf8 == lduminal x0, x1, [x2]
|
||||
0xe3,0x73,0xe2,0xf8 == lduminal x2, x3, [sp]
|
||||
0x5f,0x00,0x20,0xb8 == stadd w0, [x2]
|
||||
0xff,0x03,0x22,0xb8 == stadd w2, [sp]
|
||||
0x5f,0x00,0x60,0xb8 == staddl w0, [x2]
|
||||
0xff,0x03,0x62,0xb8 == staddl w2, [sp]
|
||||
0x5f,0x00,0x20,0x38 == staddb w0, [x2]
|
||||
0xff,0x03,0x22,0x38 == staddb w2, [sp]
|
||||
0x5f,0x00,0x20,0x78 == staddh w0, [x2]
|
||||
0xff,0x03,0x22,0x78 == staddh w2, [sp]
|
||||
0x5f,0x00,0x60,0x38 == staddlb w0, [x2]
|
||||
0xff,0x03,0x62,0x38 == staddlb w2, [sp]
|
||||
0x5f,0x00,0x60,0x78 == staddlh w0, [x2]
|
||||
0xff,0x03,0x62,0x78 == staddlh w2, [sp]
|
||||
0x5f,0x00,0x20,0xf8 == stadd x0, [x2]
|
||||
0xff,0x03,0x22,0xf8 == stadd x2, [sp]
|
||||
0x5f,0x00,0x60,0xf8 == staddl x0, [x2]
|
||||
0xff,0x03,0x62,0xf8 == staddl x2, [sp]
|
||||
0x5f,0x10,0x20,0xb8 == stclr w0, [x2]
|
||||
0xff,0x13,0x22,0xb8 == stclr w2, [sp]
|
||||
0x5f,0x10,0x60,0xb8 == stclrl w0, [x2]
|
||||
0xff,0x13,0x62,0xb8 == stclrl w2, [sp]
|
||||
0x5f,0x10,0x20,0x38 == stclrb w0, [x2]
|
||||
0xff,0x13,0x22,0x38 == stclrb w2, [sp]
|
||||
0x5f,0x10,0x20,0x78 == stclrh w0, [x2]
|
||||
0xff,0x13,0x22,0x78 == stclrh w2, [sp]
|
||||
0x5f,0x10,0x60,0x38 == stclrlb w0, [x2]
|
||||
0xff,0x13,0x62,0x38 == stclrlb w2, [sp]
|
||||
0x5f,0x10,0x60,0x78 == stclrlh w0, [x2]
|
||||
0xff,0x13,0x62,0x78 == stclrlh w2, [sp]
|
||||
0x5f,0x10,0x20,0xf8 == stclr x0, [x2]
|
||||
0xff,0x13,0x22,0xf8 == stclr x2, [sp]
|
||||
0x5f,0x10,0x60,0xf8 == stclrl x0, [x2]
|
||||
0xff,0x13,0x62,0xf8 == stclrl x2, [sp]
|
||||
0x5f,0x20,0x20,0xb8 == steor w0, [x2]
|
||||
0xff,0x23,0x22,0xb8 == steor w2, [sp]
|
||||
0x5f,0x20,0x60,0xb8 == steorl w0, [x2]
|
||||
0xff,0x23,0x62,0xb8 == steorl w2, [sp]
|
||||
0x5f,0x20,0x20,0x38 == steorb w0, [x2]
|
||||
0xff,0x23,0x22,0x38 == steorb w2, [sp]
|
||||
0x5f,0x20,0x20,0x78 == steorh w0, [x2]
|
||||
0xff,0x23,0x22,0x78 == steorh w2, [sp]
|
||||
0x5f,0x20,0x60,0x38 == steorlb w0, [x2]
|
||||
0xff,0x23,0x62,0x38 == steorlb w2, [sp]
|
||||
0x5f,0x20,0x60,0x78 == steorlh w0, [x2]
|
||||
0xff,0x23,0x62,0x78 == steorlh w2, [sp]
|
||||
0x5f,0x20,0x20,0xf8 == steor x0, [x2]
|
||||
0xff,0x23,0x22,0xf8 == steor x2, [sp]
|
||||
0x5f,0x20,0x60,0xf8 == steorl x0, [x2]
|
||||
0xff,0x23,0x62,0xf8 == steorl x2, [sp]
|
||||
0x5f,0x30,0x20,0xb8 == stset w0, [x2]
|
||||
0xff,0x33,0x22,0xb8 == stset w2, [sp]
|
||||
0x5f,0x30,0x60,0xb8 == stsetl w0, [x2]
|
||||
0xff,0x33,0x62,0xb8 == stsetl w2, [sp]
|
||||
0x5f,0x30,0x20,0x38 == stsetb w0, [x2]
|
||||
0xff,0x33,0x22,0x38 == stsetb w2, [sp]
|
||||
0x5f,0x30,0x20,0x78 == stseth w0, [x2]
|
||||
0xff,0x33,0x22,0x78 == stseth w2, [sp]
|
||||
0x5f,0x30,0x60,0x38 == stsetlb w0, [x2]
|
||||
0xff,0x33,0x62,0x38 == stsetlb w2, [sp]
|
||||
0x5f,0x30,0x60,0x78 == stsetlh w0, [x2]
|
||||
0xff,0x33,0x62,0x78 == stsetlh w2, [sp]
|
||||
0x5f,0x30,0x20,0xf8 == stset x0, [x2]
|
||||
0xff,0x33,0x22,0xf8 == stset x2, [sp]
|
||||
0x5f,0x30,0x60,0xf8 == stsetl x0, [x2]
|
||||
0xff,0x33,0x62,0xf8 == stsetl x2, [sp]
|
||||
0x5f,0x40,0x20,0xb8 == stsmax w0, [x2]
|
||||
0xff,0x43,0x22,0xb8 == stsmax w2, [sp]
|
||||
0x5f,0x40,0x60,0xb8 == stsmaxl w0, [x2]
|
||||
0xff,0x43,0x62,0xb8 == stsmaxl w2, [sp]
|
||||
0x5f,0x40,0x20,0x38 == stsmaxb w0, [x2]
|
||||
0xff,0x43,0x22,0x38 == stsmaxb w2, [sp]
|
||||
0x5f,0x40,0x20,0x78 == stsmaxh w0, [x2]
|
||||
0xff,0x43,0x22,0x78 == stsmaxh w2, [sp]
|
||||
0x5f,0x40,0x60,0x38 == stsmaxlb w0, [x2]
|
||||
0xff,0x43,0x62,0x38 == stsmaxlb w2, [sp]
|
||||
0x5f,0x40,0x60,0x78 == stsmaxlh w0, [x2]
|
||||
0xff,0x43,0x62,0x78 == stsmaxlh w2, [sp]
|
||||
0x5f,0x40,0x20,0xf8 == stsmax x0, [x2]
|
||||
0xff,0x43,0x22,0xf8 == stsmax x2, [sp]
|
||||
0x5f,0x40,0x60,0xf8 == stsmaxl x0, [x2]
|
||||
0xff,0x43,0x62,0xf8 == stsmaxl x2, [sp]
|
||||
0x5f,0x50,0x20,0xb8 == stsmin w0, [x2]
|
||||
0xff,0x53,0x22,0xb8 == stsmin w2, [sp]
|
||||
0x5f,0x50,0x60,0xb8 == stsminl w0, [x2]
|
||||
0xff,0x53,0x62,0xb8 == stsminl w2, [sp]
|
||||
0x5f,0x50,0x20,0x38 == stsminb w0, [x2]
|
||||
0xff,0x53,0x22,0x38 == stsminb w2, [sp]
|
||||
0x5f,0x50,0x20,0x78 == stsminh w0, [x2]
|
||||
0xff,0x53,0x22,0x78 == stsminh w2, [sp]
|
||||
0x5f,0x50,0x60,0x38 == stsminlb w0, [x2]
|
||||
0xff,0x53,0x62,0x38 == stsminlb w2, [sp]
|
||||
0x5f,0x50,0x60,0x78 == stsminlh w0, [x2]
|
||||
0xff,0x53,0x62,0x78 == stsminlh w2, [sp]
|
||||
0x5f,0x50,0x20,0xf8 == stsmin x0, [x2]
|
||||
0xff,0x53,0x22,0xf8 == stsmin x2, [sp]
|
||||
0x5f,0x50,0x60,0xf8 == stsminl x0, [x2]
|
||||
0xff,0x53,0x62,0xf8 == stsminl x2, [sp]
|
||||
0x5f,0x60,0x20,0xb8 == stumax w0, [x2]
|
||||
0xff,0x63,0x22,0xb8 == stumax w2, [sp]
|
||||
0x5f,0x60,0x60,0xb8 == stumaxl w0, [x2]
|
||||
0xff,0x63,0x62,0xb8 == stumaxl w2, [sp]
|
||||
0x5f,0x60,0x20,0x38 == stumaxb w0, [x2]
|
||||
0xff,0x63,0x22,0x38 == stumaxb w2, [sp]
|
||||
0x5f,0x60,0x20,0x78 == stumaxh w0, [x2]
|
||||
0xff,0x63,0x22,0x78 == stumaxh w2, [sp]
|
||||
0x5f,0x60,0x60,0x38 == stumaxlb w0, [x2]
|
||||
0xff,0x63,0x62,0x38 == stumaxlb w2, [sp]
|
||||
0x5f,0x60,0x60,0x78 == stumaxlh w0, [x2]
|
||||
0xff,0x63,0x62,0x78 == stumaxlh w2, [sp]
|
||||
0x5f,0x60,0x20,0xf8 == stumax x0, [x2]
|
||||
0xff,0x63,0x22,0xf8 == stumax x2, [sp]
|
||||
0x5f,0x60,0x60,0xf8 == stumaxl x0, [x2]
|
||||
0xff,0x63,0x62,0xf8 == stumaxl x2, [sp]
|
||||
0x5f,0x70,0x20,0xb8 == stumin w0, [x2]
|
||||
0xff,0x73,0x22,0xb8 == stumin w2, [sp]
|
||||
0x5f,0x70,0x60,0xb8 == stuminl w0, [x2]
|
||||
0xff,0x73,0x62,0xb8 == stuminl w2, [sp]
|
||||
0x5f,0x70,0x20,0x38 == stuminb w0, [x2]
|
||||
0xff,0x73,0x22,0x38 == stuminb w2, [sp]
|
||||
0x5f,0x70,0x20,0x78 == stuminh w0, [x2]
|
||||
0xff,0x73,0x22,0x78 == stuminh w2, [sp]
|
||||
6
thirdparty/capstone/suite/MC/AArch64/armv8.1a-pan.s.cs
vendored
Normal file
6
thirdparty/capstone/suite/MC/AArch64/armv8.1a-pan.s.cs
vendored
Normal file
@@ -0,0 +1,6 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0x9f,0x40,0x00,0xd5 == msr PAN, #0
|
||||
0x9f,0x41,0x00,0xd5 == msr PAN, #1
|
||||
0x65,0x42,0x18,0xd5 == msr PAN, x5
|
||||
0x6d,0x42,0x38,0xd5 == mrs x13, PAN
|
||||
8
thirdparty/capstone/suite/MC/AArch64/armv8.1a-pan.txt.cs
vendored
Normal file
8
thirdparty/capstone/suite/MC/AArch64/armv8.1a-pan.txt.cs
vendored
Normal file
@@ -0,0 +1,8 @@
|
||||
# CS_ARCH_AARCH64, None, None
|
||||
# This regression test file is new. The option flags could not be determined.
|
||||
# LLVM uses the following mattr = ['mattr=+v8.1a']
|
||||
0x9f,0x40,0x00,0xd5 == msr PAN, #0
|
||||
0x9f,0x41,0x00,0xd5 == msr PAN, #1
|
||||
0x9f,0x4f,0x00,0xd5 == msr PAN, #15
|
||||
0x65,0x42,0x18,0xd5 == msr PAN, x5
|
||||
0x6d,0x42,0x38,0xd5 == mrs x13, PAN
|
||||
26
thirdparty/capstone/suite/MC/AArch64/armv8.1a-rdma.s.cs
vendored
Normal file
26
thirdparty/capstone/suite/MC/AArch64/armv8.1a-rdma.s.cs
vendored
Normal file
@@ -0,0 +1,26 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0x20,0x84,0x42,0x2e == sqrdmlah v0.4h, v1.4h, v2.4h
|
||||
0x20,0x8c,0x42,0x2e == sqrdmlsh v0.4h, v1.4h, v2.4h
|
||||
0x20,0x84,0x82,0x2e == sqrdmlah v0.2s, v1.2s, v2.2s
|
||||
0x20,0x8c,0x82,0x2e == sqrdmlsh v0.2s, v1.2s, v2.2s
|
||||
0x20,0x84,0x82,0x6e == sqrdmlah v0.4s, v1.4s, v2.4s
|
||||
0x20,0x8c,0x82,0x6e == sqrdmlsh v0.4s, v1.4s, v2.4s
|
||||
0x20,0x84,0x42,0x6e == sqrdmlah v0.8h, v1.8h, v2.8h
|
||||
0x20,0x8c,0x42,0x6e == sqrdmlsh v0.8h, v1.8h, v2.8h
|
||||
0x20,0x84,0x42,0x7e == sqrdmlah h0, h1, h2
|
||||
0x20,0x8c,0x42,0x7e == sqrdmlsh h0, h1, h2
|
||||
0x20,0x84,0x82,0x7e == sqrdmlah s0, s1, s2
|
||||
0x20,0x8c,0x82,0x7e == sqrdmlsh s0, s1, s2
|
||||
0x20,0xd0,0x72,0x2f == sqrdmlah v0.4h, v1.4h, v2.h[3]
|
||||
0x20,0xf0,0x72,0x2f == sqrdmlsh v0.4h, v1.4h, v2.h[3]
|
||||
0x20,0xd0,0xa2,0x2f == sqrdmlah v0.2s, v1.2s, v2.s[1]
|
||||
0x20,0xf0,0xa2,0x2f == sqrdmlsh v0.2s, v1.2s, v2.s[1]
|
||||
0x20,0xd0,0x72,0x6f == sqrdmlah v0.8h, v1.8h, v2.h[3]
|
||||
0x20,0xf0,0x72,0x6f == sqrdmlsh v0.8h, v1.8h, v2.h[3]
|
||||
0x20,0xd8,0xa2,0x6f == sqrdmlah v0.4s, v1.4s, v2.s[3]
|
||||
0x20,0xf8,0xa2,0x6f == sqrdmlsh v0.4s, v1.4s, v2.s[3]
|
||||
0x20,0xd0,0x72,0x7f == sqrdmlah h0, h1, v2.h[3]
|
||||
0x20,0xf0,0x72,0x7f == sqrdmlsh h0, h1, v2.h[3]
|
||||
0x20,0xd8,0xa2,0x7f == sqrdmlah s0, s1, v2.s[3]
|
||||
0x20,0xf8,0xa2,0x7f == sqrdmlsh s0, s1, v2.s[3]
|
||||
50
thirdparty/capstone/suite/MC/AArch64/armv8.1a-rdma.txt.cs
vendored
Normal file
50
thirdparty/capstone/suite/MC/AArch64/armv8.1a-rdma.txt.cs
vendored
Normal file
@@ -0,0 +1,50 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0x20,0x84,0x02,0x2e == sqrdmlah v0.8b, v1.8b, v2.8b
|
||||
0x20,0x8c,0x02,0x2e == sqrdmlsh v0.8b, v1.8b, v2.8b
|
||||
0x20,0x84,0xc2,0x2e == sqrdmlah v0.1d, v1.1d, v2.1d
|
||||
0x20,0x8c,0xc2,0x2e == sqrdmlsh v0.1d, v1.1d, v2.1d
|
||||
0x20,0x84,0x02,0x6e == sqrdmlah v0.16b, v1.16b, v2.16b
|
||||
0x20,0x8c,0x02,0x6e == sqrdmlsh v0.16b, v1.16b, v2.16b
|
||||
0x20,0x84,0xc2,0x6e == sqrdmlah v0.2d, v1.2d, v2.2d
|
||||
0x20,0x8c,0xc2,0x6e == sqrdmlsh v0.2d, v1.2d, v2.2d
|
||||
0x20,0x84,0x02,0x7e == sqrdmlah b0, b1, b2
|
||||
0x20,0x8c,0x02,0x7e == sqrdmlsh b0, b1, b2
|
||||
0x20,0x84,0xc2,0x7e == sqrdmlah d0, d1, d2
|
||||
0x20,0x8c,0xc2,0x7e == sqrdmlsh d0, d1, d2
|
||||
0x20,0xd0,0x32,0x2f == sqrdmlah v0.8b, v1.8b, v2.b[3]
|
||||
0x20,0xf0,0x32,0x2f == sqrdmlsh v0.8b, v1.8b, v2.b[3]
|
||||
0x20,0xd0,0xe2,0x2f == sqrdmlah v0.1d, v1.1d, v2.d[1]
|
||||
0x20,0xf0,0xe2,0x2f == sqrdmlsh v0.1d, v1.1d, v2.d[1]
|
||||
0x20,0xd0,0x32,0x6f == sqrdmlah v0.16b, v1.16b, v2.b[3]
|
||||
0x20,0xf0,0x32,0x6f == sqrdmlsh v0.16b, v1.16b, v2.b[3]
|
||||
0x20,0xd8,0xe2,0x6f == sqrdmlah v0.2d, v1.2d, v2.d[3]
|
||||
0x20,0xf8,0xe2,0x6f == sqrdmlsh v0.2d, v1.2d, v2.d[3]
|
||||
0x20,0xd0,0x32,0x7f == sqrdmlah b0, b1, v2.b[3]
|
||||
0x20,0xf0,0x32,0x7f == sqrdmlsh b0, b1, v2.b[3]
|
||||
0x20,0xd8,0xe2,0x7f == sqrdmlah d0, d1, v2.d[3]
|
||||
0x20,0xf8,0xe2,0x7f == sqrdmlsh d0, d1, v2.d[3]
|
||||
0x20,0x84,0x42,0x2e == sqrdmlah v0.4h, v1.4h, v2.4h
|
||||
0x20,0x8c,0x42,0x2e == sqrdmlsh v0.4h, v1.4h, v2.4h
|
||||
0x20,0x84,0x82,0x2e == sqrdmlah v0.2s, v1.2s, v2.2s
|
||||
0x20,0x8c,0x82,0x2e == sqrdmlsh v0.2s, v1.2s, v2.2s
|
||||
0x20,0x84,0x42,0x6e == sqrdmlah v0.8h, v1.8h, v2.8h
|
||||
0x20,0x8c,0x42,0x6e == sqrdmlsh v0.8h, v1.8h, v2.8h
|
||||
0x20,0x84,0x82,0x6e == sqrdmlah v0.4s, v1.4s, v2.4s
|
||||
0x20,0x8c,0x82,0x6e == sqrdmlsh v0.4s, v1.4s, v2.4s
|
||||
0x20,0x84,0x42,0x7e == sqrdmlah h0, h1, h2
|
||||
0x20,0x8c,0x42,0x7e == sqrdmlsh h0, h1, h2
|
||||
0x20,0x84,0x82,0x7e == sqrdmlah s0, s1, s2
|
||||
0x20,0x8c,0x82,0x7e == sqrdmlsh s0, s1, s2
|
||||
0x20,0xd0,0x72,0x2f == sqrdmlah v0.4h, v1.4h, v2.h[3]
|
||||
0x20,0xf0,0x72,0x2f == sqrdmlsh v0.4h, v1.4h, v2.h[3]
|
||||
0x20,0xd0,0xa2,0x2f == sqrdmlah v0.2s, v1.2s, v2.s[1]
|
||||
0x20,0xf0,0xa2,0x2f == sqrdmlsh v0.2s, v1.2s, v2.s[1]
|
||||
0x20,0xd0,0x72,0x6f == sqrdmlah v0.8h, v1.8h, v2.h[3]
|
||||
0x20,0xf0,0x72,0x6f == sqrdmlsh v0.8h, v1.8h, v2.h[3]
|
||||
0x20,0xd8,0xa2,0x6f == sqrdmlah v0.4s, v1.4s, v2.s[3]
|
||||
0x20,0xf8,0xa2,0x6f == sqrdmlsh v0.4s, v1.4s, v2.s[3]
|
||||
0x20,0xd0,0x72,0x7f == sqrdmlah h0, h1, v2.h[3]
|
||||
0x20,0xf0,0x72,0x7f == sqrdmlsh h0, h1, v2.h[3]
|
||||
0x20,0xd8,0xa2,0x7f == sqrdmlah s0, s1, v2.s[3]
|
||||
0x20,0xf8,0xa2,0x7f == sqrdmlsh s0, s1, v2.s[3]
|
||||
29
thirdparty/capstone/suite/MC/AArch64/armv8.1a-vhe.s.cs
vendored
Normal file
29
thirdparty/capstone/suite/MC/AArch64/armv8.1a-vhe.s.cs
vendored
Normal file
@@ -0,0 +1,29 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0x20,0x20,0x1c,0xd5 == msr TTBR1_EL2, x0
|
||||
0x20,0xd0,0x1c,0xd5 == msr CONTEXTIDR_EL2, x0
|
||||
0x00,0xe3,0x1c,0xd5 == msr CNTHV_TVAL_EL2, x0
|
||||
0x40,0xe3,0x1c,0xd5 == msr CNTHV_CVAL_EL2, x0
|
||||
0x20,0xe3,0x1c,0xd5 == msr CNTHV_CTL_EL2, x0
|
||||
0x00,0x10,0x1d,0xd5 == msr SCTLR_EL12, x0
|
||||
0x40,0x10,0x1d,0xd5 == msr CPACR_EL12, x0
|
||||
0x00,0x20,0x1d,0xd5 == msr TTBR0_EL12, x0
|
||||
0x20,0x20,0x1d,0xd5 == msr TTBR1_EL12, x0
|
||||
0x40,0x20,0x1d,0xd5 == msr TCR_EL12, x0
|
||||
0x00,0x51,0x1d,0xd5 == msr AFSR0_EL12, x0
|
||||
0x20,0x51,0x1d,0xd5 == msr AFSR1_EL12, x0
|
||||
0x00,0x52,0x1d,0xd5 == msr ESR_EL12, x0
|
||||
0x00,0x60,0x1d,0xd5 == msr FAR_EL12, x0
|
||||
0x00,0xa2,0x1d,0xd5 == msr MAIR_EL12, x0
|
||||
0x00,0xa3,0x1d,0xd5 == msr AMAIR_EL12, x0
|
||||
0x00,0xc0,0x1d,0xd5 == msr VBAR_EL12, x0
|
||||
0x20,0xd0,0x1d,0xd5 == msr CONTEXTIDR_EL12, x0
|
||||
0x00,0xe1,0x1d,0xd5 == msr CNTKCTL_EL12, x0
|
||||
0x00,0xe2,0x1d,0xd5 == msr CNTP_TVAL_EL02, x0
|
||||
0x20,0xe2,0x1d,0xd5 == msr CNTP_CTL_EL02, x0
|
||||
0x40,0xe2,0x1d,0xd5 == msr CNTP_CVAL_EL02, x0
|
||||
0x00,0xe3,0x1d,0xd5 == msr CNTV_TVAL_EL02, x0
|
||||
0x20,0xe3,0x1d,0xd5 == msr CNTV_CTL_EL02, x0
|
||||
0x40,0xe3,0x1d,0xd5 == msr CNTV_CVAL_EL02, x0
|
||||
0x00,0x40,0x1d,0xd5 == msr SPSR_EL12, x0
|
||||
0x20,0x40,0x1d,0xd5 == msr ELR_EL12, x0
|
||||
30
thirdparty/capstone/suite/MC/AArch64/armv8.1a-vhe.txt.cs
vendored
Normal file
30
thirdparty/capstone/suite/MC/AArch64/armv8.1a-vhe.txt.cs
vendored
Normal file
@@ -0,0 +1,30 @@
|
||||
# CS_ARCH_AARCH64, None, None
|
||||
# This regression test file is new. The option flags could not be determined.
|
||||
# LLVM uses the following mattr = ['mattr=+v8.1a']
|
||||
0x20,0x20,0x1c,0xd5 == msr TTBR1_EL2, x0
|
||||
0x20,0xd0,0x1c,0xd5 == msr CONTEXTIDR_EL2, x0
|
||||
0x00,0xe3,0x1c,0xd5 == msr CNTHV_TVAL_EL2, x0
|
||||
0x40,0xe3,0x1c,0xd5 == msr CNTHV_CVAL_EL2, x0
|
||||
0x20,0xe3,0x1c,0xd5 == msr CNTHV_CTL_EL2, x0
|
||||
0x00,0x10,0x1d,0xd5 == msr SCTLR_EL12, x0
|
||||
0x40,0x10,0x1d,0xd5 == msr CPACR_EL12, x0
|
||||
0x00,0x20,0x1d,0xd5 == msr TTBR0_EL12, x0
|
||||
0x20,0x20,0x1d,0xd5 == msr TTBR1_EL12, x0
|
||||
0x40,0x20,0x1d,0xd5 == msr TCR_EL12, x0
|
||||
0x00,0x51,0x1d,0xd5 == msr AFSR0_EL12, x0
|
||||
0x20,0x51,0x1d,0xd5 == msr AFSR1_EL12, x0
|
||||
0x00,0x52,0x1d,0xd5 == msr ESR_EL12, x0
|
||||
0x00,0x60,0x1d,0xd5 == msr FAR_EL12, x0
|
||||
0x00,0xa2,0x1d,0xd5 == msr MAIR_EL12, x0
|
||||
0x00,0xa3,0x1d,0xd5 == msr AMAIR_EL12, x0
|
||||
0x00,0xc0,0x1d,0xd5 == msr VBAR_EL12, x0
|
||||
0x20,0xd0,0x1d,0xd5 == msr CONTEXTIDR_EL12, x0
|
||||
0x00,0xe1,0x1d,0xd5 == msr CNTKCTL_EL12, x0
|
||||
0x00,0xe2,0x1d,0xd5 == msr CNTP_TVAL_EL02, x0
|
||||
0x20,0xe2,0x1d,0xd5 == msr CNTP_CTL_EL02, x0
|
||||
0x40,0xe2,0x1d,0xd5 == msr CNTP_CVAL_EL02, x0
|
||||
0x00,0xe3,0x1d,0xd5 == msr CNTV_TVAL_EL02, x0
|
||||
0x20,0xe3,0x1d,0xd5 == msr CNTV_CTL_EL02, x0
|
||||
0x40,0xe3,0x1d,0xd5 == msr CNTV_CVAL_EL02, x0
|
||||
0x00,0x40,0x1d,0xd5 == msr SPSR_EL12, x0
|
||||
0x20,0x40,0x1d,0xd5 == msr ELR_EL12, x0
|
||||
4
thirdparty/capstone/suite/MC/AArch64/armv8.2a-at.s.cs
vendored
Normal file
4
thirdparty/capstone/suite/MC/AArch64/armv8.2a-at.s.cs
vendored
Normal file
@@ -0,0 +1,4 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0x01,0x79,0x08,0xd5 == at s1e1rp, x1
|
||||
0x22,0x79,0x08,0xd5 == at s1e1wp, x2
|
||||
4
thirdparty/capstone/suite/MC/AArch64/armv8.2a-at.txt.cs
vendored
Normal file
4
thirdparty/capstone/suite/MC/AArch64/armv8.2a-at.txt.cs
vendored
Normal file
@@ -0,0 +1,4 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0x01,0x79,0x08,0xd5 == at s1e1rp, x1
|
||||
0x22,0x79,0x08,0xd5 == at s1e1wp, x2
|
||||
19
thirdparty/capstone/suite/MC/AArch64/armv8.2a-crypto-apple.s.cs
vendored
Normal file
19
thirdparty/capstone/suite/MC/AArch64/armv8.2a-crypto-apple.s.cs
vendored
Normal file
@@ -0,0 +1,19 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0x20,0x80,0x62,0xce == sha512h.2d q0, q1, v2 ; encoding: [0x20,0x80,0x62,0xce]
|
||||
0x20,0x84,0x62,0xce == sha512h2.2d q0, q1, v2 ; encoding: [0x20,0x84,0x62,0xce]
|
||||
0x8b,0x81,0xc0,0xce == sha512su0.2d v11, v12 ; encoding: [0x8b,0x81,0xc0,0xce]
|
||||
0xab,0x89,0x6e,0xce == sha512su1.2d v11, v13, v14 ; encoding: [0xab,0x89,0x6e,0xce]
|
||||
0x99,0x09,0x07,0xce == eor3.16b v25, v12, v7, v2 ; encoding: [0x99,0x09,0x07,0xce]
|
||||
0xbe,0x8f,0x7a,0xce == rax1.2d v30, v29, v26 ; encoding: [0xbe,0x8f,0x7a,0xce]
|
||||
0xba,0xfe,0x9b,0xce == xar.2d v26, v21, v27, #63 ; encoding: [0xba,0xfe,0x9b,0xce]
|
||||
0x5f,0x07,0x22,0xce == bcax.16b v31, v26, v2, v1 ; encoding: [0x5f,0x07,0x22,0xce]
|
||||
0xf4,0x5a,0x55,0xce == sm3ss1.4s v20, v23, v21, v22 ; encoding: [0xf4,0x5a,0x55,0xce]
|
||||
0xf4,0xb2,0x55,0xce == sm3tt1a.4s v20, v23, v21[3] ; encoding: [0xf4,0xb2,0x55,0xce]
|
||||
0xf4,0xb6,0x55,0xce == sm3tt1b.4s v20, v23, v21[3] ; encoding: [0xf4,0xb6,0x55,0xce]
|
||||
0xf4,0xba,0x55,0xce == sm3tt2a.4s v20, v23, v21[3] ; encoding: [0xf4,0xba,0x55,0xce]
|
||||
0xf4,0xbe,0x55,0xce == sm3tt2b.4s v20, v23, v21[3] ; encoding: [0xf4,0xbe,0x55,0xce]
|
||||
0xbe,0xc3,0x7a,0xce == sm3partw1.4s v30, v29, v26 ; encoding: [0xbe,0xc3,0x7a,0xce]
|
||||
0xbe,0xc7,0x7a,0xce == sm3partw2.4s v30, v29, v26 ; encoding: [0xbe,0xc7,0x7a,0xce]
|
||||
0x6b,0xc9,0x73,0xce == sm4ekey.4s v11, v11, v19 ; encoding: [0x6b,0xc9,0x73,0xce]
|
||||
0xe2,0x85,0xc0,0xce == sm4e.4s v2, v15 ; encoding: [0xe2,0x85,0xc0,0xce]
|
||||
18
thirdparty/capstone/suite/MC/AArch64/armv8.2a-crypto.s.cs
vendored
Normal file
18
thirdparty/capstone/suite/MC/AArch64/armv8.2a-crypto.s.cs
vendored
Normal file
@@ -0,0 +1,18 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
0x20,0x80,0x62,0xce = sha512h q0, q1, v2.2d
|
||||
0x20,0x84,0x62,0xce = sha512h2 q0, q1, v2.2d
|
||||
0x8b,0x81,0xc0,0xce = sha512su0 v11.2d, v12.2d
|
||||
0xab,0x89,0x6e,0xce = sha512su1 v11.2d, v13.2d, v14.2d
|
||||
0x99,0x09,0x07,0xce = eor3 v25.16b, v12.16b, v7.16b, v2.16b
|
||||
0xbe,0x8f,0x7a,0xce = rax1 v30.2d, v29.2d, v26.2d
|
||||
0xba,0xfe,0x9b,0xce = xar v26.2d, v21.2d, v27.2d, #63
|
||||
0x5f,0x07,0x22,0xce = bcax v31.16b, v26.16b, v2.16b, v1.16b
|
||||
0xf4,0x5a,0x55,0xce = sm3ss1 v20.4s, v23.4s, v21.4s, v22.4s
|
||||
0xf4,0xb2,0x55,0xce = sm3tt1a v20.4s, v23.4s, v21.s[3]
|
||||
0xf4,0xb6,0x55,0xce = sm3tt1b v20.4s, v23.4s, v21.s[3]
|
||||
0xf4,0xba,0x55,0xce = sm3tt2a v20.4s, v23.4s, v21.s[3]
|
||||
0xf4,0xbe,0x55,0xce = sm3tt2b v20.4s, v23.4s, v21.s[3]
|
||||
0xbe,0xc3,0x7a,0xce = sm3partw1 v30.4s, v29.4s, v26.4s
|
||||
0xbe,0xc7,0x7a,0xce = sm3partw2 v30.4s, v29.4s, v26.4s
|
||||
0x6b,0xc9,0x73,0xce = sm4ekey v11.4s, v11.4s, v19.4s
|
||||
0xe2,0x85,0xc0,0xce = sm4e v2.4s, v15.4s
|
||||
11
thirdparty/capstone/suite/MC/AArch64/armv8.2a-dotprod.s.cs
vendored
Normal file
11
thirdparty/capstone/suite/MC/AArch64/armv8.2a-dotprod.s.cs
vendored
Normal file
@@ -0,0 +1,11 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
0x20,0x94,0x82,0x2e = udot v0.2s, v1.8b, v2.8b
|
||||
0x20,0x94,0x82,0x0e = sdot v0.2s, v1.8b, v2.8b
|
||||
0x20,0x94,0x82,0x6e = udot v0.4s, v1.16b, v2.16b
|
||||
0x20,0x94,0x82,0x4e = sdot v0.4s, v1.16b, v2.16b
|
||||
0x20,0xe0,0x82,0x2f = udot v0.2s, v1.8b, v2.4b[0]
|
||||
0x20,0xe0,0xa2,0x0f = sdot v0.2s, v1.8b, v2.4b[1]
|
||||
0x20,0xe8,0x82,0x6f = udot v0.4s, v1.16b, v2.4b[2]
|
||||
0x20,0xe8,0xa2,0x4f = sdot v0.4s, v1.16b, v2.4b[3]
|
||||
0x20,0xe0,0x82,0x2f = udot v0.2s, v1.8b, v2.4b[0]
|
||||
0x20,0xe8,0x82,0x6f = udot v0.4s, v1.16b, v2.4b[2]
|
||||
3
thirdparty/capstone/suite/MC/AArch64/armv8.2a-mmfr2.txt.cs
vendored
Normal file
3
thirdparty/capstone/suite/MC/AArch64/armv8.2a-mmfr2.txt.cs
vendored
Normal file
@@ -0,0 +1,3 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0x43,0x07,0x38,0xd5 == mrs x3, ID_AA64MMFR2_EL1
|
||||
3
thirdparty/capstone/suite/MC/AArch64/armv8.2a-persistent-memory.s.cs
vendored
Normal file
3
thirdparty/capstone/suite/MC/AArch64/armv8.2a-persistent-memory.s.cs
vendored
Normal file
@@ -0,0 +1,3 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0x27,0x7c,0x0b,0xd5 == dc cvap, x7
|
||||
3
thirdparty/capstone/suite/MC/AArch64/armv8.2a-persistent-memory.txt.cs
vendored
Normal file
3
thirdparty/capstone/suite/MC/AArch64/armv8.2a-persistent-memory.txt.cs
vendored
Normal file
@@ -0,0 +1,3 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0x27,0x7c,0x0b,0xd5 == dc cvap, x7
|
||||
27
thirdparty/capstone/suite/MC/AArch64/armv8.2a-statistical-profiling.s.cs
vendored
Normal file
27
thirdparty/capstone/suite/MC/AArch64/armv8.2a-statistical-profiling.s.cs
vendored
Normal file
@@ -0,0 +1,27 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0x3f,0x22,0x03,0xd5 == psb csync
|
||||
0x00,0x9a,0x18,0xd5 == msr PMBLIMITR_EL1, x0
|
||||
0x20,0x9a,0x18,0xd5 == msr PMBPTR_EL1, x0
|
||||
0x60,0x9a,0x18,0xd5 == msr PMBSR_EL1, x0
|
||||
0x00,0x99,0x1c,0xd5 == msr PMSCR_EL2, x0
|
||||
0x00,0x99,0x1d,0xd5 == msr PMSCR_EL12, x0
|
||||
0x00,0x99,0x18,0xd5 == msr PMSCR_EL1, x0
|
||||
0x40,0x99,0x18,0xd5 == msr PMSICR_EL1, x0
|
||||
0x60,0x99,0x18,0xd5 == msr PMSIRR_EL1, x0
|
||||
0x80,0x99,0x18,0xd5 == msr PMSFCR_EL1, x0
|
||||
0xa0,0x99,0x18,0xd5 == msr PMSEVFR_EL1, x0
|
||||
0xc0,0x99,0x18,0xd5 == msr PMSLATFR_EL1, x0
|
||||
0x00,0x9a,0x38,0xd5 == mrs x0, PMBLIMITR_EL1
|
||||
0x20,0x9a,0x38,0xd5 == mrs x0, PMBPTR_EL1
|
||||
0x60,0x9a,0x38,0xd5 == mrs x0, PMBSR_EL1
|
||||
0xe0,0x9a,0x38,0xd5 == mrs x0, PMBIDR_EL1
|
||||
0x00,0x99,0x3c,0xd5 == mrs x0, PMSCR_EL2
|
||||
0x00,0x99,0x3d,0xd5 == mrs x0, PMSCR_EL12
|
||||
0x00,0x99,0x38,0xd5 == mrs x0, PMSCR_EL1
|
||||
0x40,0x99,0x38,0xd5 == mrs x0, PMSICR_EL1
|
||||
0x60,0x99,0x38,0xd5 == mrs x0, PMSIRR_EL1
|
||||
0x80,0x99,0x38,0xd5 == mrs x0, PMSFCR_EL1
|
||||
0xa0,0x99,0x38,0xd5 == mrs x0, PMSEVFR_EL1
|
||||
0xc0,0x99,0x38,0xd5 == mrs x0, PMSLATFR_EL1
|
||||
0xe0,0x99,0x38,0xd5 == mrs x0, PMSIDR_EL1
|
||||
16
thirdparty/capstone/suite/MC/AArch64/armv8.2a-statistical-profiling.txt.cs
vendored
Normal file
16
thirdparty/capstone/suite/MC/AArch64/armv8.2a-statistical-profiling.txt.cs
vendored
Normal file
@@ -0,0 +1,16 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0x3f,0x22,0x03,0xd5 == psb csync
|
||||
0x00,0x9a,0x18,0xd5 == msr PMBLIMITR_EL1, x0
|
||||
0x20,0x9a,0x18,0xd5 == msr PMBPTR_EL1, x0
|
||||
0x60,0x9a,0x18,0xd5 == msr PMBSR_EL1, x0
|
||||
0xe0,0x9a,0x18,0xd5 == msr S3_0_C9_C10_7, x0
|
||||
0x00,0x99,0x1c,0xd5 == msr PMSCR_EL2, x0
|
||||
0x00,0x99,0x1d,0xd5 == msr PMSCR_EL12, x0
|
||||
0x00,0x99,0x18,0xd5 == msr PMSCR_EL1, x0
|
||||
0x40,0x99,0x18,0xd5 == msr PMSICR_EL1, x0
|
||||
0x60,0x99,0x18,0xd5 == msr PMSIRR_EL1, x0
|
||||
0x80,0x99,0x18,0xd5 == msr PMSFCR_EL1, x0
|
||||
0xa0,0x99,0x18,0xd5 == msr PMSEVFR_EL1, x0
|
||||
0xc0,0x99,0x18,0xd5 == msr PMSLATFR_EL1, x0
|
||||
0xe0,0x99,0x18,0xd5 == msr S3_0_C9_C9_7, x0
|
||||
6
thirdparty/capstone/suite/MC/AArch64/armv8.2a-uao.s.cs
vendored
Normal file
6
thirdparty/capstone/suite/MC/AArch64/armv8.2a-uao.s.cs
vendored
Normal file
@@ -0,0 +1,6 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0x7f,0x40,0x00,0xd5 == msr UAO, #0
|
||||
0x7f,0x41,0x00,0xd5 == msr UAO, #1
|
||||
0x81,0x42,0x18,0xd5 == msr UAO, x1
|
||||
0x82,0x42,0x38,0xd5 == mrs x2, UAO
|
||||
7
thirdparty/capstone/suite/MC/AArch64/armv8.2a-uao.txt.cs
vendored
Normal file
7
thirdparty/capstone/suite/MC/AArch64/armv8.2a-uao.txt.cs
vendored
Normal file
@@ -0,0 +1,7 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0x7f,0x40,0x00,0xd5 == msr UAO, #0
|
||||
0x7f,0x41,0x00,0xd5 == msr UAO, #1
|
||||
0x7f,0x4f,0x00,0xd5 == msr UAO, #15
|
||||
0x81,0x42,0x18,0xd5 == msr UAO, x1
|
||||
0x82,0x42,0x38,0xd5 == mrs x2, UAO
|
||||
3
thirdparty/capstone/suite/MC/AArch64/armv8.3a-ID_ISAR6_EL1.s.cs
vendored
Normal file
3
thirdparty/capstone/suite/MC/AArch64/armv8.3a-ID_ISAR6_EL1.s.cs
vendored
Normal file
@@ -0,0 +1,3 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0xe0,0x02,0x38,0xd5 == mrs x0, ID_ISAR6_EL1
|
||||
4
thirdparty/capstone/suite/MC/AArch64/armv8.3a-ID_ISAR6_EL1.txt.cs
vendored
Normal file
4
thirdparty/capstone/suite/MC/AArch64/armv8.3a-ID_ISAR6_EL1.txt.cs
vendored
Normal file
@@ -0,0 +1,4 @@
|
||||
# CS_ARCH_AARCH64, None, None
|
||||
# This regression test file is new. The option flags could not be determined.
|
||||
# LLVM uses the following mattr = ['mattr=+v8.3a']
|
||||
0xe0,0x02,0x38,0xd5 == mrs x0, ID_ISAR6_EL1
|
||||
27
thirdparty/capstone/suite/MC/AArch64/armv8.3a-complex.s.cs
vendored
Normal file
27
thirdparty/capstone/suite/MC/AArch64/armv8.3a-complex.s.cs
vendored
Normal file
@@ -0,0 +1,27 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0x20,0xc4,0x42,0x2e == fcmla v0.4h, v1.4h, v2.4h, #0
|
||||
0x20,0xc4,0x42,0x6e == fcmla v0.8h, v1.8h, v2.8h, #0
|
||||
0x20,0xc4,0x82,0x2e == fcmla v0.2s, v1.2s, v2.2s, #0
|
||||
0x20,0xc4,0x82,0x6e == fcmla v0.4s, v1.4s, v2.4s, #0
|
||||
0x20,0xc4,0xc2,0x6e == fcmla v0.2d, v1.2d, v2.2d, #0
|
||||
0x20,0xc4,0x82,0x2e == fcmla v0.2s, v1.2s, v2.2s, #0
|
||||
0x20,0xcc,0x82,0x2e == fcmla v0.2s, v1.2s, v2.2s, #90
|
||||
0x20,0xd4,0x82,0x2e == fcmla v0.2s, v1.2s, v2.2s, #180
|
||||
0x20,0xdc,0x82,0x2e == fcmla v0.2s, v1.2s, v2.2s, #270
|
||||
0x20,0xe4,0x42,0x2e == fcadd v0.4h, v1.4h, v2.4h, #90
|
||||
0x20,0xe4,0x42,0x6e == fcadd v0.8h, v1.8h, v2.8h, #90
|
||||
0x20,0xe4,0x82,0x2e == fcadd v0.2s, v1.2s, v2.2s, #90
|
||||
0x20,0xe4,0x82,0x6e == fcadd v0.4s, v1.4s, v2.4s, #90
|
||||
0x20,0xe4,0xc2,0x6e == fcadd v0.2d, v1.2d, v2.2d, #90
|
||||
0x20,0xe4,0x82,0x2e == fcadd v0.2s, v1.2s, v2.2s, #90
|
||||
0x20,0xf4,0x82,0x2e == fcadd v0.2s, v1.2s, v2.2s, #270
|
||||
0x20,0x10,0x42,0x2f == fcmla v0.4h, v1.4h, v2.h[0], #0
|
||||
0x20,0x10,0x42,0x6f == fcmla v0.8h, v1.8h, v2.h[0], #0
|
||||
0x20,0x10,0x82,0x6f == fcmla v0.4s, v1.4s, v2.s[0], #0
|
||||
0x20,0x30,0x82,0x6f == fcmla v0.4s, v1.4s, v2.s[0], #90
|
||||
0x20,0x50,0x82,0x6f == fcmla v0.4s, v1.4s, v2.s[0], #180
|
||||
0x20,0x70,0x82,0x6f == fcmla v0.4s, v1.4s, v2.s[0], #270
|
||||
0x20,0x10,0x62,0x2f == fcmla v0.4h, v1.4h, v2.h[1], #0
|
||||
0x20,0x18,0x62,0x6f == fcmla v0.8h, v1.8h, v2.h[3], #0
|
||||
0x20,0x18,0x82,0x6f == fcmla v0.4s, v1.4s, v2.s[1], #0
|
||||
27
thirdparty/capstone/suite/MC/AArch64/armv8.3a-complex.txt.cs
vendored
Normal file
27
thirdparty/capstone/suite/MC/AArch64/armv8.3a-complex.txt.cs
vendored
Normal file
@@ -0,0 +1,27 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0x20,0xc4,0x42,0x2e == fcmla v0.4h, v1.4h, v2.4h, #0
|
||||
0x20,0xc4,0x42,0x6e == fcmla v0.8h, v1.8h, v2.8h, #0
|
||||
0x20,0xc4,0x82,0x2e == fcmla v0.2s, v1.2s, v2.2s, #0
|
||||
0x20,0xc4,0x82,0x6e == fcmla v0.4s, v1.4s, v2.4s, #0
|
||||
0x20,0xc4,0xc2,0x6e == fcmla v0.2d, v1.2d, v2.2d, #0
|
||||
0x20,0xc4,0x82,0x2e == fcmla v0.2s, v1.2s, v2.2s, #0
|
||||
0x20,0xcc,0x82,0x2e == fcmla v0.2s, v1.2s, v2.2s, #90
|
||||
0x20,0xd4,0x82,0x2e == fcmla v0.2s, v1.2s, v2.2s, #180
|
||||
0x20,0xdc,0x82,0x2e == fcmla v0.2s, v1.2s, v2.2s, #270
|
||||
0x20,0xe4,0x42,0x2e == fcadd v0.4h, v1.4h, v2.4h, #90
|
||||
0x20,0xe4,0x42,0x6e == fcadd v0.8h, v1.8h, v2.8h, #90
|
||||
0x20,0xe4,0x82,0x2e == fcadd v0.2s, v1.2s, v2.2s, #90
|
||||
0x20,0xe4,0x82,0x6e == fcadd v0.4s, v1.4s, v2.4s, #90
|
||||
0x20,0xe4,0xc2,0x6e == fcadd v0.2d, v1.2d, v2.2d, #90
|
||||
0x20,0xe4,0x82,0x2e == fcadd v0.2s, v1.2s, v2.2s, #90
|
||||
0x20,0xf4,0x82,0x2e == fcadd v0.2s, v1.2s, v2.2s, #270
|
||||
0x20,0x10,0x42,0x2f == fcmla v0.4h, v1.4h, v2.h[0], #0
|
||||
0x20,0x10,0x42,0x6f == fcmla v0.8h, v1.8h, v2.h[0], #0
|
||||
0x20,0x10,0x82,0x6f == fcmla v0.4s, v1.4s, v2.s[0], #0
|
||||
0x20,0x30,0x82,0x6f == fcmla v0.4s, v1.4s, v2.s[0], #90
|
||||
0x20,0x50,0x82,0x6f == fcmla v0.4s, v1.4s, v2.s[0], #180
|
||||
0x20,0x70,0x82,0x6f == fcmla v0.4s, v1.4s, v2.s[0], #270
|
||||
0x20,0x10,0x62,0x2f == fcmla v0.4h, v1.4h, v2.h[1], #0
|
||||
0x20,0x18,0x62,0x6f == fcmla v0.8h, v1.8h, v2.h[3], #0
|
||||
0x20,0x18,0x82,0x6f == fcmla v0.4s, v1.4s, v2.s[1], #0
|
||||
19
thirdparty/capstone/suite/MC/AArch64/armv8.3a-complex_nofp16.s.cs
vendored
Normal file
19
thirdparty/capstone/suite/MC/AArch64/armv8.3a-complex_nofp16.s.cs
vendored
Normal file
@@ -0,0 +1,19 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0x20,0xc4,0x82,0x2e == fcmla v0.2s, v1.2s, v2.2s, #0
|
||||
0x20,0xc4,0x82,0x6e == fcmla v0.4s, v1.4s, v2.4s, #0
|
||||
0x20,0xc4,0xc2,0x6e == fcmla v0.2d, v1.2d, v2.2d, #0
|
||||
0x20,0xc4,0x82,0x2e == fcmla v0.2s, v1.2s, v2.2s, #0
|
||||
0x20,0xcc,0x82,0x2e == fcmla v0.2s, v1.2s, v2.2s, #90
|
||||
0x20,0xd4,0x82,0x2e == fcmla v0.2s, v1.2s, v2.2s, #180
|
||||
0x20,0xdc,0x82,0x2e == fcmla v0.2s, v1.2s, v2.2s, #270
|
||||
0x20,0xe4,0x82,0x2e == fcadd v0.2s, v1.2s, v2.2s, #90
|
||||
0x20,0xe4,0x82,0x6e == fcadd v0.4s, v1.4s, v2.4s, #90
|
||||
0x20,0xe4,0xc2,0x6e == fcadd v0.2d, v1.2d, v2.2d, #90
|
||||
0x20,0xe4,0x82,0x2e == fcadd v0.2s, v1.2s, v2.2s, #90
|
||||
0x20,0xf4,0x82,0x2e == fcadd v0.2s, v1.2s, v2.2s, #270
|
||||
0x20,0x10,0x82,0x6f == fcmla v0.4s, v1.4s, v2.s[0], #0
|
||||
0x20,0x30,0x82,0x6f == fcmla v0.4s, v1.4s, v2.s[0], #90
|
||||
0x20,0x50,0x82,0x6f == fcmla v0.4s, v1.4s, v2.s[0], #180
|
||||
0x20,0x70,0x82,0x6f == fcmla v0.4s, v1.4s, v2.s[0], #270
|
||||
0x20,0x18,0x82,0x6f == fcmla v0.4s, v1.4s, v2.s[1], #0
|
||||
3
thirdparty/capstone/suite/MC/AArch64/armv8.3a-js.s.cs
vendored
Normal file
3
thirdparty/capstone/suite/MC/AArch64/armv8.3a-js.s.cs
vendored
Normal file
@@ -0,0 +1,3 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0x00,0x00,0x7e,0x1e == fjcvtzs w0, d0
|
||||
3
thirdparty/capstone/suite/MC/AArch64/armv8.3a-js.txt.cs
vendored
Normal file
3
thirdparty/capstone/suite/MC/AArch64/armv8.3a-js.txt.cs
vendored
Normal file
@@ -0,0 +1,3 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0x00,0x00,0x7e,0x1e == fjcvtzs w0, d0
|
||||
3
thirdparty/capstone/suite/MC/AArch64/armv8.3a-pauth.s.cs
vendored
Normal file
3
thirdparty/capstone/suite/MC/AArch64/armv8.3a-pauth.s.cs
vendored
Normal file
@@ -0,0 +1,3 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0x3f,0x23,0x03,0xd5 == paciasp
|
||||
8
thirdparty/capstone/suite/MC/AArch64/armv8.3a-rcpc.s.cs
vendored
Normal file
8
thirdparty/capstone/suite/MC/AArch64/armv8.3a-rcpc.s.cs
vendored
Normal file
@@ -0,0 +1,8 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0x00,0xc0,0xbf,0x38 == ldaprb w0, [x0]
|
||||
0x20,0xc2,0xbf,0x78 == ldaprh w0, [x17]
|
||||
0x20,0xc0,0xbf,0xb8 == ldapr w0, [x1]
|
||||
0x00,0xc0,0xbf,0xf8 == ldapr x0, [x0]
|
||||
0x12,0xc0,0xbf,0xb8 == ldapr w18, [x0]
|
||||
0x0f,0xc0,0xbf,0xf8 == ldapr x15, [x0]
|
||||
6
thirdparty/capstone/suite/MC/AArch64/armv8.3a-rcpc.txt.cs
vendored
Normal file
6
thirdparty/capstone/suite/MC/AArch64/armv8.3a-rcpc.txt.cs
vendored
Normal file
@@ -0,0 +1,6 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0x00,0xc0,0xbf,0x38 == ldaprb w0, [x0]
|
||||
0x00,0xc0,0xbf,0x78 == ldaprh w0, [x0]
|
||||
0x00,0xc0,0xbf,0xb8 == ldapr w0, [x0]
|
||||
0x00,0xc0,0xbf,0xf8 == ldapr x0, [x0]
|
||||
93
thirdparty/capstone/suite/MC/AArch64/armv8.3a-signed-pointer.s.cs
vendored
Normal file
93
thirdparty/capstone/suite/MC/AArch64/armv8.3a-signed-pointer.s.cs
vendored
Normal file
@@ -0,0 +1,93 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0x00,0x21,0x38,0xd5 == mrs x0, APIAKeyLo_EL1
|
||||
0x20,0x21,0x38,0xd5 == mrs x0, APIAKeyHi_EL1
|
||||
0x40,0x21,0x38,0xd5 == mrs x0, APIBKeyLo_EL1
|
||||
0x60,0x21,0x38,0xd5 == mrs x0, APIBKeyHi_EL1
|
||||
0x00,0x22,0x38,0xd5 == mrs x0, APDAKeyLo_EL1
|
||||
0x20,0x22,0x38,0xd5 == mrs x0, APDAKeyHi_EL1
|
||||
0x40,0x22,0x38,0xd5 == mrs x0, APDBKeyLo_EL1
|
||||
0x60,0x22,0x38,0xd5 == mrs x0, APDBKeyHi_EL1
|
||||
0x00,0x23,0x38,0xd5 == mrs x0, APGAKeyLo_EL1
|
||||
0x20,0x23,0x38,0xd5 == mrs x0, APGAKeyHi_EL1
|
||||
0x00,0x21,0x18,0xd5 == msr APIAKeyLo_EL1, x0
|
||||
0x20,0x21,0x18,0xd5 == msr APIAKeyHi_EL1, x0
|
||||
0x40,0x21,0x18,0xd5 == msr APIBKeyLo_EL1, x0
|
||||
0x60,0x21,0x18,0xd5 == msr APIBKeyHi_EL1, x0
|
||||
0x00,0x22,0x18,0xd5 == msr APDAKeyLo_EL1, x0
|
||||
0x20,0x22,0x18,0xd5 == msr APDAKeyHi_EL1, x0
|
||||
0x40,0x22,0x18,0xd5 == msr APDBKeyLo_EL1, x0
|
||||
0x60,0x22,0x18,0xd5 == msr APDBKeyHi_EL1, x0
|
||||
0x00,0x23,0x18,0xd5 == msr APGAKeyLo_EL1, x0
|
||||
0x20,0x23,0x18,0xd5 == msr APGAKeyHi_EL1, x0
|
||||
0xff,0x20,0x03,0xd5 == xpaclri
|
||||
0xff,0x20,0x03,0xd5 == xpaclri
|
||||
0x1f,0x21,0x03,0xd5 == pacia1716
|
||||
0x1f,0x21,0x03,0xd5 == pacia1716
|
||||
0x5f,0x21,0x03,0xd5 == pacib1716
|
||||
0x5f,0x21,0x03,0xd5 == pacib1716
|
||||
0x9f,0x21,0x03,0xd5 == autia1716
|
||||
0x9f,0x21,0x03,0xd5 == autia1716
|
||||
0xdf,0x21,0x03,0xd5 == autib1716
|
||||
0xdf,0x21,0x03,0xd5 == autib1716
|
||||
0x1f,0x23,0x03,0xd5 == paciaz
|
||||
0x1f,0x23,0x03,0xd5 == paciaz
|
||||
0x3f,0x23,0x03,0xd5 == paciasp
|
||||
0x3f,0x23,0x03,0xd5 == paciasp
|
||||
0x5f,0x23,0x03,0xd5 == pacibz
|
||||
0x5f,0x23,0x03,0xd5 == pacibz
|
||||
0x7f,0x23,0x03,0xd5 == pacibsp
|
||||
0x7f,0x23,0x03,0xd5 == pacibsp
|
||||
0x9f,0x23,0x03,0xd5 == autiaz
|
||||
0x9f,0x23,0x03,0xd5 == autiaz
|
||||
0xbf,0x23,0x03,0xd5 == autiasp
|
||||
0xbf,0x23,0x03,0xd5 == autiasp
|
||||
0xdf,0x23,0x03,0xd5 == autibz
|
||||
0xdf,0x23,0x03,0xd5 == autibz
|
||||
0xff,0x23,0x03,0xd5 == autibsp
|
||||
0xff,0x23,0x03,0xd5 == autibsp
|
||||
0x20,0x00,0xc1,0xda == pacia x0, x1
|
||||
0x20,0x10,0xc1,0xda == autia x0, x1
|
||||
0x20,0x08,0xc1,0xda == pacda x0, x1
|
||||
0x20,0x18,0xc1,0xda == autda x0, x1
|
||||
0x20,0x04,0xc1,0xda == pacib x0, x1
|
||||
0x20,0x14,0xc1,0xda == autib x0, x1
|
||||
0x20,0x0c,0xc1,0xda == pacdb x0, x1
|
||||
0x20,0x1c,0xc1,0xda == autdb x0, x1
|
||||
0x20,0x30,0xc2,0x9a == pacga x0, x1, x2
|
||||
0xe0,0x23,0xc1,0xda == paciza x0
|
||||
0xe0,0x33,0xc1,0xda == autiza x0
|
||||
0xe0,0x2b,0xc1,0xda == pacdza x0
|
||||
0xe0,0x3b,0xc1,0xda == autdza x0
|
||||
0xe0,0x27,0xc1,0xda == pacizb x0
|
||||
0xe0,0x37,0xc1,0xda == autizb x0
|
||||
0xe0,0x2f,0xc1,0xda == pacdzb x0
|
||||
0xe0,0x3f,0xc1,0xda == autdzb x0
|
||||
0xe0,0x43,0xc1,0xda == xpaci x0
|
||||
0xe0,0x47,0xc1,0xda == xpacd x0
|
||||
0x01,0x08,0x1f,0xd7 == braa x0, x1
|
||||
0x01,0x0c,0x1f,0xd7 == brab x0, x1
|
||||
0x01,0x08,0x3f,0xd7 == blraa x0, x1
|
||||
0x01,0x0c,0x3f,0xd7 == blrab x0, x1
|
||||
0x1f,0x08,0x1f,0xd6 == braaz x0
|
||||
0x1f,0x0c,0x1f,0xd6 == brabz x0
|
||||
0x1f,0x08,0x3f,0xd6 == blraaz x0
|
||||
0x1f,0x0c,0x3f,0xd6 == blrabz x0
|
||||
0xff,0x0b,0x5f,0xd6 == retaa
|
||||
0xff,0x0f,0x5f,0xd6 == retab
|
||||
0xff,0x0b,0x9f,0xd6 == eretaa
|
||||
0xff,0x0f,0x9f,0xd6 == eretab
|
||||
0x20,0xf4,0x3f,0xf8 == ldraa x0, [x1, #4088]
|
||||
0x20,0x04,0x60,0xf8 == ldraa x0, [x1, #-4096]
|
||||
0x20,0xf4,0xbf,0xf8 == ldrab x0, [x1, #4088]
|
||||
0x20,0x04,0xe0,0xf8 == ldrab x0, [x1, #-4096]
|
||||
0x20,0xfc,0x3f,0xf8 == ldraa x0, [x1, #4088]!
|
||||
0x20,0x0c,0x60,0xf8 == ldraa x0, [x1, #-4096]!
|
||||
0x20,0xfc,0xbf,0xf8 == ldrab x0, [x1, #4088]!
|
||||
0x20,0x0c,0xe0,0xf8 == ldrab x0, [x1, #-4096]!
|
||||
0x20,0x04,0x20,0xf8 == ldraa x0, [x1]
|
||||
0x20,0x04,0xa0,0xf8 == ldrab x0, [x1]
|
||||
0x20,0x0c,0x20,0xf8 == ldraa x0, [x1, #0]!
|
||||
0x20,0x0c,0xa0,0xf8 == ldrab x0, [x1, #0]!
|
||||
0xff,0x0f,0x60,0xf8 == ldraa xzr, [sp, #-4096]!
|
||||
0xff,0x0f,0xe0,0xf8 == ldrab xzr, [sp, #-4096]!
|
||||
60
thirdparty/capstone/suite/MC/AArch64/armv8.3a-signed-pointer.txt.cs
vendored
Normal file
60
thirdparty/capstone/suite/MC/AArch64/armv8.3a-signed-pointer.txt.cs
vendored
Normal file
@@ -0,0 +1,60 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0x00,0x0c,0x20,0xf8 == ldraa x0, [x0, #0]!
|
||||
0x00,0x0c,0xa0,0xf8 == ldrab x0, [x0, #0]!
|
||||
0x3f,0x23,0x03,0xd5 == paciasp
|
||||
0xbf,0x23,0x03,0xd5 == autiasp
|
||||
0x1f,0x23,0x03,0xd5 == paciaz
|
||||
0x9f,0x23,0x03,0xd5 == autiaz
|
||||
0x1f,0x21,0x03,0xd5 == pacia1716
|
||||
0x9f,0x21,0x03,0xd5 == autia1716
|
||||
0x7f,0x23,0x03,0xd5 == pacibsp
|
||||
0xff,0x23,0x03,0xd5 == autibsp
|
||||
0x5f,0x23,0x03,0xd5 == pacibz
|
||||
0xdf,0x23,0x03,0xd5 == autibz
|
||||
0x5f,0x21,0x03,0xd5 == pacib1716
|
||||
0xdf,0x21,0x03,0xd5 == autib1716
|
||||
0xff,0x20,0x03,0xd5 == xpaclri
|
||||
0x20,0x00,0xc1,0xda == pacia x0, x1
|
||||
0x20,0x10,0xc1,0xda == autia x0, x1
|
||||
0x20,0x08,0xc1,0xda == pacda x0, x1
|
||||
0x20,0x18,0xc1,0xda == autda x0, x1
|
||||
0x20,0x04,0xc1,0xda == pacib x0, x1
|
||||
0x20,0x14,0xc1,0xda == autib x0, x1
|
||||
0x20,0x0c,0xc1,0xda == pacdb x0, x1
|
||||
0x20,0x1c,0xc1,0xda == autdb x0, x1
|
||||
0x20,0x30,0xc2,0x9a == pacga x0, x1, x2
|
||||
0xe0,0x23,0xc1,0xda == paciza x0
|
||||
0xe0,0x33,0xc1,0xda == autiza x0
|
||||
0xe0,0x2b,0xc1,0xda == pacdza x0
|
||||
0xe0,0x3b,0xc1,0xda == autdza x0
|
||||
0xe0,0x27,0xc1,0xda == pacizb x0
|
||||
0xe0,0x37,0xc1,0xda == autizb x0
|
||||
0xe0,0x2f,0xc1,0xda == pacdzb x0
|
||||
0xe0,0x3f,0xc1,0xda == autdzb x0
|
||||
0xe0,0x43,0xc1,0xda == xpaci x0
|
||||
0xe0,0x47,0xc1,0xda == xpacd x0
|
||||
0x01,0x08,0x1f,0xd7 == braa x0, x1
|
||||
0x01,0x0c,0x1f,0xd7 == brab x0, x1
|
||||
0x01,0x08,0x3f,0xd7 == blraa x0, x1
|
||||
0x01,0x0c,0x3f,0xd7 == blrab x0, x1
|
||||
0x1f,0x08,0x1f,0xd6 == braaz x0
|
||||
0x1f,0x0c,0x1f,0xd6 == brabz x0
|
||||
0x1f,0x08,0x3f,0xd6 == blraaz x0
|
||||
0x1f,0x0c,0x3f,0xd6 == blrabz x0
|
||||
0xff,0x0b,0x5f,0xd6 == retaa
|
||||
0xff,0x0f,0x5f,0xd6 == retab
|
||||
0xff,0x0b,0x9f,0xd6 == eretaa
|
||||
0xff,0x0f,0x9f,0xd6 == eretab
|
||||
0x20,0xf4,0x3f,0xf8 == ldraa x0, [x1, #4088]
|
||||
0x20,0x04,0x60,0xf8 == ldraa x0, [x1, #-4096]
|
||||
0x20,0xf4,0xbf,0xf8 == ldrab x0, [x1, #4088]
|
||||
0x20,0x04,0xe0,0xf8 == ldrab x0, [x1, #-4096]
|
||||
0x20,0xfc,0x3f,0xf8 == ldraa x0, [x1, #4088]!
|
||||
0x20,0x0c,0x60,0xf8 == ldraa x0, [x1, #-4096]!
|
||||
0x20,0xfc,0xbf,0xf8 == ldrab x0, [x1, #4088]!
|
||||
0x20,0x0c,0xe0,0xf8 == ldrab x0, [x1, #-4096]!
|
||||
0x20,0x04,0x20,0xf8 == ldraa x0, [x1]
|
||||
0x20,0x04,0xa0,0xf8 == ldrab x0, [x1]
|
||||
0x20,0x0c,0x20,0xf8 == ldraa x0, [x1, #0]!
|
||||
0x20,0x0c,0xa0,0xf8 == ldrab x0, [x1, #0]!
|
||||
92
thirdparty/capstone/suite/MC/AArch64/armv8.4a-actmon.s.cs
vendored
Normal file
92
thirdparty/capstone/suite/MC/AArch64/armv8.4a-actmon.s.cs
vendored
Normal file
@@ -0,0 +1,92 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0x00,0xd2,0x1b,0xd5 == msr AMCR_EL0, x0
|
||||
0x60,0xd2,0x1b,0xd5 == msr AMUSERENR_EL0, x0
|
||||
0x80,0xd2,0x1b,0xd5 == msr AMCNTENCLR0_EL0, x0
|
||||
0xa0,0xd2,0x1b,0xd5 == msr AMCNTENSET0_EL0, x0
|
||||
0x00,0xd4,0x1b,0xd5 == msr AMEVCNTR00_EL0, x0
|
||||
0x20,0xd4,0x1b,0xd5 == msr AMEVCNTR01_EL0, x0
|
||||
0x40,0xd4,0x1b,0xd5 == msr AMEVCNTR02_EL0, x0
|
||||
0x60,0xd4,0x1b,0xd5 == msr AMEVCNTR03_EL0, x0
|
||||
0x00,0xd3,0x1b,0xd5 == msr AMCNTENCLR1_EL0, x0
|
||||
0x20,0xd3,0x1b,0xd5 == msr AMCNTENSET1_EL0, x0
|
||||
0x00,0xdc,0x1b,0xd5 == msr AMEVCNTR10_EL0, x0
|
||||
0x20,0xdc,0x1b,0xd5 == msr AMEVCNTR11_EL0, x0
|
||||
0x40,0xdc,0x1b,0xd5 == msr AMEVCNTR12_EL0, x0
|
||||
0x60,0xdc,0x1b,0xd5 == msr AMEVCNTR13_EL0, x0
|
||||
0x80,0xdc,0x1b,0xd5 == msr AMEVCNTR14_EL0, x0
|
||||
0xa0,0xdc,0x1b,0xd5 == msr AMEVCNTR15_EL0, x0
|
||||
0xc0,0xdc,0x1b,0xd5 == msr AMEVCNTR16_EL0, x0
|
||||
0xe0,0xdc,0x1b,0xd5 == msr AMEVCNTR17_EL0, x0
|
||||
0x00,0xdd,0x1b,0xd5 == msr AMEVCNTR18_EL0, x0
|
||||
0x20,0xdd,0x1b,0xd5 == msr AMEVCNTR19_EL0, x0
|
||||
0x40,0xdd,0x1b,0xd5 == msr AMEVCNTR110_EL0, x0
|
||||
0x60,0xdd,0x1b,0xd5 == msr AMEVCNTR111_EL0, x0
|
||||
0x80,0xdd,0x1b,0xd5 == msr AMEVCNTR112_EL0, x0
|
||||
0xa0,0xdd,0x1b,0xd5 == msr AMEVCNTR113_EL0, x0
|
||||
0xc0,0xdd,0x1b,0xd5 == msr AMEVCNTR114_EL0, x0
|
||||
0xe0,0xdd,0x1b,0xd5 == msr AMEVCNTR115_EL0, x0
|
||||
0x00,0xde,0x1b,0xd5 == msr AMEVTYPER10_EL0, x0
|
||||
0x20,0xde,0x1b,0xd5 == msr AMEVTYPER11_EL0, x0
|
||||
0x40,0xde,0x1b,0xd5 == msr AMEVTYPER12_EL0, x0
|
||||
0x60,0xde,0x1b,0xd5 == msr AMEVTYPER13_EL0, x0
|
||||
0x80,0xde,0x1b,0xd5 == msr AMEVTYPER14_EL0, x0
|
||||
0xa0,0xde,0x1b,0xd5 == msr AMEVTYPER15_EL0, x0
|
||||
0xc0,0xde,0x1b,0xd5 == msr AMEVTYPER16_EL0, x0
|
||||
0xe0,0xde,0x1b,0xd5 == msr AMEVTYPER17_EL0, x0
|
||||
0x00,0xdf,0x1b,0xd5 == msr AMEVTYPER18_EL0, x0
|
||||
0x20,0xdf,0x1b,0xd5 == msr AMEVTYPER19_EL0, x0
|
||||
0x40,0xdf,0x1b,0xd5 == msr AMEVTYPER110_EL0, x0
|
||||
0x60,0xdf,0x1b,0xd5 == msr AMEVTYPER111_EL0, x0
|
||||
0x80,0xdf,0x1b,0xd5 == msr AMEVTYPER112_EL0, x0
|
||||
0xa0,0xdf,0x1b,0xd5 == msr AMEVTYPER113_EL0, x0
|
||||
0xc0,0xdf,0x1b,0xd5 == msr AMEVTYPER114_EL0, x0
|
||||
0xe0,0xdf,0x1b,0xd5 == msr AMEVTYPER115_EL0, x0
|
||||
0x00,0xd2,0x3b,0xd5 == mrs x0, AMCR_EL0
|
||||
0x20,0xd2,0x3b,0xd5 == mrs x0, AMCFGR_EL0
|
||||
0x40,0xd2,0x3b,0xd5 == mrs x0, AMCGCR_EL0
|
||||
0x60,0xd2,0x3b,0xd5 == mrs x0, AMUSERENR_EL0
|
||||
0x80,0xd2,0x3b,0xd5 == mrs x0, AMCNTENCLR0_EL0
|
||||
0xa0,0xd2,0x3b,0xd5 == mrs x0, AMCNTENSET0_EL0
|
||||
0x00,0xd4,0x3b,0xd5 == mrs x0, AMEVCNTR00_EL0
|
||||
0x20,0xd4,0x3b,0xd5 == mrs x0, AMEVCNTR01_EL0
|
||||
0x40,0xd4,0x3b,0xd5 == mrs x0, AMEVCNTR02_EL0
|
||||
0x60,0xd4,0x3b,0xd5 == mrs x0, AMEVCNTR03_EL0
|
||||
0x00,0xd6,0x3b,0xd5 == mrs x0, AMEVTYPER00_EL0
|
||||
0x20,0xd6,0x3b,0xd5 == mrs x0, AMEVTYPER01_EL0
|
||||
0x40,0xd6,0x3b,0xd5 == mrs x0, AMEVTYPER02_EL0
|
||||
0x60,0xd6,0x3b,0xd5 == mrs x0, AMEVTYPER03_EL0
|
||||
0x00,0xd3,0x3b,0xd5 == mrs x0, AMCNTENCLR1_EL0
|
||||
0x20,0xd3,0x3b,0xd5 == mrs x0, AMCNTENSET1_EL0
|
||||
0x00,0xdc,0x3b,0xd5 == mrs x0, AMEVCNTR10_EL0
|
||||
0x20,0xdc,0x3b,0xd5 == mrs x0, AMEVCNTR11_EL0
|
||||
0x40,0xdc,0x3b,0xd5 == mrs x0, AMEVCNTR12_EL0
|
||||
0x60,0xdc,0x3b,0xd5 == mrs x0, AMEVCNTR13_EL0
|
||||
0x80,0xdc,0x3b,0xd5 == mrs x0, AMEVCNTR14_EL0
|
||||
0xa0,0xdc,0x3b,0xd5 == mrs x0, AMEVCNTR15_EL0
|
||||
0xc0,0xdc,0x3b,0xd5 == mrs x0, AMEVCNTR16_EL0
|
||||
0xe0,0xdc,0x3b,0xd5 == mrs x0, AMEVCNTR17_EL0
|
||||
0x00,0xdd,0x3b,0xd5 == mrs x0, AMEVCNTR18_EL0
|
||||
0x20,0xdd,0x3b,0xd5 == mrs x0, AMEVCNTR19_EL0
|
||||
0x40,0xdd,0x3b,0xd5 == mrs x0, AMEVCNTR110_EL0
|
||||
0x60,0xdd,0x3b,0xd5 == mrs x0, AMEVCNTR111_EL0
|
||||
0x80,0xdd,0x3b,0xd5 == mrs x0, AMEVCNTR112_EL0
|
||||
0xa0,0xdd,0x3b,0xd5 == mrs x0, AMEVCNTR113_EL0
|
||||
0xc0,0xdd,0x3b,0xd5 == mrs x0, AMEVCNTR114_EL0
|
||||
0xe0,0xdd,0x3b,0xd5 == mrs x0, AMEVCNTR115_EL0
|
||||
0x00,0xde,0x3b,0xd5 == mrs x0, AMEVTYPER10_EL0
|
||||
0x20,0xde,0x3b,0xd5 == mrs x0, AMEVTYPER11_EL0
|
||||
0x40,0xde,0x3b,0xd5 == mrs x0, AMEVTYPER12_EL0
|
||||
0x60,0xde,0x3b,0xd5 == mrs x0, AMEVTYPER13_EL0
|
||||
0x80,0xde,0x3b,0xd5 == mrs x0, AMEVTYPER14_EL0
|
||||
0xa0,0xde,0x3b,0xd5 == mrs x0, AMEVTYPER15_EL0
|
||||
0xc0,0xde,0x3b,0xd5 == mrs x0, AMEVTYPER16_EL0
|
||||
0xe0,0xde,0x3b,0xd5 == mrs x0, AMEVTYPER17_EL0
|
||||
0x00,0xdf,0x3b,0xd5 == mrs x0, AMEVTYPER18_EL0
|
||||
0x20,0xdf,0x3b,0xd5 == mrs x0, AMEVTYPER19_EL0
|
||||
0x40,0xdf,0x3b,0xd5 == mrs x0, AMEVTYPER110_EL0
|
||||
0x60,0xdf,0x3b,0xd5 == mrs x0, AMEVTYPER111_EL0
|
||||
0x80,0xdf,0x3b,0xd5 == mrs x0, AMEVTYPER112_EL0
|
||||
0xa0,0xdf,0x3b,0xd5 == mrs x0, AMEVTYPER113_EL0
|
||||
0xc0,0xdf,0x3b,0xd5 == mrs x0, AMEVTYPER114_EL0
|
||||
0xe0,0xdf,0x3b,0xd5 == mrs x0, AMEVTYPER115_EL0
|
||||
91
thirdparty/capstone/suite/MC/AArch64/armv8.4a-actmon.txt.cs
vendored
Normal file
91
thirdparty/capstone/suite/MC/AArch64/armv8.4a-actmon.txt.cs
vendored
Normal file
@@ -0,0 +1,91 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
0x00,0xd2,0x1b,0xd5 = msr AMCR_EL0, x0
|
||||
0x60,0xd2,0x1b,0xd5 = msr AMUSERENR_EL0, x0
|
||||
0x80,0xd2,0x1b,0xd5 = msr AMCNTENCLR0_EL0, x0
|
||||
0xa0,0xd2,0x1b,0xd5 = msr AMCNTENSET0_EL0, x0
|
||||
0x00,0xd4,0x1b,0xd5 = msr AMEVCNTR00_EL0, x0
|
||||
0x20,0xd4,0x1b,0xd5 = msr AMEVCNTR01_EL0, x0
|
||||
0x40,0xd4,0x1b,0xd5 = msr AMEVCNTR02_EL0, x0
|
||||
0x60,0xd4,0x1b,0xd5 = msr AMEVCNTR03_EL0, x0
|
||||
0x00,0xd3,0x1b,0xd5 = msr AMCNTENCLR1_EL0, x0
|
||||
0x20,0xd3,0x1b,0xd5 = msr AMCNTENSET1_EL0, x0
|
||||
0x00,0xdc,0x1b,0xd5 = msr AMEVCNTR10_EL0, x0
|
||||
0x20,0xdc,0x1b,0xd5 = msr AMEVCNTR11_EL0, x0
|
||||
0x40,0xdc,0x1b,0xd5 = msr AMEVCNTR12_EL0, x0
|
||||
0x60,0xdc,0x1b,0xd5 = msr AMEVCNTR13_EL0, x0
|
||||
0x80,0xdc,0x1b,0xd5 = msr AMEVCNTR14_EL0, x0
|
||||
0xa0,0xdc,0x1b,0xd5 = msr AMEVCNTR15_EL0, x0
|
||||
0xc0,0xdc,0x1b,0xd5 = msr AMEVCNTR16_EL0, x0
|
||||
0xe0,0xdc,0x1b,0xd5 = msr AMEVCNTR17_EL0, x0
|
||||
0x00,0xdd,0x1b,0xd5 = msr AMEVCNTR18_EL0, x0
|
||||
0x20,0xdd,0x1b,0xd5 = msr AMEVCNTR19_EL0, x0
|
||||
0x40,0xdd,0x1b,0xd5 = msr AMEVCNTR110_EL0, x0
|
||||
0x60,0xdd,0x1b,0xd5 = msr AMEVCNTR111_EL0, x0
|
||||
0x80,0xdd,0x1b,0xd5 = msr AMEVCNTR112_EL0, x0
|
||||
0xa0,0xdd,0x1b,0xd5 = msr AMEVCNTR113_EL0, x0
|
||||
0xc0,0xdd,0x1b,0xd5 = msr AMEVCNTR114_EL0, x0
|
||||
0xe0,0xdd,0x1b,0xd5 = msr AMEVCNTR115_EL0, x0
|
||||
0x00,0xde,0x1b,0xd5 = msr AMEVTYPER10_EL0, x0
|
||||
0x20,0xde,0x1b,0xd5 = msr AMEVTYPER11_EL0, x0
|
||||
0x40,0xde,0x1b,0xd5 = msr AMEVTYPER12_EL0, x0
|
||||
0x60,0xde,0x1b,0xd5 = msr AMEVTYPER13_EL0, x0
|
||||
0x80,0xde,0x1b,0xd5 = msr AMEVTYPER14_EL0, x0
|
||||
0xa0,0xde,0x1b,0xd5 = msr AMEVTYPER15_EL0, x0
|
||||
0xc0,0xde,0x1b,0xd5 = msr AMEVTYPER16_EL0, x0
|
||||
0xe0,0xde,0x1b,0xd5 = msr AMEVTYPER17_EL0, x0
|
||||
0x00,0xdf,0x1b,0xd5 = msr AMEVTYPER18_EL0, x0
|
||||
0x20,0xdf,0x1b,0xd5 = msr AMEVTYPER19_EL0, x0
|
||||
0x40,0xdf,0x1b,0xd5 = msr AMEVTYPER110_EL0, x0
|
||||
0x60,0xdf,0x1b,0xd5 = msr AMEVTYPER111_EL0, x0
|
||||
0x80,0xdf,0x1b,0xd5 = msr AMEVTYPER112_EL0, x0
|
||||
0xa0,0xdf,0x1b,0xd5 = msr AMEVTYPER113_EL0, x0
|
||||
0xc0,0xdf,0x1b,0xd5 = msr AMEVTYPER114_EL0, x0
|
||||
0xe0,0xdf,0x1b,0xd5 = msr AMEVTYPER115_EL0, x0
|
||||
0x00,0xd2,0x3b,0xd5 = mrs x0, AMCR_EL0
|
||||
0x20,0xd2,0x3b,0xd5 = mrs x0, AMCFGR_EL0
|
||||
0x40,0xd2,0x3b,0xd5 = mrs x0, AMCGCR_EL0
|
||||
0x60,0xd2,0x3b,0xd5 = mrs x0, AMUSERENR_EL0
|
||||
0x80,0xd2,0x3b,0xd5 = mrs x0, AMCNTENCLR0_EL0
|
||||
0xa0,0xd2,0x3b,0xd5 = mrs x0, AMCNTENSET0_EL0
|
||||
0x00,0xd4,0x3b,0xd5 = mrs x0, AMEVCNTR00_EL0
|
||||
0x20,0xd4,0x3b,0xd5 = mrs x0, AMEVCNTR01_EL0
|
||||
0x40,0xd4,0x3b,0xd5 = mrs x0, AMEVCNTR02_EL0
|
||||
0x60,0xd4,0x3b,0xd5 = mrs x0, AMEVCNTR03_EL0
|
||||
0x00,0xd6,0x3b,0xd5 = mrs x0, AMEVTYPER00_EL0
|
||||
0x20,0xd6,0x3b,0xd5 = mrs x0, AMEVTYPER01_EL0
|
||||
0x40,0xd6,0x3b,0xd5 = mrs x0, AMEVTYPER02_EL0
|
||||
0x60,0xd6,0x3b,0xd5 = mrs x0, AMEVTYPER03_EL0
|
||||
0x00,0xd3,0x3b,0xd5 = mrs x0, AMCNTENCLR1_EL0
|
||||
0x20,0xd3,0x3b,0xd5 = mrs x0, AMCNTENSET1_EL0
|
||||
0x00,0xdc,0x3b,0xd5 = mrs x0, AMEVCNTR10_EL0
|
||||
0x20,0xdc,0x3b,0xd5 = mrs x0, AMEVCNTR11_EL0
|
||||
0x40,0xdc,0x3b,0xd5 = mrs x0, AMEVCNTR12_EL0
|
||||
0x60,0xdc,0x3b,0xd5 = mrs x0, AMEVCNTR13_EL0
|
||||
0x80,0xdc,0x3b,0xd5 = mrs x0, AMEVCNTR14_EL0
|
||||
0xa0,0xdc,0x3b,0xd5 = mrs x0, AMEVCNTR15_EL0
|
||||
0xc0,0xdc,0x3b,0xd5 = mrs x0, AMEVCNTR16_EL0
|
||||
0xe0,0xdc,0x3b,0xd5 = mrs x0, AMEVCNTR17_EL0
|
||||
0x00,0xdd,0x3b,0xd5 = mrs x0, AMEVCNTR18_EL0
|
||||
0x20,0xdd,0x3b,0xd5 = mrs x0, AMEVCNTR19_EL0
|
||||
0x40,0xdd,0x3b,0xd5 = mrs x0, AMEVCNTR110_EL0
|
||||
0x60,0xdd,0x3b,0xd5 = mrs x0, AMEVCNTR111_EL0
|
||||
0x80,0xdd,0x3b,0xd5 = mrs x0, AMEVCNTR112_EL0
|
||||
0xa0,0xdd,0x3b,0xd5 = mrs x0, AMEVCNTR113_EL0
|
||||
0xc0,0xdd,0x3b,0xd5 = mrs x0, AMEVCNTR114_EL0
|
||||
0xe0,0xdd,0x3b,0xd5 = mrs x0, AMEVCNTR115_EL0
|
||||
0x00,0xde,0x3b,0xd5 = mrs x0, AMEVTYPER10_EL0
|
||||
0x20,0xde,0x3b,0xd5 = mrs x0, AMEVTYPER11_EL0
|
||||
0x40,0xde,0x3b,0xd5 = mrs x0, AMEVTYPER12_EL0
|
||||
0x60,0xde,0x3b,0xd5 = mrs x0, AMEVTYPER13_EL0
|
||||
0x80,0xde,0x3b,0xd5 = mrs x0, AMEVTYPER14_EL0
|
||||
0xa0,0xde,0x3b,0xd5 = mrs x0, AMEVTYPER15_EL0
|
||||
0xc0,0xde,0x3b,0xd5 = mrs x0, AMEVTYPER16_EL0
|
||||
0xe0,0xde,0x3b,0xd5 = mrs x0, AMEVTYPER17_EL0
|
||||
0x00,0xdf,0x3b,0xd5 = mrs x0, AMEVTYPER18_EL0
|
||||
0x20,0xdf,0x3b,0xd5 = mrs x0, AMEVTYPER19_EL0
|
||||
0x40,0xdf,0x3b,0xd5 = mrs x0, AMEVTYPER110_EL0
|
||||
0x60,0xdf,0x3b,0xd5 = mrs x0, AMEVTYPER111_EL0
|
||||
0x80,0xdf,0x3b,0xd5 = mrs x0, AMEVTYPER112_EL0
|
||||
0xa0,0xdf,0x3b,0xd5 = mrs x0, AMEVTYPER113_EL0
|
||||
0xc0,0xdf,0x3b,0xd5 = mrs x0, AMEVTYPER114_EL0
|
||||
0xe0,0xdf,0x3b,0xd5 = mrs x0, AMEVTYPER115_EL0
|
||||
5
thirdparty/capstone/suite/MC/AArch64/armv8.4a-dit.s.cs
vendored
Normal file
5
thirdparty/capstone/suite/MC/AArch64/armv8.4a-dit.s.cs
vendored
Normal file
@@ -0,0 +1,5 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0x5f,0x41,0x03,0xd5 == msr DIT, #1
|
||||
0xa0,0x42,0x1b,0xd5 == msr DIT, x0
|
||||
0xa0,0x42,0x3b,0xd5 == mrs x0, DIT
|
||||
4
thirdparty/capstone/suite/MC/AArch64/armv8.4a-dit.txt.cs
vendored
Normal file
4
thirdparty/capstone/suite/MC/AArch64/armv8.4a-dit.txt.cs
vendored
Normal file
@@ -0,0 +1,4 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
0x5f,0x41,0x03,0xd5 = msr DIT, #1
|
||||
0xa0,0x42,0x1b,0xd5 = msr DIT, x0
|
||||
0xa0,0x42,0x3b,0xd5 = mrs x0, DIT
|
||||
9
thirdparty/capstone/suite/MC/AArch64/armv8.4a-flag.s.cs
vendored
Normal file
9
thirdparty/capstone/suite/MC/AArch64/armv8.4a-flag.s.cs
vendored
Normal file
@@ -0,0 +1,9 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0x1f,0x40,0x00,0xd5 == cfinv
|
||||
0x2d,0x08,0x00,0x3a == setf8 w1
|
||||
0xed,0x0b,0x00,0x3a == setf8 wzr
|
||||
0x2d,0x48,0x00,0x3a == setf16 w1
|
||||
0xed,0x4b,0x00,0x3a == setf16 wzr
|
||||
0x2f,0x84,0x1f,0xba == rmif x1, #63, #15
|
||||
0xef,0x87,0x1f,0xba == rmif xzr, #63, #15
|
||||
5
thirdparty/capstone/suite/MC/AArch64/armv8.4a-flag.txt.cs
vendored
Normal file
5
thirdparty/capstone/suite/MC/AArch64/armv8.4a-flag.txt.cs
vendored
Normal file
@@ -0,0 +1,5 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
0x1f,0x40,0x00,0xd5 = cfinv
|
||||
0x2d,0x08,0x00,0x3a = setf8 w1
|
||||
0x2d,0x48,0x00,0x3a = setf16 w1
|
||||
0x2f,0x84,0x1f,0xba = rmif x1, #63, #15
|
||||
2
thirdparty/capstone/suite/MC/AArch64/armv8.4a-flagm.s.cs
vendored
Normal file
2
thirdparty/capstone/suite/MC/AArch64/armv8.4a-flagm.s.cs
vendored
Normal file
@@ -0,0 +1,2 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
0x1f,0x40,0x00,0xd5 = cfinv
|
||||
56
thirdparty/capstone/suite/MC/AArch64/armv8.4a-ldst.s.cs
vendored
Normal file
56
thirdparty/capstone/suite/MC/AArch64/armv8.4a-ldst.s.cs
vendored
Normal file
@@ -0,0 +1,56 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0x41,0x01,0x00,0x19 == stlurb w1, [x10]
|
||||
0x41,0x01,0x10,0x19 == stlurb w1, [x10, #-256]
|
||||
0x62,0xf1,0x0f,0x19 == stlurb w2, [x11, #255]
|
||||
0xe3,0xd3,0x1f,0x19 == stlurb w3, [sp, #-3]
|
||||
0x9f,0x01,0x40,0x19 == ldapurb wzr, [x12]
|
||||
0x84,0x01,0x40,0x19 == ldapurb w4, [x12]
|
||||
0x84,0x01,0x50,0x19 == ldapurb w4, [x12, #-256]
|
||||
0xa5,0xf1,0x4f,0x19 == ldapurb w5, [x13, #255]
|
||||
0xe6,0xe3,0x5f,0x19 == ldapurb w6, [sp, #-2]
|
||||
0xc7,0x01,0xc0,0x19 == ldapursb w7, [x14]
|
||||
0xc7,0x01,0xd0,0x19 == ldapursb w7, [x14, #-256]
|
||||
0xe8,0xf1,0xcf,0x19 == ldapursb w8, [x15, #255]
|
||||
0xe9,0xf3,0xdf,0x19 == ldapursb w9, [sp, #-1]
|
||||
0x00,0x02,0x80,0x19 == ldapursb x0, [x16]
|
||||
0x00,0x02,0x90,0x19 == ldapursb x0, [x16, #-256]
|
||||
0x21,0xf2,0x8f,0x19 == ldapursb x1, [x17, #255]
|
||||
0xe2,0x03,0x80,0x19 == ldapursb x2, [sp]
|
||||
0xe2,0x03,0x80,0x19 == ldapursb x2, [sp]
|
||||
0x4a,0x02,0x00,0x59 == stlurh w10, [x18]
|
||||
0x4a,0x02,0x10,0x59 == stlurh w10, [x18, #-256]
|
||||
0x6b,0xf2,0x0f,0x59 == stlurh w11, [x19, #255]
|
||||
0xec,0x13,0x00,0x59 == stlurh w12, [sp, #1]
|
||||
0x8d,0x02,0x40,0x59 == ldapurh w13, [x20]
|
||||
0x8d,0x02,0x50,0x59 == ldapurh w13, [x20, #-256]
|
||||
0xae,0xf2,0x4f,0x59 == ldapurh w14, [x21, #255]
|
||||
0xef,0x23,0x40,0x59 == ldapurh w15, [sp, #2]
|
||||
0xd0,0x02,0xc0,0x59 == ldapursh w16, [x22]
|
||||
0xd0,0x02,0xd0,0x59 == ldapursh w16, [x22, #-256]
|
||||
0xf1,0xf2,0xcf,0x59 == ldapursh w17, [x23, #255]
|
||||
0xf2,0x33,0xc0,0x59 == ldapursh w18, [sp, #3]
|
||||
0x03,0x03,0x80,0x59 == ldapursh x3, [x24]
|
||||
0x03,0x03,0x90,0x59 == ldapursh x3, [x24, #-256]
|
||||
0x24,0xf3,0x8f,0x59 == ldapursh x4, [x25, #255]
|
||||
0xe5,0x43,0x80,0x59 == ldapursh x5, [sp, #4]
|
||||
0x53,0x03,0x00,0x99 == stlur w19, [x26]
|
||||
0x53,0x03,0x10,0x99 == stlur w19, [x26, #-256]
|
||||
0x74,0xf3,0x0f,0x99 == stlur w20, [x27, #255]
|
||||
0xf5,0x53,0x00,0x99 == stlur w21, [sp, #5]
|
||||
0x96,0x03,0x40,0x99 == ldapur w22, [x28]
|
||||
0x96,0x03,0x50,0x99 == ldapur w22, [x28, #-256]
|
||||
0xb7,0xf3,0x4f,0x99 == ldapur w23, [x29, #255]
|
||||
0xf8,0x63,0x40,0x99 == ldapur w24, [sp, #6]
|
||||
0xc6,0x03,0x80,0x99 == ldapursw x6, [x30]
|
||||
0xc6,0x03,0x90,0x99 == ldapursw x6, [x30, #-256]
|
||||
0x07,0xf0,0x8f,0x99 == ldapursw x7, [x0, #255]
|
||||
0xe8,0x73,0x80,0x99 == ldapursw x8, [sp, #7]
|
||||
0x29,0x00,0x00,0xd9 == stlur x9, [x1]
|
||||
0x29,0x00,0x10,0xd9 == stlur x9, [x1, #-256]
|
||||
0x4a,0xf0,0x0f,0xd9 == stlur x10, [x2, #255]
|
||||
0xeb,0x83,0x00,0xd9 == stlur x11, [sp, #8]
|
||||
0x6c,0x00,0x40,0xd9 == ldapur x12, [x3]
|
||||
0x6c,0x00,0x50,0xd9 == ldapur x12, [x3, #-256]
|
||||
0x8d,0xf0,0x4f,0xd9 == ldapur x13, [x4, #255]
|
||||
0xee,0x93,0x40,0xd9 == ldapur x14, [sp, #9]
|
||||
105
thirdparty/capstone/suite/MC/AArch64/armv8.4a-ldst.txt.cs
vendored
Normal file
105
thirdparty/capstone/suite/MC/AArch64/armv8.4a-ldst.txt.cs
vendored
Normal file
@@ -0,0 +1,105 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
0x41,0x01,0x00,0x19 = stlurb w1, [x10]
|
||||
0x41,0x01,0x10,0x19 = stlurb w1, [x10, #-256]
|
||||
0x62,0xf1,0x0f,0x19 = stlurb w2, [x11, #255]
|
||||
0xe3,0xd3,0x1f,0x19 = stlurb w3, [sp, #-3]
|
||||
0x84,0x01,0x40,0x19 = ldapurb w4, [x12]
|
||||
0x84,0x01,0x50,0x19 = ldapurb w4, [x12, #-256]
|
||||
0xa5,0xf1,0x4f,0x19 = ldapurb w5, [x13, #255]
|
||||
0xe6,0xe3,0x5f,0x19 = ldapurb w6, [sp, #-2]
|
||||
0xc7,0x01,0xc0,0x19 = ldapursb w7, [x14]
|
||||
0xc7,0x01,0xd0,0x19 = ldapursb w7, [x14, #-256]
|
||||
0xe8,0xf1,0xcf,0x19 = ldapursb w8, [x15, #255]
|
||||
0xe9,0xf3,0xdf,0x19 = ldapursb w9, [sp, #-1]
|
||||
0x00,0x02,0x80,0x19 = ldapursb x0, [x16]
|
||||
0x00,0x02,0x90,0x19 = ldapursb x0, [x16, #-256]
|
||||
0x21,0xf2,0x8f,0x19 = ldapursb x1, [x17, #255]
|
||||
0xe2,0x03,0x80,0x19 = ldapursb x2, [sp]
|
||||
0x4a,0x02,0x00,0x59 = stlurh w10, [x18]
|
||||
0x4a,0x02,0x10,0x59 = stlurh w10, [x18, #-256]
|
||||
0x6b,0xf2,0x0f,0x59 = stlurh w11, [x19, #255]
|
||||
0xec,0x13,0x00,0x59 = stlurh w12, [sp, #1]
|
||||
0x8d,0x02,0x40,0x59 = ldapurh w13, [x20]
|
||||
0x8d,0x02,0x50,0x59 = ldapurh w13, [x20, #-256]
|
||||
0xae,0xf2,0x4f,0x59 = ldapurh w14, [x21, #255]
|
||||
0xef,0x23,0x40,0x59 = ldapurh w15, [sp, #2]
|
||||
0xd0,0x02,0xc0,0x59 = ldapursh w16, [x22]
|
||||
0xd0,0x02,0xd0,0x59 = ldapursh w16, [x22, #-256]
|
||||
0xf1,0xf2,0xcf,0x59 = ldapursh w17, [x23, #255]
|
||||
0xf2,0x33,0xc0,0x59 = ldapursh w18, [sp, #3]
|
||||
0x03,0x03,0x80,0x59 = ldapursh x3, [x24]
|
||||
0x03,0x03,0x90,0x59 = ldapursh x3, [x24, #-256]
|
||||
0x24,0xf3,0x8f,0x59 = ldapursh x4, [x25, #255]
|
||||
0xe5,0x43,0x80,0x59 = ldapursh x5, [sp, #4]
|
||||
0x53,0x03,0x00,0x99 = stlur w19, [x26]
|
||||
0x53,0x03,0x10,0x99 = stlur w19, [x26, #-256]
|
||||
0x74,0xf3,0x0f,0x99 = stlur w20, [x27, #255]
|
||||
0xf5,0x53,0x00,0x99 = stlur w21, [sp, #5]
|
||||
0x96,0x03,0x40,0x99 = ldapur w22, [x28]
|
||||
0x96,0x03,0x50,0x99 = ldapur w22, [x28, #-256]
|
||||
0xb7,0xf3,0x4f,0x99 = ldapur w23, [x29, #255]
|
||||
0xf8,0x63,0x40,0x99 = ldapur w24, [sp, #6]
|
||||
0xc6,0x03,0x80,0x99 = ldapursw x6, [x30]
|
||||
0xc6,0x03,0x90,0x99 = ldapursw x6, [x30, #-256]
|
||||
0x07,0xf0,0x8f,0x99 = ldapursw x7, [x0, #255]
|
||||
0xe8,0x73,0x80,0x99 = ldapursw x8, [sp, #7]
|
||||
0x29,0x00,0x00,0xd9 = stlur x9, [x1]
|
||||
0x29,0x00,0x10,0xd9 = stlur x9, [x1, #-256]
|
||||
0x4a,0xf0,0x0f,0xd9 = stlur x10, [x2, #255]
|
||||
0xeb,0x83,0x00,0xd9 = stlur x11, [sp, #8]
|
||||
0x6c,0x00,0x40,0xd9 = ldapur x12, [x3]
|
||||
0x6c,0x00,0x50,0xd9 = ldapur x12, [x3, #-256]
|
||||
0x8d,0xf0,0x4f,0xd9 = ldapur x13, [x4, #255]
|
||||
0xee,0x93,0x40,0xd9 = ldapur x14, [sp, #9]
|
||||
0x41,0x01,0x00,0x19 = stlurb w1, [x10]
|
||||
0x41,0x01,0x10,0x19 = stlurb w1, [x10, #-256]
|
||||
0x62,0xf1,0x0f,0x19 = stlurb w2, [x11, #255]
|
||||
0xe3,0xd3,0x1f,0x19 = stlurb w3, [sp, #-3]
|
||||
0x84,0x01,0x40,0x19 = ldapurb w4, [x12]
|
||||
0x84,0x01,0x50,0x19 = ldapurb w4, [x12, #-256]
|
||||
0xa5,0xf1,0x4f,0x19 = ldapurb w5, [x13, #255]
|
||||
0xe6,0xe3,0x5f,0x19 = ldapurb w6, [sp, #-2]
|
||||
0xc7,0x01,0xc0,0x19 = ldapursb w7, [x14]
|
||||
0xc7,0x01,0xd0,0x19 = ldapursb w7, [x14, #-256]
|
||||
0xe8,0xf1,0xcf,0x19 = ldapursb w8, [x15, #255]
|
||||
0xe9,0xf3,0xdf,0x19 = ldapursb w9, [sp, #-1]
|
||||
0x00,0x02,0x80,0x19 = ldapursb x0, [x16]
|
||||
0x00,0x02,0x90,0x19 = ldapursb x0, [x16, #-256]
|
||||
0x21,0xf2,0x8f,0x19 = ldapursb x1, [x17, #255]
|
||||
0xe2,0x03,0x80,0x19 = ldapursb x2, [sp]
|
||||
0x4a,0x02,0x00,0x59 = stlurh w10, [x18]
|
||||
0x4a,0x02,0x10,0x59 = stlurh w10, [x18, #-256]
|
||||
0x6b,0xf2,0x0f,0x59 = stlurh w11, [x19, #255]
|
||||
0xec,0x13,0x00,0x59 = stlurh w12, [sp, #1]
|
||||
0x8d,0x02,0x40,0x59 = ldapurh w13, [x20]
|
||||
0x8d,0x02,0x50,0x59 = ldapurh w13, [x20, #-256]
|
||||
0xae,0xf2,0x4f,0x59 = ldapurh w14, [x21, #255]
|
||||
0xef,0x23,0x40,0x59 = ldapurh w15, [sp, #2]
|
||||
0xd0,0x02,0xc0,0x59 = ldapursh w16, [x22]
|
||||
0xd0,0x02,0xd0,0x59 = ldapursh w16, [x22, #-256]
|
||||
0xf1,0xf2,0xcf,0x59 = ldapursh w17, [x23, #255]
|
||||
0xf2,0x33,0xc0,0x59 = ldapursh w18, [sp, #3]
|
||||
0x03,0x03,0x80,0x59 = ldapursh x3, [x24]
|
||||
0x03,0x03,0x90,0x59 = ldapursh x3, [x24, #-256]
|
||||
0x24,0xf3,0x8f,0x59 = ldapursh x4, [x25, #255]
|
||||
0xe5,0x43,0x80,0x59 = ldapursh x5, [sp, #4]
|
||||
0x53,0x03,0x00,0x99 = stlur w19, [x26]
|
||||
0x53,0x03,0x10,0x99 = stlur w19, [x26, #-256]
|
||||
0x74,0xf3,0x0f,0x99 = stlur w20, [x27, #255]
|
||||
0xf5,0x53,0x00,0x99 = stlur w21, [sp, #5]
|
||||
0x96,0x03,0x40,0x99 = ldapur w22, [x28]
|
||||
0x96,0x03,0x50,0x99 = ldapur w22, [x28, #-256]
|
||||
0xb7,0xf3,0x4f,0x99 = ldapur w23, [x29, #255]
|
||||
0xf8,0x63,0x40,0x99 = ldapur w24, [sp, #6]
|
||||
0xc6,0x03,0x80,0x99 = ldapursw x6, [x30]
|
||||
0xc6,0x03,0x90,0x99 = ldapursw x6, [x30, #-256]
|
||||
0x07,0xf0,0x8f,0x99 = ldapursw x7, [x0, #255]
|
||||
0xe8,0x73,0x80,0x99 = ldapursw x8, [sp, #7]
|
||||
0x29,0x00,0x00,0xd9 = stlur x9, [x1]
|
||||
0x29,0x00,0x10,0xd9 = stlur x9, [x1, #-256]
|
||||
0x4a,0xf0,0x0f,0xd9 = stlur x10, [x2, #255]
|
||||
0xeb,0x83,0x00,0xd9 = stlur x11, [sp, #8]
|
||||
0x6c,0x00,0x40,0xd9 = ldapur x12, [x3]
|
||||
0x6c,0x00,0x50,0xd9 = ldapur x12, [x3, #-256]
|
||||
0x8d,0xf0,0x4f,0xd9 = ldapur x13, [x4, #255]
|
||||
0xee,0x93,0x40,0xd9 = ldapur x14, [sp, #9]
|
||||
33
thirdparty/capstone/suite/MC/AArch64/armv8.4a-mpam.s.cs
vendored
Normal file
33
thirdparty/capstone/suite/MC/AArch64/armv8.4a-mpam.s.cs
vendored
Normal file
@@ -0,0 +1,33 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0x20,0xa5,0x18,0xd5 == msr MPAM0_EL1, x0
|
||||
0x00,0xa5,0x18,0xd5 == msr MPAM1_EL1, x0
|
||||
0x00,0xa5,0x1c,0xd5 == msr MPAM2_EL2, x0
|
||||
0x00,0xa5,0x1e,0xd5 == msr MPAM3_EL3, x0
|
||||
0x00,0xa5,0x1d,0xd5 == msr MPAM1_EL12, x0
|
||||
0x00,0xa4,0x1c,0xd5 == msr MPAMHCR_EL2, x0
|
||||
0x20,0xa4,0x1c,0xd5 == msr MPAMVPMV_EL2, x0
|
||||
0x00,0xa6,0x1c,0xd5 == msr MPAMVPM0_EL2, x0
|
||||
0x20,0xa6,0x1c,0xd5 == msr MPAMVPM1_EL2, x0
|
||||
0x40,0xa6,0x1c,0xd5 == msr MPAMVPM2_EL2, x0
|
||||
0x60,0xa6,0x1c,0xd5 == msr MPAMVPM3_EL2, x0
|
||||
0x80,0xa6,0x1c,0xd5 == msr MPAMVPM4_EL2, x0
|
||||
0xa0,0xa6,0x1c,0xd5 == msr MPAMVPM5_EL2, x0
|
||||
0xc0,0xa6,0x1c,0xd5 == msr MPAMVPM6_EL2, x0
|
||||
0xe0,0xa6,0x1c,0xd5 == msr MPAMVPM7_EL2, x0
|
||||
0x20,0xa5,0x38,0xd5 == mrs x0, MPAM0_EL1
|
||||
0x00,0xa5,0x38,0xd5 == mrs x0, MPAM1_EL1
|
||||
0x00,0xa5,0x3c,0xd5 == mrs x0, MPAM2_EL2
|
||||
0x00,0xa5,0x3e,0xd5 == mrs x0, MPAM3_EL3
|
||||
0x00,0xa5,0x3d,0xd5 == mrs x0, MPAM1_EL12
|
||||
0x00,0xa4,0x3c,0xd5 == mrs x0, MPAMHCR_EL2
|
||||
0x20,0xa4,0x3c,0xd5 == mrs x0, MPAMVPMV_EL2
|
||||
0x00,0xa6,0x3c,0xd5 == mrs x0, MPAMVPM0_EL2
|
||||
0x20,0xa6,0x3c,0xd5 == mrs x0, MPAMVPM1_EL2
|
||||
0x40,0xa6,0x3c,0xd5 == mrs x0, MPAMVPM2_EL2
|
||||
0x60,0xa6,0x3c,0xd5 == mrs x0, MPAMVPM3_EL2
|
||||
0x80,0xa6,0x3c,0xd5 == mrs x0, MPAMVPM4_EL2
|
||||
0xa0,0xa6,0x3c,0xd5 == mrs x0, MPAMVPM5_EL2
|
||||
0xc0,0xa6,0x3c,0xd5 == mrs x0, MPAMVPM6_EL2
|
||||
0xe0,0xa6,0x3c,0xd5 == mrs x0, MPAMVPM7_EL2
|
||||
0x80,0xa4,0x38,0xd5 == mrs x0, MPAMIDR_EL1
|
||||
32
thirdparty/capstone/suite/MC/AArch64/armv8.4a-mpam.txt.cs
vendored
Normal file
32
thirdparty/capstone/suite/MC/AArch64/armv8.4a-mpam.txt.cs
vendored
Normal file
@@ -0,0 +1,32 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
0x20,0xa5,0x18,0xd5 = msr MPAM0_EL1, x0
|
||||
0x00,0xa5,0x18,0xd5 = msr MPAM1_EL1, x0
|
||||
0x00,0xa5,0x1c,0xd5 = msr MPAM2_EL2, x0
|
||||
0x00,0xa5,0x1e,0xd5 = msr MPAM3_EL3, x0
|
||||
0x00,0xa5,0x1d,0xd5 = msr MPAM1_EL12, x0
|
||||
0x00,0xa4,0x1c,0xd5 = msr MPAMHCR_EL2, x0
|
||||
0x20,0xa4,0x1c,0xd5 = msr MPAMVPMV_EL2, x0
|
||||
0x00,0xa6,0x1c,0xd5 = msr MPAMVPM0_EL2, x0
|
||||
0x20,0xa6,0x1c,0xd5 = msr MPAMVPM1_EL2, x0
|
||||
0x40,0xa6,0x1c,0xd5 = msr MPAMVPM2_EL2, x0
|
||||
0x60,0xa6,0x1c,0xd5 = msr MPAMVPM3_EL2, x0
|
||||
0x80,0xa6,0x1c,0xd5 = msr MPAMVPM4_EL2, x0
|
||||
0xa0,0xa6,0x1c,0xd5 = msr MPAMVPM5_EL2, x0
|
||||
0xc0,0xa6,0x1c,0xd5 = msr MPAMVPM6_EL2, x0
|
||||
0xe0,0xa6,0x1c,0xd5 = msr MPAMVPM7_EL2, x0
|
||||
0x20,0xa5,0x38,0xd5 = mrs x0, MPAM0_EL1
|
||||
0x00,0xa5,0x38,0xd5 = mrs x0, MPAM1_EL1
|
||||
0x00,0xa5,0x3c,0xd5 = mrs x0, MPAM2_EL2
|
||||
0x00,0xa5,0x3e,0xd5 = mrs x0, MPAM3_EL3
|
||||
0x00,0xa5,0x3d,0xd5 = mrs x0, MPAM1_EL12
|
||||
0x00,0xa4,0x3c,0xd5 = mrs x0, MPAMHCR_EL2
|
||||
0x20,0xa4,0x3c,0xd5 = mrs x0, MPAMVPMV_EL2
|
||||
0x00,0xa6,0x3c,0xd5 = mrs x0, MPAMVPM0_EL2
|
||||
0x20,0xa6,0x3c,0xd5 = mrs x0, MPAMVPM1_EL2
|
||||
0x40,0xa6,0x3c,0xd5 = mrs x0, MPAMVPM2_EL2
|
||||
0x60,0xa6,0x3c,0xd5 = mrs x0, MPAMVPM3_EL2
|
||||
0x80,0xa6,0x3c,0xd5 = mrs x0, MPAMVPM4_EL2
|
||||
0xa0,0xa6,0x3c,0xd5 = mrs x0, MPAMVPM5_EL2
|
||||
0xc0,0xa6,0x3c,0xd5 = mrs x0, MPAMVPM6_EL2
|
||||
0xe0,0xa6,0x3c,0xd5 = mrs x0, MPAMVPM7_EL2
|
||||
0x80,0xa4,0x38,0xd5 = mrs x0, MPAMIDR_EL1
|
||||
11
thirdparty/capstone/suite/MC/AArch64/armv8.4a-ras.s.cs
vendored
Normal file
11
thirdparty/capstone/suite/MC/AArch64/armv8.4a-ras.s.cs
vendored
Normal file
@@ -0,0 +1,11 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0xa0,0x54,0x18,0xd5 == msr ERXPFGCTL_EL1, x0
|
||||
0xa0,0x54,0x38,0xd5 == mrs x0, ERXPFGCTL_EL1
|
||||
0xc0,0x54,0x18,0xd5 == msr ERXPFGCDN_EL1, x0
|
||||
0xc0,0x54,0x38,0xd5 == mrs x0, ERXPFGCDN_EL1
|
||||
0x40,0x55,0x18,0xd5 == msr ERXMISC2_EL1, x0
|
||||
0x40,0x55,0x38,0xd5 == mrs x0, ERXMISC2_EL1
|
||||
0x60,0x55,0x18,0xd5 == msr ERXMISC3_EL1, x0
|
||||
0x60,0x55,0x38,0xd5 == mrs x0, ERXMISC3_EL1
|
||||
0x80,0x54,0x38,0xd5 == mrs x0, ERXPFGF_EL1
|
||||
50
thirdparty/capstone/suite/MC/AArch64/armv8.4a-tlb.s.cs
vendored
Normal file
50
thirdparty/capstone/suite/MC/AArch64/armv8.4a-tlb.s.cs
vendored
Normal file
@@ -0,0 +1,50 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0x1f,0x81,0x08,0xd5 == tlbi vmalle1os
|
||||
0x3f,0x81,0x08,0xd5 == tlbi vae1os, xzr
|
||||
0x20,0x81,0x08,0xd5 == tlbi vae1os, x0
|
||||
0x41,0x81,0x08,0xd5 == tlbi aside1os, x1
|
||||
0x62,0x81,0x08,0xd5 == tlbi vaae1os, x2
|
||||
0xa3,0x81,0x08,0xd5 == tlbi vale1os, x3
|
||||
0xe4,0x81,0x08,0xd5 == tlbi vaale1os, x4
|
||||
0x05,0x84,0x0c,0xd5 == tlbi ipas2e1os, x5
|
||||
0x86,0x84,0x0c,0xd5 == tlbi ipas2le1os, x6
|
||||
0x27,0x81,0x0c,0xd5 == tlbi vae2os, x7
|
||||
0xa8,0x81,0x0c,0xd5 == tlbi vale2os, x8
|
||||
0xdf,0x81,0x0c,0xd5 == tlbi vmalls12e1os
|
||||
0x29,0x81,0x0e,0xd5 == tlbi vae3os, x9
|
||||
0xaa,0x81,0x0e,0xd5 == tlbi vale3os, x10
|
||||
0x1f,0x81,0x0c,0xd5 == tlbi alle2os
|
||||
0x9f,0x81,0x0c,0xd5 == tlbi alle1os
|
||||
0x1f,0x81,0x0e,0xd5 == tlbi alle3os
|
||||
0x23,0x86,0x08,0xd5 == tlbi rvae1, x3
|
||||
0x63,0x86,0x08,0xd5 == tlbi rvaae1, x3
|
||||
0xa3,0x86,0x08,0xd5 == tlbi rvale1, x3
|
||||
0xe3,0x86,0x08,0xd5 == tlbi rvaale1, x3
|
||||
0x23,0x82,0x08,0xd5 == tlbi rvae1is, x3
|
||||
0x63,0x82,0x08,0xd5 == tlbi rvaae1is, x3
|
||||
0xa3,0x82,0x08,0xd5 == tlbi rvale1is, x3
|
||||
0xe3,0x82,0x08,0xd5 == tlbi rvaale1is, x3
|
||||
0x23,0x85,0x08,0xd5 == tlbi rvae1os, x3
|
||||
0x63,0x85,0x08,0xd5 == tlbi rvaae1os, x3
|
||||
0xa3,0x85,0x08,0xd5 == tlbi rvale1os, x3
|
||||
0xe3,0x85,0x08,0xd5 == tlbi rvaale1os, x3
|
||||
0x43,0x80,0x0c,0xd5 == tlbi ripas2e1is, x3
|
||||
0xc3,0x80,0x0c,0xd5 == tlbi ripas2le1is, x3
|
||||
0x43,0x84,0x0c,0xd5 == tlbi ripas2e1, x3
|
||||
0xc3,0x84,0x0c,0xd5 == tlbi ripas2le1, x3
|
||||
0x63,0x84,0x0c,0xd5 == tlbi ripas2e1os, x3
|
||||
0xe3,0x84,0x0c,0xd5 == tlbi ripas2le1os, x3
|
||||
0x23,0x86,0x0c,0xd5 == tlbi rvae2, x3
|
||||
0xa3,0x86,0x0c,0xd5 == tlbi rvale2, x3
|
||||
0x23,0x82,0x0c,0xd5 == tlbi rvae2is, x3
|
||||
0xa3,0x82,0x0c,0xd5 == tlbi rvale2is, x3
|
||||
0x23,0x85,0x0c,0xd5 == tlbi rvae2os, x3
|
||||
0xa3,0x85,0x0c,0xd5 == tlbi rvale2os, x3
|
||||
0x23,0x86,0x0e,0xd5 == tlbi rvae3, x3
|
||||
0xa3,0x86,0x0e,0xd5 == tlbi rvale3, x3
|
||||
0x23,0x82,0x0e,0xd5 == tlbi rvae3is, x3
|
||||
0xa3,0x82,0x0e,0xd5 == tlbi rvale3is, x3
|
||||
0x23,0x85,0x0e,0xd5 == tlbi rvae3os, x3
|
||||
0xa3,0x85,0x0e,0xd5 == tlbi rvale3os, x3
|
||||
0xbf,0x85,0x0e,0xd5 == tlbi rvale3os, xzr
|
||||
9
thirdparty/capstone/suite/MC/AArch64/armv8.4a-trace.s.cs
vendored
Normal file
9
thirdparty/capstone/suite/MC/AArch64/armv8.4a-trace.s.cs
vendored
Normal file
@@ -0,0 +1,9 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0x20,0x12,0x18,0xd5 == msr TRFCR_EL1, x0
|
||||
0x20,0x12,0x1c,0xd5 == msr TRFCR_EL2, x0
|
||||
0x20,0x12,0x1d,0xd5 == msr TRFCR_EL12, x0
|
||||
0x20,0x12,0x38,0xd5 == mrs x0, TRFCR_EL1
|
||||
0x20,0x12,0x3c,0xd5 == mrs x0, TRFCR_EL2
|
||||
0x20,0x12,0x3d,0xd5 == mrs x0, TRFCR_EL12
|
||||
0x5f,0x22,0x03,0xd5 == tsb csync
|
||||
8
thirdparty/capstone/suite/MC/AArch64/armv8.4a-trace.txt.cs
vendored
Normal file
8
thirdparty/capstone/suite/MC/AArch64/armv8.4a-trace.txt.cs
vendored
Normal file
@@ -0,0 +1,8 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
0x20,0x12,0x18,0xd5 = msr TRFCR_EL1, x0
|
||||
0x20,0x12,0x1c,0xd5 = msr TRFCR_EL2, x0
|
||||
0x20,0x12,0x1d,0xd5 = msr TRFCR_EL12, x0
|
||||
0x20,0x12,0x38,0xd5 = mrs x0, TRFCR_EL1
|
||||
0x20,0x12,0x3c,0xd5 = mrs x0, TRFCR_EL2
|
||||
0x20,0x12,0x3d,0xd5 = mrs x0, TRFCR_EL12
|
||||
0x5f,0x22,0x03,0xd5 = tsb csync
|
||||
11
thirdparty/capstone/suite/MC/AArch64/armv8.4a-virt.s.cs
vendored
Normal file
11
thirdparty/capstone/suite/MC/AArch64/armv8.4a-virt.s.cs
vendored
Normal file
@@ -0,0 +1,11 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0x40,0x26,0x1c,0xd5 == msr VSTCR_EL2, x0
|
||||
0x00,0x26,0x1c,0xd5 == msr VSTTBR_EL2, x0
|
||||
0x2c,0x13,0x1c,0xd5 == msr SDER32_EL2, x12
|
||||
0x00,0xe4,0x1c,0xd5 == msr CNTHVS_TVAL_EL2, x0
|
||||
0x40,0xe4,0x1c,0xd5 == msr CNTHVS_CVAL_EL2, x0
|
||||
0x20,0xe4,0x1c,0xd5 == msr CNTHVS_CTL_EL2, x0
|
||||
0x00,0xe5,0x1c,0xd5 == msr CNTHPS_TVAL_EL2, x0
|
||||
0x40,0xe5,0x1c,0xd5 == msr CNTHPS_CVAL_EL2, x0
|
||||
0x20,0xe5,0x1c,0xd5 == msr CNTHPS_CTL_EL2, x0
|
||||
4
thirdparty/capstone/suite/MC/AArch64/armv8.4a-vncr.s.cs
vendored
Normal file
4
thirdparty/capstone/suite/MC/AArch64/armv8.4a-vncr.s.cs
vendored
Normal file
@@ -0,0 +1,4 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0x00,0x22,0x3c,0xd5 == mrs x0, VNCR_EL2
|
||||
0x00,0x22,0x1c,0xd5 == msr VNCR_EL2, x0
|
||||
3
thirdparty/capstone/suite/MC/AArch64/armv8.4a-vncr.txt.cs
vendored
Normal file
3
thirdparty/capstone/suite/MC/AArch64/armv8.4a-vncr.txt.cs
vendored
Normal file
@@ -0,0 +1,3 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
0x00,0x22,0x3c,0xd5 = mrs x0, VNCR_EL2
|
||||
0x00,0x22,0x1c,0xd5 = msr VNCR_EL2, x0
|
||||
4
thirdparty/capstone/suite/MC/AArch64/armv8.5a-altnzcv.s.cs
vendored
Normal file
4
thirdparty/capstone/suite/MC/AArch64/armv8.5a-altnzcv.s.cs
vendored
Normal file
@@ -0,0 +1,4 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0x3f,0x40,0x00,0xd5 == xaflag
|
||||
0x5f,0x40,0x00,0xd5 == axflag
|
||||
10
thirdparty/capstone/suite/MC/AArch64/armv8.5a-bti.s.cs
vendored
Normal file
10
thirdparty/capstone/suite/MC/AArch64/armv8.5a-bti.s.cs
vendored
Normal file
@@ -0,0 +1,10 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0x1f,0x24,0x03,0xd5 == bti
|
||||
0x5f,0x24,0x03,0xd5 == bti c
|
||||
0x9f,0x24,0x03,0xd5 == bti j
|
||||
0xdf,0x24,0x03,0xd5 == bti jc
|
||||
0x1f,0x24,0x03,0xd5 == bti
|
||||
0x5f,0x24,0x03,0xd5 == bti c
|
||||
0x9f,0x24,0x03,0xd5 == bti j
|
||||
0xdf,0x24,0x03,0xd5 == bti jc
|
||||
43
thirdparty/capstone/suite/MC/AArch64/armv8.5a-dataproc.txt.cs
vendored
Normal file
43
thirdparty/capstone/suite/MC/AArch64/armv8.5a-dataproc.txt.cs
vendored
Normal file
@@ -0,0 +1,43 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
0x3f,0x40,0x00,0xd5 = xaflag
|
||||
0x5f,0x40,0x00,0xd5 = axflag
|
||||
0x20,0x40,0x28,0x1e = frint32z s0, s1
|
||||
0x20,0x40,0x68,0x1e = frint32z d0, d1
|
||||
0x62,0x40,0x29,0x1e = frint64z s2, s3
|
||||
0x62,0x40,0x69,0x1e = frint64z d2, d3
|
||||
0xa4,0xc0,0x28,0x1e = frint32x s4, s5
|
||||
0xa4,0xc0,0x68,0x1e = frint32x d4, d5
|
||||
0xe6,0xc0,0x29,0x1e = frint64x s6, s7
|
||||
0xe6,0xc0,0x69,0x1e = frint64x d6, d7
|
||||
0x20,0x40,0x28,0x1e = frint32z s0, s1
|
||||
0x20,0x40,0x68,0x1e = frint32z d0, d1
|
||||
0x62,0x40,0x29,0x1e = frint64z s2, s3
|
||||
0x62,0x40,0x69,0x1e = frint64z d2, d3
|
||||
0xa4,0xc0,0x28,0x1e = frint32x s4, s5
|
||||
0xa4,0xc0,0x68,0x1e = frint32x d4, d5
|
||||
0xe6,0xc0,0x29,0x1e = frint64x s6, s7
|
||||
0xe6,0xc0,0x69,0x1e = frint64x d6, d7
|
||||
0x20,0xe8,0x21,0x0e = frint32z v0.2s, v1.2s
|
||||
0x20,0xe8,0x61,0x4e = frint32z v0.2d, v1.2d
|
||||
0x20,0xe8,0x21,0x4e = frint32z v0.4s, v1.4s
|
||||
0x62,0xf8,0x21,0x0e = frint64z v2.2s, v3.2s
|
||||
0x62,0xf8,0x61,0x4e = frint64z v2.2d, v3.2d
|
||||
0x62,0xf8,0x21,0x4e = frint64z v2.4s, v3.4s
|
||||
0xa4,0xe8,0x21,0x2e = frint32x v4.2s, v5.2s
|
||||
0xa4,0xe8,0x61,0x6e = frint32x v4.2d, v5.2d
|
||||
0xa4,0xe8,0x21,0x6e = frint32x v4.4s, v5.4s
|
||||
0xe6,0xf8,0x21,0x2e = frint64x v6.2s, v7.2s
|
||||
0xe6,0xf8,0x61,0x6e = frint64x v6.2d, v7.2d
|
||||
0xe6,0xf8,0x21,0x6e = frint64x v6.4s, v7.4s
|
||||
0x20,0xe8,0x21,0x0e = frint32z v0.2s, v1.2s
|
||||
0x20,0xe8,0x61,0x4e = frint32z v0.2d, v1.2d
|
||||
0x20,0xe8,0x21,0x4e = frint32z v0.4s, v1.4s
|
||||
0x62,0xf8,0x21,0x0e = frint64z v2.2s, v3.2s
|
||||
0x62,0xf8,0x61,0x4e = frint64z v2.2d, v3.2d
|
||||
0x62,0xf8,0x21,0x4e = frint64z v2.4s, v3.4s
|
||||
0xa4,0xe8,0x21,0x2e = frint32x v4.2s, v5.2s
|
||||
0xa4,0xe8,0x61,0x6e = frint32x v4.2d, v5.2d
|
||||
0xa4,0xe8,0x21,0x6e = frint32x v4.4s, v5.4s
|
||||
0xe6,0xf8,0x21,0x2e = frint64x v6.2s, v7.2s
|
||||
0xe6,0xf8,0x61,0x6e = frint64x v6.2d, v7.2d
|
||||
0xe6,0xf8,0x21,0x6e = frint64x v6.4s, v7.4s
|
||||
22
thirdparty/capstone/suite/MC/AArch64/armv8.5a-frint.s.cs
vendored
Normal file
22
thirdparty/capstone/suite/MC/AArch64/armv8.5a-frint.s.cs
vendored
Normal file
@@ -0,0 +1,22 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0x20,0x40,0x28,0x1e == frint32z s0, s1
|
||||
0x20,0x40,0x68,0x1e == frint32z d0, d1
|
||||
0x62,0x40,0x29,0x1e == frint64z s2, s3
|
||||
0x62,0x40,0x69,0x1e == frint64z d2, d3
|
||||
0xa4,0xc0,0x28,0x1e == frint32x s4, s5
|
||||
0xa4,0xc0,0x68,0x1e == frint32x d4, d5
|
||||
0xe6,0xc0,0x29,0x1e == frint64x s6, s7
|
||||
0xe6,0xc0,0x69,0x1e == frint64x d6, d7
|
||||
0x20,0xe8,0x21,0x0e == frint32z v0.2s, v1.2s
|
||||
0x20,0xe8,0x61,0x4e == frint32z v0.2d, v1.2d
|
||||
0x20,0xe8,0x21,0x4e == frint32z v0.4s, v1.4s
|
||||
0x62,0xf8,0x21,0x0e == frint64z v2.2s, v3.2s
|
||||
0x62,0xf8,0x61,0x4e == frint64z v2.2d, v3.2d
|
||||
0x62,0xf8,0x21,0x4e == frint64z v2.4s, v3.4s
|
||||
0xa4,0xe8,0x21,0x2e == frint32x v4.2s, v5.2s
|
||||
0xa4,0xe8,0x61,0x6e == frint32x v4.2d, v5.2d
|
||||
0xa4,0xe8,0x21,0x6e == frint32x v4.4s, v5.4s
|
||||
0xe6,0xf8,0x21,0x2e == frint64x v6.2s, v7.2s
|
||||
0xe6,0xf8,0x61,0x6e == frint64x v6.2d, v7.2d
|
||||
0xe6,0xf8,0x21,0x6e == frint64x v6.4s, v7.4s
|
||||
145
thirdparty/capstone/suite/MC/AArch64/armv8.5a-mte.s.cs
vendored
Normal file
145
thirdparty/capstone/suite/MC/AArch64/armv8.5a-mte.s.cs
vendored
Normal file
@@ -0,0 +1,145 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0x20,0x10,0xdf,0x9a == irg x0, x1
|
||||
0x3f,0x10,0xdf,0x9a == irg sp, x1
|
||||
0xe0,0x13,0xdf,0x9a == irg x0, sp
|
||||
0x20,0x10,0xc2,0x9a == irg x0, x1, x2
|
||||
0x3f,0x10,0xc2,0x9a == irg sp, x1, x2
|
||||
0x20,0x04,0x80,0x91 == addg x0, x1, #0, #1
|
||||
0x5f,0x0c,0x82,0x91 == addg sp, x2, #32, #3
|
||||
0xe0,0x17,0x84,0x91 == addg x0, sp, #64, #5
|
||||
0x83,0x18,0xbf,0x91 == addg x3, x4, #1008, #6
|
||||
0xc5,0x3c,0x87,0x91 == addg x5, x6, #112, #15
|
||||
0x20,0x04,0x80,0xd1 == subg x0, x1, #0, #1
|
||||
0x5f,0x0c,0x82,0xd1 == subg sp, x2, #32, #3
|
||||
0xe0,0x17,0x84,0xd1 == subg x0, sp, #64, #5
|
||||
0x83,0x18,0xbf,0xd1 == subg x3, x4, #1008, #6
|
||||
0xc5,0x3c,0x87,0xd1 == subg x5, x6, #112, #15
|
||||
0x20,0x14,0xc2,0x9a == gmi x0, x1, x2
|
||||
0xe3,0x17,0xc4,0x9a == gmi x3, sp, x4
|
||||
0x1f,0x14,0xde,0x9a == gmi xzr, x0, x30
|
||||
0x1e,0x14,0xdf,0x9a == gmi x30, x0, xzr
|
||||
0x20,0x08,0x20,0xd9 == stg x0, [x1]
|
||||
0x21,0x08,0x30,0xd9 == stg x1, [x1, #-4096]
|
||||
0x42,0xf8,0x2f,0xd9 == stg x2, [x2, #4080]
|
||||
0xe3,0x1b,0x20,0xd9 == stg x3, [sp, #16]
|
||||
0xff,0x1b,0x20,0xd9 == stg sp, [sp, #16]
|
||||
0x20,0x08,0x60,0xd9 == stzg x0, [x1]
|
||||
0x21,0x08,0x70,0xd9 == stzg x1, [x1, #-4096]
|
||||
0x42,0xf8,0x6f,0xd9 == stzg x2, [x2, #4080]
|
||||
0xe3,0x1b,0x60,0xd9 == stzg x3, [sp, #16]
|
||||
0xff,0x1b,0x60,0xd9 == stzg sp, [sp, #16]
|
||||
0x20,0x0c,0x30,0xd9 == stg x0, [x1, #-4096]!
|
||||
0x41,0xfc,0x2f,0xd9 == stg x1, [x2, #4080]!
|
||||
0xe2,0x1f,0x20,0xd9 == stg x2, [sp, #16]!
|
||||
0xff,0x1f,0x20,0xd9 == stg sp, [sp, #16]!
|
||||
0x20,0x0c,0x70,0xd9 == stzg x0, [x1, #-4096]!
|
||||
0x41,0xfc,0x6f,0xd9 == stzg x1, [x2, #4080]!
|
||||
0xe2,0x1f,0x60,0xd9 == stzg x2, [sp, #16]!
|
||||
0xff,0x1f,0x60,0xd9 == stzg sp, [sp, #16]!
|
||||
0x20,0x04,0x30,0xd9 == stg x0, [x1], #-4096
|
||||
0x41,0xf4,0x2f,0xd9 == stg x1, [x2], #4080
|
||||
0xe2,0x17,0x20,0xd9 == stg x2, [sp], #16
|
||||
0xff,0x17,0x20,0xd9 == stg sp, [sp], #16
|
||||
0x20,0x04,0x70,0xd9 == stzg x0, [x1], #-4096
|
||||
0x41,0xf4,0x6f,0xd9 == stzg x1, [x2], #4080
|
||||
0xe2,0x17,0x60,0xd9 == stzg x2, [sp], #16
|
||||
0xff,0x17,0x60,0xd9 == stzg sp, [sp], #16
|
||||
0x20,0x08,0xa0,0xd9 == st2g x0, [x1]
|
||||
0x21,0x08,0xb0,0xd9 == st2g x1, [x1, #-4096]
|
||||
0x42,0xf8,0xaf,0xd9 == st2g x2, [x2, #4080]
|
||||
0xe3,0x1b,0xa0,0xd9 == st2g x3, [sp, #16]
|
||||
0xff,0x1b,0xa0,0xd9 == st2g sp, [sp, #16]
|
||||
0x20,0x08,0xe0,0xd9 == stz2g x0, [x1]
|
||||
0x21,0x08,0xf0,0xd9 == stz2g x1, [x1, #-4096]
|
||||
0x42,0xf8,0xef,0xd9 == stz2g x2, [x2, #4080]
|
||||
0xe3,0x1b,0xe0,0xd9 == stz2g x3, [sp, #16]
|
||||
0xff,0x1b,0xe0,0xd9 == stz2g sp, [sp, #16]
|
||||
0x20,0x0c,0xb0,0xd9 == st2g x0, [x1, #-4096]!
|
||||
0x41,0xfc,0xaf,0xd9 == st2g x1, [x2, #4080]!
|
||||
0xe2,0x1f,0xa0,0xd9 == st2g x2, [sp, #16]!
|
||||
0xff,0x1f,0xa0,0xd9 == st2g sp, [sp, #16]!
|
||||
0x20,0x0c,0xf0,0xd9 == stz2g x0, [x1, #-4096]!
|
||||
0x41,0xfc,0xef,0xd9 == stz2g x1, [x2, #4080]!
|
||||
0xe2,0x1f,0xe0,0xd9 == stz2g x2, [sp, #16]!
|
||||
0xff,0x1f,0xe0,0xd9 == stz2g sp, [sp, #16]!
|
||||
0x20,0x04,0xb0,0xd9 == st2g x0, [x1], #-4096
|
||||
0x41,0xf4,0xaf,0xd9 == st2g x1, [x2], #4080
|
||||
0xe2,0x17,0xa0,0xd9 == st2g x2, [sp], #16
|
||||
0xff,0x17,0xa0,0xd9 == st2g sp, [sp], #16
|
||||
0x20,0x04,0xf0,0xd9 == stz2g x0, [x1], #-4096
|
||||
0x41,0xf4,0xef,0xd9 == stz2g x1, [x2], #4080
|
||||
0xe2,0x17,0xe0,0xd9 == stz2g x2, [sp], #16
|
||||
0xff,0x17,0xe0,0xd9 == stz2g sp, [sp], #16
|
||||
0x40,0x04,0x00,0x69 == stgp x0, x1, [x2]
|
||||
0x40,0x04,0x20,0x69 == stgp x0, x1, [x2, #-1024]
|
||||
0x40,0x84,0x1f,0x69 == stgp x0, x1, [x2, #1008]
|
||||
0xe0,0x87,0x00,0x69 == stgp x0, x1, [sp, #16]
|
||||
0x5f,0x84,0x00,0x69 == stgp xzr, x1, [x2, #16]
|
||||
0x40,0xfc,0x00,0x69 == stgp x0, xzr, [x2, #16]
|
||||
0x40,0x04,0xa0,0x69 == stgp x0, x1, [x2, #-1024]!
|
||||
0x40,0x84,0x9f,0x69 == stgp x0, x1, [x2, #1008]!
|
||||
0xe0,0x87,0x80,0x69 == stgp x0, x1, [sp, #16]!
|
||||
0x5f,0x84,0x80,0x69 == stgp xzr, x1, [x2, #16]!
|
||||
0x40,0xfc,0x80,0x69 == stgp x0, xzr, [x2, #16]!
|
||||
0x40,0x04,0xa0,0x68 == stgp x0, x1, [x2], #-1024
|
||||
0x40,0x84,0x9f,0x68 == stgp x0, x1, [x2], #1008
|
||||
0xe0,0x87,0x80,0x68 == stgp x0, x1, [sp], #16
|
||||
0x5f,0x84,0x80,0x68 == stgp xzr, x1, [x2], #16
|
||||
0x40,0xfc,0x80,0x68 == stgp x0, xzr, [x2], #16
|
||||
0x60,0x76,0x08,0xd5 == dc igvac, x0
|
||||
0x81,0x76,0x08,0xd5 == dc igsw, x1
|
||||
0x82,0x7a,0x08,0xd5 == dc cgsw, x2
|
||||
0x83,0x7e,0x08,0xd5 == dc cigsw, x3
|
||||
0x64,0x7a,0x0b,0xd5 == dc cgvac, x4
|
||||
0x65,0x7c,0x0b,0xd5 == dc cgvap, x5
|
||||
0x66,0x7d,0x0b,0xd5 == dc cgvadp, x6
|
||||
0x67,0x7e,0x0b,0xd5 == dc cigvac, x7
|
||||
0x68,0x74,0x0b,0xd5 == dc gva, x8
|
||||
0xa9,0x76,0x08,0xd5 == dc igdvac, x9
|
||||
0xca,0x76,0x08,0xd5 == dc igdsw, x10
|
||||
0xcb,0x7a,0x08,0xd5 == dc cgdsw, x11
|
||||
0xcc,0x7e,0x08,0xd5 == dc cigdsw, x12
|
||||
0xad,0x7a,0x0b,0xd5 == dc cgdvac, x13
|
||||
0xae,0x7c,0x0b,0xd5 == dc cgdvap, x14
|
||||
0xaf,0x7d,0x0b,0xd5 == dc cgdvadp, x15
|
||||
0xb0,0x7e,0x0b,0xd5 == dc cigdvac, x16
|
||||
0x91,0x74,0x0b,0xd5 == dc gzva, x17
|
||||
0xe0,0x42,0x3b,0xd5 == mrs x0, TCO
|
||||
0xc1,0x10,0x38,0xd5 == mrs x1, GCR_EL1
|
||||
0xa2,0x10,0x38,0xd5 == mrs x2, RGSR_EL1
|
||||
0x03,0x56,0x38,0xd5 == mrs x3, TFSR_EL1
|
||||
0x04,0x56,0x3c,0xd5 == mrs x4, TFSR_EL2
|
||||
0x05,0x56,0x3e,0xd5 == mrs x5, TFSR_EL3
|
||||
0x06,0x56,0x3d,0xd5 == mrs x6, TFSR_EL12
|
||||
0x27,0x56,0x38,0xd5 == mrs x7, TFSRE0_EL1
|
||||
0x87,0x00,0x39,0xd5 == mrs x7, GMID_EL1
|
||||
0x9f,0x40,0x03,0xd5 == msr TCO, #0
|
||||
0xe0,0x42,0x1b,0xd5 == msr TCO, x0
|
||||
0xc1,0x10,0x18,0xd5 == msr GCR_EL1, x1
|
||||
0xa2,0x10,0x18,0xd5 == msr RGSR_EL1, x2
|
||||
0x03,0x56,0x18,0xd5 == msr TFSR_EL1, x3
|
||||
0x04,0x56,0x1c,0xd5 == msr TFSR_EL2, x4
|
||||
0x05,0x56,0x1e,0xd5 == msr TFSR_EL3, x5
|
||||
0x06,0x56,0x1d,0xd5 == msr TFSR_EL12, x6
|
||||
0x27,0x56,0x18,0xd5 == msr TFSRE0_EL1, x7
|
||||
0x20,0x00,0xc2,0x9a == subp x0, x1, x2
|
||||
0xe0,0x03,0xdf,0x9a == subp x0, sp, sp
|
||||
0x20,0x00,0xc2,0xba == subps x0, x1, x2
|
||||
0xe0,0x03,0xdf,0xba == subps x0, sp, sp
|
||||
0x1f,0x00,0xc1,0xba == subps xzr, x0, x1
|
||||
0x1f,0x00,0xc1,0xba == subps xzr, x0, x1
|
||||
0xff,0x03,0xdf,0xba == subps xzr, sp, sp
|
||||
0xff,0x03,0xdf,0xba == subps xzr, sp, sp
|
||||
0x20,0x00,0x60,0xd9 == ldg x0, [x1]
|
||||
0xe2,0x03,0x70,0xd9 == ldg x2, [sp, #-4096]
|
||||
0x83,0xf0,0x6f,0xd9 == ldg x3, [x4, #4080]
|
||||
0x20,0x00,0xe0,0xd9 == ldgm x0, [x1]
|
||||
0xe1,0x03,0xe0,0xd9 == ldgm x1, [sp]
|
||||
0x5f,0x00,0xe0,0xd9 == ldgm xzr, [x2]
|
||||
0x20,0x00,0xa0,0xd9 == stgm x0, [x1]
|
||||
0xe1,0x03,0xa0,0xd9 == stgm x1, [sp]
|
||||
0x5f,0x00,0xa0,0xd9 == stgm xzr, [x2]
|
||||
0x20,0x00,0x20,0xd9 == stzgm x0, [x1]
|
||||
0xe1,0x03,0x20,0xd9 == stzgm x1, [sp]
|
||||
0x5f,0x00,0x20,0xd9 == stzgm xzr, [x2]
|
||||
248
thirdparty/capstone/suite/MC/AArch64/armv8.5a-mte.txt.cs
vendored
Normal file
248
thirdparty/capstone/suite/MC/AArch64/armv8.5a-mte.txt.cs
vendored
Normal file
@@ -0,0 +1,248 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
0x20,0x10,0xdf,0x9a = irg x0, x1
|
||||
0x3f,0x10,0xdf,0x9a = irg sp, x1
|
||||
0xe0,0x13,0xdf,0x9a = irg x0, sp
|
||||
0x20,0x10,0xc2,0x9a = irg x0, x1, x2
|
||||
0x3f,0x10,0xc2,0x9a = irg sp, x1, x2
|
||||
0x20,0x10,0xdf,0x9a = irg x0, x1
|
||||
0x3f,0x10,0xdf,0x9a = irg sp, x1
|
||||
0xe0,0x13,0xdf,0x9a = irg x0, sp
|
||||
0x20,0x10,0xc2,0x9a = irg x0, x1, x2
|
||||
0x3f,0x10,0xc2,0x9a = irg sp, x1, x2
|
||||
0x20,0x04,0x80,0x91 = addg x0, x1, #0, #1
|
||||
0x5f,0x0c,0x82,0x91 = addg sp, x2, #32, #3
|
||||
0xe0,0x17,0x84,0x91 = addg x0, sp, #64, #5
|
||||
0x83,0x18,0xbf,0x91 = addg x3, x4, #1008, #6
|
||||
0xc5,0x3c,0x87,0x91 = addg x5, x6, #112, #15
|
||||
0x20,0x04,0x80,0xd1 = subg x0, x1, #0, #1
|
||||
0x5f,0x0c,0x82,0xd1 = subg sp, x2, #32, #3
|
||||
0xe0,0x17,0x84,0xd1 = subg x0, sp, #64, #5
|
||||
0x83,0x18,0xbf,0xd1 = subg x3, x4, #1008, #6
|
||||
0xc5,0x3c,0x87,0xd1 = subg x5, x6, #112, #15
|
||||
0x20,0x04,0x80,0x91 = addg x0, x1, #0, #1
|
||||
0x5f,0x0c,0x82,0x91 = addg sp, x2, #32, #3
|
||||
0xe0,0x17,0x84,0x91 = addg x0, sp, #64, #5
|
||||
0x83,0x18,0xbf,0x91 = addg x3, x4, #1008, #6
|
||||
0xc5,0x3c,0x87,0x91 = addg x5, x6, #112, #15
|
||||
0x20,0x04,0x80,0xd1 = subg x0, x1, #0, #1
|
||||
0x5f,0x0c,0x82,0xd1 = subg sp, x2, #32, #3
|
||||
0xe0,0x17,0x84,0xd1 = subg x0, sp, #64, #5
|
||||
0x83,0x18,0xbf,0xd1 = subg x3, x4, #1008, #6
|
||||
0xc5,0x3c,0x87,0xd1 = subg x5, x6, #112, #15
|
||||
0x20,0x14,0xc2,0x9a = gmi x0, x1, x2
|
||||
0xe3,0x17,0xc4,0x9a = gmi x3, sp, x4
|
||||
0x1f,0x14,0xde,0x9a = gmi xzr, x0, x30
|
||||
0x1e,0x14,0xdf,0x9a = gmi x30, x0, xzr
|
||||
0x20,0x14,0xc2,0x9a = gmi x0, x1, x2
|
||||
0xe3,0x17,0xc4,0x9a = gmi x3, sp, x4
|
||||
0x1f,0x14,0xde,0x9a = gmi xzr, x0, x30
|
||||
0x1e,0x14,0xdf,0x9a = gmi x30, x0, xzr
|
||||
0x20,0x00,0xc2,0x9a = subp x0, x1, x2
|
||||
0x20,0x00,0xc2,0xba = subps x0, x1, x2
|
||||
0xe0,0x03,0xdf,0x9a = subp x0, sp, sp
|
||||
0xe0,0x03,0xdf,0xba = subps x0, sp, sp
|
||||
0x1f,0x00,0xc1,0xba = subps xzr, x0, x1
|
||||
0xff,0x03,0xdf,0xba = subps xzr, sp, sp
|
||||
0x20,0x00,0xc2,0x9a = subp x0, x1, x2
|
||||
0x20,0x00,0xc2,0xba = subps x0, x1, x2
|
||||
0xe0,0x03,0xdf,0x9a = subp x0, sp, sp
|
||||
0xe0,0x03,0xdf,0xba = subps x0, sp, sp
|
||||
0x1f,0x00,0xc1,0xba = subps xzr, x0, x1
|
||||
0xff,0x03,0xdf,0xba = subps xzr, sp, sp
|
||||
0x20,0x08,0x30,0xd9 = stg x0, [x1, #-4096]
|
||||
0x41,0xf8,0x2f,0xd9 = stg x1, [x2, #4080]
|
||||
0xe2,0x1b,0x20,0xd9 = stg x2, [sp, #16]
|
||||
0x23,0x08,0x20,0xd9 = stg x3, [x1]
|
||||
0x3f,0x08,0x20,0xd9 = stg sp, [x1]
|
||||
0x20,0x08,0x30,0xd9 = stg x0, [x1, #-4096]
|
||||
0x41,0xf8,0x2f,0xd9 = stg x1, [x2, #4080]
|
||||
0xe2,0x1b,0x20,0xd9 = stg x2, [sp, #16]
|
||||
0x23,0x08,0x20,0xd9 = stg x3, [x1]
|
||||
0x3f,0x08,0x20,0xd9 = stg sp, [x1]
|
||||
0x20,0x08,0x70,0xd9 = stzg x0, [x1, #-4096]
|
||||
0x41,0xf8,0x6f,0xd9 = stzg x1, [x2, #4080]
|
||||
0xe2,0x1b,0x60,0xd9 = stzg x2, [sp, #16]
|
||||
0x23,0x08,0x60,0xd9 = stzg x3, [x1]
|
||||
0x3f,0x08,0x60,0xd9 = stzg sp, [x1]
|
||||
0x20,0x08,0x70,0xd9 = stzg x0, [x1, #-4096]
|
||||
0x41,0xf8,0x6f,0xd9 = stzg x1, [x2, #4080]
|
||||
0xe2,0x1b,0x60,0xd9 = stzg x2, [sp, #16]
|
||||
0x23,0x08,0x60,0xd9 = stzg x3, [x1]
|
||||
0x3f,0x08,0x60,0xd9 = stzg sp, [x1]
|
||||
0x20,0x0c,0x30,0xd9 = stg x0, [x1, #-4096]!
|
||||
0x41,0xfc,0x2f,0xd9 = stg x1, [x2, #4080]!
|
||||
0xe2,0x1f,0x20,0xd9 = stg x2, [sp, #16]!
|
||||
0xff,0x1f,0x20,0xd9 = stg sp, [sp, #16]!
|
||||
0x20,0x0c,0x30,0xd9 = stg x0, [x1, #-4096]!
|
||||
0x41,0xfc,0x2f,0xd9 = stg x1, [x2, #4080]!
|
||||
0xe2,0x1f,0x20,0xd9 = stg x2, [sp, #16]!
|
||||
0xff,0x1f,0x20,0xd9 = stg sp, [sp, #16]!
|
||||
0x20,0x0c,0x70,0xd9 = stzg x0, [x1, #-4096]!
|
||||
0x41,0xfc,0x6f,0xd9 = stzg x1, [x2, #4080]!
|
||||
0xe2,0x1f,0x60,0xd9 = stzg x2, [sp, #16]!
|
||||
0xff,0x1f,0x60,0xd9 = stzg sp, [sp, #16]!
|
||||
0x20,0x0c,0x70,0xd9 = stzg x0, [x1, #-4096]!
|
||||
0x41,0xfc,0x6f,0xd9 = stzg x1, [x2, #4080]!
|
||||
0xe2,0x1f,0x60,0xd9 = stzg x2, [sp, #16]!
|
||||
0xff,0x1f,0x60,0xd9 = stzg sp, [sp, #16]!
|
||||
0x20,0x04,0x30,0xd9 = stg x0, [x1], #-4096
|
||||
0x41,0xf4,0x2f,0xd9 = stg x1, [x2], #4080
|
||||
0xe2,0x17,0x20,0xd9 = stg x2, [sp], #16
|
||||
0xff,0x17,0x20,0xd9 = stg sp, [sp], #16
|
||||
0x20,0x04,0x30,0xd9 = stg x0, [x1], #-4096
|
||||
0x41,0xf4,0x2f,0xd9 = stg x1, [x2], #4080
|
||||
0xe2,0x17,0x20,0xd9 = stg x2, [sp], #16
|
||||
0xff,0x17,0x20,0xd9 = stg sp, [sp], #16
|
||||
0x20,0x04,0x70,0xd9 = stzg x0, [x1], #-4096
|
||||
0x41,0xf4,0x6f,0xd9 = stzg x1, [x2], #4080
|
||||
0xe2,0x17,0x60,0xd9 = stzg x2, [sp], #16
|
||||
0xff,0x17,0x60,0xd9 = stzg sp, [sp], #16
|
||||
0x20,0x04,0x70,0xd9 = stzg x0, [x1], #-4096
|
||||
0x41,0xf4,0x6f,0xd9 = stzg x1, [x2], #4080
|
||||
0xe2,0x17,0x60,0xd9 = stzg x2, [sp], #16
|
||||
0xff,0x17,0x60,0xd9 = stzg sp, [sp], #16
|
||||
0x20,0x08,0xb0,0xd9 = st2g x0, [x1, #-4096]
|
||||
0x41,0xf8,0xaf,0xd9 = st2g x1, [x2, #4080]
|
||||
0xe2,0x1b,0xa0,0xd9 = st2g x2, [sp, #16]
|
||||
0x23,0x08,0xa0,0xd9 = st2g x3, [x1]
|
||||
0x3f,0x08,0xa0,0xd9 = st2g sp, [x1]
|
||||
0x20,0x08,0xb0,0xd9 = st2g x0, [x1, #-4096]
|
||||
0x41,0xf8,0xaf,0xd9 = st2g x1, [x2, #4080]
|
||||
0xe2,0x1b,0xa0,0xd9 = st2g x2, [sp, #16]
|
||||
0x23,0x08,0xa0,0xd9 = st2g x3, [x1]
|
||||
0x3f,0x08,0xa0,0xd9 = st2g sp, [x1]
|
||||
0x20,0x08,0xf0,0xd9 = stz2g x0, [x1, #-4096]
|
||||
0x41,0xf8,0xef,0xd9 = stz2g x1, [x2, #4080]
|
||||
0xe2,0x1b,0xe0,0xd9 = stz2g x2, [sp, #16]
|
||||
0x23,0x08,0xe0,0xd9 = stz2g x3, [x1]
|
||||
0x3f,0x08,0xe0,0xd9 = stz2g sp, [x1]
|
||||
0x20,0x08,0xf0,0xd9 = stz2g x0, [x1, #-4096]
|
||||
0x41,0xf8,0xef,0xd9 = stz2g x1, [x2, #4080]
|
||||
0xe2,0x1b,0xe0,0xd9 = stz2g x2, [sp, #16]
|
||||
0x23,0x08,0xe0,0xd9 = stz2g x3, [x1]
|
||||
0x3f,0x08,0xe0,0xd9 = stz2g sp, [x1]
|
||||
0x20,0x0c,0xb0,0xd9 = st2g x0, [x1, #-4096]!
|
||||
0x41,0xfc,0xaf,0xd9 = st2g x1, [x2, #4080]!
|
||||
0xe2,0x1f,0xa0,0xd9 = st2g x2, [sp, #16]!
|
||||
0xff,0x1f,0xa0,0xd9 = st2g sp, [sp, #16]!
|
||||
0x20,0x0c,0xb0,0xd9 = st2g x0, [x1, #-4096]!
|
||||
0x41,0xfc,0xaf,0xd9 = st2g x1, [x2, #4080]!
|
||||
0xe2,0x1f,0xa0,0xd9 = st2g x2, [sp, #16]!
|
||||
0xff,0x1f,0xa0,0xd9 = st2g sp, [sp, #16]!
|
||||
0x20,0x0c,0xf0,0xd9 = stz2g x0, [x1, #-4096]!
|
||||
0x41,0xfc,0xef,0xd9 = stz2g x1, [x2, #4080]!
|
||||
0xe2,0x1f,0xe0,0xd9 = stz2g x2, [sp, #16]!
|
||||
0xff,0x1f,0xe0,0xd9 = stz2g sp, [sp, #16]!
|
||||
0x20,0x0c,0xf0,0xd9 = stz2g x0, [x1, #-4096]!
|
||||
0x41,0xfc,0xef,0xd9 = stz2g x1, [x2, #4080]!
|
||||
0xe2,0x1f,0xe0,0xd9 = stz2g x2, [sp, #16]!
|
||||
0xff,0x1f,0xe0,0xd9 = stz2g sp, [sp, #16]!
|
||||
0x20,0x04,0xb0,0xd9 = st2g x0, [x1], #-4096
|
||||
0x41,0xf4,0xaf,0xd9 = st2g x1, [x2], #4080
|
||||
0xe2,0x17,0xa0,0xd9 = st2g x2, [sp], #16
|
||||
0xff,0x17,0xa0,0xd9 = st2g sp, [sp], #16
|
||||
0x20,0x04,0xb0,0xd9 = st2g x0, [x1], #-4096
|
||||
0x41,0xf4,0xaf,0xd9 = st2g x1, [x2], #4080
|
||||
0xe2,0x17,0xa0,0xd9 = st2g x2, [sp], #16
|
||||
0xff,0x17,0xa0,0xd9 = st2g sp, [sp], #16
|
||||
0x20,0x04,0xf0,0xd9 = stz2g x0, [x1], #-4096
|
||||
0x41,0xf4,0xef,0xd9 = stz2g x1, [x2], #4080
|
||||
0xe2,0x17,0xe0,0xd9 = stz2g x2, [sp], #16
|
||||
0xff,0x17,0xe0,0xd9 = stz2g sp, [sp], #16
|
||||
0x20,0x04,0xf0,0xd9 = stz2g x0, [x1], #-4096
|
||||
0x41,0xf4,0xef,0xd9 = stz2g x1, [x2], #4080
|
||||
0xe2,0x17,0xe0,0xd9 = stz2g x2, [sp], #16
|
||||
0xff,0x17,0xe0,0xd9 = stz2g sp, [sp], #16
|
||||
0x40,0x04,0x20,0x69 = stgp x0, x1, [x2, #-1024]
|
||||
0x40,0x84,0x1f,0x69 = stgp x0, x1, [x2, #1008]
|
||||
0xe0,0x87,0x00,0x69 = stgp x0, x1, [sp, #16]
|
||||
0x5f,0x84,0x00,0x69 = stgp xzr, x1, [x2, #16]
|
||||
0x40,0xfc,0x00,0x69 = stgp x0, xzr, [x2, #16]
|
||||
0x40,0x7c,0x00,0x69 = stgp x0, xzr, [x2]
|
||||
0x40,0x04,0x20,0x69 = stgp x0, x1, [x2, #-1024]
|
||||
0x40,0x84,0x1f,0x69 = stgp x0, x1, [x2, #1008]
|
||||
0xe0,0x87,0x00,0x69 = stgp x0, x1, [sp, #16]
|
||||
0x5f,0x84,0x00,0x69 = stgp xzr, x1, [x2, #16]
|
||||
0x40,0xfc,0x00,0x69 = stgp x0, xzr, [x2, #16]
|
||||
0x40,0x7c,0x00,0x69 = stgp x0, xzr, [x2]
|
||||
0x40,0x04,0xa0,0x69 = stgp x0, x1, [x2, #-1024]!
|
||||
0x40,0x84,0x9f,0x69 = stgp x0, x1, [x2, #1008]!
|
||||
0xe0,0x87,0x80,0x69 = stgp x0, x1, [sp, #16]!
|
||||
0x5f,0x84,0x80,0x69 = stgp xzr, x1, [x2, #16]!
|
||||
0x40,0xfc,0x80,0x69 = stgp x0, xzr, [x2, #16]!
|
||||
0x40,0x04,0xa0,0x69 = stgp x0, x1, [x2, #-1024]!
|
||||
0x40,0x84,0x9f,0x69 = stgp x0, x1, [x2, #1008]!
|
||||
0xe0,0x87,0x80,0x69 = stgp x0, x1, [sp, #16]!
|
||||
0x5f,0x84,0x80,0x69 = stgp xzr, x1, [x2, #16]!
|
||||
0x40,0xfc,0x80,0x69 = stgp x0, xzr, [x2, #16]!
|
||||
0x40,0x04,0xa0,0x68 = stgp x0, x1, [x2], #-1024
|
||||
0x40,0x84,0x9f,0x68 = stgp x0, x1, [x2], #1008
|
||||
0xe0,0x87,0x80,0x68 = stgp x0, x1, [sp], #16
|
||||
0x5f,0x84,0x80,0x68 = stgp xzr, x1, [x2], #16
|
||||
0x40,0xfc,0x80,0x68 = stgp x0, xzr, [x2], #16
|
||||
0x40,0x04,0xa0,0x68 = stgp x0, x1, [x2], #-1024
|
||||
0x40,0x84,0x9f,0x68 = stgp x0, x1, [x2], #1008
|
||||
0xe0,0x87,0x80,0x68 = stgp x0, x1, [sp], #16
|
||||
0x5f,0x84,0x80,0x68 = stgp xzr, x1, [x2], #16
|
||||
0x40,0xfc,0x80,0x68 = stgp x0, xzr, [x2], #16
|
||||
0x20,0x00,0x60,0xd9 = ldg x0, [x1]
|
||||
0xe2,0x03,0x70,0xd9 = ldg x2, [sp, #-4096]
|
||||
0x83,0xf0,0x6f,0xd9 = ldg x3, [x4, #4080]
|
||||
0x20,0x00,0x60,0xd9 = ldg x0, [x1]
|
||||
0xe2,0x03,0x70,0xd9 = ldg x2, [sp, #-4096]
|
||||
0x83,0xf0,0x6f,0xd9 = ldg x3, [x4, #4080]
|
||||
0x20,0x00,0xe0,0xd9 = ldgm x0, [x1]
|
||||
0xe1,0x03,0xe0,0xd9 = ldgm x1, [sp]
|
||||
0x5f,0x00,0xe0,0xd9 = ldgm xzr, [x2]
|
||||
0x20,0x00,0xa0,0xd9 = stgm x0, [x1]
|
||||
0xe1,0x03,0xa0,0xd9 = stgm x1, [sp]
|
||||
0x5f,0x00,0xa0,0xd9 = stgm xzr, [x2]
|
||||
0x20,0x00,0x20,0xd9 = stzgm x0, [x1]
|
||||
0xe1,0x03,0x20,0xd9 = stzgm x1, [sp]
|
||||
0x5f,0x00,0x20,0xd9 = stzgm xzr, [x2]
|
||||
0x20,0x00,0xe0,0xd9 = ldgm x0, [x1]
|
||||
0xe1,0x03,0xe0,0xd9 = ldgm x1, [sp]
|
||||
0x5f,0x00,0xe0,0xd9 = ldgm xzr, [x2]
|
||||
0x20,0x00,0xa0,0xd9 = stgm x0, [x1]
|
||||
0xe1,0x03,0xa0,0xd9 = stgm x1, [sp]
|
||||
0x5f,0x00,0xa0,0xd9 = stgm xzr, [x2]
|
||||
0x20,0x00,0x20,0xd9 = stzgm x0, [x1]
|
||||
0xe1,0x03,0x20,0xd9 = stzgm x1, [sp]
|
||||
0x5f,0x00,0x20,0xd9 = stzgm xzr, [x2]
|
||||
0x60,0x76,0x08,0xd5 = dc igvac, x0
|
||||
0x81,0x76,0x08,0xd5 = dc igsw, x1
|
||||
0x82,0x7a,0x08,0xd5 = dc cgsw, x2
|
||||
0x83,0x7e,0x08,0xd5 = dc cigsw, x3
|
||||
0x64,0x7a,0x0b,0xd5 = dc cgvac, x4
|
||||
0x65,0x7c,0x0b,0xd5 = dc cgvap, x5
|
||||
0x66,0x7d,0x0b,0xd5 = dc cgvadp, x6
|
||||
0x67,0x7e,0x0b,0xd5 = dc cigvac, x7
|
||||
0x68,0x74,0x0b,0xd5 = dc gva, x8
|
||||
0xa9,0x76,0x08,0xd5 = dc igdvac, x9
|
||||
0xca,0x76,0x08,0xd5 = dc igdsw, x10
|
||||
0xcb,0x7a,0x08,0xd5 = dc cgdsw, x11
|
||||
0xcc,0x7e,0x08,0xd5 = dc cigdsw, x12
|
||||
0xad,0x7a,0x0b,0xd5 = dc cgdvac, x13
|
||||
0xae,0x7c,0x0b,0xd5 = dc cgdvap, x14
|
||||
0xaf,0x7d,0x0b,0xd5 = dc cgdvadp, x15
|
||||
0xb0,0x7e,0x0b,0xd5 = dc cigdvac, x16
|
||||
0x91,0x74,0x0b,0xd5 = dc gzva, x17
|
||||
0xe0,0x42,0x3b,0xd5 = mrs x0, TCO
|
||||
0xc1,0x10,0x38,0xd5 = mrs x1, GCR_EL1
|
||||
0xa2,0x10,0x38,0xd5 = mrs x2, RGSR_EL1
|
||||
0x03,0x56,0x38,0xd5 = mrs x3, TFSR_EL1
|
||||
0x04,0x56,0x3c,0xd5 = mrs x4, TFSR_EL2
|
||||
0x05,0x56,0x3e,0xd5 = mrs x5, TFSR_EL3
|
||||
0x06,0x56,0x3d,0xd5 = mrs x6, TFSR_EL12
|
||||
0x27,0x56,0x38,0xd5 = mrs x7, TFSRE0_EL1
|
||||
0x88,0x00,0x39,0xd5 = mrs x8, GMID_EL1
|
||||
0x9f,0x40,0x03,0xd5 = msr TCO, #0
|
||||
0xe0,0x42,0x1b,0xd5 = msr TCO, x0
|
||||
0xc1,0x10,0x18,0xd5 = msr GCR_EL1, x1
|
||||
0xa2,0x10,0x18,0xd5 = msr RGSR_EL1, x2
|
||||
0x03,0x56,0x18,0xd5 = msr TFSR_EL1, x3
|
||||
0x04,0x56,0x1c,0xd5 = msr TFSR_EL2, x4
|
||||
0x05,0x56,0x1e,0xd5 = msr TFSR_EL3, x5
|
||||
0x06,0x56,0x1d,0xd5 = msr TFSR_EL12, x6
|
||||
0x27,0x56,0x18,0xd5 = msr TFSRE0_EL1, x7
|
||||
0x88,0x00,0x19,0xd5 = msr S3_1_C0_C0_4, x8
|
||||
3
thirdparty/capstone/suite/MC/AArch64/armv8.5a-persistent-memory.s.cs
vendored
Normal file
3
thirdparty/capstone/suite/MC/AArch64/armv8.5a-persistent-memory.s.cs
vendored
Normal file
@@ -0,0 +1,3 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0x27,0x7d,0x0b,0xd5 == dc cvadp, x7
|
||||
3
thirdparty/capstone/suite/MC/AArch64/armv8.5a-persistent-memory.txt.cs
vendored
Normal file
3
thirdparty/capstone/suite/MC/AArch64/armv8.5a-persistent-memory.txt.cs
vendored
Normal file
@@ -0,0 +1,3 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0x27,0x7d,0x0b,0xd5 == dc cvadp, x7
|
||||
5
thirdparty/capstone/suite/MC/AArch64/armv8.5a-predres.s.cs
vendored
Normal file
5
thirdparty/capstone/suite/MC/AArch64/armv8.5a-predres.s.cs
vendored
Normal file
@@ -0,0 +1,5 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0x80,0x73,0x0b,0xd5 == cfp rctx, x0
|
||||
0xa1,0x73,0x0b,0xd5 == dvp rctx, x1
|
||||
0xe2,0x73,0x0b,0xd5 == cpp rctx, x2
|
||||
4
thirdparty/capstone/suite/MC/AArch64/armv8.5a-rand.s.cs
vendored
Normal file
4
thirdparty/capstone/suite/MC/AArch64/armv8.5a-rand.s.cs
vendored
Normal file
@@ -0,0 +1,4 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0x00,0x24,0x3b,0xd5 == mrs x0, RNDR
|
||||
0x21,0x24,0x3b,0xd5 == mrs x1, RNDRRS
|
||||
3
thirdparty/capstone/suite/MC/AArch64/armv8.5a-rand.txt.cs
vendored
Normal file
3
thirdparty/capstone/suite/MC/AArch64/armv8.5a-rand.txt.cs
vendored
Normal file
@@ -0,0 +1,3 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
0x00,0x24,0x3b,0xd5 = mrs x0, RNDR
|
||||
0x21,0x24,0x3b,0xd5 = mrs x1, RNDRRS
|
||||
3
thirdparty/capstone/suite/MC/AArch64/armv8.5a-sb.s.cs
vendored
Normal file
3
thirdparty/capstone/suite/MC/AArch64/armv8.5a-sb.s.cs
vendored
Normal file
@@ -0,0 +1,3 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0xff,0x30,0x03,0xd5 == sb
|
||||
13
thirdparty/capstone/suite/MC/AArch64/armv8.5a-specrestrict.s.cs
vendored
Normal file
13
thirdparty/capstone/suite/MC/AArch64/armv8.5a-specrestrict.s.cs
vendored
Normal file
@@ -0,0 +1,13 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0x89,0x03,0x38,0xd5 == mrs x9, {{id_pfr2_el1|ID_PFR2_EL1}}
|
||||
0xe8,0xd0,0x3b,0xd5 == mrs x8, {{scxtnum_el0|SCXTNUM_EL0}}
|
||||
0xe7,0xd0,0x38,0xd5 == mrs x7, {{scxtnum_el1|SCXTNUM_EL1}}
|
||||
0xe6,0xd0,0x3c,0xd5 == mrs x6, {{scxtnum_el2|SCXTNUM_EL2}}
|
||||
0xe5,0xd0,0x3e,0xd5 == mrs x5, {{scxtnum_el3|SCXTNUM_EL3}}
|
||||
0xe4,0xd0,0x3d,0xd5 == mrs x4, {{scxtnum_el12|SCXTNUM_EL12}}
|
||||
0xe8,0xd0,0x1b,0xd5 == msr {{scxtnum_el0|SCXTNUM_EL0}}, x8
|
||||
0xe7,0xd0,0x18,0xd5 == msr {{scxtnum_el1|SCXTNUM_EL1}}, x7
|
||||
0xe6,0xd0,0x1c,0xd5 == msr {{scxtnum_el2|SCXTNUM_EL2}}, x6
|
||||
0xe5,0xd0,0x1e,0xd5 == msr {{scxtnum_el3|SCXTNUM_EL3}}, x5
|
||||
0xe4,0xd0,0x1d,0xd5 == msr {{scxtnum_el12|SCXTNUM_EL12}}, x4
|
||||
5
thirdparty/capstone/suite/MC/AArch64/armv8.5a-ssbs.s.cs
vendored
Normal file
5
thirdparty/capstone/suite/MC/AArch64/armv8.5a-ssbs.s.cs
vendored
Normal file
@@ -0,0 +1,5 @@
|
||||
# CS_ARCH_AARCH64, 0, None
|
||||
|
||||
0xc2,0x42,0x3b,0xd5 == mrs x2, {{ssbs|SSBS}}
|
||||
0xc3,0x42,0x1b,0xd5 == msr {{ssbs|SSBS}}, x3
|
||||
0x3f,0x41,0x03,0xd5 == msr {{ssbs|SSBS}}, #1
|
||||
6
thirdparty/capstone/suite/MC/AArch64/armv8.5a-ssbs.txt.cs
vendored
Normal file
6
thirdparty/capstone/suite/MC/AArch64/armv8.5a-ssbs.txt.cs
vendored
Normal file
@@ -0,0 +1,6 @@
|
||||
# CS_ARCH_AARCH64, None, None
|
||||
# This regression test file is new. The option flags could not be determined.
|
||||
# LLVM uses the following mattr = ['mattr=+ssbs', 'mattr=+v8.5a', 'mattr=+v8r', 'mattr=-ssbs']
|
||||
0x3f 0x41 0x03 0xd5 == msr SSBS, #1
|
||||
0xc3 0x42 0x1b 0xd5 == msr SSBS, x3
|
||||
0xc2 0x42 0x3b 0xd5 == mrs x2, SSBS
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user