Hello_User/XenonRecomp
1
0
Fork 0
mirror of https://github.com/hedge-dev/XenonRecomp.git synced 2025-07-26 23:13:54 +00:00
Code Issues Packages Projects Releases Wiki Activity

Initial Commit

Browse Source
This commit is contained in:
Sajid
2024-09-07 18:00:09 +06:00
commit 0f9a53f75a
3352 changed files with 1563708 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

120
thirdparty/capstone/tests/MC/AArch64/ete-sysregs.s.yaml vendored Normal file
View File

@@ -0,0 +1,120 @@
test_cases:
-
input:
bytes: [ 0x00, 0x0a, 0x31, 0xd5 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
expected:
insns:
-
asm_text: "mrs x0, TRCRSR"
-
input:
bytes: [ 0x80, 0x08, 0x31, 0xd5 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
expected:
insns:
-
asm_text: "mrs x0, TRCEXTINSELR"
-
input:
bytes: [ 0x80, 0x08, 0x31, 0xd5 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
expected:
insns:
-
asm_text: "mrs x0, TRCEXTINSELR"
-
input:
bytes: [ 0x80, 0x09, 0x31, 0xd5 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
expected:
insns:
-
asm_text: "mrs x0, TRCEXTINSELR1"
-
input:
bytes: [ 0x80, 0x0a, 0x31, 0xd5 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
expected:
insns:
-
asm_text: "mrs x0, TRCEXTINSELR2"
-
input:
bytes: [ 0x80, 0x0b, 0x31, 0xd5 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
expected:
insns:
-
asm_text: "mrs x0, TRCEXTINSELR3"
-
input:
bytes: [ 0x00, 0x0a, 0x11, 0xd5 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
expected:
insns:
-
asm_text: "msr TRCRSR, x0"
-
input:
bytes: [ 0x80, 0x08, 0x11, 0xd5 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
expected:
insns:
-
asm_text: "msr TRCEXTINSELR, x0"
-
input:
bytes: [ 0x80, 0x08, 0x11, 0xd5 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
expected:
insns:
-
asm_text: "msr TRCEXTINSELR, x0"
-
input:
bytes: [ 0x80, 0x09, 0x11, 0xd5 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
expected:
insns:
-
asm_text: "msr TRCEXTINSELR1, x0"
-
input:
bytes: [ 0x80, 0x0a, 0x11, 0xd5 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
expected:
insns:
-
asm_text: "msr TRCEXTINSELR2, x0"
-
input:
bytes: [ 0x80, 0x0b, 0x11, 0xd5 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
expected:
insns:
-
asm_text: "msr TRCEXTINSELR3, x0"