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Sajid
2024-09-07 18:00:09 +06:00
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4
thirdparty/capstone/tests/details/README.md vendored Normal file
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## Test instruction details
This directory contains test cases for the `cs_detail` struct.
Test files are consumed by the `cstest` tool (see: `suite/cstest`).

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thirdparty/capstone/tests/details/aarch64.yaml vendored Normal file
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test_cases:
-
input:
bytes: [ 0x09, 0x00, 0x38, 0xd5, 0xbf, 0x40, 0x00, 0xd5, 0x0c, 0x05, 0x13, 0xd5, 0x20, 0x50, 0x02, 0x0e, 0x20, 0xe4, 0x3d, 0x0f, 0x00, 0x18, 0xa0, 0x5f, 0xa2, 0x00, 0xae, 0x9e, 0x9f, 0x37, 0x03, 0xd5, 0xbf, 0x33, 0x03, 0xd5, 0xdf, 0x3f, 0x03, 0xd5, 0x21, 0x7c, 0x02, 0x9b, 0x21, 0x7c, 0x00, 0x53, 0x00, 0x40, 0x21, 0x4b, 0xe1, 0x0b, 0x40, 0xb9, 0x20, 0x04, 0x81, 0xda, 0x20, 0x08, 0x02, 0x8b, 0x10, 0x5b, 0xe8, 0x3c, 0xfd, 0x7b, 0xba, 0xa9, 0xfd, 0xc7, 0x43, 0xf8 ]
arch: "CS_ARCH_AARCH64"
options: [ "CS_OPT_DETAIL" ]
address: 0x2c
expected:
insns:
-
asm_text: "mrs x9, MIDR_EL1"
details:
aarch64:
operands:
-
type: AARCH64_OP_REG
reg: x9
access: CS_AC_WRITE
-
type: AARCH64_OP_SYSREG
sub_type: AARCH64_OP_REG_MRS
sys_raw_val: 0xc000
cc: AArch64CC_Invalid
update_flags: 1
regs_write: [ nzcv, x9 ]
-
asm_text: "msr SPSel, #0"
details:
aarch64:
operands:
-
type: AARCH64_OP_SYSALIAS
sub_type: AARCH64_OP_PSTATEIMM0_15
sys_raw_val: 0x5
-
type: AARCH64_OP_IMM
imm: 0x0
access: CS_AC_READ
cc: AArch64CC_Invalid
-
asm_text: "msr DBGDTRTX_EL0, x12"
details:
aarch64:
operands:
-
type: AARCH64_OP_SYSREG
sub_type: AARCH64_OP_REG_MSR
sys_raw_val: 0x9828
-
type: AARCH64_OP_REG
reg: x12
access: CS_AC_READ
cc: AArch64CC_Invalid
regs_read: [ x12 ]
-
asm_text: "tbx v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b"
details:
aarch64:
operands:
-
type: AARCH64_OP_REG
reg: d0
access: CS_AC_READ_WRITE
vas: AARCH64LAYOUT_VL_8B
is_vreg: 1
-
type: AARCH64_OP_REG
reg: q1
access: CS_AC_READ
vas: AARCH64LAYOUT_VL_16B
is_vreg: 1
-
type: AARCH64_OP_REG
reg: q2
access: CS_AC_READ
vas: AARCH64LAYOUT_VL_16B
is_vreg: 1
-
type: AARCH64_OP_REG
reg: q3
access: CS_AC_READ
vas: AARCH64LAYOUT_VL_16B
is_vreg: 1
-
type: AARCH64_OP_REG
reg: d2
access: CS_AC_READ
vas: AARCH64LAYOUT_VL_8B
is_vreg: 1
cc: AArch64CC_Invalid
writeback: 1
regs_read: [ d0, q1, q2, q3, d2 ]
regs_write: [ d0 ]
-
asm_text: "scvtf v0.2s, v1.2s, #3"
details:
aarch64:
operands:
-
type: AARCH64_OP_REG
reg: d0
access: CS_AC_WRITE
vas: AARCH64LAYOUT_VL_2S
-
type: AARCH64_OP_REG
reg: d1
access: CS_AC_READ
vas: AARCH64LAYOUT_VL_2S
-
type: AARCH64_OP_IMM
imm: 0x3
access: CS_AC_READ
cc: AArch64CC_Invalid
regs_read: [ d1 ]
regs_write: [ d0 ]
-
asm_text: "fmla s0, s0, v0.s[3]"
details:
aarch64:
operands:
-
type: AARCH64_OP_REG
reg: s0
access: CS_AC_READ_WRITE
-
type: AARCH64_OP_REG
reg: s0
access: CS_AC_READ
-
type: AARCH64_OP_REG
reg: q0
access: CS_AC_READ
vas: AARCH64LAYOUT_VL_S
vector_index: 3
vector_index_is_set: true
cc: AArch64CC_Invalid
writeback: 1
regs_read: [ fpcr, s0, q0 ]
regs_write: [ s0 ]
-
asm_text: "fmov x2, v5.d[1]"
details:
aarch64:
operands:
-
type: AARCH64_OP_REG
reg: x2
access: CS_AC_WRITE
-
type: AARCH64_OP_REG
reg: q5
access: CS_AC_READ
vas: AARCH64LAYOUT_VL_D
vector_index: 1
vector_index_is_set: true
cc: AArch64CC_Invalid
regs_read: [ q5 ]
regs_write: [ x2 ]
-
asm_text: "dsb nsh"
details:
aarch64:
operands:
-
type: AARCH64_OP_SYSALIAS
sub_type: AARCH64_OP_DB
sys_raw_val: 0x7
cc: AArch64CC_Invalid
-
asm_text: "dmb osh"
details:
aarch64:
operands:
-
type: AARCH64_OP_SYSALIAS
sub_type: AARCH64_OP_DB
sys_raw_val: 0x3
cc: AArch64CC_Invalid
-
asm_text: "isb"
-
asm_text: "mul x1, x1, x2"
details:
aarch64:
operands:
-
type: AARCH64_OP_REG
reg: x1
access: CS_AC_WRITE
-
type: AARCH64_OP_REG
reg: x1
access: CS_AC_READ
-
type: AARCH64_OP_REG
reg: x2
access: CS_AC_READ
cc: AArch64CC_Invalid
regs_read: [ x1, x2 ]
regs_write: [ x1 ]
-
asm_text: "lsr w1, w1, #0"
details:
aarch64:
operands:
-
type: AARCH64_OP_REG
reg: w1
access: CS_AC_WRITE
-
type: AARCH64_OP_REG
reg: w1
access: CS_AC_READ
cc: AArch64CC_Invalid
regs_read: [ w1 ]
regs_write: [ w1 ]
-
asm_text: "sub w0, w0, w1, uxtw"
details:
aarch64:
operands:
-
type: AARCH64_OP_REG
reg: w0
access: CS_AC_WRITE
-
type: AARCH64_OP_REG
reg: w0
access: CS_AC_READ
-
type: AARCH64_OP_REG
reg: w1
access: CS_AC_READ
ext: AARCH64_EXT_UXTW
cc: AArch64CC_Invalid
regs_read: [ w0, w1 ]
regs_write: [ w0 ]
-
asm_text: "ldr w1, [sp, #8]"
details:
aarch64:
operands:
-
type: AARCH64_OP_REG
reg: w1
access: CS_AC_WRITE
-
type: AARCH64_OP_MEM
mem_base: sp
mem_disp: 0x8
access: CS_AC_READ
cc: AArch64CC_Invalid
regs_read: [ sp ]
regs_write: [ w1 ]
-
asm_text: "cneg x0, x1, ne"
details:
aarch64:
operands:
-
type: AARCH64_OP_REG
reg: x0
access: CS_AC_WRITE
-
type: AARCH64_OP_REG
reg: x1
access: CS_AC_READ
cc: AArch64CC_NE
regs_read: [ nzcv, x1 ]
regs_write: [ x0 ]
-
asm_text: "add x0, x1, x2, lsl #2"
details:
aarch64:
operands:
-
type: AARCH64_OP_REG
reg: x0
access: CS_AC_WRITE
-
type: AARCH64_OP_REG
reg: x1
access: CS_AC_READ
-
type: AARCH64_OP_REG
reg: x2
access: CS_AC_READ
shift_type: AARCH64_SFT_LSL
shift_value: 2
cc: AArch64CC_Invalid
regs_read: [ x1, x2 ]
regs_write: [ x0 ]
-
asm_text: "ldr q16, [x24, w8, uxtw #4]"
details:
aarch64:
operands:
-
type: AARCH64_OP_REG
reg: q16
access: CS_AC_WRITE
-
type: AARCH64_OP_MEM
mem_base: x24
mem_index: w8
access: CS_AC_READ
shift_type: AARCH64_SFT_LSL
shift_value: 4
ext: AARCH64_EXT_UXTW
cc: AArch64CC_Invalid
regs_read: [ x24, w8 ]
regs_write: [ q16 ]
-
asm_text: "stp x29, x30, [sp, #-0x60]!"
details:
aarch64:
operands:
-
type: AARCH64_OP_REG
reg: x29
access: CS_AC_READ
-
type: AARCH64_OP_REG
reg: x30
access: CS_AC_READ
-
type: AARCH64_OP_MEM
mem_base: sp
mem_disp: -0x60
access: CS_AC_WRITE
cc: AArch64CC_Invalid
writeback: 1
regs_read: [ x29, x30, sp ]
regs_write: [ sp ]
-
asm_text: "ldr x29, [sp], #0x3c"
details:
aarch64:
operands:
-
type: AARCH64_OP_REG
reg: x29
access: CS_AC_WRITE
-
type: AARCH64_OP_MEM
mem_base: sp
access: CS_AC_READ
-
type: AARCH64_OP_IMM
imm: 0x3c
access: CS_AC_READ
post_indexed: 1
cc: AArch64CC_Invalid
writeback: 1
regs_read: [ sp ]
regs_write: [ sp, x29 ]
-
input:
bytes: [ 0xc0,0x08,0x9f,0xe0 ]
arch: "CS_ARCH_AARCH64"
options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
address: 0x0
expected:
insns:
-
asm_text: "ld1w {za0h.s[w12, 0]}, p2/z, [x6]"
details:
aarch64:
operands:
-
type: AARCH64_OP_SME
sme:
type: AARCH64_SME_OP_TILE_VEC
tile: za0.s
slice_reg: w12
slice_offset_imm: 0
is_vertical: -1
access: CS_AC_WRITE
vas: AARCH64LAYOUT_VL_S
-
type: AARCH64_OP_PRED
pred_reg: p2
access: CS_AC_READ
-
type: AARCH64_OP_MEM
mem_base: x6
access: CS_AC_READ
regs_read: [ w12, p2, x6 ]
regs_write: [ za0.s ]
groups: [ HasSME ]
-
input:
bytes: [ 0x41,0x31,0xa2,0xe0 ]
arch: "CS_ARCH_AARCH64"
options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
address: 0x0
expected:
insns:
-
asm_text: "st1w {za0h.s[w13, 1]}, p4, [x10, x2, lsl #2]"
details:
aarch64:
operands:
-
type: AARCH64_OP_SME
sme:
type: AARCH64_SME_OP_TILE_VEC
tile: za0.s
slice_reg: w13
slice_offset_imm: 1
is_vertical: -1
access: CS_AC_READ
vas: AARCH64LAYOUT_VL_S
-
type: AARCH64_OP_PRED
pred_reg: p4
access: CS_AC_READ
-
type: AARCH64_OP_MEM
mem_base: x10
mem_index: x2
access: CS_AC_WRITE
shift_type: ARM_SFT_ASR
shift_value: 2
regs_read: [ za0.s, w13, p4, x10, x2 ]
groups: [ HasSME ]
-
input:
bytes: [ 0x67,0x44,0x71,0x25 ]
arch: "CS_ARCH_AARCH64"
options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
address: 0x0
expected:
insns:
-
asm_text: "psel p7, p1, p3.s[w13, 1]"
details:
aarch64:
operands:
-
type: AARCH64_OP_PRED
pred_reg: p7
access: CS_AC_WRITE
-
type: AARCH64_OP_PRED
pred_reg: p1
access: CS_AC_READ
-
type: AARCH64_OP_PRED
pred_reg: p3
pred_vec_select: w13
pred_imm_index: 1
pred_imm_index_set: true
access: CS_AC_READ
vas: AARCH64LAYOUT_VL_S
regs_read: [ p1, p3, w13 ]
regs_write: [ p7 ]
groups: [ HasSVE2p1_or_HasSME ]
-
input:
bytes: [ 0x7f,0x47,0x03,0xd5 ]
arch: "CS_ARCH_AARCH64"
options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
address: 0x0
expected:
insns:
-
asm_text: "smstart"
details:
aarch64:
cc: AArch64CC_Invalid
groups: [ privilege ]
-
input:
bytes: [ 0x55,0x00,0x08,0xc0 ]
arch: "CS_ARCH_AARCH64"
options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
address: 0x0
expected:
insns:
-
asm_text: "zero {za0.h}"
details:
aarch64:
operands:
-
type: AARCH64_OP_SME
sme:
type: AARCH64_SME_OP_TILE
tile: za0.h
access: CS_AC_WRITE
vas: AARCH64LAYOUT_VL_H
cc: AArch64CC_Invalid
regs_write: [ za0.h ]
groups: [ HasSME ]
-
input:
bytes: [ 0x02,0xf8,0x55,0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
address: 0x0
expected:
insns:
-
asm_text: "sdot za.s[w11, 2, vgx4], { z0.h - z3.h }, z5.h[2]"
details:
aarch64:
operands:
-
type: AARCH64_OP_SME
sme:
type: AARCH64_SME_OP_TILE_VEC
tile: za
slice_reg: w11
slice_offset_imm: 2
is_vertical: -1
access: CS_AC_READ_WRITE
vas: AARCH64LAYOUT_VL_S
-
type: AARCH64_OP_REG
reg: z0
is_list_member: 1
access: CS_AC_READ
vas: AARCH64LAYOUT_VL_H
-
type: AARCH64_OP_REG
reg: z1
is_list_member: 1
access: CS_AC_READ
vas: AARCH64LAYOUT_VL_H
-
type: AARCH64_OP_REG
reg: z2
is_list_member: 1
access: CS_AC_READ
vas: AARCH64LAYOUT_VL_H
-
type: AARCH64_OP_REG
reg: z3
is_list_member: 1
access: CS_AC_READ
vas: AARCH64LAYOUT_VL_H
-
type: AARCH64_OP_REG
reg: z5
access: CS_AC_READ
vas: AARCH64LAYOUT_VL_H
vector_index: 2
vector_index_is_set: true
cc: AArch64CC_Invalid
writeback: 1
regs_read: [ za, w11, z0, z1, z2, z3, z5 ]
regs_write: [ za ]
groups: [ HasSME2 ]
-
input:
bytes: [ 0xa4,0x0e,0x06,0xc0 ]
arch: "CS_ARCH_AARCH64"
options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
address: 0x0
expected:
insns:
-
asm_text: "movaz { z4.d - z7.d }, za.d[w8, 5, vgx4]"
details:
aarch64:
operands:
-
type: AARCH64_OP_REG
reg: z4
is_list_member: 1
access: CS_AC_WRITE
vas: AARCH64LAYOUT_VL_D
-
type: AARCH64_OP_REG
reg: z5
is_list_member: 1
access: CS_AC_WRITE
vas: AARCH64LAYOUT_VL_D
-
type: AARCH64_OP_REG
reg: z6
is_list_member: 1
access: CS_AC_WRITE
vas: AARCH64LAYOUT_VL_D
-
type: AARCH64_OP_REG
reg: z7
is_list_member: 1
access: CS_AC_WRITE
vas: AARCH64LAYOUT_VL_D
-
type: AARCH64_OP_SME
sme:
type: AARCH64_SME_OP_TILE_VEC
tile: za
slice_reg: w8
slice_offset_imm: 5
is_vertical: -1
access: CS_AC_READ_WRITE
vas: AARCH64LAYOUT_VL_D
cc: AArch64CC_Invalid
writeback: 1
regs_read: [ za, w8 ]
regs_write: [ z4, z5, z6, z7, za ]
groups: [ HasSME2p1 ]
-
input:
bytes: [ 0x80,0xa0,0x8d,0xc0 ]
arch: "CS_ARCH_AARCH64"
options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
address: 0x0
expected:
insns:
-
asm_text: "luti2 { z0.s - z3.s }, zt0, z4[1]"
details:
aarch64:
operands:
-
type: AARCH64_OP_REG
reg: z0
is_list_member: 1
access: CS_AC_WRITE
vas: AARCH64LAYOUT_VL_S
-
type: AARCH64_OP_REG
reg: z1
is_list_member: 1
access: CS_AC_WRITE
vas: AARCH64LAYOUT_VL_S
-
type: AARCH64_OP_REG
reg: z2
is_list_member: 1
access: CS_AC_WRITE
vas: AARCH64LAYOUT_VL_S
-
type: AARCH64_OP_REG
reg: z3
is_list_member: 1
access: CS_AC_WRITE
vas: AARCH64LAYOUT_VL_S
-
type: AARCH64_OP_REG
reg: zt0
access: CS_AC_READ
-
type: AARCH64_OP_REG
reg: z4
access: CS_AC_READ
vector_index: 1
vector_index_is_set: true
cc: AArch64CC_Invalid
regs_read: [ zt0, z4 ]
regs_write: [ z0, z1, z2, z3 ]
groups: [ HasSME2 ]
-
input:
bytes: [ 0x00,0xb1,0x10,0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
address: 0x0
expected:
insns:
-
asm_text: "fmla za.h[w9, 0, vgx4], { z8.h - z11.h }, z0.h[0]"
details:
aarch64:
operands:
-
type: AARCH64_OP_SME
sme:
type: AARCH64_SME_OP_TILE_VEC
tile: za
slice_reg: w9
slice_offset_imm: 0
is_vertical: -1
access: CS_AC_READ_WRITE
vas: AARCH64LAYOUT_VL_H
-
type: AARCH64_OP_REG
reg: z8
is_list_member: 1
access: CS_AC_READ
vas: AARCH64LAYOUT_VL_H
-
type: AARCH64_OP_REG
reg: z9
is_list_member: 1
access: CS_AC_READ
vas: AARCH64LAYOUT_VL_H
-
type: AARCH64_OP_REG
reg: z10
is_list_member: 1
access: CS_AC_READ
vas: AARCH64LAYOUT_VL_H
-
type: AARCH64_OP_REG
reg: z11
is_list_member: 1
access: CS_AC_READ
vas: AARCH64LAYOUT_VL_H
-
type: AARCH64_OP_REG
reg: z0
access: CS_AC_READ
vas: AARCH64LAYOUT_VL_H
vector_index: 0
vector_index_is_set: true
cc: AArch64CC_Invalid
writeback: 1
regs_read: [ za, w9, z8, z9, z10, z11, z0 ]
regs_write: [ za ]
groups: [ HasSME2p1, HasSMEF16F16 ]
-
input:
bytes: [ 0x05,0xd0,0x9b,0xc1 ]
arch: "CS_ARCH_AARCH64"
options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
address: 0x0
expected:
insns:
-
asm_text: "fmlal za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z11.h[1]"
details:
aarch64:
operands:
-
type: AARCH64_OP_SME
sme:
type: AARCH64_SME_OP_TILE_VEC
tile: za
slice_reg: w10
slice_offset_ir_first: 2
slice_offset_ir_offset: 3
slice_offset_ir_set: true
is_vertical: -1
access: CS_AC_READ_WRITE
vas: AARCH64LAYOUT_VL_S
-
type: AARCH64_OP_REG
reg: z0
is_list_member: 1
access: CS_AC_READ
vas: AARCH64LAYOUT_VL_H
-
type: AARCH64_OP_REG
reg: z1
is_list_member: 1
access: CS_AC_READ
vas: AARCH64LAYOUT_VL_H
-
type: AARCH64_OP_REG
reg: z2
is_list_member: 1
access: CS_AC_READ
vas: AARCH64LAYOUT_VL_H
-
type: AARCH64_OP_REG
reg: z3
is_list_member: 1
access: CS_AC_READ
vas: AARCH64LAYOUT_VL_H
-
type: AARCH64_OP_REG
reg: z11
access: CS_AC_READ
vas: AARCH64LAYOUT_VL_H
vector_index: 1
vector_index_is_set: true
cc: AArch64CC_Invalid
writeback: 1
regs_read: [ za, w10, z0, z1, z2, z3, z11 ]
regs_write: [ za ]
groups: [ HasSME2 ]
-
input:
bytes: [ 0x15,0x50,0xdf,0x05 ]
arch: "CS_ARCH_AARCH64"
options: [ CS_OPT_DETAIL ]
address: 0x0
expected:
insns:
-
asm_text: "mov z21.d, p15/m, #-0x80"
details:
aarch64:
operands:
-
type: AARCH64_OP_REG
reg: z21
access: CS_AC_READ_WRITE
vas: AARCH64LAYOUT_VL_D
-
type: AARCH64_OP_PRED
pred_reg: p15
access: CS_AC_READ
-
type: AARCH64_OP_IMM
imm: -0x80
access: CS_AC_READ
-
input:
bytes: [ 0xd3,0x03,0x9b,0xc0 ]
arch: "CS_ARCH_AARCH64"
options: [ CS_OPT_DETAIL ]
address: 0x0
expected:
insns:
-
asm_text: "luti4 { z19.b, z23.b, z27.b, z31.b }, zt0, { z30, z31 }"
details:
aarch64:
operands:
-
type: AARCH64_OP_REG
reg: z19
is_list_member: 1
access: CS_AC_WRITE
vas: AARCH64LAYOUT_VL_B
-
type: AARCH64_OP_REG
reg: z23
is_list_member: 1
access: CS_AC_WRITE
vas: AARCH64LAYOUT_VL_B
-
type: AARCH64_OP_REG
reg: z27
is_list_member: 1
access: CS_AC_WRITE
vas: AARCH64LAYOUT_VL_B
-
type: AARCH64_OP_REG
reg: z31
is_list_member: 1
access: CS_AC_WRITE
vas: AARCH64LAYOUT_VL_B
-
type: AARCH64_OP_REG
reg: zt0
access: CS_AC_READ
-
type: AARCH64_OP_REG
reg: z30
is_list_member: 1
access: CS_AC_READ
-
type: AARCH64_OP_REG
reg: z31
is_list_member: 1
access: CS_AC_READ
regs_read: [ zt0, z30, z31 ]
regs_write: [ z19, z23, z27, z31 ]
groups: [ HasSME2p1, HasSME_LUTv2 ]

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test_cases:
-
input:
bytes: [ 0x02, 0x00, 0xbb, 0x27, 0x50, 0x7a, 0xbd, 0x23, 0xd0, 0xff, 0xde, 0x23, 0x00, 0x00, 0x5e, 0xb7 ]
arch: "alpha"
options: [ CS_OPT_DETAIL ]
address: 0x0
expected:
insns:
-
asm_text: "ldah $15,2($13)"
details:
alpha:
operands:
-
type: ALPHA_OP_REG
reg: $15
-
type: ALPHA_OP_IMM
imm: 0x2
-
type: ALPHA_OP_REG
reg: $13
-
asm_text: "lda $15,0x7a50($15)"
details:
alpha:
operands:
-
type: ALPHA_OP_REG
reg: $15
-
type: ALPHA_OP_IMM
imm: 0x7a50
-
type: ALPHA_OP_REG
reg: $15
-
asm_text: "lda $30,0xffd0($30)"
details:
alpha:
operands:
-
type: ALPHA_OP_REG
reg: $30
-
type: ALPHA_OP_IMM
imm: 0xffd0
-
type: ALPHA_OP_REG
reg: $30
-
asm_text: "stq $12,0($30)"
details:
alpha:
operands:
-
type: ALPHA_OP_REG
reg: $12
-
type: ALPHA_OP_IMM
imm: 0x0
-
type: ALPHA_OP_REG
reg: $30
-
input:
bytes: [ 0x27, 0xbb, 0x00, 0x02, 0x23, 0xbd, 0x7a, 0x50, 0x23, 0xde, 0xff, 0xd0, 0xb7, 0x5e, 0x00, 0x00 ]
arch: "alpha"
options: [ CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL ]
address: 0x0
expected:
insns:
-
asm_text: "ldah $15,2($13)"
details:
alpha:
operands:
-
type: ALPHA_OP_REG
reg: $15
-
type: ALPHA_OP_IMM
imm: 0x2
-
type: ALPHA_OP_REG
reg: $13
-
asm_text: "lda $15,0x7a50($15)"
details:
alpha:
operands:
-
type: ALPHA_OP_REG
reg: $15
-
type: ALPHA_OP_IMM
imm: 0x7a50
-
type: ALPHA_OP_REG
reg: $15
-
asm_text: "lda $30,0xffd0($30)"
details:
alpha:
operands:
-
type: ALPHA_OP_REG
reg: $30
-
type: ALPHA_OP_IMM
imm: 0xffd0
-
type: ALPHA_OP_REG
reg: $30
-
asm_text: "stq $12,0($30)"
details:
alpha:
operands:
-
type: ALPHA_OP_REG
reg: $12
-
type: ALPHA_OP_IMM
imm: 0x0
-
type: ALPHA_OP_REG
reg: $30

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test_cases:
-
input:
bytes: [ 0x94, 0x09, 0x00, 0x00, 0x37, 0x13, 0x03, 0x00, 0x87, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ]
arch: "bpf"
options: [ CS_OPT_DETAIL, CS_MODE_BPF_CLASSIC ]
address: 0x0
expected:
insns:
-
asm_text: "mod 0x31337"
details:
groups: [ BPF_GRP_ALU ]
bpf:
operands:
-
type: BPF_OP_IMM
imm: 0x31337
regs_read: [ a ]
regs_write: [ a ]
-
asm_text: "txa"
details:
regs_read: [ x ]
groups: [ BPF_GRP_MISC ]
regs_write: [ a ]
-
asm_text: "tax"
details:
regs_read: [ a ]
groups: [ BPF_GRP_MISC ]
regs_write: [ x ]
-
asm_text: "ret a"
details:
groups: [ BPF_GRP_RETURN ]
bpf:
operands:
-
type: BPF_OP_REG
reg: a
regs_read: [ a ]
-
asm_text: "ld #len"
details:
groups: [ BPF_GRP_LOAD ]
bpf:
operands:
-
type: BPF_OP_EXT
ext: BPF_EXT_LEN
regs_write: [ a ]
-
input:
bytes: [ 0x97, 0x09, 0x00, 0x00, 0x37, 0x13, 0x03, 0x00, 0xdc, 0x02, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xdb, 0x3a, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x84, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6d, 0x33, 0x17, 0x02, 0x00, 0x00, 0x00, 0x00 ]
arch: "bpf"
options: [ CS_OPT_DETAIL, CS_MODE_BPF_EXTENDED ]
address: 0x0
expected:
insns:
-
asm_text: "mod64 r9, 0x31337"
details:
groups: [ BPF_GRP_ALU ]
bpf:
operands:
-
type: BPF_OP_REG
reg: r9
-
type: BPF_OP_IMM
imm: 0x31337
regs_read: [ r9 ]
regs_write: [ r9 ]
-
asm_text: "be32 r2"
details:
groups: [ BPF_GRP_ALU ]
bpf:
operands:
-
type: BPF_OP_REG
reg: r2
regs_read: [ r2 ]
regs_write: [ r2 ]
-
asm_text: "ldb [0x0]"
details:
groups: [ BPF_GRP_LOAD ]
bpf:
operands:
-
type: BPF_OP_MEM
mem_disp: 0x0
regs_write: [ r0 ]
-
asm_text: "xadddw [r10+0x100], r3"
details:
groups: [ BPF_GRP_STORE ]
bpf:
operands:
-
type: BPF_OP_MEM
mem_base: r10
mem_disp: 0x100
-
type: BPF_OP_REG
reg: r3
regs_read: [ r3, r10 ]
-
asm_text: "neg r2"
details:
groups: [ BPF_GRP_ALU ]
bpf:
operands:
-
type: BPF_OP_REG
reg: r2
regs_read: [ r2 ]
regs_write: [ r2 ]
-
asm_text: "jsgt r3, r3, +0x217"
details:
groups: [ BPF_GRP_JUMP ]
bpf:
operands:
-
type: BPF_OP_REG
reg: r3
-
type: BPF_OP_REG
reg: r3
-
type: BPF_OP_OFF
off: 0x217
regs_read: [ r3 ]

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thirdparty/capstone/tests/details/evm.yaml vendored Normal file
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test_cases:
-
input:
bytes: [ 0x60, 0x61, 0x50 ]
arch: "evm"
options: [ CS_OPT_DETAIL ]
address: 0x0
expected:
insns:
-
asm_text: "push1 61"
details:
evm:
push: 1
fee: 3
groups: [ EVM_GRP_STACK_WRITE ]
-
asm_text: "pop"
details:
evm:
pop: 1
fee: 2
groups: [ EVM_GRP_STACK_READ ]

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test_cases:
-
input:
bytes: [ 0x0c, 0x00, 0x08, 0x14, 0x8c, 0xfd, 0xbf, 0x02 ]
arch: "loongarch"
options: [ CS_OPT_DETAIL, CS_MODE_LOONGARCH32 ]
address: 0x0
expected:
insns:
-
asm_text: "lu12i.w $t0, 0x4000"
details:
loongarch:
operands:
-
type: LOONGARCH_OP_REG
reg: t0
-
type: LOONGARCH_OP_IMM
imm: 0x4000
-
asm_text: "addi.w $t0, $t0, -1"
details:
loongarch:
operands:
-
type: LOONGARCH_OP_REG
reg: t0
-
type: LOONGARCH_OP_REG
reg: t0
-
type: LOONGARCH_OP_IMM
imm: -1
-
input:
bytes: [ 0x80, 0x80, 0x00, 0x40, 0x63, 0x80, 0xff, 0x02, 0x78, 0x20, 0xc0, 0x29, 0x00, 0x84, 0x00, 0x01, 0x00, 0xa4, 0x14, 0x01 ]
arch: "loongarch"
options: [ CS_OPT_DETAIL, CS_MODE_LOONGARCH64]
address: 0x0
expected:
insns:
-
asm_text: "beqz $a0, 0x80"
details:
loongarch:
operands:
-
type: LOONGARCH_OP_REG
reg: a0
-
type: LOONGARCH_OP_IMM
imm: 0x80
groups: [ LOONGARCH_GRP_JUMP, LOONGARCH_GRP_BRANCH_RELATIVE ]
-
asm_text: "addi.d $sp, $sp, -0x20"
details:
loongarch:
operands:
-
type: LOONGARCH_OP_REG
reg: sp
-
type: LOONGARCH_OP_REG
reg: sp
-
type: LOONGARCH_OP_IMM
imm: -0x20
groups: [ LOONGARCH_FEATURE_ISLA64 ]
-
asm_text: "st.d $s1, $sp, 8"
details:
loongarch:
operands:
-
type: LOONGARCH_OP_REG
reg: s1
-
type: LOONGARCH_OP_MEM
mem_base: sp
mem_disp: 0x8
groups: [ LOONGARCH_FEATURE_ISLA64 ]
-
asm_text: "fadd.s $fa0, $fa0, $fa1"
details:
loongarch:
operands:
-
type: LOONGARCH_OP_REG
reg: fa0
-
type: LOONGARCH_OP_REG
reg: fa0
-
type: LOONGARCH_OP_REG
reg: fa1
-
asm_text: "movgr2fr.w $fa0, $zero"
details:
loongarch:
operands:
-
type: LOONGARCH_OP_REG
reg: fa0
-
type: LOONGARCH_OP_REG
reg: zero

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test_cases:
-
input:
bytes: [ 0xf0, 0x10, 0xf0, 0x00, 0x48, 0xaf, 0xff, 0xff, 0x7f, 0xff, 0x11, 0xb0, 0x01, 0x37, 0x7f, 0xff, 0xff, 0xff, 0x12, 0x34, 0x56, 0x78, 0x01, 0x33, 0x10, 0x10, 0x10, 0x10, 0x32, 0x32, 0x32, 0x32, 0x4c, 0x00, 0x54, 0x04, 0x48, 0xe7, 0xe0, 0x30, 0x4c, 0xdf, 0x0c, 0x07, 0xd4, 0x40, 0x87, 0x5a, 0x4e, 0x71, 0x02, 0xb4, 0xc0, 0xde, 0xc0, 0xde, 0x5c, 0x00, 0x1d, 0x80, 0x71, 0x12, 0x01, 0x23, 0xf2, 0x3c, 0x44, 0x22, 0x40, 0x49, 0x0e, 0x56, 0x54, 0xc5, 0xf2, 0x3c, 0x44, 0x00, 0x44, 0x7a, 0x00, 0x00, 0xf2, 0x00, 0x0a, 0x28, 0x4e, 0xb9, 0x00, 0x00, 0x00, 0x12, 0x4e, 0x75 ]
arch: "m68k"
options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ]
address: 0x1000
expected:
insns:
-
asm_text: "fmovem #$0, (a0)"
details:
regs_read: [ a0 ]
m68k:
operands:
-
type: M68K_OP_REG_BITS
register_bits: 0x0
-
type: M68K_OP_MEM
address_mode: M68K_AM_REGI_ADDR
-
asm_text: "movem.w d0-d7/a0-a7, $7fff(a7)"
details:
regs_read: [ d0, d1, d2, d3, d4, d5, d6, d7, a0, a1, a2, a3, a4, a5, a6, a7 ]
m68k:
operands:
-
type: M68K_OP_REG_BITS
register_bits: 0xffff
-
type: M68K_OP_MEM
mem:
base_reg: a7
disp: 0x7fff
address_mode: M68K_AM_REGI_ADDR_DISP
-
asm_text: "move.b ([$7fffffff, a0], d0.w, $12345678), ([$10101010, a0, d0.w], $32323232)"
details:
regs_read: [ d0, a0 ]
m68k:
operands:
-
type: M68K_OP_MEM
mem:
base_reg: a0
index_reg: d0
index_size: -1
address_mode: M68K_AM_MEMI_POST_INDEX
-
type: M68K_OP_MEM
mem:
base_reg: a0
index_reg: d0
index_size: -1
address_mode: M68K_AM_MEMI_PRE_INDEX
-
asm_text: "mulu.l d0, d4:d5"
details:
regs_read: [ d0 ]
regs_write: [ d4, d5 ]
m68k:
operands:
-
type: M68K_OP_REG
reg: d0
-
type: M68K_OP_REG_PAIR
reg_pair_0: d4
reg_pair_1: d5
-
asm_text: "movem.l d0-d2/a2-a3, -(a7)"
details:
regs_read: [ d0, d1, d2, a2, a3 ]
regs_write: [ a7 ]
m68k:
operands:
-
type: M68K_OP_REG_BITS
register_bits: 0xc07
-
type: M68K_OP_MEM
address_mode: M68K_AM_REGI_ADDR_PRE_DEC
-
asm_text: "movem.l (a7)+, d0-d2/a2-a3"
details:
regs_write: [ a7, d0, d1, d2, a2, a3 ]
m68k:
operands:
-
type: M68K_OP_MEM
address_mode: M68K_AM_REGI_ADDR_POST_INC
-
type: M68K_OP_REG_BITS
register_bits: 0xc07
-
asm_text: "add.w d0, d2"
details:
regs_read: [ d0 ]
regs_write: [ d2 ]
m68k:
operands:
-
type: M68K_OP_REG
reg: d0
-
type: M68K_OP_REG
reg: d2
-
asm_text: "or.w d3, (a2)+"
details:
regs_read: [ d3 ]
regs_write: [ a2 ]
m68k:
operands:
-
type: M68K_OP_REG
reg: d3
-
type: M68K_OP_MEM
address_mode: M68K_AM_REGI_ADDR_POST_INC
-
asm_text: "nop"
-
asm_text: "andi.l #$c0dec0de, (a4, d5.l * 4)"
details:
regs_read: [ d5, a4 ]
m68k:
operands:
-
type: M68K_OP_IMM
imm: 0xc0dec0de
-
type: M68K_OP_MEM
mem:
base_reg: a4
index_reg: d5
index_size: 1
scale: 4
address_mode: M68K_AM_AREGI_INDEX_BASE_DISP
-
asm_text: "move.b d0, ([a6, d7.w], $123)"
details:
regs_read: [ d0, d7, a6 ]
m68k:
operands:
-
type: M68K_OP_REG
reg: d0
-
type: M68K_OP_MEM
mem:
base_reg: a6
index_reg: d7
index_size: -1
address_mode: M68K_AM_MEMI_PRE_INDEX
-
asm_text: "fadd.s #3.141500, fp0"
details:
regs_write: [ fp0 ]
m68k:
operands:
-
type: M68K_OP_FP_SINGLE
simm: 3.141500
-
type: M68K_OP_REG
reg: fp0
-
asm_text: "scc.b d5"
details:
regs_write: [ d5 ]
m68k:
operands:
-
type: M68K_OP_REG
reg: d5
-
asm_text: "fmove.s #1000.000000, fp0"
details:
regs_write: [ fp0 ]
m68k:
operands:
-
type: M68K_OP_FP_SINGLE
simm: 1000.000000
-
type: M68K_OP_REG
reg: fp0
-
asm_text: "fsub fp2, fp4"
details:
regs_read: [ fp2 ]
regs_write: [ fp4 ]
m68k:
operands:
-
type: M68K_OP_REG
reg: fp2
-
type: M68K_OP_REG
reg: fp4
-
asm_text: "jsr $12.l"
details:
m68k:
operands:
-
type: M68K_OP_MEM
address_mode: M68K_AM_ABSOLUTE_DATA_LONG
-
asm_text: "rts"

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thirdparty/capstone/tests/details/mips.yaml vendored Normal file
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test_cases:
-
input:
bytes: [ 0x0c, 0x10, 0x00, 0x97, 0x00, 0x00, 0x00, 0x00, 0x24, 0x02, 0x00, 0x0c, 0x8f, 0xa2, 0x00, 0x00, 0x34, 0x21, 0x34, 0x56 ]
arch: "mips"
options: [ CS_OPT_DETAIL, CS_MODE_MIPS32, CS_MODE_BIG_ENDIAN ]
address: 0x0
expected:
insns:
-
asm_text: "jal 0x40025c"
details:
mips:
operands:
-
type: MIPS_OP_IMM
imm: 0x40025c
-
asm_text: "nop"
-
asm_text: "addiu $v0, $zero, 0xc"
details:
mips:
operands:
-
type: MIPS_OP_REG
reg: v0
-
type: MIPS_OP_REG
reg: zero
-
type: MIPS_OP_IMM
imm: 0xc
-
asm_text: "lw $v0, ($sp)"
details:
mips:
operands:
-
type: MIPS_OP_REG
reg: v0
-
type: MIPS_OP_MEM
mem_base: sp
-
asm_text: "ori $at, $at, 0x3456"
details:
mips:
operands:
-
type: MIPS_OP_REG
reg: at
-
type: MIPS_OP_REG
reg: at
-
type: MIPS_OP_IMM
imm: 0x3456
-
input:
bytes: [ 0x56, 0x34, 0x21, 0x34, 0xc2, 0x17, 0x01, 0x00 ]
arch: "mips"
options: [ CS_OPT_DETAIL, CS_MODE_MIPS64, CS_MODE_LITTLE_ENDIAN ]
address: 0x0
expected:
insns:
-
asm_text: "ori $at, $at, 0x3456"
details:
mips:
operands:
-
type: MIPS_OP_REG
reg: at
-
type: MIPS_OP_REG
reg: at
-
type: MIPS_OP_IMM
imm: 0x3456
-
asm_text: "srl $v0, $at, 0x1f"
details:
mips:
operands:
-
type: MIPS_OP_REG
reg: v0
-
type: MIPS_OP_REG
reg: at
-
type: MIPS_OP_IMM
imm: 0x1f
-
input:
bytes: [ 0x00, 0x07, 0x00, 0x07, 0x00, 0x11, 0x93, 0x7c, 0x01, 0x8c, 0x8b, 0x7c, 0x00, 0xc7, 0x48, 0xd0 ]
arch: "mips"
options: [ CS_OPT_DETAIL, CS_MODE_MIPS32R6, CS_MODE_MICRO, CS_MODE_BIG_ENDIAN ]
address: 0x0
expected:
insns:
-
asm_text: "break 7, 0"
details:
mips:
operands:
-
type: MIPS_OP_IMM
imm: 0x7
-
type: MIPS_OP_IMM
imm: 0x0
-
asm_text: "wait 0x11"
details:
mips:
operands:
-
type: MIPS_OP_IMM
imm: 0x11
-
asm_text: "syscall 0x18c"
details:
mips:
operands:
-
type: MIPS_OP_IMM
imm: 0x18c
-
asm_text: "rotrv $t1, $a2, $a3"
details:
mips:
operands:
-
type: MIPS_OP_REG
reg: t1
-
type: MIPS_OP_REG
reg: a2
-
type: MIPS_OP_REG
reg: a3
-
input:
bytes: [ 0xec, 0x80, 0x00, 0x19, 0x7c, 0x43, 0x22, 0xa0 ]
arch: "mips"
options: [ CS_OPT_DETAIL, CS_MODE_MIPS32R6, CS_MODE_BIG_ENDIAN ]
address: 0x0
expected:
insns:
-
asm_text: "addiupc $a0, 0x64"
details:
mips:
operands:
-
type: MIPS_OP_REG
reg: a0
-
type: MIPS_OP_IMM
imm: 0x64
-
asm_text: "align $a0, $v0, $v1, 2"
details:
mips:
operands:
-
type: MIPS_OP_REG
reg: a0
-
type: MIPS_OP_REG
reg: v0
-
type: MIPS_OP_REG
reg: v1
-
type: MIPS_OP_IMM
imm: 0x2
-
input:
bytes: [ 0x70, 0x00, 0xb2, 0xff ]
arch: "mips"
options: [ CS_MODE_MIPS64, CS_MODE_MIPS2, CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL ]
address: 0x0
expected:
insns:
-
asm_text: "sdc3 $18, 0x70($sp)"
details:
mips:
operands:
-
type: MIPS_OP_REG
reg: s2
-
type: MIPS_OP_MEM
mem_base: sp
mem_disp: 0x70
-
input:
bytes: [ 0x70, 0x00, 0xb2, 0xff ]
arch: "mips"
options: [ CS_OPT_DETAIL, CS_MODE_MIPS64, CS_MODE_LITTLE_ENDIAN]
address: 0x0
expected:
insns:
-
asm_text: "sd $s2, 0x70($sp)"
details:
mips:
operands:
-
type: MIPS_OP_REG
reg: s2
-
type: MIPS_OP_MEM
mem_base: sp
mem_disp: 0x70

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thirdparty/capstone/tests/details/mos65xx.yaml vendored Normal file
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test_cases:
-
input:
bytes: [ 0xa1, 0x12, 0xa5, 0x12, 0xa9, 0x12, 0xad, 0x34, 0x12, 0xb1, 0x12, 0xb5, 0x12, 0xb9, 0x34, 0x12, 0xbd, 0x34, 0x12, 0x0d, 0x34, 0x12, 0x00, 0x81, 0x87, 0x6c, 0x01, 0x00, 0x85, 0xff, 0x10, 0x00, 0x19, 0x42, 0x42, 0x00, 0x49, 0x42 ]
arch: "mos65xx"
options: [ CS_OPT_DETAIL, CS_MODE_MOS65XX_6502, CS_OPT_SYNTAX_MOTOROLA ]
address: 0x1000
expected:
insns:
-
asm_text: "lda ($12, x)"
details:
mos65xx:
am: MOS65XX_AM_ZP_X_IND
modifies_flags: 1
operands:
-
type: MOS65XX_OP_MEM
mem: 0x12
-
asm_text: "lda $12"
details:
mos65xx:
am: MOS65XX_AM_ZP
modifies_flags: 1
operands:
-
type: MOS65XX_OP_MEM
mem: 0x12
-
asm_text: "lda #$12"
details:
mos65xx:
am: MOS65XX_AM_IMM
modifies_flags: 1
operands:
-
type: MOS65XX_OP_IMM
imm: 0x12
-
asm_text: "lda $1234"
details:
mos65xx:
am: MOS65XX_AM_ABS
modifies_flags: 1
operands:
-
type: MOS65XX_OP_MEM
mem: 0x1234
-
asm_text: "lda ($12), y"
details:
mos65xx:
am: MOS65XX_AM_ZP_IND_Y
modifies_flags: 1
operands:
-
type: MOS65XX_OP_MEM
mem: 0x12
-
asm_text: "lda $12, x"
details:
mos65xx:
am: MOS65XX_AM_ZP_X
modifies_flags: 1
operands:
-
type: MOS65XX_OP_MEM
mem: 0x12
-
asm_text: "lda $1234, y"
details:
mos65xx:
am: MOS65XX_AM_ABS_Y
modifies_flags: 1
operands:
-
type: MOS65XX_OP_MEM
mem: 0x1234
-
asm_text: "lda $1234, x"
details:
mos65xx:
am: MOS65XX_AM_ABS_X
modifies_flags: 1
operands:
-
type: MOS65XX_OP_MEM
mem: 0x1234
-
asm_text: "ora $1234"
details:
mos65xx:
am: MOS65XX_AM_ABS
modifies_flags: 1
operands:
-
type: MOS65XX_OP_MEM
mem: 0x1234
-
asm_text: "brk $81"
details:
mos65xx:
am: MOS65XX_AM_INT
modifies_flags: -1
operands:
-
type: MOS65XX_OP_MEM
mem: 0x81
-
input:
bytes: [ 0x1a, 0x3a, 0x02, 0x12, 0x03, 0x5c, 0x34, 0x12 ]
arch: "mos65xx"
options: [ CS_OPT_DETAIL, CS_MODE_MOS65XX_65C02, CS_OPT_SYNTAX_MOTOROLA ]
address: 0x1000
expected:
insns:
-
asm_text: "inc a"
details:
mos65xx:
am: MOS65XX_AM_ACC
modifies_flags: 1
operands:
-
type: MOS65XX_OP_REG
reg: A
-
asm_text: "dec a"
details:
mos65xx:
am: MOS65XX_AM_ACC
modifies_flags: 1
operands:
-
type: MOS65XX_OP_REG
reg: A
-
asm_text: "nop"
details:
mos65xx:
am: MOS65XX_AM_IMP
modifies_flags: -1
-
asm_text: "nop"
details:
mos65xx:
am: MOS65XX_AM_IMP
modifies_flags: -1
-
asm_text: "nop"
details:
mos65xx:
am: MOS65XX_AM_IMP
modifies_flags: -1
-
input:
bytes: [ 0x07, 0x12, 0x27, 0x12, 0x47, 0x12, 0x67, 0x12, 0x87, 0x12, 0xa7, 0x12, 0xc7, 0x12, 0xe7, 0x12, 0x10, 0xfe, 0x0f, 0x12, 0xfd, 0x4f, 0x12, 0xfd, 0x8f, 0x12, 0xfd, 0xcf, 0x12, 0xfd ]
arch: "mos65xx"
options: [ CS_OPT_DETAIL, CS_MODE_MOS65XX_W65C02, CS_OPT_SYNTAX_MOTOROLA ]
address: 0x1000
expected:
insns:
-
asm_text: "rmb0 $12"
details:
mos65xx:
am: MOS65XX_AM_ZP
modifies_flags: -1
operands:
-
type: MOS65XX_OP_MEM
mem: 0x12
-
asm_text: "rmb2 $12"
details:
mos65xx:
am: MOS65XX_AM_ZP
modifies_flags: -1
operands:
-
type: MOS65XX_OP_MEM
mem: 0x12
-
asm_text: "rmb4 $12"
details:
mos65xx:
am: MOS65XX_AM_ZP
modifies_flags: -1
operands:
-
type: MOS65XX_OP_MEM
mem: 0x12
-
asm_text: "rmb6 $12"
details:
mos65xx:
am: MOS65XX_AM_ZP
modifies_flags: -1
operands:
-
type: MOS65XX_OP_MEM
mem: 0x12
-
asm_text: "smb0 $12"
details:
mos65xx:
am: MOS65XX_AM_ZP
modifies_flags: -1
operands:
-
type: MOS65XX_OP_MEM
mem: 0x12
-
asm_text: "smb2 $12"
details:
mos65xx:
am: MOS65XX_AM_ZP
modifies_flags: -1
operands:
-
type: MOS65XX_OP_MEM
mem: 0x12
-
asm_text: "smb4 $12"
details:
mos65xx:
am: MOS65XX_AM_ZP
modifies_flags: -1
operands:
-
type: MOS65XX_OP_MEM
mem: 0x12
-
asm_text: "smb6 $12"
details:
mos65xx:
am: MOS65XX_AM_ZP
modifies_flags: -1
operands:
-
type: MOS65XX_OP_MEM
mem: 0x12
-
asm_text: "bpl $1010"
details:
mos65xx:
am: MOS65XX_AM_REL
modifies_flags: -1
operands:
-
type: MOS65XX_OP_MEM
mem: 0x1010
-
asm_text: "bbr0 $12, $1012"
details:
mos65xx:
am: MOS65XX_AM_ZP_REL
modifies_flags: -1
operands:
-
type: MOS65XX_OP_MEM
mem: 0x12
-
type: MOS65XX_OP_MEM
mem: 0x1012
-
asm_text: "bbr4 $12, $1015"
details:
mos65xx:
am: MOS65XX_AM_ZP_REL
modifies_flags: -1
operands:
-
type: MOS65XX_OP_MEM
mem: 0x12
-
type: MOS65XX_OP_MEM
mem: 0x1015
-
asm_text: "bbs0 $12, $1018"
details:
mos65xx:
am: MOS65XX_AM_ZP_REL
modifies_flags: -1
operands:
-
type: MOS65XX_OP_MEM
mem: 0x12
-
type: MOS65XX_OP_MEM
mem: 0x1018
-
asm_text: "bbs4 $12, $101b"
details:
mos65xx:
am: MOS65XX_AM_ZP_REL
modifies_flags: -1
operands:
-
type: MOS65XX_OP_MEM
mem: 0x12
-
type: MOS65XX_OP_MEM
mem: 0x101b
-
input:
bytes: [ 0xa9, 0x34, 0x12, 0xad, 0x34, 0x12, 0xbd, 0x34, 0x12, 0xb9, 0x34, 0x12, 0xaf, 0x56, 0x34, 0x12, 0xbf, 0x56, 0x34, 0x12, 0xa5, 0x12, 0xb5, 0x12, 0xb2, 0x12, 0xa1, 0x12, 0xb1, 0x12, 0xa7, 0x12, 0xb7, 0x12, 0xa3, 0x12, 0xb3, 0x12, 0xc2, 0x00, 0xe2, 0x00, 0x54, 0x34, 0x12, 0x44, 0x34, 0x12, 0x02, 0x12 ]
arch: "mos65xx"
options: [ CS_OPT_DETAIL, CS_MODE_MOS65XX_65816_LONG_MX, CS_OPT_SYNTAX_MOTOROLA ]
address: 0x1000
expected:
insns:
-
asm_text: "lda #$1234"
details:
mos65xx:
am: MOS65XX_AM_IMM
modifies_flags: 1
operands:
-
type: MOS65XX_OP_IMM
imm: 0x1234
-
asm_text: "lda $1234"
details:
mos65xx:
am: MOS65XX_AM_ABS
modifies_flags: 1
operands:
-
type: MOS65XX_OP_MEM
mem: 0x1234
-
asm_text: "lda $1234, x"
details:
mos65xx:
am: MOS65XX_AM_ABS_X
modifies_flags: 1
operands:
-
type: MOS65XX_OP_MEM
mem: 0x1234
-
asm_text: "lda $1234, y"
details:
mos65xx:
am: MOS65XX_AM_ABS_Y
modifies_flags: 1
operands:
-
type: MOS65XX_OP_MEM
mem: 0x1234
-
asm_text: "lda $123456"
details:
mos65xx:
am: MOS65XX_AM_ABS_LONG
modifies_flags: 1
operands:
-
type: MOS65XX_OP_MEM
mem: 0x123456
-
asm_text: "lda $123456, x"
details:
mos65xx:
am: MOS65XX_AM_ABS_LONG_X
modifies_flags: 1
operands:
-
type: MOS65XX_OP_MEM
mem: 0x123456
-
asm_text: "lda $12"
details:
mos65xx:
am: MOS65XX_AM_ZP
modifies_flags: 1
operands:
-
type: MOS65XX_OP_MEM
mem: 0x12
-
asm_text: "lda $12, x"
details:
mos65xx:
am: MOS65XX_AM_ZP_X
modifies_flags: 1
operands:
-
type: MOS65XX_OP_MEM
mem: 0x12
-
asm_text: "lda ($12)"
details:
mos65xx:
am: MOS65XX_AM_ZP_IND
modifies_flags: 1
operands:
-
type: MOS65XX_OP_MEM
mem: 0x12
-
asm_text: "lda ($12, x)"
details:
mos65xx:
am: MOS65XX_AM_ZP_X_IND
modifies_flags: 1
operands:
-
type: MOS65XX_OP_MEM
mem: 0x12
-
asm_text: "lda ($12), y"
details:
mos65xx:
am: MOS65XX_AM_ZP_IND_Y
modifies_flags: 1
operands:
-
type: MOS65XX_OP_MEM
mem: 0x12
-
asm_text: "lda [$12]"
details:
mos65xx:
am: MOS65XX_AM_ZP_IND_LONG
modifies_flags: 1
operands:
-
type: MOS65XX_OP_MEM
mem: 0x12
-
asm_text: "lda [$12], y"
details:
mos65xx:
am: MOS65XX_AM_ZP_IND_LONG_Y
modifies_flags: 1
operands:
-
type: MOS65XX_OP_MEM
mem: 0x12
-
asm_text: "lda $12, s"
details:
mos65xx:
am: MOS65XX_AM_SR
modifies_flags: 1
operands:
-
type: MOS65XX_OP_MEM
mem: 0x12
-
asm_text: "lda ($12, s), y"
details:
mos65xx:
am: MOS65XX_AM_SR_IND_Y
modifies_flags: 1
operands:
-
type: MOS65XX_OP_MEM
mem: 0x12
-
asm_text: "rep #$00"
details:
mos65xx:
am: MOS65XX_AM_IMM
modifies_flags: 1
operands:
-
type: MOS65XX_OP_IMM
imm: 0x0
-
asm_text: "sep #$00"
details:
mos65xx:
am: MOS65XX_AM_IMM
modifies_flags: 1
operands:
-
type: MOS65XX_OP_IMM
imm: 0x0
-
asm_text: "mvn $12, $34"
details:
mos65xx:
am: MOS65XX_AM_BLOCK
modifies_flags: -1
operands:
-
type: MOS65XX_OP_MEM
mem: 0x12
-
type: MOS65XX_OP_MEM
mem: 0x34
-
asm_text: "mvp $12, $34"
details:
mos65xx:
am: MOS65XX_AM_BLOCK
modifies_flags: -1
operands:
-
type: MOS65XX_OP_MEM
mem: 0x12
-
type: MOS65XX_OP_MEM
mem: 0x34
-
asm_text: "cop $12"
details:
mos65xx:
am: MOS65XX_AM_INT
modifies_flags: -1
operands:
-
type: MOS65XX_OP_MEM
mem: 0x12

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thirdparty/capstone/tests/details/ppc.yaml vendored Normal file
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thirdparty/capstone/tests/details/riscv.yaml vendored Normal file
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thirdparty/capstone/tests/details/sh.yaml vendored Normal file
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test_cases:
-
input:
bytes: [ 0x0c, 0x31, 0x10, 0x20, 0x22, 0x21, 0x36, 0x64, 0x46, 0x25, 0x12, 0x12, 0x1c, 0x02, 0x08, 0xc1, 0x05, 0xc7, 0x0c, 0x71, 0x1f, 0x02, 0x22, 0xcf, 0x06, 0x89, 0x23, 0x00, 0x2b, 0x41, 0x0b, 0x00, 0x0e, 0x40, 0x32, 0x00, 0x0a, 0xf1, 0x09, 0x00 ]
arch: "sh"
options: [ CS_OPT_DETAIL, CS_MODE_SH4A, CS_MODE_SHFPU ]
address: 0x80000000
expected:
insns:
-
asm_text: "add r0,r1"
details:
regs_read: [ r0 ]
regs_write: [ r1 ]
-
asm_text: "mov.b r1,@r0"
details:
regs_read: [ r0, r1 ]
-
asm_text: "mov.l r2,@r1"
details:
regs_read: [ r1, r2 ]
-
asm_text: "mov.l @r3+,r4"
details:
regs_write: [ r3, r4 ]
-
asm_text: "mov.l r4,@-r5"
details:
regs_read: [ r4 ]
regs_write: [ r5 ]
-
asm_text: "mov.l r1,@(8,r2)"
details:
regs_read: [ r2, r1 ]
-
asm_text: "mov.b @(r0,r1),r2"
details:
regs_read: [ r0, r1 ]
regs_write: [ r2 ]
-
asm_text: "mov.w r0,@(16,gbr)"
details:
regs_read: [ gbr, r0 ]
-
asm_text: "mova 0x80000028,r0"
details:
regs_write: [ r0 ]
-
asm_text: "add #12,r1"
details:
regs_write: [ r1 ]
-
asm_text: "mac.l @r1+,@r2+"
details:
regs_write: [ r1, r2 ]
-
asm_text: "or.b #34,@(r0,gbr)"
details:
regs_read: [ gbr, r0 ]
-
asm_text: "bt 0x80000028"
details:
groups: [ SH_GRP_JUMP, SH_GRP_BRANCH_RELATIVE ]
-
asm_text: "braf r0"
details:
regs_read: [ r0 ]
groups: [ SH_GRP_JUMP, SH_GRP_BRANCH_RELATIVE ]
-
asm_text: "jmp @r1"
details:
regs_read: [ r1 ]
groups: [ SH_GRP_JUMP ]
-
asm_text: "rts"
-
asm_text: "ldc r0,sr"
details:
regs_read: [ r0 ]
regs_write: [ sr ]
-
asm_text: "stc ssr,r0"
details:
regs_read: [ ssr ]
regs_write: [ r0 ]
-
asm_text: "fmov fr0,@r1"
details:
regs_read: [ r1, fr0 ]
-
asm_text: "nop"
-
input:
bytes: [ 0x32, 0x11, 0x92, 0x00, 0x32, 0x49, 0x31, 0x00 ]
arch: "sh"
options: [ CS_OPT_DETAIL, CS_MODE_SH2A, CS_MODE_SHFPU, CS_MODE_BIG_ENDIAN ]
address: 0x0
expected:
insns:
-
asm_text: "movu.w @(1024,r1),r2"
details:
regs_read: [ r1 ]
regs_write: [ r2 ]
-
asm_text: "bld.b #4,@(256,r2)"
details:
regs_read: [ r2 ]

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thirdparty/capstone/tests/details/sparc.yaml vendored Normal file
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test_cases:
-
input:
bytes: [ 0x80, 0xa0, 0x40, 0x02, 0x85, 0xc2, 0x60, 0x08, 0x85, 0xe8, 0x20, 0x01, 0x81, 0xe8, 0x00, 0x00, 0x90, 0x10, 0x20, 0x01, 0xd5, 0xf6, 0x10, 0x16, 0x21, 0x00, 0x00, 0x0a, 0x86, 0x00, 0x40, 0x02, 0x01, 0x00, 0x00, 0x00, 0x12, 0xbf, 0xff, 0xff, 0x10, 0xbf, 0xff, 0xff, 0xa0, 0x02, 0x00, 0x09, 0x0d, 0xbf, 0xff, 0xff, 0xd4, 0x20, 0x60, 0x00, 0xd4, 0x4e, 0x00, 0x16, 0x2a, 0xc2, 0x80, 0x03 ]
arch: "sparc"
options: [ CS_OPT_DETAIL ]
address: 0x1000
expected:
insns:
-
asm_text: "cmp %g1, %g2"
details:
sparc:
operands:
-
type: SPARC_OP_REG
reg: g1
-
type: SPARC_OP_REG
reg: g2
-
asm_text: "jmpl %o1+8, %g2"
details:
sparc:
operands:
-
type: SPARC_OP_MEM
mem_base: o1
mem_disp: 0x8
-
type: SPARC_OP_REG
reg: g2
-
asm_text: "restore %g0, 1, %g2"
details:
sparc:
operands:
-
type: SPARC_OP_REG
reg: g0
-
type: SPARC_OP_IMM
imm: 0x1
-
type: SPARC_OP_REG
reg: g2
-
asm_text: "restore"
-
asm_text: "mov 1, %o0"
details:
sparc:
operands:
-
type: SPARC_OP_IMM
imm: 0x1
-
type: SPARC_OP_REG
reg: o0
-
asm_text: "casx [%i0], %l6, %o2"
details:
sparc:
operands:
-
type: SPARC_OP_MEM
mem_base: i0
-
type: SPARC_OP_REG
reg: l6
-
type: SPARC_OP_REG
reg: o2
-
asm_text: "sethi 0xa, %l0"
details:
sparc:
operands:
-
type: SPARC_OP_IMM
imm: 0xa
-
type: SPARC_OP_REG
reg: l0
-
asm_text: "add %g1, %g2, %g3"
details:
sparc:
operands:
-
type: SPARC_OP_REG
reg: g1
-
type: SPARC_OP_REG
reg: g2
-
type: SPARC_OP_REG
reg: g3
-
asm_text: "nop"
-
asm_text: "bne 0x1020"
details:
sparc:
operands:
-
type: SPARC_OP_IMM
imm: 0x1020
cc: SPARC_CC_ICC_NE
-
asm_text: "ba 0x1024"
details:
sparc:
operands:
-
type: SPARC_OP_IMM
imm: 0x1024
-
asm_text: "add %o0, %o1, %l0"
details:
sparc:
operands:
-
type: SPARC_OP_REG
reg: o0
-
type: SPARC_OP_REG
reg: o1
-
type: SPARC_OP_REG
reg: l0
-
asm_text: "fbg 0x102c"
details:
sparc:
operands:
-
type: SPARC_OP_IMM
imm: 0x102c
cc: SPARC_CC_FCC_G
-
asm_text: "st %o2, [%g1]"
details:
sparc:
operands:
-
type: SPARC_OP_REG
reg: o2
-
type: SPARC_OP_MEM
mem_base: g1
-
asm_text: "ldsb [%i0+%l6], %o2"
details:
sparc:
operands:
-
type: SPARC_OP_MEM
mem_base: i0
mem_index: l6
-
type: SPARC_OP_REG
reg: o2
-
asm_text: "brnz,a,pn %o2, 0x1048"
details:
sparc:
operands:
-
type: SPARC_OP_REG
reg: o2
-
type: SPARC_OP_IMM
imm: 0x1048
hint: SPARC_HINT_A_PN
-
input:
bytes: [ 0x81, 0xa8, 0x0a, 0x24, 0x89, 0xa0, 0x10, 0x20, 0x89, 0xa0, 0x1a, 0x60, 0x89, 0xa0, 0x00, 0xe0 ]
arch: "sparc"
options: [ CS_OPT_DETAIL ]
address: 0x1000
expected:
insns:
-
asm_text: "fcmps %f0, %f4"
details:
sparc:
operands:
-
type: SPARC_OP_REG
reg: f0
-
type: SPARC_OP_REG
reg: f4
-
asm_text: "fstox %f0, %f4"
details:
sparc:
operands:
-
type: SPARC_OP_REG
reg: f0
-
type: SPARC_OP_REG
reg: f4
-
asm_text: "fqtoi %f0, %f4"
details:
sparc:
operands:
-
type: SPARC_OP_REG
reg: f0
-
type: SPARC_OP_REG
reg: f4
-
asm_text: "fnegq %f0, %f4"
details:
sparc:
operands:
-
type: SPARC_OP_REG
reg: f0
-
type: SPARC_OP_REG
reg: f4

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thirdparty/capstone/tests/details/systemz.yaml vendored Normal file
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test_cases:
-
input:
bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x1a, 0x5a, 0x0f, 0x1f, 0xff, 0xc2, 0x09, 0x80, 0x00, 0x00, 0x00, 0x07, 0xf7, 0xeb, 0x2a, 0xff, 0xff, 0x7f, 0x57, 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x57, 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x24, 0xb2, 0x4f, 0x00, 0x78, 0xec, 0x18, 0x00, 0x00, 0xc1, 0x7f ]
arch: "CS_ARCH_SYSZ"
options: [ CS_OPT_DETAIL ]
address: 0x1000
expected:
insns:
-
asm_text: "adb %f0, 0"
details:
systemz:
operands:
-
type: SYSZ_OP_REG
reg: f0
-
type: SYSZ_OP_IMM
imm: 0x0
-
asm_text: "a %r0, 0xfff(%r15, %r1)"
details:
systemz:
operands:
-
type: SYSZ_OP_REG
reg: "0"
-
type: SYSZ_OP_MEM
mem_base: "1"
mem_index: "15"
mem_disp: 0xfff
-
asm_text: "afi %r0, -0x80000000"
details:
systemz:
operands:
-
type: SYSZ_OP_REG
reg: "0"
-
type: SYSZ_OP_IMM
imm: -0x80000000
-
asm_text: "br %r7"
details:
systemz:
operands:
-
type: SYSZ_OP_REG
reg: "7"
-
asm_text: "xiy 0x7ffff(%r15), 0x2a"
details:
systemz:
operands:
-
type: SYSZ_OP_MEM
mem_base: "15"
mem_disp: 0x7ffff
-
type: SYSZ_OP_IMM
imm: 0x2a
-
asm_text: "xy %r0, 0x7ffff(%r1, %r15)"
details:
systemz:
operands:
-
type: SYSZ_OP_REG
reg: "0"
-
type: SYSZ_OP_MEM
mem_base: "15"
mem_index: "1"
mem_disp: 0x7ffff
-
asm_text: "stmg %r0, %r0, 0(%r15)"
details:
systemz:
operands:
-
type: SYSZ_OP_REG
reg: "0"
-
type: SYSZ_OP_REG
reg: "0"
-
type: SYSZ_OP_MEM
mem_base: "15"
-
asm_text: "ear %r7, %a8"
details:
systemz:
operands:
-
type: SYSZ_OP_REG
reg: "7"
-
type: SYSZ_OP_REG
reg: a8
-
asm_text: "clije %r1, 0xc1, 0x1028"
details:
systemz:
operands:
-
type: SYSZ_OP_REG
reg: "1"
-
type: SYSZ_OP_IMM
imm: 0xc1
-
type: SYSZ_OP_IMM
imm: 0x1028

147
thirdparty/capstone/tests/details/tms320c64x.yaml vendored Normal file
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test_cases:
-
input:
bytes: [ 0x01, 0xac, 0x88, 0x40, 0x81, 0xac, 0x88, 0x43, 0x00, 0x00, 0x00, 0x00, 0x02, 0x90, 0x32, 0x96, 0x02, 0x80, 0x46, 0x9e, 0x05, 0x3c, 0x83, 0xe6, 0x0b, 0x0c, 0x8b, 0x24 ]
arch: "tms320c64x"
options: [ CS_OPT_DETAIL ]
address: 0x1000
expected:
insns:
-
asm_text: "add.D1 a11, a4, a3"
details:
tms320c64x:
operands:
-
type: TMS320C64X_OP_REG
reg: a11
-
type: TMS320C64X_OP_REG
reg: a4
-
type: TMS320C64X_OP_REG
reg: a3
funit_unit: TMS320C64X_FUNIT_D
funit_side: 1
funit_side_set: true
parallel: 0
parallel_set: true
-
asm_text: "[ a1] add.D2 b11, b4, b3 ||"
details:
tms320c64x:
operands:
-
type: TMS320C64X_OP_REG
reg: b11
-
type: TMS320C64X_OP_REG
reg: b4
-
type: TMS320C64X_OP_REG
reg: b3
funit_unit: TMS320C64X_FUNIT_D
funit_side: 2
funit_side_set: true
cond_reg: a1
cond_zero: -1
parallel: 1
parallel_set: true
-
asm_text: "NOP"
details:
tms320c64x:
funit_unit: TMS320C64X_FUNIT_NO
parallel: 0
parallel_set: true
-
asm_text: "ldbu.D1T2 *++a4[1], b5"
details:
tms320c64x:
operands:
-
type: TMS320C64X_OP_MEM
mem_base: a4
mem_disptype: TMS320C64X_MEM_DISP_CONSTANT
mem_disp_const: 0x1
mem_unit: 2
mem_direction: TMS320C64X_MEM_DIR_FW
mem_modify: TMS320C64X_MEM_MOD_PRE
mem_scaled: 1
-
type: TMS320C64X_OP_REG
reg: b5
funit_unit: TMS320C64X_FUNIT_D
funit_side: 2
funit_side_set: true
parallel: 0
parallel_set: true
-
asm_text: "ldbu.D2T2 *+b15[0x46], b5"
details:
tms320c64x:
operands:
-
type: TMS320C64X_OP_MEM
mem_base: b15
mem_disptype: TMS320C64X_MEM_DISP_CONSTANT
mem_disp_const: 0x46
mem_unit: 2
mem_direction: TMS320C64X_MEM_DIR_FW
mem_modify: TMS320C64X_MEM_MOD_NO
mem_scaled: -1
-
type: TMS320C64X_OP_REG
reg: b5
funit_unit: TMS320C64X_FUNIT_D
funit_side: 2
funit_side_set: true
parallel: 0
parallel_set: true
-
asm_text: "lddw.D1T2 *+a15[4], b11:b10"
details:
tms320c64x:
operands:
-
type: TMS320C64X_OP_MEM
mem_base: a15
mem_disptype: TMS320C64X_MEM_DISP_CONSTANT
mem_disp_const: 0x4
mem_unit: 2
mem_direction: TMS320C64X_MEM_DIR_FW
mem_modify: TMS320C64X_MEM_MOD_NO
mem_scaled: 1
-
type: TMS320C64X_OP_REGPAIR
reg_pair_0: b11
reg_pair_1: b10
funit_unit: TMS320C64X_FUNIT_D
funit_side: 2
funit_side_set: true
parallel: 0
parallel_set: true
-
asm_text: "ldndw.D1T1 *+a3(a4), a23:a22"
details:
tms320c64x:
operands:
-
type: TMS320C64X_OP_MEM
mem_base: a3
mem_disptype: TMS320C64X_MEM_DISP_REGISTER
mem_disp_reg: a4
mem_unit: 1
mem_direction: TMS320C64X_MEM_DIR_FW
mem_modify: TMS320C64X_MEM_MOD_NO
mem_scaled: -1
-
type: TMS320C64X_OP_REGPAIR
reg_pair_0: a23
reg_pair_1: a22
funit_unit: TMS320C64X_FUNIT_D
funit_side: 1
funit_side_set: true
parallel: 0
parallel_set: true

101
thirdparty/capstone/tests/details/tricore.yaml vendored Normal file
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test_cases:
-
input:
bytes: [ 0x09, 0xcf, 0xbc, 0xf5, 0x09, 0xf4, 0x01, 0x00, 0x89, 0xfb, 0x8f, 0x74, 0x89, 0xfe, 0x48, 0x01, 0x29, 0x00, 0x19, 0x25, 0x29, 0x03, 0x09, 0xf4, 0x85, 0xf9, 0x68, 0x0f, 0x16, 0x01 ]
arch: "tricore"
options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
address: 0x0
expected:
insns:
-
asm_text: "ld.a a15, [+a12]#-4"
details:
tricore:
operands:
-
type: TRICORE_OP_REG
reg: a15
-
type: TRICORE_OP_MEM
mem_base: a12
mem_disp: -4
-
asm_text: "ld.b d4, [a15+]#1"
details:
tricore:
operands:
-
type: TRICORE_OP_REG
reg: d4
-
type: TRICORE_OP_MEM
mem_base: a15
mem_disp: 0x1
-
asm_text: "st.h [+a15]#0x1cf, d11"
details:
tricore:
operands:
-
type: TRICORE_OP_MEM
mem_base: a15
mem_disp: 0x1cf
-
type: TRICORE_OP_REG
reg: d11
-
asm_text: "st.d [a15+]#8, e14"
details:
tricore:
operands:
-
type: TRICORE_OP_MEM
mem_base: a15
mem_disp: 0x8
-
type: TRICORE_OP_REG
reg: e14
-
asm_text: "ld.w d0, [p0+c]#0x99"
details:
tricore:
operands:
-
type: TRICORE_OP_REG
reg: d0
-
type: TRICORE_OP_MEM
mem_base: p0
mem_disp: 0x99
-
asm_text: "ld.b d3, [p0+c]#-0x37"
details:
tricore:
operands:
-
type: TRICORE_OP_REG
reg: d3
-
type: TRICORE_OP_MEM
mem_base: p0
mem_disp: -0x37
-
asm_text: "ld.da p8, #0xf0003428"
details:
tricore:
operands:
-
type: TRICORE_OP_REG
reg: p8
-
type: TRICORE_OP_IMM
imm: 0xf0003428
-
asm_text: "and d15, #1"
details:
tricore:
operands:
-
type: TRICORE_OP_IMM
imm: 0x1

58
thirdparty/capstone/tests/details/wasm.yaml vendored Normal file
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test_cases:
-
input:
bytes: [ 0x20, 0x00, 0x20, 0x01, 0x41, 0x20, 0x10, 0xc9, 0x01, 0x45, 0x0b ]
arch: "wasm"
options: [ CS_OPT_DETAIL ]
address: 0x0
expected:
insns:
-
asm_text: "get_local 0x0"
details:
groups: [ WASM_GRP_VARIABLE ]
wasm:
operands:
-
type: WASM_OP_VARUINT32
varuint32: 0x0
size: 1
-
asm_text: "get_local 0x1"
details:
groups: [ WASM_GRP_VARIABLE ]
wasm:
operands:
-
type: WASM_OP_VARUINT32
varuint32: 0x1
size: 1
-
asm_text: "i32.const 0x20"
details:
groups: [ WASM_GRP_NUMBERIC ]
wasm:
operands:
-
type: WASM_OP_VARUINT32
varuint32: 0x20
size: 1
-
asm_text: "call 0xc9"
details:
groups: [ WASM_GRP_CONTROL ]
wasm:
operands:
-
type: WASM_OP_VARUINT32
varuint32: 0xc9
size: 2
-
asm_text: "i32.eqz"
details:
groups: [ WASM_GRP_NUMBERIC ]
-
asm_text: "end"
details:
groups: [ WASM_GRP_CONTROL ]

1242
thirdparty/capstone/tests/details/x86.yaml vendored Normal file
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128
thirdparty/capstone/tests/details/xcore.yaml vendored Normal file
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test_cases:
-
input:
bytes: [ 0xfe, 0x0f, 0xfe, 0x17, 0x13, 0x17, 0xc6, 0xfe, 0xec, 0x17, 0x97, 0xf8, 0xec, 0x4f, 0x1f, 0xfd, 0xec, 0x37, 0x07, 0xf2, 0x45, 0x5b, 0xf9, 0xfa, 0x02, 0x06, 0x1b, 0x10, 0x09, 0xfd, 0xec, 0xa7 ]
arch: "xcore"
options: [ CS_OPT_DETAIL ]
address: 0x0
expected:
insns:
-
asm_text: "get r11, ed"
details:
xcore:
operands:
-
type: XCORE_OP_REG
reg: r11
-
type: XCORE_OP_REG
reg: ed
-
asm_text: "ldw et, sp[4]"
details:
xcore:
operands:
-
type: XCORE_OP_REG
reg: et
-
type: XCORE_OP_MEM
mem_base: sp
mem_disp: 0x4
-
asm_text: "setd res[r3], r4"
details:
xcore:
operands:
-
type: XCORE_OP_REG
reg: r4
-
asm_text: "init t[r2]:lr, r1"
details:
xcore:
operands:
-
type: XCORE_OP_MEM
mem_base: r2
mem_index: lr
-
type: XCORE_OP_REG
reg: r1
-
asm_text: "divu r9, r1, r3"
details:
xcore:
operands:
-
type: XCORE_OP_REG
reg: r9
-
type: XCORE_OP_REG
reg: r1
-
type: XCORE_OP_REG
reg: r3
-
asm_text: "lda16 r9, r3[-r11]"
details:
xcore:
operands:
-
type: XCORE_OP_REG
reg: r9
-
asm_text: "ldw dp, dp[0x81c5]"
details:
xcore:
operands:
-
type: XCORE_OP_REG
reg: dp
-
asm_text: "lmul r11, r0, r2, r5, r8, r10"
details:
xcore:
operands:
-
type: XCORE_OP_REG
reg: r11
-
type: XCORE_OP_REG
reg: r0
-
type: XCORE_OP_REG
reg: r2
-
type: XCORE_OP_REG
reg: r5
-
type: XCORE_OP_REG
reg: r8
-
type: XCORE_OP_REG
reg: r10
-
asm_text: "add r1, r2, r3"
details:
xcore:
operands:
-
type: XCORE_OP_REG
reg: r1
-
type: XCORE_OP_REG
reg: r2
-
type: XCORE_OP_REG
reg: r3
-
asm_text: "ldaw r8, r2[-9]"
details:
xcore:
operands:
-
type: XCORE_OP_REG
reg: r8