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Add missing thirdparty files

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Sajid
2024-09-08 17:16:32 +06:00
parent 458577aaee
commit 13ec7258e1
488 changed files with 1066961 additions and 1 deletions
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1000
thirdparty/capstone/arch/X86/X86ATTInstPrinter.c vendored Normal file
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thirdparty/capstone/arch/X86/X86BaseInfo.h vendored Normal file
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//===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains small standalone helper functions and enum definitions for
// the X86 target useful for the compiler back-end and the MC libraries.
// As such, it deliberately does not include references to LLVM core
// code gen types, passes, etc..
//
//===----------------------------------------------------------------------===//
#ifndef CS_X86_BASEINFO_H
#define CS_X86_BASEINFO_H
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
// Enums for memory operand decoding. Each memory operand is represented with
// a 5 operand sequence in the form:
// [BaseReg, ScaleAmt, IndexReg, Disp, Segment]
// These enums help decode this.
enum {
X86_AddrBaseReg = 0,
X86_AddrScaleAmt = 1,
X86_AddrIndexReg = 2,
X86_AddrDisp = 3,
/// AddrSegmentReg - The operand # of the segment in the memory operand.
X86_AddrSegmentReg = 4,
/// AddrNumOperands - Total number of operands in a memory reference.
X86_AddrNumOperands = 5
};
enum IPREFIXES {
X86_IP_NO_PREFIX = 0,
X86_IP_HAS_OP_SIZE = 1,
X86_IP_HAS_AD_SIZE = 2,
X86_IP_HAS_REPEAT_NE = 4,
X86_IP_HAS_REPEAT = 8,
X86_IP_HAS_LOCK = 16,
X86_IP_HAS_NOTRACK = 64
};
#endif

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thirdparty/capstone/arch/X86/X86Disassembler.c vendored Normal file
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//===-- X86Disassembler.h - Disassembler for x86 and x86_64 -----*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
#ifndef CS_X86_DISASSEMBLER_H
#define CS_X86_DISASSEMBLER_H
#include "capstone/capstone.h"
#include "../../MCInst.h"
#include "../../MCRegisterInfo.h"
#include "X86DisassemblerDecoderCommon.h"
bool X86_getInstruction(csh handle, const uint8_t *code, size_t code_len,
MCInst *instr, uint16_t *size, uint64_t address, void *info);
void X86_init(MCRegisterInfo *MRI);
#endif

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thirdparty/capstone/arch/X86/X86DisassemblerDecoder.c vendored Normal file
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/*===-- X86DisassemblerDecoderInternal.h - Disassembler decoder ---*- C -*-===*
*
* The LLVM Compiler Infrastructure
*
* This file is distributed under the University of Illinois Open Source
* License. See LICENSE.TXT for details.
*
*===----------------------------------------------------------------------===*
*
* This file is part of the X86 Disassembler.
* It contains the public interface of the instruction decoder.
* Documentation for the disassembler can be found in X86Disassembler.h.
*
*===----------------------------------------------------------------------===*/
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
#ifndef CS_X86_DISASSEMBLERDECODER_H
#define CS_X86_DISASSEMBLERDECODER_H
#if defined(CAPSTONE_HAS_OSXKERNEL)
#include <libkern/libkern.h>
#else
#include <stdio.h>
#endif
#include "X86DisassemblerDecoderCommon.h"
/*
* Accessor functions for various fields of an Intel instruction
*/
#define modFromModRM(modRM) (((modRM) & 0xc0) >> 6)
#define regFromModRM(modRM) (((modRM) & 0x38) >> 3)
#define rmFromModRM(modRM) ((modRM) & 0x7)
#define scaleFromSIB(sib) (((sib) & 0xc0) >> 6)
#define indexFromSIB(sib) (((sib) & 0x38) >> 3)
#define baseFromSIB(sib) ((sib) & 0x7)
#define wFromREX(rex) (((rex) & 0x8) >> 3)
#define rFromREX(rex) (((rex) & 0x4) >> 2)
#define xFromREX(rex) (((rex) & 0x2) >> 1)
#define bFromREX(rex) ((rex) & 0x1)
#define rFromEVEX2of4(evex) (((~(evex)) & 0x80) >> 7)
#define xFromEVEX2of4(evex) (((~(evex)) & 0x40) >> 6)
#define bFromEVEX2of4(evex) (((~(evex)) & 0x20) >> 5)
#define r2FromEVEX2of4(evex) (((~(evex)) & 0x10) >> 4)
#define mmFromEVEX2of4(evex) ((evex) & 0x3)
#define wFromEVEX3of4(evex) (((evex) & 0x80) >> 7)
#define vvvvFromEVEX3of4(evex) (((~(evex)) & 0x78) >> 3)
#define ppFromEVEX3of4(evex) ((evex) & 0x3)
#define zFromEVEX4of4(evex) (((evex) & 0x80) >> 7)
#define l2FromEVEX4of4(evex) (((evex) & 0x40) >> 6)
#define lFromEVEX4of4(evex) (((evex) & 0x20) >> 5)
#define bFromEVEX4of4(evex) (((evex) & 0x10) >> 4)
#define v2FromEVEX4of4(evex) (((~evex) & 0x8) >> 3)
#define aaaFromEVEX4of4(evex) ((evex) & 0x7)
#define rFromVEX2of3(vex) (((~(vex)) & 0x80) >> 7)
#define xFromVEX2of3(vex) (((~(vex)) & 0x40) >> 6)
#define bFromVEX2of3(vex) (((~(vex)) & 0x20) >> 5)
#define mmmmmFromVEX2of3(vex) ((vex) & 0x1f)
#define wFromVEX3of3(vex) (((vex) & 0x80) >> 7)
#define vvvvFromVEX3of3(vex) (((~(vex)) & 0x78) >> 3)
#define lFromVEX3of3(vex) (((vex) & 0x4) >> 2)
#define ppFromVEX3of3(vex) ((vex) & 0x3)
#define rFromVEX2of2(vex) (((~(vex)) & 0x80) >> 7)
#define vvvvFromVEX2of2(vex) (((~(vex)) & 0x78) >> 3)
#define lFromVEX2of2(vex) (((vex) & 0x4) >> 2)
#define ppFromVEX2of2(vex) ((vex) & 0x3)
#define rFromXOP2of3(xop) (((~(xop)) & 0x80) >> 7)
#define xFromXOP2of3(xop) (((~(xop)) & 0x40) >> 6)
#define bFromXOP2of3(xop) (((~(xop)) & 0x20) >> 5)
#define mmmmmFromXOP2of3(xop) ((xop) & 0x1f)
#define wFromXOP3of3(xop) (((xop) & 0x80) >> 7)
#define vvvvFromXOP3of3(vex) (((~(vex)) & 0x78) >> 3)
#define lFromXOP3of3(xop) (((xop) & 0x4) >> 2)
#define ppFromXOP3of3(xop) ((xop) & 0x3)
/*
* These enums represent Intel registers for use by the decoder.
*/
#define REGS_8BIT \
ENTRY(AL) \
ENTRY(CL) \
ENTRY(DL) \
ENTRY(BL) \
ENTRY(AH) \
ENTRY(CH) \
ENTRY(DH) \
ENTRY(BH) \
ENTRY(R8B) \
ENTRY(R9B) \
ENTRY(R10B) \
ENTRY(R11B) \
ENTRY(R12B) \
ENTRY(R13B) \
ENTRY(R14B) \
ENTRY(R15B) \
ENTRY(SPL) \
ENTRY(BPL) \
ENTRY(SIL) \
ENTRY(DIL)
#define EA_BASES_16BIT \
ENTRY(BX_SI) \
ENTRY(BX_DI) \
ENTRY(BP_SI) \
ENTRY(BP_DI) \
ENTRY(SI) \
ENTRY(DI) \
ENTRY(BP) \
ENTRY(BX) \
ENTRY(R8W) \
ENTRY(R9W) \
ENTRY(R10W) \
ENTRY(R11W) \
ENTRY(R12W) \
ENTRY(R13W) \
ENTRY(R14W) \
ENTRY(R15W)
#define REGS_16BIT \
ENTRY(AX) \
ENTRY(CX) \
ENTRY(DX) \
ENTRY(BX) \
ENTRY(SP) \
ENTRY(BP) \
ENTRY(SI) \
ENTRY(DI) \
ENTRY(R8W) \
ENTRY(R9W) \
ENTRY(R10W) \
ENTRY(R11W) \
ENTRY(R12W) \
ENTRY(R13W) \
ENTRY(R14W) \
ENTRY(R15W)
#define EA_BASES_32BIT \
ENTRY(EAX) \
ENTRY(ECX) \
ENTRY(EDX) \
ENTRY(EBX) \
ENTRY(sib) \
ENTRY(EBP) \
ENTRY(ESI) \
ENTRY(EDI) \
ENTRY(R8D) \
ENTRY(R9D) \
ENTRY(R10D) \
ENTRY(R11D) \
ENTRY(R12D) \
ENTRY(R13D) \
ENTRY(R14D) \
ENTRY(R15D)
#define REGS_32BIT \
ENTRY(EAX) \
ENTRY(ECX) \
ENTRY(EDX) \
ENTRY(EBX) \
ENTRY(ESP) \
ENTRY(EBP) \
ENTRY(ESI) \
ENTRY(EDI) \
ENTRY(R8D) \
ENTRY(R9D) \
ENTRY(R10D) \
ENTRY(R11D) \
ENTRY(R12D) \
ENTRY(R13D) \
ENTRY(R14D) \
ENTRY(R15D)
#define EA_BASES_64BIT \
ENTRY(RAX) \
ENTRY(RCX) \
ENTRY(RDX) \
ENTRY(RBX) \
ENTRY(sib64) \
ENTRY(RBP) \
ENTRY(RSI) \
ENTRY(RDI) \
ENTRY(R8) \
ENTRY(R9) \
ENTRY(R10) \
ENTRY(R11) \
ENTRY(R12) \
ENTRY(R13) \
ENTRY(R14) \
ENTRY(R15)
#define REGS_64BIT \
ENTRY(RAX) \
ENTRY(RCX) \
ENTRY(RDX) \
ENTRY(RBX) \
ENTRY(RSP) \
ENTRY(RBP) \
ENTRY(RSI) \
ENTRY(RDI) \
ENTRY(R8) \
ENTRY(R9) \
ENTRY(R10) \
ENTRY(R11) \
ENTRY(R12) \
ENTRY(R13) \
ENTRY(R14) \
ENTRY(R15)
#define REGS_MMX \
ENTRY(MM0) \
ENTRY(MM1) \
ENTRY(MM2) \
ENTRY(MM3) \
ENTRY(MM4) \
ENTRY(MM5) \
ENTRY(MM6) \
ENTRY(MM7)
#define REGS_XMM \
ENTRY(XMM0) \
ENTRY(XMM1) \
ENTRY(XMM2) \
ENTRY(XMM3) \
ENTRY(XMM4) \
ENTRY(XMM5) \
ENTRY(XMM6) \
ENTRY(XMM7) \
ENTRY(XMM8) \
ENTRY(XMM9) \
ENTRY(XMM10) \
ENTRY(XMM11) \
ENTRY(XMM12) \
ENTRY(XMM13) \
ENTRY(XMM14) \
ENTRY(XMM15) \
ENTRY(XMM16) \
ENTRY(XMM17) \
ENTRY(XMM18) \
ENTRY(XMM19) \
ENTRY(XMM20) \
ENTRY(XMM21) \
ENTRY(XMM22) \
ENTRY(XMM23) \
ENTRY(XMM24) \
ENTRY(XMM25) \
ENTRY(XMM26) \
ENTRY(XMM27) \
ENTRY(XMM28) \
ENTRY(XMM29) \
ENTRY(XMM30) \
ENTRY(XMM31)
#define REGS_YMM \
ENTRY(YMM0) \
ENTRY(YMM1) \
ENTRY(YMM2) \
ENTRY(YMM3) \
ENTRY(YMM4) \
ENTRY(YMM5) \
ENTRY(YMM6) \
ENTRY(YMM7) \
ENTRY(YMM8) \
ENTRY(YMM9) \
ENTRY(YMM10) \
ENTRY(YMM11) \
ENTRY(YMM12) \
ENTRY(YMM13) \
ENTRY(YMM14) \
ENTRY(YMM15) \
ENTRY(YMM16) \
ENTRY(YMM17) \
ENTRY(YMM18) \
ENTRY(YMM19) \
ENTRY(YMM20) \
ENTRY(YMM21) \
ENTRY(YMM22) \
ENTRY(YMM23) \
ENTRY(YMM24) \
ENTRY(YMM25) \
ENTRY(YMM26) \
ENTRY(YMM27) \
ENTRY(YMM28) \
ENTRY(YMM29) \
ENTRY(YMM30) \
ENTRY(YMM31)
#define REGS_ZMM \
ENTRY(ZMM0) \
ENTRY(ZMM1) \
ENTRY(ZMM2) \
ENTRY(ZMM3) \
ENTRY(ZMM4) \
ENTRY(ZMM5) \
ENTRY(ZMM6) \
ENTRY(ZMM7) \
ENTRY(ZMM8) \
ENTRY(ZMM9) \
ENTRY(ZMM10) \
ENTRY(ZMM11) \
ENTRY(ZMM12) \
ENTRY(ZMM13) \
ENTRY(ZMM14) \
ENTRY(ZMM15) \
ENTRY(ZMM16) \
ENTRY(ZMM17) \
ENTRY(ZMM18) \
ENTRY(ZMM19) \
ENTRY(ZMM20) \
ENTRY(ZMM21) \
ENTRY(ZMM22) \
ENTRY(ZMM23) \
ENTRY(ZMM24) \
ENTRY(ZMM25) \
ENTRY(ZMM26) \
ENTRY(ZMM27) \
ENTRY(ZMM28) \
ENTRY(ZMM29) \
ENTRY(ZMM30) \
ENTRY(ZMM31)
#define REGS_MASKS \
ENTRY(K0) \
ENTRY(K1) \
ENTRY(K2) \
ENTRY(K3) \
ENTRY(K4) \
ENTRY(K5) \
ENTRY(K6) \
ENTRY(K7)
#define REGS_SEGMENT \
ENTRY(ES) \
ENTRY(CS) \
ENTRY(SS) \
ENTRY(DS) \
ENTRY(FS) \
ENTRY(GS)
#define REGS_DEBUG \
ENTRY(DR0) \
ENTRY(DR1) \
ENTRY(DR2) \
ENTRY(DR3) \
ENTRY(DR4) \
ENTRY(DR5) \
ENTRY(DR6) \
ENTRY(DR7) \
ENTRY(DR8) \
ENTRY(DR9) \
ENTRY(DR10) \
ENTRY(DR11) \
ENTRY(DR12) \
ENTRY(DR13) \
ENTRY(DR14) \
ENTRY(DR15)
#define REGS_CONTROL \
ENTRY(CR0) \
ENTRY(CR1) \
ENTRY(CR2) \
ENTRY(CR3) \
ENTRY(CR4) \
ENTRY(CR5) \
ENTRY(CR6) \
ENTRY(CR7) \
ENTRY(CR8) \
ENTRY(CR9) \
ENTRY(CR10) \
ENTRY(CR11) \
ENTRY(CR12) \
ENTRY(CR13) \
ENTRY(CR14) \
ENTRY(CR15)
#define REGS_BOUND \
ENTRY(BND0) \
ENTRY(BND1) \
ENTRY(BND2) \
ENTRY(BND3)
#define ALL_EA_BASES \
EA_BASES_16BIT \
EA_BASES_32BIT \
EA_BASES_64BIT
#define ALL_SIB_BASES \
REGS_32BIT \
REGS_64BIT
#define ALL_REGS \
REGS_8BIT \
REGS_16BIT \
REGS_32BIT \
REGS_64BIT \
REGS_MMX \
REGS_XMM \
REGS_YMM \
REGS_ZMM \
REGS_MASKS \
REGS_SEGMENT \
REGS_DEBUG \
REGS_CONTROL \
REGS_BOUND \
ENTRY(RIP)
/*
* EABase - All possible values of the base field for effective-address
* computations, a.k.a. the Mod and R/M fields of the ModR/M byte. We
* distinguish between bases (EA_BASE_*) and registers that just happen to be
* referred to when Mod == 0b11 (EA_REG_*).
*/
typedef enum {
EA_BASE_NONE,
#define ENTRY(x) EA_BASE_##x,
ALL_EA_BASES
#undef ENTRY
#define ENTRY(x) EA_REG_##x,
ALL_REGS
#undef ENTRY
EA_max
} EABase;
/*
* SIBIndex - All possible values of the SIB index field.
* Borrows entries from ALL_EA_BASES with the special case that
* sib is synonymous with NONE.
* Vector SIB: index can be XMM or YMM.
*/
typedef enum {
SIB_INDEX_NONE,
#define ENTRY(x) SIB_INDEX_##x,
ALL_EA_BASES
REGS_XMM
REGS_YMM
REGS_ZMM
#undef ENTRY
SIB_INDEX_max
} SIBIndex;
/*
* SIBBase - All possible values of the SIB base field.
*/
typedef enum {
SIB_BASE_NONE,
#define ENTRY(x) SIB_BASE_##x,
ALL_SIB_BASES
#undef ENTRY
SIB_BASE_max
} SIBBase;
/*
* EADisplacement - Possible displacement types for effective-address
* computations.
*/
typedef enum {
EA_DISP_NONE,
EA_DISP_8,
EA_DISP_16,
EA_DISP_32
} EADisplacement;
/*
* Reg - All possible values of the reg field in the ModR/M byte.
*/
typedef enum {
#define ENTRY(x) MODRM_REG_##x,
ALL_REGS
#undef ENTRY
MODRM_REG_max
} Reg;
/*
* SegmentOverride - All possible segment overrides.
*/
typedef enum {
SEG_OVERRIDE_NONE,
SEG_OVERRIDE_CS,
SEG_OVERRIDE_SS,
SEG_OVERRIDE_DS,
SEG_OVERRIDE_ES,
SEG_OVERRIDE_FS,
SEG_OVERRIDE_GS,
SEG_OVERRIDE_max
} SegmentOverride;
/*
* VEXLeadingOpcodeByte - Possible values for the VEX.m-mmmm field
*/
typedef enum {
VEX_LOB_0F = 0x1,
VEX_LOB_0F38 = 0x2,
VEX_LOB_0F3A = 0x3
} VEXLeadingOpcodeByte;
typedef enum {
XOP_MAP_SELECT_8 = 0x8,
XOP_MAP_SELECT_9 = 0x9,
XOP_MAP_SELECT_A = 0xA
} XOPMapSelect;
/*
* VEXPrefixCode - Possible values for the VEX.pp/EVEX.pp field
*/
typedef enum {
VEX_PREFIX_NONE = 0x0,
VEX_PREFIX_66 = 0x1,
VEX_PREFIX_F3 = 0x2,
VEX_PREFIX_F2 = 0x3
} VEXPrefixCode;
typedef enum {
TYPE_NO_VEX_XOP = 0x0,
TYPE_VEX_2B = 0x1,
TYPE_VEX_3B = 0x2,
TYPE_EVEX = 0x3,
TYPE_XOP = 0x4
} VectorExtensionType;
struct reader_info {
const uint8_t *code;
uint64_t size;
uint64_t offset;
};
/*
* byteReader_t - Type for the byte reader that the consumer must provide to
* the decoder. Reads a single byte from the instruction's address space.
* @param arg - A baton that the consumer can associate with any internal
* state that it needs.
* @param byte - A pointer to a single byte in memory that should be set to
* contain the value at address.
* @param address - The address in the instruction's address space that should
* be read from.
* @return - -1 if the byte cannot be read for any reason; 0 otherwise.
*/
typedef int (*byteReader_t)(const struct reader_info *arg, uint8_t* byte, uint64_t address);
/// The specification for how to extract and interpret a full instruction and
/// its operands.
struct InstructionSpecifier {
#ifdef CAPSTONE_X86_REDUCE
uint8_t operands;
#else
uint16_t operands;
#endif
};
/*
* The x86 internal instruction, which is produced by the decoder.
*/
typedef struct InternalInstruction {
// from here, all members must be initialized to ZERO to work properly
uint8_t operandSize;
uint8_t prefix0, prefix1, prefix2, prefix3;
/* The value of the REX prefix, if present */
uint8_t rexPrefix;
/* The segment override type */
SegmentOverride segmentOverride;
bool consumedModRM;
uint8_t orgModRM; // save original modRM because we will modify modRM
/* The SIB byte, used for more complex 32- or 64-bit memory operands */
bool consumedSIB;
uint8_t sib;
/* The displacement, used for memory operands */
bool consumedDisplacement;
int64_t displacement;
/* The value of the two-byte escape prefix (usually 0x0f) */
uint8_t twoByteEscape;
/* The value of the three-byte escape prefix (usually 0x38 or 0x3a) */
uint8_t threeByteEscape;
/* SIB state */
SIBIndex sibIndexBase;
SIBIndex sibIndex;
uint8_t sibScale;
SIBBase sibBase;
// Embedded rounding control.
uint8_t RC;
uint8_t numImmediatesConsumed;
/* 0xf2 or 0xf3 is xacquire or xrelease */
uint8_t xAcquireRelease;
// Address-size override
bool hasAdSize;
// Operand-size override
bool hasOpSize;
// Lock prefix
bool hasLockPrefix;
// The repeat prefix if any
uint8_t repeatPrefix;
// The possible mandatory prefix
uint8_t mandatoryPrefix;
/* The value of the vector extension prefix(EVEX/VEX/XOP), if present */
uint8_t vectorExtensionPrefix[4];
/* Offsets from the start of the instruction to the pieces of data, which is
needed to find relocation entries for adding symbolic operands */
uint8_t displacementOffset;
uint8_t immediateOffset;
uint8_t modRMOffset;
// end-of-zero-members
/* Reader interface (C) */
byteReader_t reader;
/* Opaque value passed to the reader */
const void* readerArg;
/* The address of the next byte to read via the reader */
uint64_t readerCursor;
/* General instruction information */
/* The mode to disassemble for (64-bit, protected, real) */
DisassemblerMode mode;
/* The start of the instruction, usable with the reader */
uint64_t startLocation;
/* The length of the instruction, in bytes */
size_t length;
/* Prefix state */
/* The type of the vector extension prefix */
VectorExtensionType vectorExtensionType;
/* Sizes of various critical pieces of data, in bytes */
uint8_t registerSize;
uint8_t addressSize;
uint8_t displacementSize;
uint8_t immediateSize;
uint8_t immSize; // immediate size for X86_OP_IMM operand
/* opcode state */
/* The last byte of the opcode, not counting any ModR/M extension */
uint8_t opcode;
/* decode state */
/* The type of opcode, used for indexing into the array of decode tables */
OpcodeType opcodeType;
/* The instruction ID, extracted from the decode table */
uint16_t instructionID;
/* The specifier for the instruction, from the instruction info table */
const struct InstructionSpecifier *spec;
/* state for additional bytes, consumed during operand decode. Pattern:
consumed___ indicates that the byte was already consumed and does not
need to be consumed again */
/* The VEX.vvvv field, which contains a third register operand for some AVX
instructions */
Reg vvvv;
/* The writemask for AVX-512 instructions which is contained in EVEX.aaa */
Reg writemask;
/* The ModR/M byte, which contains most register operands and some portion of
all memory operands */
uint8_t modRM;
// special data to handle MOVcr, MOVdr, MOVrc, MOVrd
uint8_t firstByte; // save the first byte in stream
/* Immediates. There can be two in some cases */
uint8_t numImmediatesTranslated;
uint64_t immediates[2];
/* A register or immediate operand encoded into the opcode */
Reg opcodeRegister;
/* Portions of the ModR/M byte */
/* These fields determine the allowable values for the ModR/M fields, which
depend on operand and address widths */
EABase eaRegBase;
Reg regBase;
/* The Mod and R/M fields can encode a base for an effective address, or a
register. These are separated into two fields here */
EABase eaBase;
EADisplacement eaDisplacement;
/* The reg field always encodes a register */
Reg reg;
const struct OperandSpecifier *operands;
} InternalInstruction;
/* decodeInstruction - Decode one instruction and store the decoding results in
* a buffer provided by the consumer.
* @param insn - The buffer to store the instruction in. Allocated by the
* consumer.
* @param reader - The byteReader_t for the bytes to be read.
* @param readerArg - An argument to pass to the reader for storing context
* specific to the consumer. May be NULL.
* @param logger - The dlog_t to be used in printing status messages from the
* disassembler. May be NULL.
* @param loggerArg - An argument to pass to the logger for storing context
* specific to the logger. May be NULL.
* @param startLoc - The address (in the reader's address space) of the first
* byte in the instruction.
* @param mode - The mode (16-bit, 32-bit, 64-bit) to decode in.
* @return - Nonzero if there was an error during decode, 0 otherwise.
*/
int decodeInstruction(struct InternalInstruction* insn,
byteReader_t reader,
const void* readerArg,
uint64_t startLoc,
DisassemblerMode mode);
//const char *x86DisassemblerGetInstrName(unsigned Opcode, const void *mii);
#endif

483
thirdparty/capstone/arch/X86/X86DisassemblerDecoderCommon.h vendored Normal file
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/*===-- X86DisassemblerDecoderCommon.h - Disassembler decoder -----*- C -*-===*
*
* The LLVM Compiler Infrastructure
*
* This file is distributed under the University of Illinois Open Source
* License. See LICENSE.TXT for details.
*
*===----------------------------------------------------------------------===*
*
* This file is part of the X86 Disassembler.
* It contains common definitions used by both the disassembler and the table
* generator.
* Documentation for the disassembler can be found in X86Disassembler.h.
*
*===----------------------------------------------------------------------===*/
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
/*
* This header file provides those definitions that need to be shared between
* the decoder and the table generator in a C-friendly manner.
*/
#ifndef CS_X86_DISASSEMBLERDECODERCOMMON_H
#define CS_X86_DISASSEMBLERDECODERCOMMON_H
#define INSTRUCTIONS_SYM x86DisassemblerInstrSpecifiers
#define CONTEXTS_SYM x86DisassemblerContexts
#define ONEBYTE_SYM x86DisassemblerOneByteOpcodes
#define TWOBYTE_SYM x86DisassemblerTwoByteOpcodes
#define THREEBYTE38_SYM x86DisassemblerThreeByte38Opcodes
#define THREEBYTE3A_SYM x86DisassemblerThreeByte3AOpcodes
#define XOP8_MAP_SYM x86DisassemblerXOP8Opcodes
#define XOP9_MAP_SYM x86DisassemblerXOP9Opcodes
#define XOPA_MAP_SYM x86DisassemblerXOPAOpcodes
#define THREEDNOW_MAP_SYM x86Disassembler3DNowOpcodes
/*
* Attributes of an instruction that must be known before the opcode can be
* processed correctly. Most of these indicate the presence of particular
* prefixes, but ATTR_64BIT is simply an attribute of the decoding context.
*/
#define ATTRIBUTE_BITS \
ENUM_ENTRY(ATTR_NONE, 0x00) \
ENUM_ENTRY(ATTR_64BIT, (0x1 << 0)) \
ENUM_ENTRY(ATTR_XS, (0x1 << 1)) \
ENUM_ENTRY(ATTR_XD, (0x1 << 2)) \
ENUM_ENTRY(ATTR_REXW, (0x1 << 3)) \
ENUM_ENTRY(ATTR_OPSIZE, (0x1 << 4)) \
ENUM_ENTRY(ATTR_ADSIZE, (0x1 << 5)) \
ENUM_ENTRY(ATTR_VEX, (0x1 << 6)) \
ENUM_ENTRY(ATTR_VEXL, (0x1 << 7)) \
ENUM_ENTRY(ATTR_EVEX, (0x1 << 8)) \
ENUM_ENTRY(ATTR_EVEXL, (0x1 << 9)) \
ENUM_ENTRY(ATTR_EVEXL2, (0x1 << 10)) \
ENUM_ENTRY(ATTR_EVEXK, (0x1 << 11)) \
ENUM_ENTRY(ATTR_EVEXKZ, (0x1 << 12)) \
ENUM_ENTRY(ATTR_EVEXB, (0x1 << 13))
#define ENUM_ENTRY(n, v) n = v,
enum attributeBits {
ATTRIBUTE_BITS
ATTR_max
};
#undef ENUM_ENTRY
/*
* Combinations of the above attributes that are relevant to instruction
* decode. Although other combinations are possible, they can be reduced to
* these without affecting the ultimately decoded instruction.
*/
// Class name Rank Rationale for rank assignment
#define INSTRUCTION_CONTEXTS \
ENUM_ENTRY(IC, 0, "says nothing about the instruction") \
ENUM_ENTRY(IC_64BIT, 1, "says the instruction applies in " \
"64-bit mode but no more") \
ENUM_ENTRY(IC_OPSIZE, 3, "requires an OPSIZE prefix, so " \
"operands change width") \
ENUM_ENTRY(IC_ADSIZE, 3, "requires an ADSIZE prefix, so " \
"operands change width") \
ENUM_ENTRY(IC_OPSIZE_ADSIZE, 4, "requires ADSIZE and OPSIZE prefixes") \
ENUM_ENTRY(IC_XD, 2, "may say something about the opcode " \
"but not the operands") \
ENUM_ENTRY(IC_XS, 2, "may say something about the opcode " \
"but not the operands") \
ENUM_ENTRY(IC_XD_OPSIZE, 3, "requires an OPSIZE prefix, so " \
"operands change width") \
ENUM_ENTRY(IC_XS_OPSIZE, 3, "requires an OPSIZE prefix, so " \
"operands change width") \
ENUM_ENTRY(IC_XD_ADSIZE, 3, "requires an ADSIZE prefix, so " \
"operands change width") \
ENUM_ENTRY(IC_XS_ADSIZE, 3, "requires an ADSIZE prefix, so " \
"operands change width") \
ENUM_ENTRY(IC_64BIT_REXW, 5, "requires a REX.W prefix, so operands "\
"change width; overrides IC_OPSIZE") \
ENUM_ENTRY(IC_64BIT_REXW_ADSIZE, 6, "requires a REX.W prefix and 0x67 " \
"prefix") \
ENUM_ENTRY(IC_64BIT_OPSIZE, 3, "Just as meaningful as IC_OPSIZE") \
ENUM_ENTRY(IC_64BIT_ADSIZE, 3, "Just as meaningful as IC_ADSIZE") \
ENUM_ENTRY(IC_64BIT_OPSIZE_ADSIZE, 4, "Just as meaningful as IC_OPSIZE/" \
"IC_ADSIZE") \
ENUM_ENTRY(IC_64BIT_XD, 6, "XD instructions are SSE; REX.W is " \
"secondary") \
ENUM_ENTRY(IC_64BIT_XS, 6, "Just as meaningful as IC_64BIT_XD") \
ENUM_ENTRY(IC_64BIT_XD_OPSIZE, 3, "Just as meaningful as IC_XD_OPSIZE") \
ENUM_ENTRY(IC_64BIT_XS_OPSIZE, 3, "Just as meaningful as IC_XS_OPSIZE") \
ENUM_ENTRY(IC_64BIT_XD_ADSIZE, 3, "Just as meaningful as IC_XD_ADSIZE") \
ENUM_ENTRY(IC_64BIT_XS_ADSIZE, 3, "Just as meaningful as IC_XS_ADSIZE") \
ENUM_ENTRY(IC_64BIT_REXW_XS, 7, "OPSIZE could mean a different " \
"opcode") \
ENUM_ENTRY(IC_64BIT_REXW_XD, 7, "Just as meaningful as " \
"IC_64BIT_REXW_XS") \
ENUM_ENTRY(IC_64BIT_REXW_OPSIZE, 8, "The Dynamic Duo! Prefer over all " \
"else because this changes most " \
"operands' meaning") \
ENUM_ENTRY(IC_VEX, 1, "requires a VEX prefix") \
ENUM_ENTRY(IC_VEX_XS, 2, "requires VEX and the XS prefix") \
ENUM_ENTRY(IC_VEX_XD, 2, "requires VEX and the XD prefix") \
ENUM_ENTRY(IC_VEX_OPSIZE, 2, "requires VEX and the OpSize prefix") \
ENUM_ENTRY(IC_VEX_W, 3, "requires VEX and the W prefix") \
ENUM_ENTRY(IC_VEX_W_XS, 4, "requires VEX, W, and XS prefix") \
ENUM_ENTRY(IC_VEX_W_XD, 4, "requires VEX, W, and XD prefix") \
ENUM_ENTRY(IC_VEX_W_OPSIZE, 4, "requires VEX, W, and OpSize") \
ENUM_ENTRY(IC_VEX_L, 3, "requires VEX and the L prefix") \
ENUM_ENTRY(IC_VEX_L_XS, 4, "requires VEX and the L and XS prefix")\
ENUM_ENTRY(IC_VEX_L_XD, 4, "requires VEX and the L and XD prefix")\
ENUM_ENTRY(IC_VEX_L_OPSIZE, 4, "requires VEX, L, and OpSize") \
ENUM_ENTRY(IC_VEX_L_W, 4, "requires VEX, L and W") \
ENUM_ENTRY(IC_VEX_L_W_XS, 5, "requires VEX, L, W and XS prefix") \
ENUM_ENTRY(IC_VEX_L_W_XD, 5, "requires VEX, L, W and XD prefix") \
ENUM_ENTRY(IC_VEX_L_W_OPSIZE, 5, "requires VEX, L, W and OpSize") \
ENUM_ENTRY(IC_EVEX, 1, "requires an EVEX prefix") \
ENUM_ENTRY(IC_EVEX_XS, 2, "requires EVEX and the XS prefix") \
ENUM_ENTRY(IC_EVEX_XD, 2, "requires EVEX and the XD prefix") \
ENUM_ENTRY(IC_EVEX_OPSIZE, 2, "requires EVEX and the OpSize prefix") \
ENUM_ENTRY(IC_EVEX_W, 3, "requires EVEX and the W prefix") \
ENUM_ENTRY(IC_EVEX_W_XS, 4, "requires EVEX, W, and XS prefix") \
ENUM_ENTRY(IC_EVEX_W_XD, 4, "requires EVEX, W, and XD prefix") \
ENUM_ENTRY(IC_EVEX_W_OPSIZE, 4, "requires EVEX, W, and OpSize") \
ENUM_ENTRY(IC_EVEX_L, 3, "requires EVEX and the L prefix") \
ENUM_ENTRY(IC_EVEX_L_XS, 4, "requires EVEX and the L and XS prefix")\
ENUM_ENTRY(IC_EVEX_L_XD, 4, "requires EVEX and the L and XD prefix")\
ENUM_ENTRY(IC_EVEX_L_OPSIZE, 4, "requires EVEX, L, and OpSize") \
ENUM_ENTRY(IC_EVEX_L_W, 3, "requires EVEX, L and W") \
ENUM_ENTRY(IC_EVEX_L_W_XS, 4, "requires EVEX, L, W and XS prefix") \
ENUM_ENTRY(IC_EVEX_L_W_XD, 4, "requires EVEX, L, W and XD prefix") \
ENUM_ENTRY(IC_EVEX_L_W_OPSIZE, 4, "requires EVEX, L, W and OpSize") \
ENUM_ENTRY(IC_EVEX_L2, 3, "requires EVEX and the L2 prefix") \
ENUM_ENTRY(IC_EVEX_L2_XS, 4, "requires EVEX and the L2 and XS prefix")\
ENUM_ENTRY(IC_EVEX_L2_XD, 4, "requires EVEX and the L2 and XD prefix")\
ENUM_ENTRY(IC_EVEX_L2_OPSIZE, 4, "requires EVEX, L2, and OpSize") \
ENUM_ENTRY(IC_EVEX_L2_W, 3, "requires EVEX, L2 and W") \
ENUM_ENTRY(IC_EVEX_L2_W_XS, 4, "requires EVEX, L2, W and XS prefix") \
ENUM_ENTRY(IC_EVEX_L2_W_XD, 4, "requires EVEX, L2, W and XD prefix") \
ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE, 4, "requires EVEX, L2, W and OpSize") \
ENUM_ENTRY(IC_EVEX_K, 1, "requires an EVEX_K prefix") \
ENUM_ENTRY(IC_EVEX_XS_K, 2, "requires EVEX_K and the XS prefix") \
ENUM_ENTRY(IC_EVEX_XD_K, 2, "requires EVEX_K and the XD prefix") \
ENUM_ENTRY(IC_EVEX_OPSIZE_K, 2, "requires EVEX_K and the OpSize prefix") \
ENUM_ENTRY(IC_EVEX_W_K, 3, "requires EVEX_K and the W prefix") \
ENUM_ENTRY(IC_EVEX_W_XS_K, 4, "requires EVEX_K, W, and XS prefix") \
ENUM_ENTRY(IC_EVEX_W_XD_K, 4, "requires EVEX_K, W, and XD prefix") \
ENUM_ENTRY(IC_EVEX_W_OPSIZE_K, 4, "requires EVEX_K, W, and OpSize") \
ENUM_ENTRY(IC_EVEX_L_K, 3, "requires EVEX_K and the L prefix") \
ENUM_ENTRY(IC_EVEX_L_XS_K, 4, "requires EVEX_K and the L and XS prefix")\
ENUM_ENTRY(IC_EVEX_L_XD_K, 4, "requires EVEX_K and the L and XD prefix")\
ENUM_ENTRY(IC_EVEX_L_OPSIZE_K, 4, "requires EVEX_K, L, and OpSize") \
ENUM_ENTRY(IC_EVEX_L_W_K, 3, "requires EVEX_K, L and W") \
ENUM_ENTRY(IC_EVEX_L_W_XS_K, 4, "requires EVEX_K, L, W and XS prefix") \
ENUM_ENTRY(IC_EVEX_L_W_XD_K, 4, "requires EVEX_K, L, W and XD prefix") \
ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_K, 4, "requires EVEX_K, L, W and OpSize") \
ENUM_ENTRY(IC_EVEX_L2_K, 3, "requires EVEX_K and the L2 prefix") \
ENUM_ENTRY(IC_EVEX_L2_XS_K, 4, "requires EVEX_K and the L2 and XS prefix")\
ENUM_ENTRY(IC_EVEX_L2_XD_K, 4, "requires EVEX_K and the L2 and XD prefix")\
ENUM_ENTRY(IC_EVEX_L2_OPSIZE_K, 4, "requires EVEX_K, L2, and OpSize") \
ENUM_ENTRY(IC_EVEX_L2_W_K, 3, "requires EVEX_K, L2 and W") \
ENUM_ENTRY(IC_EVEX_L2_W_XS_K, 4, "requires EVEX_K, L2, W and XS prefix") \
ENUM_ENTRY(IC_EVEX_L2_W_XD_K, 4, "requires EVEX_K, L2, W and XD prefix") \
ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_K, 4, "requires EVEX_K, L2, W and OpSize") \
ENUM_ENTRY(IC_EVEX_B, 1, "requires an EVEX_B prefix") \
ENUM_ENTRY(IC_EVEX_XS_B, 2, "requires EVEX_B and the XS prefix") \
ENUM_ENTRY(IC_EVEX_XD_B, 2, "requires EVEX_B and the XD prefix") \
ENUM_ENTRY(IC_EVEX_OPSIZE_B, 2, "requires EVEX_B and the OpSize prefix") \
ENUM_ENTRY(IC_EVEX_W_B, 3, "requires EVEX_B and the W prefix") \
ENUM_ENTRY(IC_EVEX_W_XS_B, 4, "requires EVEX_B, W, and XS prefix") \
ENUM_ENTRY(IC_EVEX_W_XD_B, 4, "requires EVEX_B, W, and XD prefix") \
ENUM_ENTRY(IC_EVEX_W_OPSIZE_B, 4, "requires EVEX_B, W, and OpSize") \
ENUM_ENTRY(IC_EVEX_L_B, 3, "requires EVEX_B and the L prefix") \
ENUM_ENTRY(IC_EVEX_L_XS_B, 4, "requires EVEX_B and the L and XS prefix")\
ENUM_ENTRY(IC_EVEX_L_XD_B, 4, "requires EVEX_B and the L and XD prefix")\
ENUM_ENTRY(IC_EVEX_L_OPSIZE_B, 4, "requires EVEX_B, L, and OpSize") \
ENUM_ENTRY(IC_EVEX_L_W_B, 3, "requires EVEX_B, L and W") \
ENUM_ENTRY(IC_EVEX_L_W_XS_B, 4, "requires EVEX_B, L, W and XS prefix") \
ENUM_ENTRY(IC_EVEX_L_W_XD_B, 4, "requires EVEX_B, L, W and XD prefix") \
ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_B, 4, "requires EVEX_B, L, W and OpSize") \
ENUM_ENTRY(IC_EVEX_L2_B, 3, "requires EVEX_B and the L2 prefix") \
ENUM_ENTRY(IC_EVEX_L2_XS_B, 4, "requires EVEX_B and the L2 and XS prefix")\
ENUM_ENTRY(IC_EVEX_L2_XD_B, 4, "requires EVEX_B and the L2 and XD prefix")\
ENUM_ENTRY(IC_EVEX_L2_OPSIZE_B, 4, "requires EVEX_B, L2, and OpSize") \
ENUM_ENTRY(IC_EVEX_L2_W_B, 3, "requires EVEX_B, L2 and W") \
ENUM_ENTRY(IC_EVEX_L2_W_XS_B, 4, "requires EVEX_B, L2, W and XS prefix") \
ENUM_ENTRY(IC_EVEX_L2_W_XD_B, 4, "requires EVEX_B, L2, W and XD prefix") \
ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_B, 4, "requires EVEX_B, L2, W and OpSize") \
ENUM_ENTRY(IC_EVEX_K_B, 1, "requires EVEX_B and EVEX_K prefix") \
ENUM_ENTRY(IC_EVEX_XS_K_B, 2, "requires EVEX_B, EVEX_K and the XS prefix") \
ENUM_ENTRY(IC_EVEX_XD_K_B, 2, "requires EVEX_B, EVEX_K and the XD prefix") \
ENUM_ENTRY(IC_EVEX_OPSIZE_K_B, 2, "requires EVEX_B, EVEX_K and the OpSize prefix") \
ENUM_ENTRY(IC_EVEX_W_K_B, 3, "requires EVEX_B, EVEX_K and the W prefix") \
ENUM_ENTRY(IC_EVEX_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, W, and XS prefix") \
ENUM_ENTRY(IC_EVEX_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, W, and XD prefix") \
ENUM_ENTRY(IC_EVEX_W_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, W, and OpSize") \
ENUM_ENTRY(IC_EVEX_L_K_B, 3, "requires EVEX_B, EVEX_K and the L prefix") \
ENUM_ENTRY(IC_EVEX_L_XS_K_B, 4, "requires EVEX_B, EVEX_K and the L and XS prefix")\
ENUM_ENTRY(IC_EVEX_L_XD_K_B, 4, "requires EVEX_B, EVEX_K and the L and XD prefix")\
ENUM_ENTRY(IC_EVEX_L_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, L, and OpSize") \
ENUM_ENTRY(IC_EVEX_L_W_K_B, 3, "requires EVEX_B, EVEX_K, L and W") \
ENUM_ENTRY(IC_EVEX_L_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, L, W and XS prefix") \
ENUM_ENTRY(IC_EVEX_L_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, L, W and XD prefix") \
ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_K_B,4, "requires EVEX_B, EVEX_K, L, W and OpSize") \
ENUM_ENTRY(IC_EVEX_L2_K_B, 3, "requires EVEX_B, EVEX_K and the L2 prefix") \
ENUM_ENTRY(IC_EVEX_L2_XS_K_B, 4, "requires EVEX_B, EVEX_K and the L2 and XS prefix")\
ENUM_ENTRY(IC_EVEX_L2_XD_K_B, 4, "requires EVEX_B, EVEX_K and the L2 and XD prefix")\
ENUM_ENTRY(IC_EVEX_L2_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, L2, and OpSize") \
ENUM_ENTRY(IC_EVEX_L2_W_K_B, 3, "requires EVEX_B, EVEX_K, L2 and W") \
ENUM_ENTRY(IC_EVEX_L2_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, L2, W and XS prefix") \
ENUM_ENTRY(IC_EVEX_L2_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, L2, W and XD prefix") \
ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_K_B,4, "requires EVEX_B, EVEX_K, L2, W and OpSize") \
ENUM_ENTRY(IC_EVEX_KZ_B, 1, "requires EVEX_B and EVEX_KZ prefix") \
ENUM_ENTRY(IC_EVEX_XS_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the XS prefix") \
ENUM_ENTRY(IC_EVEX_XD_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the XD prefix") \
ENUM_ENTRY(IC_EVEX_OPSIZE_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the OpSize prefix") \
ENUM_ENTRY(IC_EVEX_W_KZ_B, 3, "requires EVEX_B, EVEX_KZ and the W prefix") \
ENUM_ENTRY(IC_EVEX_W_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ, W, and XS prefix") \
ENUM_ENTRY(IC_EVEX_W_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ, W, and XD prefix") \
ENUM_ENTRY(IC_EVEX_W_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, W, and OpSize") \
ENUM_ENTRY(IC_EVEX_L_KZ_B, 3, "requires EVEX_B, EVEX_KZ and the L prefix") \
ENUM_ENTRY(IC_EVEX_L_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L and XS prefix")\
ENUM_ENTRY(IC_EVEX_L_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L and XD prefix")\
ENUM_ENTRY(IC_EVEX_L_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, and OpSize") \
ENUM_ENTRY(IC_EVEX_L_W_KZ_B, 3, "requires EVEX_B, EVEX_KZ, L and W") \
ENUM_ENTRY(IC_EVEX_L_W_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, W and XS prefix") \
ENUM_ENTRY(IC_EVEX_L_W_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, W and XD prefix") \
ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, W and OpSize") \
ENUM_ENTRY(IC_EVEX_L2_KZ_B, 3, "requires EVEX_B, EVEX_KZ and the L2 prefix") \
ENUM_ENTRY(IC_EVEX_L2_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L2 and XS prefix")\
ENUM_ENTRY(IC_EVEX_L2_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L2 and XD prefix")\
ENUM_ENTRY(IC_EVEX_L2_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, and OpSize") \
ENUM_ENTRY(IC_EVEX_L2_W_KZ_B, 3, "requires EVEX_B, EVEX_KZ, L2 and W") \
ENUM_ENTRY(IC_EVEX_L2_W_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, W and XS prefix") \
ENUM_ENTRY(IC_EVEX_L2_W_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, W and XD prefix") \
ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, W and OpSize") \
ENUM_ENTRY(IC_EVEX_KZ, 1, "requires an EVEX_KZ prefix") \
ENUM_ENTRY(IC_EVEX_XS_KZ, 2, "requires EVEX_KZ and the XS prefix") \
ENUM_ENTRY(IC_EVEX_XD_KZ, 2, "requires EVEX_KZ and the XD prefix") \
ENUM_ENTRY(IC_EVEX_OPSIZE_KZ, 2, "requires EVEX_KZ and the OpSize prefix") \
ENUM_ENTRY(IC_EVEX_W_KZ, 3, "requires EVEX_KZ and the W prefix") \
ENUM_ENTRY(IC_EVEX_W_XS_KZ, 4, "requires EVEX_KZ, W, and XS prefix") \
ENUM_ENTRY(IC_EVEX_W_XD_KZ, 4, "requires EVEX_KZ, W, and XD prefix") \
ENUM_ENTRY(IC_EVEX_W_OPSIZE_KZ, 4, "requires EVEX_KZ, W, and OpSize") \
ENUM_ENTRY(IC_EVEX_L_KZ, 3, "requires EVEX_KZ and the L prefix") \
ENUM_ENTRY(IC_EVEX_L_XS_KZ, 4, "requires EVEX_KZ and the L and XS prefix")\
ENUM_ENTRY(IC_EVEX_L_XD_KZ, 4, "requires EVEX_KZ and the L and XD prefix")\
ENUM_ENTRY(IC_EVEX_L_OPSIZE_KZ, 4, "requires EVEX_KZ, L, and OpSize") \
ENUM_ENTRY(IC_EVEX_L_W_KZ, 3, "requires EVEX_KZ, L and W") \
ENUM_ENTRY(IC_EVEX_L_W_XS_KZ, 4, "requires EVEX_KZ, L, W and XS prefix") \
ENUM_ENTRY(IC_EVEX_L_W_XD_KZ, 4, "requires EVEX_KZ, L, W and XD prefix") \
ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_KZ, 4, "requires EVEX_KZ, L, W and OpSize") \
ENUM_ENTRY(IC_EVEX_L2_KZ, 3, "requires EVEX_KZ and the L2 prefix") \
ENUM_ENTRY(IC_EVEX_L2_XS_KZ, 4, "requires EVEX_KZ and the L2 and XS prefix")\
ENUM_ENTRY(IC_EVEX_L2_XD_KZ, 4, "requires EVEX_KZ and the L2 and XD prefix")\
ENUM_ENTRY(IC_EVEX_L2_OPSIZE_KZ, 4, "requires EVEX_KZ, L2, and OpSize") \
ENUM_ENTRY(IC_EVEX_L2_W_KZ, 3, "requires EVEX_KZ, L2 and W") \
ENUM_ENTRY(IC_EVEX_L2_W_XS_KZ, 4, "requires EVEX_KZ, L2, W and XS prefix") \
ENUM_ENTRY(IC_EVEX_L2_W_XD_KZ, 4, "requires EVEX_KZ, L2, W and XD prefix") \
ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_KZ, 4, "requires EVEX_KZ, L2, W and OpSize")
#define ENUM_ENTRY(n, r, d) n,
typedef enum {
INSTRUCTION_CONTEXTS
IC_max
} InstructionContext;
#undef ENUM_ENTRY
/*
* Opcode types, which determine which decode table to use, both in the Intel
* manual and also for the decoder.
*/
typedef enum {
ONEBYTE = 0,
TWOBYTE = 1,
THREEBYTE_38 = 2,
THREEBYTE_3A = 3,
XOP8_MAP = 4,
XOP9_MAP = 5,
XOPA_MAP = 6,
THREEDNOW_MAP = 7
} OpcodeType;
/*
* The following structs are used for the hierarchical decode table. After
* determining the instruction's class (i.e., which IC_* constant applies to
* it), the decoder reads the opcode. Some instructions require specific
* values of the ModR/M byte, so the ModR/M byte indexes into the final table.
*
* If a ModR/M byte is not required, "required" is left unset, and the values
* for each instructionID are identical.
*/
typedef uint16_t InstrUID;
/*
* ModRMDecisionType - describes the type of ModR/M decision, allowing the
* consumer to determine the number of entries in it.
*
* MODRM_ONEENTRY - No matter what the value of the ModR/M byte is, the decoded
* instruction is the same.
* MODRM_SPLITRM - If the ModR/M byte is between 0x00 and 0xbf, the opcode
* corresponds to one instruction; otherwise, it corresponds to
* a different instruction.
* MODRM_SPLITMISC- If the ModR/M byte is between 0x00 and 0xbf, ModR/M byte
* divided by 8 is used to select instruction; otherwise, each
* value of the ModR/M byte could correspond to a different
* instruction.
* MODRM_SPLITREG - ModR/M byte divided by 8 is used to select instruction. This
corresponds to instructions that use reg field as opcode
* MODRM_FULL - Potentially, each value of the ModR/M byte could correspond
* to a different instruction.
*/
#define MODRMTYPES \
ENUM_ENTRY(MODRM_ONEENTRY) \
ENUM_ENTRY(MODRM_SPLITRM) \
ENUM_ENTRY(MODRM_SPLITMISC) \
ENUM_ENTRY(MODRM_SPLITREG) \
ENUM_ENTRY(MODRM_FULL)
#define ENUM_ENTRY(n) n,
typedef enum {
MODRMTYPES
MODRM_max
} ModRMDecisionType;
#undef ENUM_ENTRY
#define CASE_ENCODING_RM \
case ENCODING_RM: \
case ENCODING_RM_CD2: \
case ENCODING_RM_CD4: \
case ENCODING_RM_CD8: \
case ENCODING_RM_CD16: \
case ENCODING_RM_CD32: \
case ENCODING_RM_CD64
#define CASE_ENCODING_VSIB \
case ENCODING_VSIB: \
case ENCODING_VSIB_CD2: \
case ENCODING_VSIB_CD4: \
case ENCODING_VSIB_CD8: \
case ENCODING_VSIB_CD16: \
case ENCODING_VSIB_CD32: \
case ENCODING_VSIB_CD64
// Physical encodings of instruction operands.
#define ENCODINGS \
ENUM_ENTRY(ENCODING_NONE, "") \
ENUM_ENTRY(ENCODING_REG, "Register operand in ModR/M byte.") \
ENUM_ENTRY(ENCODING_RM, "R/M operand in ModR/M byte.") \
ENUM_ENTRY(ENCODING_RM_CD2, "R/M operand with CDisp scaling of 2") \
ENUM_ENTRY(ENCODING_RM_CD4, "R/M operand with CDisp scaling of 4") \
ENUM_ENTRY(ENCODING_RM_CD8, "R/M operand with CDisp scaling of 8") \
ENUM_ENTRY(ENCODING_RM_CD16,"R/M operand with CDisp scaling of 16") \
ENUM_ENTRY(ENCODING_RM_CD32,"R/M operand with CDisp scaling of 32") \
ENUM_ENTRY(ENCODING_RM_CD64,"R/M operand with CDisp scaling of 64") \
ENUM_ENTRY(ENCODING_VSIB, "VSIB operand in ModR/M byte.") \
ENUM_ENTRY(ENCODING_VSIB_CD2, "VSIB operand with CDisp scaling of 2") \
ENUM_ENTRY(ENCODING_VSIB_CD4, "VSIB operand with CDisp scaling of 4") \
ENUM_ENTRY(ENCODING_VSIB_CD8, "VSIB operand with CDisp scaling of 8") \
ENUM_ENTRY(ENCODING_VSIB_CD16,"VSIB operand with CDisp scaling of 16") \
ENUM_ENTRY(ENCODING_VSIB_CD32,"VSIB operand with CDisp scaling of 32") \
ENUM_ENTRY(ENCODING_VSIB_CD64,"VSIB operand with CDisp scaling of 64") \
ENUM_ENTRY(ENCODING_VVVV, "Register operand in VEX.vvvv byte.") \
ENUM_ENTRY(ENCODING_WRITEMASK, "Register operand in EVEX.aaa byte.") \
ENUM_ENTRY(ENCODING_IB, "1-byte immediate") \
ENUM_ENTRY(ENCODING_IW, "2-byte") \
ENUM_ENTRY(ENCODING_ID, "4-byte") \
ENUM_ENTRY(ENCODING_IO, "8-byte") \
ENUM_ENTRY(ENCODING_RB, "(AL..DIL, R8L..R15L) Register code added to " \
"the opcode byte") \
ENUM_ENTRY(ENCODING_RW, "(AX..DI, R8W..R15W)") \
ENUM_ENTRY(ENCODING_RD, "(EAX..EDI, R8D..R15D)") \
ENUM_ENTRY(ENCODING_RO, "(RAX..RDI, R8..R15)") \
ENUM_ENTRY(ENCODING_FP, "Position on floating-point stack in ModR/M " \
"byte.") \
ENUM_ENTRY(ENCODING_Iv, "Immediate of operand size") \
ENUM_ENTRY(ENCODING_Ia, "Immediate of address size") \
ENUM_ENTRY(ENCODING_IRC, "Immediate for static rounding control") \
ENUM_ENTRY(ENCODING_Rv, "Register code of operand size added to the " \
"opcode byte") \
ENUM_ENTRY(ENCODING_DUP, "Duplicate of another operand; ID is encoded " \
"in type") \
ENUM_ENTRY(ENCODING_SI, "Source index; encoded in OpSize/Adsize prefix") \
ENUM_ENTRY(ENCODING_DI, "Destination index; encoded in prefixes")
#define ENUM_ENTRY(n, d) n,
typedef enum {
ENCODINGS
ENCODING_max
} OperandEncoding;
#undef ENUM_ENTRY
/*
* Semantic interpretations of instruction operands.
*/
#define TYPES \
ENUM_ENTRY(TYPE_NONE, "") \
ENUM_ENTRY(TYPE_REL, "immediate address") \
ENUM_ENTRY(TYPE_R8, "1-byte register operand") \
ENUM_ENTRY(TYPE_R16, "2-byte") \
ENUM_ENTRY(TYPE_R32, "4-byte") \
ENUM_ENTRY(TYPE_R64, "8-byte") \
ENUM_ENTRY(TYPE_IMM, "immediate operand") \
ENUM_ENTRY(TYPE_IMM3, "1-byte immediate operand between 0 and 7") \
ENUM_ENTRY(TYPE_IMM5, "1-byte immediate operand between 0 and 31") \
ENUM_ENTRY(TYPE_AVX512ICC, "1-byte immediate operand for AVX512 icmp") \
ENUM_ENTRY(TYPE_UIMM8, "1-byte unsigned immediate operand") \
ENUM_ENTRY(TYPE_M, "Memory operand") \
ENUM_ENTRY(TYPE_MVSIBX, "Memory operand using XMM index") \
ENUM_ENTRY(TYPE_MVSIBY, "Memory operand using YMM index") \
ENUM_ENTRY(TYPE_MVSIBZ, "Memory operand using ZMM index") \
ENUM_ENTRY(TYPE_SRCIDX, "memory at source index") \
ENUM_ENTRY(TYPE_DSTIDX, "memory at destination index") \
ENUM_ENTRY(TYPE_MOFFS, "memory offset (relative to segment base)") \
ENUM_ENTRY(TYPE_ST, "Position on the floating-point stack") \
ENUM_ENTRY(TYPE_MM64, "8-byte MMX register") \
ENUM_ENTRY(TYPE_XMM, "16-byte") \
ENUM_ENTRY(TYPE_YMM, "32-byte") \
ENUM_ENTRY(TYPE_ZMM, "64-byte") \
ENUM_ENTRY(TYPE_VK, "mask register") \
ENUM_ENTRY(TYPE_SEGMENTREG, "Segment register operand") \
ENUM_ENTRY(TYPE_DEBUGREG, "Debug register operand") \
ENUM_ENTRY(TYPE_CONTROLREG, "Control register operand") \
ENUM_ENTRY(TYPE_BNDR, "MPX bounds register") \
\
ENUM_ENTRY(TYPE_Rv, "Register operand of operand size") \
ENUM_ENTRY(TYPE_RELv, "Immediate address of operand size") \
ENUM_ENTRY(TYPE_DUP0, "Duplicate of operand 0") \
ENUM_ENTRY(TYPE_DUP1, "operand 1") \
ENUM_ENTRY(TYPE_DUP2, "operand 2") \
ENUM_ENTRY(TYPE_DUP3, "operand 3") \
ENUM_ENTRY(TYPE_DUP4, "operand 4") \
#define ENUM_ENTRY(n, d) n,
typedef enum {
TYPES
TYPE_max
} OperandType;
#undef ENUM_ENTRY
/*
* The specification for how to extract and interpret one operand.
*/
typedef struct OperandSpecifier {
uint8_t encoding;
uint8_t type;
} OperandSpecifier;
#define X86_MAX_OPERANDS 6
/*
* Decoding mode for the Intel disassembler. 16-bit, 32-bit, and 64-bit mode
* are supported, and represent real mode, IA-32e, and IA-32e in 64-bit mode,
* respectively.
*/
typedef enum {
MODE_16BIT,
MODE_32BIT,
MODE_64BIT
} DisassemblerMode;
#endif

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/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
/// getRegisterName - This method is automatically generated by tblgen
/// from the register set description. This returns the assembler name
/// for the specified register.
static const char *getRegisterName(unsigned RegNo)
{
#ifndef CAPSTONE_DIET
static const char AsmStrs[] = {
/* 0 */ 's', 't', '(', '0', ')', 0,
/* 6 */ 's', 't', '(', '1', ')', 0,
/* 12 */ 's', 't', '(', '2', ')', 0,
/* 18 */ 's', 't', '(', '3', ')', 0,
/* 24 */ 's', 't', '(', '4', ')', 0,
/* 30 */ 's', 't', '(', '5', ')', 0,
/* 36 */ 's', 't', '(', '6', ')', 0,
/* 42 */ 's', 't', '(', '7', ')', 0,
/* 48 */ 'x', 'm', 'm', '1', '0', 0,
/* 54 */ 'y', 'm', 'm', '1', '0', 0,
/* 60 */ 'z', 'm', 'm', '1', '0', 0,
/* 66 */ 'c', 'r', '1', '0', 0,
/* 71 */ 'd', 'r', '1', '0', 0,
/* 76 */ 'x', 'm', 'm', '2', '0', 0,
/* 82 */ 'y', 'm', 'm', '2', '0', 0,
/* 88 */ 'z', 'm', 'm', '2', '0', 0,
/* 94 */ 'x', 'm', 'm', '3', '0', 0,
/* 100 */ 'y', 'm', 'm', '3', '0', 0,
/* 106 */ 'z', 'm', 'm', '3', '0', 0,
/* 112 */ 'b', 'n', 'd', '0', 0,
/* 117 */ 'k', '0', 0,
/* 120 */ 'x', 'm', 'm', '0', 0,
/* 125 */ 'y', 'm', 'm', '0', 0,
/* 130 */ 'z', 'm', 'm', '0', 0,
/* 135 */ 'f', 'p', '0', 0,
/* 139 */ 'c', 'r', '0', 0,
/* 143 */ 'd', 'r', '0', 0,
/* 147 */ 'x', 'm', 'm', '1', '1', 0,
/* 153 */ 'y', 'm', 'm', '1', '1', 0,
/* 159 */ 'z', 'm', 'm', '1', '1', 0,
/* 165 */ 'c', 'r', '1', '1', 0,
/* 170 */ 'd', 'r', '1', '1', 0,
/* 175 */ 'x', 'm', 'm', '2', '1', 0,
/* 181 */ 'y', 'm', 'm', '2', '1', 0,
/* 187 */ 'z', 'm', 'm', '2', '1', 0,
/* 193 */ 'x', 'm', 'm', '3', '1', 0,
/* 199 */ 'y', 'm', 'm', '3', '1', 0,
/* 205 */ 'z', 'm', 'm', '3', '1', 0,
/* 211 */ 'b', 'n', 'd', '1', 0,
/* 216 */ 'k', '1', 0,
/* 219 */ 'x', 'm', 'm', '1', 0,
/* 224 */ 'y', 'm', 'm', '1', 0,
/* 229 */ 'z', 'm', 'm', '1', 0,
/* 234 */ 'f', 'p', '1', 0,
/* 238 */ 'c', 'r', '1', 0,
/* 242 */ 'd', 'r', '1', 0,
/* 246 */ 'x', 'm', 'm', '1', '2', 0,
/* 252 */ 'y', 'm', 'm', '1', '2', 0,
/* 258 */ 'z', 'm', 'm', '1', '2', 0,
/* 264 */ 'c', 'r', '1', '2', 0,
/* 269 */ 'd', 'r', '1', '2', 0,
/* 274 */ 'x', 'm', 'm', '2', '2', 0,
/* 280 */ 'y', 'm', 'm', '2', '2', 0,
/* 286 */ 'z', 'm', 'm', '2', '2', 0,
/* 292 */ 'b', 'n', 'd', '2', 0,
/* 297 */ 'k', '2', 0,
/* 300 */ 'x', 'm', 'm', '2', 0,
/* 305 */ 'y', 'm', 'm', '2', 0,
/* 310 */ 'z', 'm', 'm', '2', 0,
/* 315 */ 'f', 'p', '2', 0,
/* 319 */ 'c', 'r', '2', 0,
/* 323 */ 'd', 'r', '2', 0,
/* 327 */ 'x', 'm', 'm', '1', '3', 0,
/* 333 */ 'y', 'm', 'm', '1', '3', 0,
/* 339 */ 'z', 'm', 'm', '1', '3', 0,
/* 345 */ 'c', 'r', '1', '3', 0,
/* 350 */ 'd', 'r', '1', '3', 0,
/* 355 */ 'x', 'm', 'm', '2', '3', 0,
/* 361 */ 'y', 'm', 'm', '2', '3', 0,
/* 367 */ 'z', 'm', 'm', '2', '3', 0,
/* 373 */ 'b', 'n', 'd', '3', 0,
/* 378 */ 'k', '3', 0,
/* 381 */ 'x', 'm', 'm', '3', 0,
/* 386 */ 'y', 'm', 'm', '3', 0,
/* 391 */ 'z', 'm', 'm', '3', 0,
/* 396 */ 'f', 'p', '3', 0,
/* 400 */ 'c', 'r', '3', 0,
/* 404 */ 'd', 'r', '3', 0,
/* 408 */ 'x', 'm', 'm', '1', '4', 0,
/* 414 */ 'y', 'm', 'm', '1', '4', 0,
/* 420 */ 'z', 'm', 'm', '1', '4', 0,
/* 426 */ 'c', 'r', '1', '4', 0,
/* 431 */ 'd', 'r', '1', '4', 0,
/* 436 */ 'x', 'm', 'm', '2', '4', 0,
/* 442 */ 'y', 'm', 'm', '2', '4', 0,
/* 448 */ 'z', 'm', 'm', '2', '4', 0,
/* 454 */ 'k', '4', 0,
/* 457 */ 'x', 'm', 'm', '4', 0,
/* 462 */ 'y', 'm', 'm', '4', 0,
/* 467 */ 'z', 'm', 'm', '4', 0,
/* 472 */ 'f', 'p', '4', 0,
/* 476 */ 'c', 'r', '4', 0,
/* 480 */ 'd', 'r', '4', 0,
/* 484 */ 'x', 'm', 'm', '1', '5', 0,
/* 490 */ 'y', 'm', 'm', '1', '5', 0,
/* 496 */ 'z', 'm', 'm', '1', '5', 0,
/* 502 */ 'c', 'r', '1', '5', 0,
/* 507 */ 'd', 'r', '1', '5', 0,
/* 512 */ 'x', 'm', 'm', '2', '5', 0,
/* 518 */ 'y', 'm', 'm', '2', '5', 0,
/* 524 */ 'z', 'm', 'm', '2', '5', 0,
/* 530 */ 'k', '5', 0,
/* 533 */ 'x', 'm', 'm', '5', 0,
/* 538 */ 'y', 'm', 'm', '5', 0,
/* 543 */ 'z', 'm', 'm', '5', 0,
/* 548 */ 'f', 'p', '5', 0,
/* 552 */ 'c', 'r', '5', 0,
/* 556 */ 'd', 'r', '5', 0,
/* 560 */ 'x', 'm', 'm', '1', '6', 0,
/* 566 */ 'y', 'm', 'm', '1', '6', 0,
/* 572 */ 'z', 'm', 'm', '1', '6', 0,
/* 578 */ 'x', 'm', 'm', '2', '6', 0,
/* 584 */ 'y', 'm', 'm', '2', '6', 0,
/* 590 */ 'z', 'm', 'm', '2', '6', 0,
/* 596 */ 'k', '6', 0,
/* 599 */ 'x', 'm', 'm', '6', 0,
/* 604 */ 'y', 'm', 'm', '6', 0,
/* 609 */ 'z', 'm', 'm', '6', 0,
/* 614 */ 'f', 'p', '6', 0,
/* 618 */ 'c', 'r', '6', 0,
/* 622 */ 'd', 'r', '6', 0,
/* 626 */ 'x', 'm', 'm', '1', '7', 0,
/* 632 */ 'y', 'm', 'm', '1', '7', 0,
/* 638 */ 'z', 'm', 'm', '1', '7', 0,
/* 644 */ 'x', 'm', 'm', '2', '7', 0,
/* 650 */ 'y', 'm', 'm', '2', '7', 0,
/* 656 */ 'z', 'm', 'm', '2', '7', 0,
/* 662 */ 'k', '7', 0,
/* 665 */ 'x', 'm', 'm', '7', 0,
/* 670 */ 'y', 'm', 'm', '7', 0,
/* 675 */ 'z', 'm', 'm', '7', 0,
/* 680 */ 'f', 'p', '7', 0,
/* 684 */ 'c', 'r', '7', 0,
/* 688 */ 'd', 'r', '7', 0,
/* 692 */ 'x', 'm', 'm', '1', '8', 0,
/* 698 */ 'y', 'm', 'm', '1', '8', 0,
/* 704 */ 'z', 'm', 'm', '1', '8', 0,
/* 710 */ 'x', 'm', 'm', '2', '8', 0,
/* 716 */ 'y', 'm', 'm', '2', '8', 0,
/* 722 */ 'z', 'm', 'm', '2', '8', 0,
/* 728 */ 'x', 'm', 'm', '8', 0,
/* 733 */ 'y', 'm', 'm', '8', 0,
/* 738 */ 'z', 'm', 'm', '8', 0,
/* 743 */ 'c', 'r', '8', 0,
/* 747 */ 'd', 'r', '8', 0,
/* 751 */ 'x', 'm', 'm', '1', '9', 0,
/* 757 */ 'y', 'm', 'm', '1', '9', 0,
/* 763 */ 'z', 'm', 'm', '1', '9', 0,
/* 769 */ 'x', 'm', 'm', '2', '9', 0,
/* 775 */ 'y', 'm', 'm', '2', '9', 0,
/* 781 */ 'z', 'm', 'm', '2', '9', 0,
/* 787 */ 'x', 'm', 'm', '9', 0,
/* 792 */ 'y', 'm', 'm', '9', 0,
/* 797 */ 'z', 'm', 'm', '9', 0,
/* 802 */ 'c', 'r', '9', 0,
/* 806 */ 'd', 'r', '9', 0,
/* 810 */ 'R', '1', '0', 'B', 'H', 0,
/* 816 */ 'R', '1', '1', 'B', 'H', 0,
/* 822 */ 'R', '1', '2', 'B', 'H', 0,
/* 828 */ 'R', '1', '3', 'B', 'H', 0,
/* 834 */ 'R', '1', '4', 'B', 'H', 0,
/* 840 */ 'R', '1', '5', 'B', 'H', 0,
/* 846 */ 'R', '8', 'B', 'H', 0,
/* 851 */ 'R', '9', 'B', 'H', 0,
/* 856 */ 'D', 'I', 'H', 0,
/* 860 */ 'S', 'I', 'H', 0,
/* 864 */ 'B', 'P', 'H', 0,
/* 868 */ 'S', 'P', 'H', 0,
/* 872 */ 'R', '1', '0', 'W', 'H', 0,
/* 878 */ 'R', '1', '1', 'W', 'H', 0,
/* 884 */ 'R', '1', '2', 'W', 'H', 0,
/* 890 */ 'R', '1', '3', 'W', 'H', 0,
/* 896 */ 'R', '1', '4', 'W', 'H', 0,
/* 902 */ 'R', '1', '5', 'W', 'H', 0,
/* 908 */ 'R', '8', 'W', 'H', 0,
/* 913 */ 'R', '9', 'W', 'H', 0,
/* 918 */ 'H', 'D', 'I', 0,
/* 922 */ 'H', 'S', 'I', 0,
/* 926 */ 'H', 'B', 'P', 0,
/* 930 */ 'H', 'I', 'P', 0,
/* 934 */ 'H', 'S', 'P', 0,
/* 938 */ 'H', 'A', 'X', 0,
/* 942 */ 'H', 'B', 'X', 0,
/* 946 */ 'H', 'C', 'X', 0,
/* 950 */ 'H', 'D', 'X', 0,
/* 954 */ 'r', '1', '0', 'b', 0,
/* 959 */ 'r', '1', '1', 'b', 0,
/* 964 */ 'r', '1', '2', 'b', 0,
/* 969 */ 'r', '1', '3', 'b', 0,
/* 974 */ 'r', '1', '4', 'b', 0,
/* 979 */ 'r', '1', '5', 'b', 0,
/* 984 */ 'r', '8', 'b', 0,
/* 988 */ 'r', '9', 'b', 0,
/* 992 */ 'r', '1', '0', 'd', 0,
/* 997 */ 'r', '1', '1', 'd', 0,
/* 1002 */ 'r', '1', '2', 'd', 0,
/* 1007 */ 'r', '1', '3', 'd', 0,
/* 1012 */ 'r', '1', '4', 'd', 0,
/* 1017 */ 'r', '1', '5', 'd', 0,
/* 1022 */ 'r', '8', 'd', 0,
/* 1026 */ 'r', '9', 'd', 0,
/* 1030 */ 'd', 'i', 'r', 'f', 'l', 'a', 'g', 0,
/* 1038 */ 'a', 'h', 0,
/* 1041 */ 'b', 'h', 0,
/* 1044 */ 'c', 'h', 0,
/* 1047 */ 'd', 'h', 0,
/* 1050 */ 'e', 'd', 'i', 0,
/* 1054 */ 'r', 'd', 'i', 0,
/* 1058 */ 'e', 's', 'i', 0,
/* 1062 */ 'r', 's', 'i', 0,
/* 1066 */ 'a', 'l', 0,
/* 1069 */ 'b', 'l', 0,
/* 1072 */ 'c', 'l', 0,
/* 1075 */ 'd', 'l', 0,
/* 1078 */ 'd', 'i', 'l', 0,
/* 1082 */ 's', 'i', 'l', 0,
/* 1086 */ 'b', 'p', 'l', 0,
/* 1090 */ 's', 'p', 'l', 0,
/* 1094 */ 'e', 'b', 'p', 0,
/* 1098 */ 'r', 'b', 'p', 0,
/* 1102 */ 'e', 'i', 'p', 0,
/* 1106 */ 'r', 'i', 'p', 0,
/* 1110 */ 'e', 's', 'p', 0,
/* 1114 */ 'r', 's', 'p', 0,
/* 1118 */ 's', 's', 'p', 0,
/* 1122 */ 'c', 's', 0,
/* 1125 */ 'd', 's', 0,
/* 1128 */ 'e', 's', 0,
/* 1131 */ 'f', 's', 0,
/* 1134 */ 'f', 'l', 'a', 'g', 's', 0,
/* 1140 */ 's', 's', 0,
/* 1143 */ 'r', '1', '0', 'w', 0,
/* 1148 */ 'r', '1', '1', 'w', 0,
/* 1153 */ 'r', '1', '2', 'w', 0,
/* 1158 */ 'r', '1', '3', 'w', 0,
/* 1163 */ 'r', '1', '4', 'w', 0,
/* 1168 */ 'r', '1', '5', 'w', 0,
/* 1173 */ 'r', '8', 'w', 0,
/* 1177 */ 'r', '9', 'w', 0,
/* 1181 */ 'f', 'p', 's', 'w', 0,
/* 1186 */ 'e', 'a', 'x', 0,
/* 1190 */ 'r', 'a', 'x', 0,
/* 1194 */ 'e', 'b', 'x', 0,
/* 1198 */ 'r', 'b', 'x', 0,
/* 1202 */ 'e', 'c', 'x', 0,
/* 1206 */ 'r', 'c', 'x', 0,
/* 1210 */ 'e', 'd', 'x', 0,
/* 1214 */ 'r', 'd', 'x', 0,
/* 1218 */ 'e', 'i', 'z', 0,
/* 1222 */ 'r', 'i', 'z', 0,
};
static const uint16_t RegAsmOffset[] = {
1038, 1066, 1187, 1041, 1069, 1095, 864, 1086, 1195, 1044, 1072, 1122, 1203, 1030,
1047, 1051, 856, 1078, 1075, 1125, 1211, 1186, 1094, 1194, 1202, 1050, 1210, 1134,
1102, 1218, 1128, 1058, 1110, 1181, 1131, 1137, 938, 926, 942, 946, 918, 950,
930, 922, 934, 1103, 1190, 1098, 1198, 1206, 1054, 1214, 1106, 1222, 1062, 1114,
1059, 860, 1082, 1111, 868, 1090, 1140, 1118, 112, 211, 292, 373, 139, 238,
319, 400, 476, 552, 618, 684, 743, 802, 66, 165, 264, 345, 426, 502,
143, 242, 323, 404, 480, 556, 622, 688, 747, 806, 71, 170, 269, 350,
431, 507, 135, 234, 315, 396, 472, 548, 614, 680, 117, 216, 297, 378,
454, 530, 596, 662, 121, 220, 301, 382, 458, 534, 600, 666, 744, 803,
67, 166, 265, 346, 427, 503, 0, 6, 12, 18, 24, 30, 36, 42,
120, 219, 300, 381, 457, 533, 599, 665, 728, 787, 48, 147, 246, 327,
408, 484, 560, 626, 692, 751, 76, 175, 274, 355, 436, 512, 578, 644,
710, 769, 94, 193, 125, 224, 305, 386, 462, 538, 604, 670, 733, 792,
54, 153, 252, 333, 414, 490, 566, 632, 698, 757, 82, 181, 280, 361,
442, 518, 584, 650, 716, 775, 100, 199, 130, 229, 310, 391, 467, 543,
609, 675, 738, 797, 60, 159, 258, 339, 420, 496, 572, 638, 704, 763,
88, 187, 286, 367, 448, 524, 590, 656, 722, 781, 106, 205, 984, 988,
954, 959, 964, 969, 974, 979, 846, 851, 810, 816, 822, 828, 834, 840,
1022, 1026, 992, 997, 1002, 1007, 1012, 1017, 1173, 1177, 1143, 1148, 1153, 1158,
1163, 1168, 908, 913, 872, 878, 884, 890, 896, 902,
};
return AsmStrs+RegAsmOffset[RegNo-1];
#else
return NULL;
#endif
}

291
thirdparty/capstone/arch/X86/X86GenRegisterName1.inc vendored Normal file
View File

@@ -0,0 +1,291 @@
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
/// getRegisterName - This method is automatically generated by tblgen
/// from the register set description. This returns the assembler name
/// for the specified register.
static const char *getRegisterName(unsigned RegNo)
{
#ifndef CAPSTONE_DIET
static const char AsmStrs[] = {
/* 0 */ 's', 't', '(', '0', ')', 0,
/* 6 */ 's', 't', '(', '1', ')', 0,
/* 12 */ 's', 't', '(', '2', ')', 0,
/* 18 */ 's', 't', '(', '3', ')', 0,
/* 24 */ 's', 't', '(', '4', ')', 0,
/* 30 */ 's', 't', '(', '5', ')', 0,
/* 36 */ 's', 't', '(', '6', ')', 0,
/* 42 */ 's', 't', '(', '7', ')', 0,
/* 48 */ 'x', 'm', 'm', '1', '0', 0,
/* 54 */ 'y', 'm', 'm', '1', '0', 0,
/* 60 */ 'z', 'm', 'm', '1', '0', 0,
/* 66 */ 'c', 'r', '1', '0', 0,
/* 71 */ 'd', 'r', '1', '0', 0,
/* 76 */ 'x', 'm', 'm', '2', '0', 0,
/* 82 */ 'y', 'm', 'm', '2', '0', 0,
/* 88 */ 'z', 'm', 'm', '2', '0', 0,
/* 94 */ 'x', 'm', 'm', '3', '0', 0,
/* 100 */ 'y', 'm', 'm', '3', '0', 0,
/* 106 */ 'z', 'm', 'm', '3', '0', 0,
/* 112 */ 'b', 'n', 'd', '0', 0,
/* 117 */ 'k', '0', 0,
/* 120 */ 'x', 'm', 'm', '0', 0,
/* 125 */ 'y', 'm', 'm', '0', 0,
/* 130 */ 'z', 'm', 'm', '0', 0,
/* 135 */ 'f', 'p', '0', 0,
/* 139 */ 'c', 'r', '0', 0,
/* 143 */ 'd', 'r', '0', 0,
/* 147 */ 'x', 'm', 'm', '1', '1', 0,
/* 153 */ 'y', 'm', 'm', '1', '1', 0,
/* 159 */ 'z', 'm', 'm', '1', '1', 0,
/* 165 */ 'c', 'r', '1', '1', 0,
/* 170 */ 'd', 'r', '1', '1', 0,
/* 175 */ 'x', 'm', 'm', '2', '1', 0,
/* 181 */ 'y', 'm', 'm', '2', '1', 0,
/* 187 */ 'z', 'm', 'm', '2', '1', 0,
/* 193 */ 'x', 'm', 'm', '3', '1', 0,
/* 199 */ 'y', 'm', 'm', '3', '1', 0,
/* 205 */ 'z', 'm', 'm', '3', '1', 0,
/* 211 */ 'b', 'n', 'd', '1', 0,
/* 216 */ 'k', '1', 0,
/* 219 */ 'x', 'm', 'm', '1', 0,
/* 224 */ 'y', 'm', 'm', '1', 0,
/* 229 */ 'z', 'm', 'm', '1', 0,
/* 234 */ 'f', 'p', '1', 0,
/* 238 */ 'c', 'r', '1', 0,
/* 242 */ 'd', 'r', '1', 0,
/* 246 */ 'x', 'm', 'm', '1', '2', 0,
/* 252 */ 'y', 'm', 'm', '1', '2', 0,
/* 258 */ 'z', 'm', 'm', '1', '2', 0,
/* 264 */ 'c', 'r', '1', '2', 0,
/* 269 */ 'd', 'r', '1', '2', 0,
/* 274 */ 'x', 'm', 'm', '2', '2', 0,
/* 280 */ 'y', 'm', 'm', '2', '2', 0,
/* 286 */ 'z', 'm', 'm', '2', '2', 0,
/* 292 */ 'b', 'n', 'd', '2', 0,
/* 297 */ 'k', '2', 0,
/* 300 */ 'x', 'm', 'm', '2', 0,
/* 305 */ 'y', 'm', 'm', '2', 0,
/* 310 */ 'z', 'm', 'm', '2', 0,
/* 315 */ 'f', 'p', '2', 0,
/* 319 */ 'c', 'r', '2', 0,
/* 323 */ 'd', 'r', '2', 0,
/* 327 */ 'x', 'm', 'm', '1', '3', 0,
/* 333 */ 'y', 'm', 'm', '1', '3', 0,
/* 339 */ 'z', 'm', 'm', '1', '3', 0,
/* 345 */ 'c', 'r', '1', '3', 0,
/* 350 */ 'd', 'r', '1', '3', 0,
/* 355 */ 'x', 'm', 'm', '2', '3', 0,
/* 361 */ 'y', 'm', 'm', '2', '3', 0,
/* 367 */ 'z', 'm', 'm', '2', '3', 0,
/* 373 */ 'b', 'n', 'd', '3', 0,
/* 378 */ 'k', '3', 0,
/* 381 */ 'x', 'm', 'm', '3', 0,
/* 386 */ 'y', 'm', 'm', '3', 0,
/* 391 */ 'z', 'm', 'm', '3', 0,
/* 396 */ 'f', 'p', '3', 0,
/* 400 */ 'c', 'r', '3', 0,
/* 404 */ 'd', 'r', '3', 0,
/* 408 */ 'x', 'm', 'm', '1', '4', 0,
/* 414 */ 'y', 'm', 'm', '1', '4', 0,
/* 420 */ 'z', 'm', 'm', '1', '4', 0,
/* 426 */ 'c', 'r', '1', '4', 0,
/* 431 */ 'd', 'r', '1', '4', 0,
/* 436 */ 'x', 'm', 'm', '2', '4', 0,
/* 442 */ 'y', 'm', 'm', '2', '4', 0,
/* 448 */ 'z', 'm', 'm', '2', '4', 0,
/* 454 */ 'k', '4', 0,
/* 457 */ 'x', 'm', 'm', '4', 0,
/* 462 */ 'y', 'm', 'm', '4', 0,
/* 467 */ 'z', 'm', 'm', '4', 0,
/* 472 */ 'f', 'p', '4', 0,
/* 476 */ 'c', 'r', '4', 0,
/* 480 */ 'd', 'r', '4', 0,
/* 484 */ 'x', 'm', 'm', '1', '5', 0,
/* 490 */ 'y', 'm', 'm', '1', '5', 0,
/* 496 */ 'z', 'm', 'm', '1', '5', 0,
/* 502 */ 'c', 'r', '1', '5', 0,
/* 507 */ 'd', 'r', '1', '5', 0,
/* 512 */ 'x', 'm', 'm', '2', '5', 0,
/* 518 */ 'y', 'm', 'm', '2', '5', 0,
/* 524 */ 'z', 'm', 'm', '2', '5', 0,
/* 530 */ 'k', '5', 0,
/* 533 */ 'x', 'm', 'm', '5', 0,
/* 538 */ 'y', 'm', 'm', '5', 0,
/* 543 */ 'z', 'm', 'm', '5', 0,
/* 548 */ 'f', 'p', '5', 0,
/* 552 */ 'c', 'r', '5', 0,
/* 556 */ 'd', 'r', '5', 0,
/* 560 */ 'x', 'm', 'm', '1', '6', 0,
/* 566 */ 'y', 'm', 'm', '1', '6', 0,
/* 572 */ 'z', 'm', 'm', '1', '6', 0,
/* 578 */ 'x', 'm', 'm', '2', '6', 0,
/* 584 */ 'y', 'm', 'm', '2', '6', 0,
/* 590 */ 'z', 'm', 'm', '2', '6', 0,
/* 596 */ 'k', '6', 0,
/* 599 */ 'x', 'm', 'm', '6', 0,
/* 604 */ 'y', 'm', 'm', '6', 0,
/* 609 */ 'z', 'm', 'm', '6', 0,
/* 614 */ 'f', 'p', '6', 0,
/* 618 */ 'c', 'r', '6', 0,
/* 622 */ 'd', 'r', '6', 0,
/* 626 */ 'x', 'm', 'm', '1', '7', 0,
/* 632 */ 'y', 'm', 'm', '1', '7', 0,
/* 638 */ 'z', 'm', 'm', '1', '7', 0,
/* 644 */ 'x', 'm', 'm', '2', '7', 0,
/* 650 */ 'y', 'm', 'm', '2', '7', 0,
/* 656 */ 'z', 'm', 'm', '2', '7', 0,
/* 662 */ 'k', '7', 0,
/* 665 */ 'x', 'm', 'm', '7', 0,
/* 670 */ 'y', 'm', 'm', '7', 0,
/* 675 */ 'z', 'm', 'm', '7', 0,
/* 680 */ 'f', 'p', '7', 0,
/* 684 */ 'c', 'r', '7', 0,
/* 688 */ 'd', 'r', '7', 0,
/* 692 */ 'x', 'm', 'm', '1', '8', 0,
/* 698 */ 'y', 'm', 'm', '1', '8', 0,
/* 704 */ 'z', 'm', 'm', '1', '8', 0,
/* 710 */ 'x', 'm', 'm', '2', '8', 0,
/* 716 */ 'y', 'm', 'm', '2', '8', 0,
/* 722 */ 'z', 'm', 'm', '2', '8', 0,
/* 728 */ 'x', 'm', 'm', '8', 0,
/* 733 */ 'y', 'm', 'm', '8', 0,
/* 738 */ 'z', 'm', 'm', '8', 0,
/* 743 */ 'c', 'r', '8', 0,
/* 747 */ 'd', 'r', '8', 0,
/* 751 */ 'x', 'm', 'm', '1', '9', 0,
/* 757 */ 'y', 'm', 'm', '1', '9', 0,
/* 763 */ 'z', 'm', 'm', '1', '9', 0,
/* 769 */ 'x', 'm', 'm', '2', '9', 0,
/* 775 */ 'y', 'm', 'm', '2', '9', 0,
/* 781 */ 'z', 'm', 'm', '2', '9', 0,
/* 787 */ 'x', 'm', 'm', '9', 0,
/* 792 */ 'y', 'm', 'm', '9', 0,
/* 797 */ 'z', 'm', 'm', '9', 0,
/* 802 */ 'c', 'r', '9', 0,
/* 806 */ 'd', 'r', '9', 0,
/* 810 */ 'R', '1', '0', 'B', 'H', 0,
/* 816 */ 'R', '1', '1', 'B', 'H', 0,
/* 822 */ 'R', '1', '2', 'B', 'H', 0,
/* 828 */ 'R', '1', '3', 'B', 'H', 0,
/* 834 */ 'R', '1', '4', 'B', 'H', 0,
/* 840 */ 'R', '1', '5', 'B', 'H', 0,
/* 846 */ 'R', '8', 'B', 'H', 0,
/* 851 */ 'R', '9', 'B', 'H', 0,
/* 856 */ 'D', 'I', 'H', 0,
/* 860 */ 'S', 'I', 'H', 0,
/* 864 */ 'B', 'P', 'H', 0,
/* 868 */ 'S', 'P', 'H', 0,
/* 872 */ 'R', '1', '0', 'W', 'H', 0,
/* 878 */ 'R', '1', '1', 'W', 'H', 0,
/* 884 */ 'R', '1', '2', 'W', 'H', 0,
/* 890 */ 'R', '1', '3', 'W', 'H', 0,
/* 896 */ 'R', '1', '4', 'W', 'H', 0,
/* 902 */ 'R', '1', '5', 'W', 'H', 0,
/* 908 */ 'R', '8', 'W', 'H', 0,
/* 913 */ 'R', '9', 'W', 'H', 0,
/* 918 */ 'H', 'D', 'I', 0,
/* 922 */ 'H', 'S', 'I', 0,
/* 926 */ 'H', 'B', 'P', 0,
/* 930 */ 'H', 'I', 'P', 0,
/* 934 */ 'H', 'S', 'P', 0,
/* 938 */ 'H', 'A', 'X', 0,
/* 942 */ 'H', 'B', 'X', 0,
/* 946 */ 'H', 'C', 'X', 0,
/* 950 */ 'H', 'D', 'X', 0,
/* 954 */ 'r', '1', '0', 'b', 0,
/* 959 */ 'r', '1', '1', 'b', 0,
/* 964 */ 'r', '1', '2', 'b', 0,
/* 969 */ 'r', '1', '3', 'b', 0,
/* 974 */ 'r', '1', '4', 'b', 0,
/* 979 */ 'r', '1', '5', 'b', 0,
/* 984 */ 'r', '8', 'b', 0,
/* 988 */ 'r', '9', 'b', 0,
/* 992 */ 'r', '1', '0', 'd', 0,
/* 997 */ 'r', '1', '1', 'd', 0,
/* 1002 */ 'r', '1', '2', 'd', 0,
/* 1007 */ 'r', '1', '3', 'd', 0,
/* 1012 */ 'r', '1', '4', 'd', 0,
/* 1017 */ 'r', '1', '5', 'd', 0,
/* 1022 */ 'r', '8', 'd', 0,
/* 1026 */ 'r', '9', 'd', 0,
/* 1030 */ 'd', 'i', 'r', 'f', 'l', 'a', 'g', 0,
/* 1038 */ 'a', 'h', 0,
/* 1041 */ 'b', 'h', 0,
/* 1044 */ 'c', 'h', 0,
/* 1047 */ 'd', 'h', 0,
/* 1050 */ 'e', 'd', 'i', 0,
/* 1054 */ 'r', 'd', 'i', 0,
/* 1058 */ 'e', 's', 'i', 0,
/* 1062 */ 'r', 's', 'i', 0,
/* 1066 */ 'a', 'l', 0,
/* 1069 */ 'b', 'l', 0,
/* 1072 */ 'c', 'l', 0,
/* 1075 */ 'd', 'l', 0,
/* 1078 */ 'd', 'i', 'l', 0,
/* 1082 */ 's', 'i', 'l', 0,
/* 1086 */ 'b', 'p', 'l', 0,
/* 1090 */ 's', 'p', 'l', 0,
/* 1094 */ 'e', 'b', 'p', 0,
/* 1098 */ 'r', 'b', 'p', 0,
/* 1102 */ 'e', 'i', 'p', 0,
/* 1106 */ 'r', 'i', 'p', 0,
/* 1110 */ 'e', 's', 'p', 0,
/* 1114 */ 'r', 's', 'p', 0,
/* 1118 */ 's', 's', 'p', 0,
/* 1122 */ 'c', 's', 0,
/* 1125 */ 'd', 's', 0,
/* 1128 */ 'e', 's', 0,
/* 1131 */ 'f', 's', 0,
/* 1134 */ 'f', 'l', 'a', 'g', 's', 0,
/* 1140 */ 's', 's', 0,
/* 1143 */ 'r', '1', '0', 'w', 0,
/* 1148 */ 'r', '1', '1', 'w', 0,
/* 1153 */ 'r', '1', '2', 'w', 0,
/* 1158 */ 'r', '1', '3', 'w', 0,
/* 1163 */ 'r', '1', '4', 'w', 0,
/* 1168 */ 'r', '1', '5', 'w', 0,
/* 1173 */ 'r', '8', 'w', 0,
/* 1177 */ 'r', '9', 'w', 0,
/* 1181 */ 'f', 'p', 's', 'w', 0,
/* 1186 */ 'e', 'a', 'x', 0,
/* 1190 */ 'r', 'a', 'x', 0,
/* 1194 */ 'e', 'b', 'x', 0,
/* 1198 */ 'r', 'b', 'x', 0,
/* 1202 */ 'e', 'c', 'x', 0,
/* 1206 */ 'r', 'c', 'x', 0,
/* 1210 */ 'e', 'd', 'x', 0,
/* 1214 */ 'r', 'd', 'x', 0,
/* 1218 */ 'e', 'i', 'z', 0,
/* 1222 */ 'r', 'i', 'z', 0,
};
static const uint16_t RegAsmOffset[] = {
1038, 1066, 1187, 1041, 1069, 1095, 864, 1086, 1195, 1044, 1072, 1122, 1203, 1030,
1047, 1051, 856, 1078, 1075, 1125, 1211, 1186, 1094, 1194, 1202, 1050, 1210, 1134,
1102, 1218, 1128, 1058, 1110, 1181, 1131, 1137, 938, 926, 942, 946, 918, 950,
930, 922, 934, 1103, 1190, 1098, 1198, 1206, 1054, 1214, 1106, 1222, 1062, 1114,
1059, 860, 1082, 1111, 868, 1090, 1140, 1118, 112, 211, 292, 373, 139, 238,
319, 400, 476, 552, 618, 684, 743, 802, 66, 165, 264, 345, 426, 502,
143, 242, 323, 404, 480, 556, 622, 688, 747, 806, 71, 170, 269, 350,
431, 507, 135, 234, 315, 396, 472, 548, 614, 680, 117, 216, 297, 378,
454, 530, 596, 662, 121, 220, 301, 382, 458, 534, 600, 666, 744, 803,
67, 166, 265, 346, 427, 503, 0, 6, 12, 18, 24, 30, 36, 42,
120, 219, 300, 381, 457, 533, 599, 665, 728, 787, 48, 147, 246, 327,
408, 484, 560, 626, 692, 751, 76, 175, 274, 355, 436, 512, 578, 644,
710, 769, 94, 193, 125, 224, 305, 386, 462, 538, 604, 670, 733, 792,
54, 153, 252, 333, 414, 490, 566, 632, 698, 757, 82, 181, 280, 361,
442, 518, 584, 650, 716, 775, 100, 199, 130, 229, 310, 391, 467, 543,
609, 675, 738, 797, 60, 159, 258, 339, 420, 496, 572, 638, 704, 763,
88, 187, 286, 367, 448, 524, 590, 656, 722, 781, 106, 205, 984, 988,
954, 959, 964, 969, 974, 979, 846, 851, 810, 816, 822, 828, 834, 840,
1022, 1026, 992, 997, 1002, 1007, 1012, 1017, 1173, 1177, 1143, 1148, 1153, 1158,
1163, 1168, 908, 913, 872, 878, 884, 890, 896, 902,
};
return AsmStrs+RegAsmOffset[RegNo-1];
#else
return NULL;
#endif
}

335
thirdparty/capstone/arch/X86/X86ImmSize.inc vendored Normal file
View File

@@ -0,0 +1,335 @@
{1, 1, X86_AAD8i8},
{1, 1, X86_AAM8i8},
{2, 2, X86_ADC16i16},
{2, 2, X86_ADC16mi},
{1, 2, X86_ADC16mi8},
{2, 2, X86_ADC16ri},
{1, 2, X86_ADC16ri8},
{4, 4, X86_ADC32i32},
{4, 4, X86_ADC32mi},
{1, 4, X86_ADC32mi8},
{4, 4, X86_ADC32ri},
{1, 4, X86_ADC32ri8},
{4, 8, X86_ADC64i32},
{4, 8, X86_ADC64mi32},
{1, 8, X86_ADC64mi8},
{4, 8, X86_ADC64ri32},
{1, 8, X86_ADC64ri8},
{1, 1, X86_ADC8i8},
{1, 1, X86_ADC8mi},
{1, 1, X86_ADC8mi8},
{1, 1, X86_ADC8ri},
{1, 1, X86_ADC8ri8},
{2, 2, X86_ADD16i16},
{2, 2, X86_ADD16mi},
{1, 2, X86_ADD16mi8},
{2, 2, X86_ADD16ri},
{1, 2, X86_ADD16ri8},
{4, 4, X86_ADD32i32},
{4, 4, X86_ADD32mi},
{1, 4, X86_ADD32mi8},
{4, 4, X86_ADD32ri},
{1, 4, X86_ADD32ri8},
{4, 8, X86_ADD64i32},
{4, 8, X86_ADD64mi32},
{1, 8, X86_ADD64mi8},
{4, 8, X86_ADD64ri32},
{1, 8, X86_ADD64ri8},
{1, 1, X86_ADD8i8},
{1, 1, X86_ADD8mi},
{1, 1, X86_ADD8mi8},
{1, 1, X86_ADD8ri},
{1, 1, X86_ADD8ri8},
{2, 2, X86_AND16i16},
{2, 2, X86_AND16mi},
{1, 2, X86_AND16mi8},
{2, 2, X86_AND16ri},
{1, 2, X86_AND16ri8},
{4, 4, X86_AND32i32},
{4, 4, X86_AND32mi},
{1, 4, X86_AND32mi8},
{4, 4, X86_AND32ri},
{1, 4, X86_AND32ri8},
{4, 8, X86_AND64i32},
{4, 8, X86_AND64mi32},
{1, 8, X86_AND64mi8},
{4, 8, X86_AND64ri32},
{1, 8, X86_AND64ri8},
{1, 1, X86_AND8i8},
{1, 1, X86_AND8mi},
{1, 1, X86_AND8mi8},
{1, 1, X86_AND8ri},
{1, 1, X86_AND8ri8},
{1, 1, X86_BT16mi8},
{1, 1, X86_BT16ri8},
{1, 1, X86_BT32mi8},
{1, 1, X86_BT32ri8},
{1, 1, X86_BT64mi8},
{1, 1, X86_BT64ri8},
{1, 1, X86_BTC16mi8},
{1, 1, X86_BTC16ri8},
{1, 1, X86_BTC32mi8},
{1, 1, X86_BTC32ri8},
{1, 1, X86_BTC64mi8},
{1, 1, X86_BTC64ri8},
{1, 1, X86_BTR16mi8},
{1, 1, X86_BTR16ri8},
{1, 1, X86_BTR32mi8},
{1, 1, X86_BTR32ri8},
{1, 1, X86_BTR64mi8},
{1, 1, X86_BTR64ri8},
{1, 1, X86_BTS16mi8},
{1, 1, X86_BTS16ri8},
{1, 1, X86_BTS32mi8},
{1, 1, X86_BTS32ri8},
{1, 1, X86_BTS64mi8},
{1, 1, X86_BTS64ri8},
{2, 2, X86_CALLpcrel16},
{2, 4, X86_CALLpcrel32},
{2, 2, X86_CMP16i16},
{2, 2, X86_CMP16mi},
{1, 2, X86_CMP16mi8},
{2, 2, X86_CMP16ri},
{1, 2, X86_CMP16ri8},
{4, 4, X86_CMP32i32},
{4, 4, X86_CMP32mi},
{1, 4, X86_CMP32mi8},
{4, 4, X86_CMP32ri},
{1, 4, X86_CMP32ri8},
{4, 8, X86_CMP64i32},
{4, 8, X86_CMP64mi32},
{1, 8, X86_CMP64mi8},
{4, 8, X86_CMP64ri32},
{1, 8, X86_CMP64ri8},
{1, 1, X86_CMP8i8},
{1, 1, X86_CMP8mi},
{1, 1, X86_CMP8mi8},
{1, 1, X86_CMP8ri},
{1, 1, X86_CMP8ri8},
{1, 2, X86_IMUL16rmi8},
{1, 2, X86_IMUL16rri8},
{1, 4, X86_IMUL32rmi8},
{1, 4, X86_IMUL32rri8},
{4, 8, X86_IMUL64rmi32},
{1, 8, X86_IMUL64rmi8},
{4, 8, X86_IMUL64rri32},
{1, 8, X86_IMUL64rri8},
{2, 2, X86_IN16ri},
{4, 4, X86_IN32ri},
{1, 1, X86_IN8ri},
{2, 2, X86_JMP_2},
{2, 2, X86_MOV16mi},
{2, 2, X86_MOV16ri},
{2, 2, X86_MOV16ri_alt},
{4, 4, X86_MOV32mi},
{4, 4, X86_MOV32ri},
{4, 4, X86_MOV32ri_alt},
{4, 8, X86_MOV64mi32},
{8, 8, X86_MOV64ri},
{4, 8, X86_MOV64ri32},
{1, 1, X86_MOV8mi},
{1, 1, X86_MOV8ri},
{1, 1, X86_MOV8ri_alt},
{2, 2, X86_OR16i16},
{2, 2, X86_OR16mi},
{1, 2, X86_OR16mi8},
{2, 2, X86_OR16ri},
{1, 2, X86_OR16ri8},
{4, 4, X86_OR32i32},
{4, 4, X86_OR32mi},
{1, 4, X86_OR32mi8},
{4, 4, X86_OR32ri},
{1, 4, X86_OR32ri8},
{4, 8, X86_OR64i32},
{4, 8, X86_OR64mi32},
{1, 8, X86_OR64mi8},
{4, 8, X86_OR64ri32},
{1, 8, X86_OR64ri8},
{1, 1, X86_OR8i8},
{1, 1, X86_OR8mi},
{1, 1, X86_OR8mi8},
{1, 1, X86_OR8ri},
{1, 1, X86_OR8ri8},
{1, 2, X86_PUSH16i8},
{1, 4, X86_PUSH32i8},
{4, 8, X86_PUSH64i32},
{1, 8, X86_PUSH64i8},
{2, 2, X86_PUSHi16},
{4, 4, X86_PUSHi32},
{1, 1, X86_RCL16mi},
{1, 1, X86_RCL16ri},
{1, 1, X86_RCL32mi},
{1, 1, X86_RCL32ri},
{1, 1, X86_RCL64mi},
{1, 1, X86_RCL64ri},
{1, 1, X86_RCL8mi},
{1, 1, X86_RCL8ri},
{1, 1, X86_RCR16mi},
{1, 1, X86_RCR16ri},
{1, 1, X86_RCR32mi},
{1, 1, X86_RCR32ri},
{1, 1, X86_RCR64mi},
{1, 1, X86_RCR64ri},
{1, 1, X86_RCR8mi},
{1, 1, X86_RCR8ri},
//{4, 4, X86_RELEASE_ADD32mi},
//{4, 8, X86_RELEASE_ADD64mi32},
//{1, 1, X86_RELEASE_ADD8mi},
//{4, 4, X86_RELEASE_AND32mi},
//{4, 8, X86_RELEASE_AND64mi32},
//{1, 1, X86_RELEASE_AND8mi},
//{2, 2, X86_RELEASE_MOV16mi},
//{4, 4, X86_RELEASE_MOV32mi},
//{4, 8, X86_RELEASE_MOV64mi32},
//{1, 1, X86_RELEASE_MOV8mi},
//{4, 4, X86_RELEASE_OR32mi},
//{4, 8, X86_RELEASE_OR64mi32},
//{1, 1, X86_RELEASE_OR8mi},
//{4, 4, X86_RELEASE_XOR32mi},
//{4, 8, X86_RELEASE_XOR64mi32},
//{1, 1, X86_RELEASE_XOR8mi},
{1, 1, X86_ROL16mi},
{1, 1, X86_ROL16ri},
{1, 1, X86_ROL32mi},
{1, 1, X86_ROL32ri},
{1, 1, X86_ROL64mi},
{1, 1, X86_ROL64ri},
{1, 1, X86_ROL8mi},
{1, 1, X86_ROL8ri},
{1, 1, X86_ROR16mi},
{1, 1, X86_ROR16ri},
{1, 1, X86_ROR32mi},
{1, 1, X86_ROR32ri},
{1, 1, X86_ROR64mi},
{1, 1, X86_ROR64ri},
{1, 1, X86_ROR8mi},
{1, 1, X86_ROR8ri},
{4, 4, X86_RORX32mi},
{4, 4, X86_RORX32ri},
{8, 8, X86_RORX64mi},
{8, 8, X86_RORX64ri},
{1, 1, X86_SAL16mi},
{1, 1, X86_SAL16ri},
{1, 1, X86_SAL32mi},
{1, 1, X86_SAL32ri},
{1, 1, X86_SAL64mi},
{1, 1, X86_SAL64ri},
{1, 1, X86_SAL8mi},
{1, 1, X86_SAL8ri},
{1, 1, X86_SAR16mi},
{1, 1, X86_SAR16ri},
{1, 1, X86_SAR32mi},
{1, 1, X86_SAR32ri},
{1, 1, X86_SAR64mi},
{1, 1, X86_SAR64ri},
{1, 1, X86_SAR8mi},
{1, 1, X86_SAR8ri},
{2, 2, X86_SBB16i16},
{2, 2, X86_SBB16mi},
{1, 2, X86_SBB16mi8},
{2, 2, X86_SBB16ri},
{1, 2, X86_SBB16ri8},
{4, 4, X86_SBB32i32},
{4, 4, X86_SBB32mi},
{1, 4, X86_SBB32mi8},
{4, 4, X86_SBB32ri},
{1, 4, X86_SBB32ri8},
{4, 8, X86_SBB64i32},
{4, 8, X86_SBB64mi32},
{1, 8, X86_SBB64mi8},
{4, 8, X86_SBB64ri32},
{1, 8, X86_SBB64ri8},
{1, 1, X86_SBB8i8},
{1, 1, X86_SBB8mi},
{1, 1, X86_SBB8mi8},
{1, 1, X86_SBB8ri},
{1, 1, X86_SBB8ri8},
{1, 1, X86_SHL16mi},
{1, 1, X86_SHL16ri},
{1, 1, X86_SHL32mi},
{1, 1, X86_SHL32ri},
{1, 1, X86_SHL64mi},
{1, 1, X86_SHL64ri},
{1, 1, X86_SHL8mi},
{1, 1, X86_SHL8ri},
{1, 1, X86_SHLD16mri8},
{1, 1, X86_SHLD16rri8},
{1, 1, X86_SHLD32mri8},
{1, 1, X86_SHLD32rri8},
{1, 1, X86_SHLD64mri8},
{1, 1, X86_SHLD64rri8},
{1, 1, X86_SHR16mi},
{1, 1, X86_SHR16ri},
{1, 1, X86_SHR32mi},
{1, 1, X86_SHR32ri},
{1, 1, X86_SHR64mi},
{1, 1, X86_SHR64ri},
{1, 1, X86_SHR8mi},
{1, 1, X86_SHR8ri},
{1, 1, X86_SHRD16mri8},
{1, 1, X86_SHRD16rri8},
{1, 1, X86_SHRD32mri8},
{1, 1, X86_SHRD32rri8},
{1, 1, X86_SHRD64mri8},
{1, 1, X86_SHRD64rri8},
{2, 2, X86_SUB16i16},
{2, 2, X86_SUB16mi},
{1, 2, X86_SUB16mi8},
{2, 2, X86_SUB16ri},
{1, 2, X86_SUB16ri8},
{4, 4, X86_SUB32i32},
{4, 4, X86_SUB32mi},
{1, 4, X86_SUB32mi8},
{4, 4, X86_SUB32ri},
{1, 4, X86_SUB32ri8},
{4, 8, X86_SUB64i32},
{4, 8, X86_SUB64mi32},
{1, 8, X86_SUB64mi8},
{4, 8, X86_SUB64ri32},
{1, 8, X86_SUB64ri8},
{1, 1, X86_SUB8i8},
{1, 1, X86_SUB8mi},
{1, 1, X86_SUB8mi8},
{1, 1, X86_SUB8ri},
{1, 1, X86_SUB8ri8},
{2, 2, X86_TEST16i16},
{2, 2, X86_TEST16mi},
// {2, 2, X86_TEST16mi_alt},
{2, 2, X86_TEST16ri},
//{2, 2, X86_TEST16ri_alt},
{4, 4, X86_TEST32i32},
{4, 4, X86_TEST32mi},
//{4, 4, X86_TEST32mi_alt},
{4, 4, X86_TEST32ri},
//{4, 4, X86_TEST32ri_alt},
{4, 8, X86_TEST64i32},
{4, 8, X86_TEST64mi32},
//{4, 4, X86_TEST64mi32_alt},
{4, 8, X86_TEST64ri32},
//{4, 4, X86_TEST64ri32_alt},
{1, 1, X86_TEST8i8},
{1, 1, X86_TEST8mi},
//{1, 1, X86_TEST8mi_alt},
{1, 1, X86_TEST8ri},
//{1, 1, X86_TEST8ri_NOREX},
//{1, 1, X86_TEST8ri_alt},
{2, 2, X86_XOR16i16},
{2, 2, X86_XOR16mi},
{1, 2, X86_XOR16mi8},
{2, 2, X86_XOR16ri},
{1, 2, X86_XOR16ri8},
{4, 4, X86_XOR32i32},
{4, 4, X86_XOR32mi},
{1, 4, X86_XOR32mi8},
{4, 4, X86_XOR32ri},
{1, 4, X86_XOR32ri8},
{4, 8, X86_XOR64i32},
{4, 8, X86_XOR64mi32},
{1, 8, X86_XOR64mi8},
{4, 8, X86_XOR64ri32},
{1, 8, X86_XOR64ri8},
{1, 1, X86_XOR8i8},
{1, 1, X86_XOR8mi},
{1, 1, X86_XOR8mi8},
{1, 1, X86_XOR8ri},
{1, 1, X86_XOR8ri8},

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//= X86IntelInstPrinter.h - Convert X86 MCInst to assembly syntax -*- C++ -*-=//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This class prints an X86 MCInst to Intel style .s file syntax.
//
//===----------------------------------------------------------------------===//
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
#ifndef CS_X86_INSTPRINTER_H
#define CS_X86_INSTPRINTER_H
#include "../../MCInst.h"
#include "../../SStream.h"
void X86_Intel_printInst(MCInst *MI, SStream *OS, void *Info);
void X86_ATT_printInst(MCInst *MI, SStream *OS, void *Info);
#endif

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//===--- X86InstPrinterCommon.cpp - X86 assembly instruction printing -----===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file includes common code for rendering MCInst instances as Intel-style
// and Intel-style assembly.
//
//===----------------------------------------------------------------------===//
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
#ifdef _MSC_VER
#pragma warning(disable:4996) // disable MSVC's warning on strncpy()
#pragma warning(disable:28719) // disable MSVC's warning on strncpy()
#endif
#if !defined(CAPSTONE_HAS_OSXKERNEL)
#include <ctype.h>
#endif
#include <capstone/platform.h>
#if defined(CAPSTONE_HAS_OSXKERNEL)
#include <Availability.h>
#include <libkern/libkern.h>
#else
#include <stdio.h>
#include <stdlib.h>
#endif
#include <string.h>
#include "../../utils.h"
#include "../../MCInst.h"
#include "../../SStream.h"
#include "X86InstPrinterCommon.h"
#include "X86Mapping.h"
#ifndef CAPSTONE_X86_REDUCE
void printSSEAVXCC(MCInst *MI, unsigned Op, SStream *O)
{
uint8_t Imm = (uint8_t)(MCOperand_getImm(MCInst_getOperand(MI, Op)) & 0x1f);
switch (Imm) {
default: break;//printf("Invalid avxcc argument!\n"); break;
case 0: SStream_concat0(O, "eq"); op_addAvxCC(MI, X86_AVX_CC_EQ); break;
case 1: SStream_concat0(O, "lt"); op_addAvxCC(MI, X86_AVX_CC_LT); break;
case 2: SStream_concat0(O, "le"); op_addAvxCC(MI, X86_AVX_CC_LE); break;
case 3: SStream_concat0(O, "unord"); op_addAvxCC(MI, X86_AVX_CC_UNORD); break;
case 4: SStream_concat0(O, "neq"); op_addAvxCC(MI, X86_AVX_CC_NEQ); break;
case 5: SStream_concat0(O, "nlt"); op_addAvxCC(MI, X86_AVX_CC_NLT); break;
case 6: SStream_concat0(O, "nle"); op_addAvxCC(MI, X86_AVX_CC_NLE); break;
case 7: SStream_concat0(O, "ord"); op_addAvxCC(MI, X86_AVX_CC_ORD); break;
case 8: SStream_concat0(O, "eq_uq"); op_addAvxCC(MI, X86_AVX_CC_EQ_UQ); break;
case 9: SStream_concat0(O, "nge"); op_addAvxCC(MI, X86_AVX_CC_NGE); break;
case 0xa: SStream_concat0(O, "ngt"); op_addAvxCC(MI, X86_AVX_CC_NGT); break;
case 0xb: SStream_concat0(O, "false"); op_addAvxCC(MI, X86_AVX_CC_FALSE); break;
case 0xc: SStream_concat0(O, "neq_oq"); op_addAvxCC(MI, X86_AVX_CC_NEQ_OQ); break;
case 0xd: SStream_concat0(O, "ge"); op_addAvxCC(MI, X86_AVX_CC_GE); break;
case 0xe: SStream_concat0(O, "gt"); op_addAvxCC(MI, X86_AVX_CC_GT); break;
case 0xf: SStream_concat0(O, "true"); op_addAvxCC(MI, X86_AVX_CC_TRUE); break;
case 0x10: SStream_concat0(O, "eq_os"); op_addAvxCC(MI, X86_AVX_CC_EQ_OS); break;
case 0x11: SStream_concat0(O, "lt_oq"); op_addAvxCC(MI, X86_AVX_CC_LT_OQ); break;
case 0x12: SStream_concat0(O, "le_oq"); op_addAvxCC(MI, X86_AVX_CC_LE_OQ); break;
case 0x13: SStream_concat0(O, "unord_s"); op_addAvxCC(MI, X86_AVX_CC_UNORD_S); break;
case 0x14: SStream_concat0(O, "neq_us"); op_addAvxCC(MI, X86_AVX_CC_NEQ_US); break;
case 0x15: SStream_concat0(O, "nlt_uq"); op_addAvxCC(MI, X86_AVX_CC_NLT_UQ); break;
case 0x16: SStream_concat0(O, "nle_uq"); op_addAvxCC(MI, X86_AVX_CC_NLE_UQ); break;
case 0x17: SStream_concat0(O, "ord_s"); op_addAvxCC(MI, X86_AVX_CC_ORD_S); break;
case 0x18: SStream_concat0(O, "eq_us"); op_addAvxCC(MI, X86_AVX_CC_EQ_US); break;
case 0x19: SStream_concat0(O, "nge_uq"); op_addAvxCC(MI, X86_AVX_CC_NGE_UQ); break;
case 0x1a: SStream_concat0(O, "ngt_uq"); op_addAvxCC(MI, X86_AVX_CC_NGT_UQ); break;
case 0x1b: SStream_concat0(O, "false_os"); op_addAvxCC(MI, X86_AVX_CC_FALSE_OS); break;
case 0x1c: SStream_concat0(O, "neq_os"); op_addAvxCC(MI, X86_AVX_CC_NEQ_OS); break;
case 0x1d: SStream_concat0(O, "ge_oq"); op_addAvxCC(MI, X86_AVX_CC_GE_OQ); break;
case 0x1e: SStream_concat0(O, "gt_oq"); op_addAvxCC(MI, X86_AVX_CC_GT_OQ); break;
case 0x1f: SStream_concat0(O, "true_us"); op_addAvxCC(MI, X86_AVX_CC_TRUE_US); break;
}
MI->popcode_adjust = Imm + 1;
}
void printXOPCC(MCInst *MI, unsigned Op, SStream *O)
{
int64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, Op));
switch (Imm) {
default: // llvm_unreachable("Invalid xopcc argument!");
case 0: SStream_concat0(O, "lt"); op_addXopCC(MI, X86_XOP_CC_LT); break;
case 1: SStream_concat0(O, "le"); op_addXopCC(MI, X86_XOP_CC_LE); break;
case 2: SStream_concat0(O, "gt"); op_addXopCC(MI, X86_XOP_CC_GT); break;
case 3: SStream_concat0(O, "ge"); op_addXopCC(MI, X86_XOP_CC_GE); break;
case 4: SStream_concat0(O, "eq"); op_addXopCC(MI, X86_XOP_CC_EQ); break;
case 5: SStream_concat0(O, "neq"); op_addXopCC(MI, X86_XOP_CC_NEQ); break;
case 6: SStream_concat0(O, "false"); op_addXopCC(MI, X86_XOP_CC_FALSE); break;
case 7: SStream_concat0(O, "true"); op_addXopCC(MI, X86_XOP_CC_TRUE); break;
}
}
void printRoundingControl(MCInst *MI, unsigned Op, SStream *O)
{
int64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, Op)) & 0x3;
switch (Imm) {
case 0: SStream_concat0(O, "{rn-sae}"); op_addAvxSae(MI); op_addAvxRoundingMode(MI, X86_AVX_RM_RN); break;
case 1: SStream_concat0(O, "{rd-sae}"); op_addAvxSae(MI); op_addAvxRoundingMode(MI, X86_AVX_RM_RD); break;
case 2: SStream_concat0(O, "{ru-sae}"); op_addAvxSae(MI); op_addAvxRoundingMode(MI, X86_AVX_RM_RU); break;
case 3: SStream_concat0(O, "{rz-sae}"); op_addAvxSae(MI); op_addAvxRoundingMode(MI, X86_AVX_RM_RZ); break;
default: break; // never reach
}
}
#endif

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/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
#ifndef CS_X86_INSTPRINTERCOMMON_H
#define CS_X86_INSTPRINTERCOMMON_H
#include "../../MCInst.h"
#include "../../SStream.h"
#define CS_X86_MAXIMUM_OPERAND_SIZE 6
void printSSEAVXCC(MCInst *MI, unsigned Op, SStream *O);
void printXOPCC(MCInst *MI, unsigned Op, SStream *O);
void printRoundingControl(MCInst *MI, unsigned Op, SStream *O);
#endif

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/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
#ifndef CS_X86_MAP_H
#define CS_X86_MAP_H
#include "capstone/capstone.h"
#include "../../cs_priv.h"
// map instruction to its characteristics
typedef struct insn_map_x86 {
unsigned short id;
unsigned short mapid;
unsigned char is64bit;
#ifndef CAPSTONE_DIET
uint16_t regs_use[12]; // list of implicit registers used by this instruction
uint16_t regs_mod[20]; // list of implicit registers modified by this instruction
unsigned char groups[8]; // list of group this instruction belong to
bool branch; // branch instruction?
bool indirect_branch; // indirect branch instruction?
#endif
} insn_map_x86;
extern const insn_map_x86 insns[];
// map sib_base to x86_reg
x86_reg x86_map_sib_base(int r);
// map sib_index to x86_reg
x86_reg x86_map_sib_index(int r);
// map seg_override to x86_reg
x86_reg x86_map_segment(int r);
// return name of register in friendly string
const char *X86_reg_name(csh handle, unsigned int reg);
// given internal insn id, return public instruction info
void X86_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
// return insn name, given insn id
const char *X86_insn_name(csh handle, unsigned int id);
// return group name, given group id
const char *X86_group_name(csh handle, unsigned int id);
// return register of given instruction id
// return 0 if not found
// this is to handle instructions embedding accumulate registers into AsmStrs[]
x86_reg X86_insn_reg_intel(unsigned int id, enum cs_ac_type *access);
x86_reg X86_insn_reg_att(unsigned int id, enum cs_ac_type *access);
bool X86_insn_reg_intel2(unsigned int id, x86_reg *reg1, enum cs_ac_type *access1, x86_reg *reg2, enum cs_ac_type *access2);
bool X86_insn_reg_att2(unsigned int id, x86_reg *reg1, enum cs_ac_type *access1, x86_reg *reg2, enum cs_ac_type *access2);
extern const uint64_t arch_masks[9];
// handle LOCK/REP/REPNE prefixes
// return True if we patch mnemonic, like in MULPD case
bool X86_lockrep(MCInst *MI, SStream *O);
// map registers to sizes
extern const uint8_t regsize_map_32[];
extern const uint8_t regsize_map_64[];
void op_addReg(MCInst *MI, int reg);
void op_addImm(MCInst *MI, int v);
void op_addAvxBroadcast(MCInst *MI, x86_avx_bcast v);
void op_addXopCC(MCInst *MI, int v);
void op_addSseCC(MCInst *MI, int v);
void op_addAvxCC(MCInst *MI, int v);
void op_addAvxZeroOpmask(MCInst *MI);
void op_addAvxSae(MCInst *MI);
void op_addAvxRoundingMode(MCInst *MI, int v);
// given internal insn id, return operand access info
const uint8_t *X86_get_op_access(cs_struct *h, unsigned int id, uint64_t *eflags);
void X86_reg_access(const cs_insn *insn,
cs_regs regs_read, uint8_t *regs_read_count,
cs_regs regs_write, uint8_t *regs_write_count);
// given the instruction id, return the size of its immediate operand (or 0)
uint8_t X86_immediate_size(unsigned int id, uint8_t *enc_size);
unsigned short X86_register_map(unsigned short id);
unsigned int find_insn(unsigned int id);
void X86_postprinter(csh handle, cs_insn *insn, char *mnem, MCInst *mci);
#endif

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/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
"aaa", // X86_INS_AAA
"aad", // X86_INS_AAD
"aam", // X86_INS_AAM
"aas", // X86_INS_AAS
"adc", // X86_INS_ADC
"adcx", // X86_INS_ADCX
"add", // X86_INS_ADD
"adox", // X86_INS_ADOX
"and", // X86_INS_AND
"andn", // X86_INS_ANDN
"arpl", // X86_INS_ARPL
"bextr", // X86_INS_BEXTR
"blcfill", // X86_INS_BLCFILL
"blci", // X86_INS_BLCI
"blcic", // X86_INS_BLCIC
"blcmsk", // X86_INS_BLCMSK
"blcs", // X86_INS_BLCS
"blsfill", // X86_INS_BLSFILL
"blsi", // X86_INS_BLSI
"blsic", // X86_INS_BLSIC
"blsmsk", // X86_INS_BLSMSK
"blsr", // X86_INS_BLSR
"bound", // X86_INS_BOUND
"bsf", // X86_INS_BSF
"bsr", // X86_INS_BSR
"bswap", // X86_INS_BSWAP
"bt", // X86_INS_BT
"btc", // X86_INS_BTC
"btr", // X86_INS_BTR
"bts", // X86_INS_BTS
"bzhi", // X86_INS_BZHI
"call", // X86_INS_CALL
"cbw", // X86_INS_CBW
"cdq", // X86_INS_CDQ
"cdqe", // X86_INS_CDQE
"clac", // X86_INS_CLAC
"clc", // X86_INS_CLC
"cld", // X86_INS_CLD
"cldemote", // X86_INS_CLDEMOTE
"clflushopt", // X86_INS_CLFLUSHOPT
"clgi", // X86_INS_CLGI
"cli", // X86_INS_CLI
"clrssbsy", // X86_INS_CLRSSBSY
"clts", // X86_INS_CLTS
"clwb", // X86_INS_CLWB
"clzero", // X86_INS_CLZERO
"cmc", // X86_INS_CMC
"cmova", // X86_INS_CMOVA
"cmovae", // X86_INS_CMOVAE
"cmovb", // X86_INS_CMOVB
"cmovbe", // X86_INS_CMOVBE
"cmove", // X86_INS_CMOVE
"cmovg", // X86_INS_CMOVG
"cmovge", // X86_INS_CMOVGE
"cmovl", // X86_INS_CMOVL
"cmovle", // X86_INS_CMOVLE
"cmovne", // X86_INS_CMOVNE
"cmovno", // X86_INS_CMOVNO
"cmovnp", // X86_INS_CMOVNP
"cmovns", // X86_INS_CMOVNS
"cmovo", // X86_INS_CMOVO
"cmovp", // X86_INS_CMOVP
"cmovs", // X86_INS_CMOVS
"cmp", // X86_INS_CMP
"cmpsb", // X86_INS_CMPSB
"cmpsd", // X86_INS_CMPSD
"cmpsq", // X86_INS_CMPSQ
"cmpsw", // X86_INS_CMPSW
"cmpxchg16b", // X86_INS_CMPXCHG16B
"cmpxchg", // X86_INS_CMPXCHG
"cmpxchg8b", // X86_INS_CMPXCHG8B
"cpuid", // X86_INS_CPUID
"cqo", // X86_INS_CQO
"cwd", // X86_INS_CWD
"cwde", // X86_INS_CWDE
"daa", // X86_INS_DAA
"das", // X86_INS_DAS
"data16", // X86_INS_DATA16
"dec", // X86_INS_DEC
"div", // X86_INS_DIV
"endbr32", // X86_INS_ENDBR32
"endbr64", // X86_INS_ENDBR64
"enter", // X86_INS_ENTER
"lcall", // X86_INS_LCALL
"ljmp", // X86_INS_LJMP
"jmp", // X86_INS_JMP
"fsetpm", // X86_INS_FSETPM
"getsec", // X86_INS_GETSEC
"hlt", // X86_INS_HLT
"idiv", // X86_INS_IDIV
"imul", // X86_INS_IMUL
"in", // X86_INS_IN
"inc", // X86_INS_INC
"incsspd", // X86_INS_INCSSPD
"incsspq", // X86_INS_INCSSPQ
"insb", // X86_INS_INSB
"insd", // X86_INS_INSD
"insw", // X86_INS_INSW
"int", // X86_INS_INT
"int1", // X86_INS_INT1
"int3", // X86_INS_INT3
"into", // X86_INS_INTO
"invd", // X86_INS_INVD
"invept", // X86_INS_INVEPT
"invlpg", // X86_INS_INVLPG
"invlpga", // X86_INS_INVLPGA
"invpcid", // X86_INS_INVPCID
"invvpid", // X86_INS_INVVPID
"iret", // X86_INS_IRET
"iretd", // X86_INS_IRETD
"iretq", // X86_INS_IRETQ
"jae", // X86_INS_JAE
"ja", // X86_INS_JA
"jbe", // X86_INS_JBE
"jb", // X86_INS_JB
"jcxz", // X86_INS_JCXZ
"jecxz", // X86_INS_JECXZ
"je", // X86_INS_JE
"jge", // X86_INS_JGE
"jg", // X86_INS_JG
"jle", // X86_INS_JLE
"jl", // X86_INS_JL
"jne", // X86_INS_JNE
"jno", // X86_INS_JNO
"jnp", // X86_INS_JNP
"jns", // X86_INS_JNS
"jo", // X86_INS_JO
"jp", // X86_INS_JP
"jrcxz", // X86_INS_JRCXZ
"js", // X86_INS_JS
"lahf", // X86_INS_LAHF
"lar", // X86_INS_LAR
"lds", // X86_INS_LDS
"lea", // X86_INS_LEA
"leave", // X86_INS_LEAVE
"les", // X86_INS_LES
"lfs", // X86_INS_LFS
"lgdt", // X86_INS_LGDT
"lgs", // X86_INS_LGS
"lidt", // X86_INS_LIDT
"lldt", // X86_INS_LLDT
"llwpcb", // X86_INS_LLWPCB
"lmsw", // X86_INS_LMSW
"lock", // X86_INS_LOCK
"lodsb", // X86_INS_LODSB
"lodsd", // X86_INS_LODSD
"lodsq", // X86_INS_LODSQ
"lodsw", // X86_INS_LODSW
"loop", // X86_INS_LOOP
"loope", // X86_INS_LOOPE
"loopne", // X86_INS_LOOPNE
"retf", // X86_INS_RETF
"retfq", // X86_INS_RETFQ
"lsl", // X86_INS_LSL
"lss", // X86_INS_LSS
"ltr", // X86_INS_LTR
"lwpins", // X86_INS_LWPINS
"lwpval", // X86_INS_LWPVAL
"lzcnt", // X86_INS_LZCNT
"monitorx", // X86_INS_MONITORX
"montmul", // X86_INS_MONTMUL
"mov", // X86_INS_MOV
"movabs", // X86_INS_MOVABS
"movbe", // X86_INS_MOVBE
"movdir64b", // X86_INS_MOVDIR64B
"movdiri", // X86_INS_MOVDIRI
"movsb", // X86_INS_MOVSB
"movsd", // X86_INS_MOVSD
"movsq", // X86_INS_MOVSQ
"movsw", // X86_INS_MOVSW
"movsx", // X86_INS_MOVSX
"movsxd", // X86_INS_MOVSXD
"movzx", // X86_INS_MOVZX
"mul", // X86_INS_MUL
"mulx", // X86_INS_MULX
"mwaitx", // X86_INS_MWAITX
"neg", // X86_INS_NEG
"nop", // X86_INS_NOP
"not", // X86_INS_NOT
"or", // X86_INS_OR
"out", // X86_INS_OUT
"outsb", // X86_INS_OUTSB
"outsd", // X86_INS_OUTSD
"outsw", // X86_INS_OUTSW
"pconfig", // X86_INS_PCONFIG
"pdep", // X86_INS_PDEP
"pext", // X86_INS_PEXT
"pop", // X86_INS_POP
"popaw", // X86_INS_POPAW
"popal", // X86_INS_POPAL
"popf", // X86_INS_POPF
"popfd", // X86_INS_POPFD
"popfq", // X86_INS_POPFQ
"ptwrite", // X86_INS_PTWRITE
"push", // X86_INS_PUSH
"pushaw", // X86_INS_PUSHAW
"pushal", // X86_INS_PUSHAL
"pushf", // X86_INS_PUSHF
"pushfd", // X86_INS_PUSHFD
"pushfq", // X86_INS_PUSHFQ
"rcl", // X86_INS_RCL
"rcr", // X86_INS_RCR
"rdfsbase", // X86_INS_RDFSBASE
"rdgsbase", // X86_INS_RDGSBASE
"rdmsr", // X86_INS_RDMSR
"rdpid", // X86_INS_RDPID
"rdpkru", // X86_INS_RDPKRU
"rdpmc", // X86_INS_RDPMC
"rdrand", // X86_INS_RDRAND
"rdseed", // X86_INS_RDSEED
"rdsspd", // X86_INS_RDSSPD
"rdsspq", // X86_INS_RDSSPQ
"rdtsc", // X86_INS_RDTSC
"rdtscp", // X86_INS_RDTSCP
"repne", // X86_INS_REPNE
"rep", // X86_INS_REP
"ret", // X86_INS_RET
"rex64", // X86_INS_REX64
"rol", // X86_INS_ROL
"ror", // X86_INS_ROR
"rorx", // X86_INS_RORX
"rsm", // X86_INS_RSM
"rstorssp", // X86_INS_RSTORSSP
"sahf", // X86_INS_SAHF
"sal", // X86_INS_SAL
"salc", // X86_INS_SALC
"sar", // X86_INS_SAR
"sarx", // X86_INS_SARX
"saveprevssp", // X86_INS_SAVEPREVSSP
"sbb", // X86_INS_SBB
"scasb", // X86_INS_SCASB
"scasd", // X86_INS_SCASD
"scasq", // X86_INS_SCASQ
"scasw", // X86_INS_SCASW
"setae", // X86_INS_SETAE
"seta", // X86_INS_SETA
"setbe", // X86_INS_SETBE
"setb", // X86_INS_SETB
"sete", // X86_INS_SETE
"setge", // X86_INS_SETGE
"setg", // X86_INS_SETG
"setle", // X86_INS_SETLE
"setl", // X86_INS_SETL
"setne", // X86_INS_SETNE
"setno", // X86_INS_SETNO
"setnp", // X86_INS_SETNP
"setns", // X86_INS_SETNS
"seto", // X86_INS_SETO
"setp", // X86_INS_SETP
"setssbsy", // X86_INS_SETSSBSY
"sets", // X86_INS_SETS
"sgdt", // X86_INS_SGDT
"shl", // X86_INS_SHL
"shld", // X86_INS_SHLD
"shlx", // X86_INS_SHLX
"shr", // X86_INS_SHR
"shrd", // X86_INS_SHRD
"shrx", // X86_INS_SHRX
"sidt", // X86_INS_SIDT
"skinit", // X86_INS_SKINIT
"sldt", // X86_INS_SLDT
"slwpcb", // X86_INS_SLWPCB
"smsw", // X86_INS_SMSW
"stac", // X86_INS_STAC
"stc", // X86_INS_STC
"std", // X86_INS_STD
"stgi", // X86_INS_STGI
"sti", // X86_INS_STI
"stosb", // X86_INS_STOSB
"stosd", // X86_INS_STOSD
"stosq", // X86_INS_STOSQ
"stosw", // X86_INS_STOSW
"str", // X86_INS_STR
"sub", // X86_INS_SUB
"swapgs", // X86_INS_SWAPGS
"syscall", // X86_INS_SYSCALL
"sysenter", // X86_INS_SYSENTER
"sysexit", // X86_INS_SYSEXIT
"sysexitq", // X86_INS_SYSEXITQ
"sysret", // X86_INS_SYSRET
"sysretq", // X86_INS_SYSRETQ
"t1mskc", // X86_INS_T1MSKC
"test", // X86_INS_TEST
"tpause", // X86_INS_TPAUSE
"tzcnt", // X86_INS_TZCNT
"tzmsk", // X86_INS_TZMSK
"ud0", // X86_INS_UD0
"ud1", // X86_INS_UD1
"ud2", // X86_INS_UD2
"umonitor", // X86_INS_UMONITOR
"umwait", // X86_INS_UMWAIT
"verr", // X86_INS_VERR
"verw", // X86_INS_VERW
"vmcall", // X86_INS_VMCALL
"vmclear", // X86_INS_VMCLEAR
"vmfunc", // X86_INS_VMFUNC
"vmlaunch", // X86_INS_VMLAUNCH
"vmload", // X86_INS_VMLOAD
"vmmcall", // X86_INS_VMMCALL
"vmptrld", // X86_INS_VMPTRLD
"vmptrst", // X86_INS_VMPTRST
"vmread", // X86_INS_VMREAD
"vmresume", // X86_INS_VMRESUME
"vmrun", // X86_INS_VMRUN
"vmsave", // X86_INS_VMSAVE
"vmwrite", // X86_INS_VMWRITE
"vmxoff", // X86_INS_VMXOFF
"vmxon", // X86_INS_VMXON
"wbinvd", // X86_INS_WBINVD
"wbnoinvd", // X86_INS_WBNOINVD
"wrfsbase", // X86_INS_WRFSBASE
"wrgsbase", // X86_INS_WRGSBASE
"wrmsr", // X86_INS_WRMSR
"wrpkru", // X86_INS_WRPKRU
"wrssd", // X86_INS_WRSSD
"wrssq", // X86_INS_WRSSQ
"wrussd", // X86_INS_WRUSSD
"wrussq", // X86_INS_WRUSSQ
"xadd", // X86_INS_XADD
"xchg", // X86_INS_XCHG
"xcryptcbc", // X86_INS_XCRYPTCBC
"xcryptcfb", // X86_INS_XCRYPTCFB
"xcryptctr", // X86_INS_XCRYPTCTR
"xcryptecb", // X86_INS_XCRYPTECB
"xcryptofb", // X86_INS_XCRYPTOFB
"xgetbv", // X86_INS_XGETBV
"xlatb", // X86_INS_XLATB
"xor", // X86_INS_XOR
"xrstor", // X86_INS_XRSTOR
"xrstor64", // X86_INS_XRSTOR64
"xrstors", // X86_INS_XRSTORS
"xrstors64", // X86_INS_XRSTORS64
"xsave", // X86_INS_XSAVE
"xsave64", // X86_INS_XSAVE64
"xsavec", // X86_INS_XSAVEC
"xsavec64", // X86_INS_XSAVEC64
"xsaveopt", // X86_INS_XSAVEOPT
"xsaveopt64", // X86_INS_XSAVEOPT64
"xsaves", // X86_INS_XSAVES
"xsaves64", // X86_INS_XSAVES64
"xsetbv", // X86_INS_XSETBV
"xsha1", // X86_INS_XSHA1
"xsha256", // X86_INS_XSHA256
"xstore", // X86_INS_XSTORE

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/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
{ X86_AH, X86_REG_AH },
{ X86_AL, X86_REG_AL },
{ X86_AX, X86_REG_AX },
{ X86_BH, X86_REG_BH },
{ X86_BL, X86_REG_BL },
{ X86_BP, X86_REG_BP },
{ X86_BPH, 0 },
{ X86_BPL, X86_REG_BPL },
{ X86_BX, X86_REG_BX },
{ X86_CH, X86_REG_CH },
{ X86_CL, X86_REG_CL },
{ X86_CS, X86_REG_CS },
{ X86_CX, X86_REG_CX },
{ X86_DF, 0 },
{ X86_DH, X86_REG_DH },
{ X86_DI, X86_REG_DI },
{ X86_DIH, 0 },
{ X86_DIL, X86_REG_DIL },
{ X86_DL, X86_REG_DL },
{ X86_DS, X86_REG_DS },
{ X86_DX, X86_REG_DX },
{ X86_EAX, X86_REG_EAX },
{ X86_EBP, X86_REG_EBP },
{ X86_EBX, X86_REG_EBX },
{ X86_ECX, X86_REG_ECX },
{ X86_EDI, X86_REG_EDI },
{ X86_EDX, X86_REG_EDX },
{ X86_EFLAGS, X86_REG_EFLAGS },
{ X86_EIP, X86_REG_EIP },
{ X86_EIZ, X86_REG_EIZ },
{ X86_ES, X86_REG_ES },
{ X86_ESI, X86_REG_ESI },
{ X86_ESP, X86_REG_ESP },
{ X86_FPSW, X86_REG_FPSW },
{ X86_FS, X86_REG_FS },
{ X86_GS, X86_REG_GS },
{ X86_HAX, 0 },
{ X86_HBP, 0 },
{ X86_HBX, 0 },
{ X86_HCX, 0 },
{ X86_HDI, 0 },
{ X86_HDX, 0 },
{ X86_HIP, 0 },
{ X86_HSI, 0 },
{ X86_HSP, 0 },
{ X86_IP, X86_REG_IP },
{ X86_RAX, X86_REG_RAX },
{ X86_RBP, X86_REG_RBP },
{ X86_RBX, X86_REG_RBX },
{ X86_RCX, X86_REG_RCX },
{ X86_RDI, X86_REG_RDI },
{ X86_RDX, X86_REG_RDX },
{ X86_RIP, X86_REG_RIP },
{ X86_RIZ, X86_REG_RIZ },
{ X86_RSI, X86_REG_RSI },
{ X86_RSP, X86_REG_RSP },
{ X86_SI, X86_REG_SI },
{ X86_SIH, 0 },
{ X86_SIL, X86_REG_SIL },
{ X86_SP, X86_REG_SP },
{ X86_SPH, 0 },
{ X86_SPL, X86_REG_SPL },
{ X86_SS, X86_REG_SS },
{ X86_SSP, 0 },
{ X86_BND0, X86_REG_BND0 },
{ X86_BND1, X86_REG_BND1 },
{ X86_BND2, X86_REG_BND2 },
{ X86_BND3, X86_REG_BND3 },
{ X86_CR0, X86_REG_CR0 },
{ X86_CR1, X86_REG_CR1 },
{ X86_CR2, X86_REG_CR2 },
{ X86_CR3, X86_REG_CR3 },
{ X86_CR4, X86_REG_CR4 },
{ X86_CR5, X86_REG_CR5 },
{ X86_CR6, X86_REG_CR6 },
{ X86_CR7, X86_REG_CR7 },
{ X86_CR8, X86_REG_CR8 },
{ X86_CR9, X86_REG_CR9 },
{ X86_CR10, X86_REG_CR10 },
{ X86_CR11, X86_REG_CR11 },
{ X86_CR12, X86_REG_CR12 },
{ X86_CR13, X86_REG_CR13 },
{ X86_CR14, X86_REG_CR14 },
{ X86_CR15, X86_REG_CR15 },
{ X86_DR0, X86_REG_DR0 },
{ X86_DR1, X86_REG_DR1 },
{ X86_DR2, X86_REG_DR2 },
{ X86_DR3, X86_REG_DR3 },
{ X86_DR4, X86_REG_DR4 },
{ X86_DR5, X86_REG_DR5 },
{ X86_DR6, X86_REG_DR6 },
{ X86_DR7, X86_REG_DR7 },
{ X86_DR8, X86_REG_DR8 },
{ X86_DR9, X86_REG_DR9 },
{ X86_DR10, X86_REG_DR10 },
{ X86_DR11, X86_REG_DR11 },
{ X86_DR12, X86_REG_DR12 },
{ X86_DR13, X86_REG_DR13 },
{ X86_DR14, X86_REG_DR14 },
{ X86_DR15, X86_REG_DR15 },
{ X86_FP0, X86_REG_FP0 },
{ X86_FP1, X86_REG_FP1 },
{ X86_FP2, X86_REG_FP2 },
{ X86_FP3, X86_REG_FP3 },
{ X86_FP4, X86_REG_FP4 },
{ X86_FP5, X86_REG_FP5 },
{ X86_FP6, X86_REG_FP6 },
{ X86_FP7, X86_REG_FP7 },
{ X86_K0, X86_REG_K0 },
{ X86_K1, X86_REG_K1 },
{ X86_K2, X86_REG_K2 },
{ X86_K3, X86_REG_K3 },
{ X86_K4, X86_REG_K4 },
{ X86_K5, X86_REG_K5 },
{ X86_K6, X86_REG_K6 },
{ X86_K7, X86_REG_K7 },
{ X86_MM0, X86_REG_MM0 },
{ X86_MM1, X86_REG_MM1 },
{ X86_MM2, X86_REG_MM2 },
{ X86_MM3, X86_REG_MM3 },
{ X86_MM4, X86_REG_MM4 },
{ X86_MM5, X86_REG_MM5 },
{ X86_MM6, X86_REG_MM6 },
{ X86_MM7, X86_REG_MM7 },
{ X86_R8, X86_REG_R8 },
{ X86_R9, X86_REG_R9 },
{ X86_R10, X86_REG_R10 },
{ X86_R11, X86_REG_R11 },
{ X86_R12, X86_REG_R12 },
{ X86_R13, X86_REG_R13 },
{ X86_R14, X86_REG_R14 },
{ X86_R15, X86_REG_R15 },
{ X86_ST0, X86_REG_ST0 },
{ X86_ST1, X86_REG_ST1 },
{ X86_ST2, X86_REG_ST2 },
{ X86_ST3, X86_REG_ST3 },
{ X86_ST4, X86_REG_ST4 },
{ X86_ST5, X86_REG_ST5 },
{ X86_ST6, X86_REG_ST6 },
{ X86_ST7, X86_REG_ST7 },
{ X86_XMM0, X86_REG_XMM0 },
{ X86_XMM1, X86_REG_XMM1 },
{ X86_XMM2, X86_REG_XMM2 },
{ X86_XMM3, X86_REG_XMM3 },
{ X86_XMM4, X86_REG_XMM4 },
{ X86_XMM5, X86_REG_XMM5 },
{ X86_XMM6, X86_REG_XMM6 },
{ X86_XMM7, X86_REG_XMM7 },
{ X86_XMM8, X86_REG_XMM8 },
{ X86_XMM9, X86_REG_XMM9 },
{ X86_XMM10, X86_REG_XMM10 },
{ X86_XMM11, X86_REG_XMM11 },
{ X86_XMM12, X86_REG_XMM12 },
{ X86_XMM13, X86_REG_XMM13 },
{ X86_XMM14, X86_REG_XMM14 },
{ X86_XMM15, X86_REG_XMM15 },
{ X86_XMM16, X86_REG_XMM16 },
{ X86_XMM17, X86_REG_XMM17 },
{ X86_XMM18, X86_REG_XMM18 },
{ X86_XMM19, X86_REG_XMM19 },
{ X86_XMM20, X86_REG_XMM20 },
{ X86_XMM21, X86_REG_XMM21 },
{ X86_XMM22, X86_REG_XMM22 },
{ X86_XMM23, X86_REG_XMM23 },
{ X86_XMM24, X86_REG_XMM24 },
{ X86_XMM25, X86_REG_XMM25 },
{ X86_XMM26, X86_REG_XMM26 },
{ X86_XMM27, X86_REG_XMM27 },
{ X86_XMM28, X86_REG_XMM28 },
{ X86_XMM29, X86_REG_XMM29 },
{ X86_XMM30, X86_REG_XMM30 },
{ X86_XMM31, X86_REG_XMM31 },
{ X86_YMM0, X86_REG_YMM0 },
{ X86_YMM1, X86_REG_YMM1 },
{ X86_YMM2, X86_REG_YMM2 },
{ X86_YMM3, X86_REG_YMM3 },
{ X86_YMM4, X86_REG_YMM4 },
{ X86_YMM5, X86_REG_YMM5 },
{ X86_YMM6, X86_REG_YMM6 },
{ X86_YMM7, X86_REG_YMM7 },
{ X86_YMM8, X86_REG_YMM8 },
{ X86_YMM9, X86_REG_YMM9 },
{ X86_YMM10, X86_REG_YMM10 },
{ X86_YMM11, X86_REG_YMM11 },
{ X86_YMM12, X86_REG_YMM12 },
{ X86_YMM13, X86_REG_YMM13 },
{ X86_YMM14, X86_REG_YMM14 },
{ X86_YMM15, X86_REG_YMM15 },
{ X86_YMM16, X86_REG_YMM16 },
{ X86_YMM17, X86_REG_YMM17 },
{ X86_YMM18, X86_REG_YMM18 },
{ X86_YMM19, X86_REG_YMM19 },
{ X86_YMM20, X86_REG_YMM20 },
{ X86_YMM21, X86_REG_YMM21 },
{ X86_YMM22, X86_REG_YMM22 },
{ X86_YMM23, X86_REG_YMM23 },
{ X86_YMM24, X86_REG_YMM24 },
{ X86_YMM25, X86_REG_YMM25 },
{ X86_YMM26, X86_REG_YMM26 },
{ X86_YMM27, X86_REG_YMM27 },
{ X86_YMM28, X86_REG_YMM28 },
{ X86_YMM29, X86_REG_YMM29 },
{ X86_YMM30, X86_REG_YMM30 },
{ X86_YMM31, X86_REG_YMM31 },
{ X86_ZMM0, X86_REG_ZMM0 },
{ X86_ZMM1, X86_REG_ZMM1 },
{ X86_ZMM2, X86_REG_ZMM2 },
{ X86_ZMM3, X86_REG_ZMM3 },
{ X86_ZMM4, X86_REG_ZMM4 },
{ X86_ZMM5, X86_REG_ZMM5 },
{ X86_ZMM6, X86_REG_ZMM6 },
{ X86_ZMM7, X86_REG_ZMM7 },
{ X86_ZMM8, X86_REG_ZMM8 },
{ X86_ZMM9, X86_REG_ZMM9 },
{ X86_ZMM10, X86_REG_ZMM10 },
{ X86_ZMM11, X86_REG_ZMM11 },
{ X86_ZMM12, X86_REG_ZMM12 },
{ X86_ZMM13, X86_REG_ZMM13 },
{ X86_ZMM14, X86_REG_ZMM14 },
{ X86_ZMM15, X86_REG_ZMM15 },
{ X86_ZMM16, X86_REG_ZMM16 },
{ X86_ZMM17, X86_REG_ZMM17 },
{ X86_ZMM18, X86_REG_ZMM18 },
{ X86_ZMM19, X86_REG_ZMM19 },
{ X86_ZMM20, X86_REG_ZMM20 },
{ X86_ZMM21, X86_REG_ZMM21 },
{ X86_ZMM22, X86_REG_ZMM22 },
{ X86_ZMM23, X86_REG_ZMM23 },
{ X86_ZMM24, X86_REG_ZMM24 },
{ X86_ZMM25, X86_REG_ZMM25 },
{ X86_ZMM26, X86_REG_ZMM26 },
{ X86_ZMM27, X86_REG_ZMM27 },
{ X86_ZMM28, X86_REG_ZMM28 },
{ X86_ZMM29, X86_REG_ZMM29 },
{ X86_ZMM30, X86_REG_ZMM30 },
{ X86_ZMM31, X86_REG_ZMM31 },
{ X86_R8B, X86_REG_R8B },
{ X86_R9B, X86_REG_R9B },
{ X86_R10B, X86_REG_R10B },
{ X86_R11B, X86_REG_R11B },
{ X86_R12B, X86_REG_R12B },
{ X86_R13B, X86_REG_R13B },
{ X86_R14B, X86_REG_R14B },
{ X86_R15B, X86_REG_R15B },
{ X86_R8BH, 0 },
{ X86_R9BH, 0 },
{ X86_R10BH, 0 },
{ X86_R11BH, 0 },
{ X86_R12BH, 0 },
{ X86_R13BH, 0 },
{ X86_R14BH, 0 },
{ X86_R15BH, 0 },
{ X86_R8D, X86_REG_R8D },
{ X86_R9D, X86_REG_R9D },
{ X86_R10D, X86_REG_R10D },
{ X86_R11D, X86_REG_R11D },
{ X86_R12D, X86_REG_R12D },
{ X86_R13D, X86_REG_R13D },
{ X86_R14D, X86_REG_R14D },
{ X86_R15D, X86_REG_R15D },
{ X86_R8W, X86_REG_R8W },
{ X86_R9W, X86_REG_R9W },
{ X86_R10W, X86_REG_R10W },
{ X86_R11W, X86_REG_R11W },
{ X86_R12W, X86_REG_R12W },
{ X86_R13W, X86_REG_R13W },
{ X86_R14W, X86_REG_R14W },
{ X86_R15W, X86_REG_R15W },
{ X86_R8WH, 0 },
{ X86_R9WH, 0 },
{ X86_R10WH, 0 },
{ X86_R11WH, 0 },
{ X86_R12WH, 0 },
{ X86_R13WH, 0 },
{ X86_R14WH, 0 },
{ X86_R15WH, 0 },

94
thirdparty/capstone/arch/X86/X86Module.c vendored Normal file
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/* Capstone Disassembly Engine */
/* By Dang Hoang Vu <danghvu@gmail.com> 2013 */
#ifdef CAPSTONE_HAS_X86
#include "../../cs_priv.h"
#include "../../MCRegisterInfo.h"
#include "X86Disassembler.h"
#include "X86InstPrinter.h"
#include "X86Mapping.h"
#include "X86Module.h"
cs_err X86_global_init(cs_struct *ud)
{
MCRegisterInfo *mri;
mri = cs_mem_malloc(sizeof(*mri));
X86_init(mri);
// by default, we use Intel syntax
ud->printer = X86_Intel_printInst;
ud->syntax = CS_OPT_SYNTAX_INTEL;
ud->printer_info = mri;
ud->disasm = X86_getInstruction;
ud->reg_name = X86_reg_name;
ud->insn_id = X86_get_insn_id;
ud->insn_name = X86_insn_name;
ud->group_name = X86_group_name;
ud->post_printer = X86_postprinter;
#ifndef CAPSTONE_DIET
ud->reg_access = X86_reg_access;
#endif
if (ud->mode == CS_MODE_64)
ud->regsize_map = regsize_map_64;
else
ud->regsize_map = regsize_map_32;
return CS_ERR_OK;
}
cs_err X86_option(cs_struct *handle, cs_opt_type type, size_t value)
{
switch(type) {
default:
break;
case CS_OPT_MODE:
if (value == CS_MODE_64)
handle->regsize_map = regsize_map_64;
else
handle->regsize_map = regsize_map_32;
handle->mode = (cs_mode)value;
break;
case CS_OPT_SYNTAX:
switch(value) {
default:
// wrong syntax value
handle->errnum = CS_ERR_OPTION;
return CS_ERR_OPTION;
case CS_OPT_SYNTAX_DEFAULT:
case CS_OPT_SYNTAX_INTEL:
handle->syntax = CS_OPT_SYNTAX_INTEL;
handle->printer = X86_Intel_printInst;
break;
case CS_OPT_SYNTAX_MASM:
handle->printer = X86_Intel_printInst;
handle->syntax = (int)value;
break;
case CS_OPT_SYNTAX_ATT:
#if !defined(CAPSTONE_DIET) && !defined(CAPSTONE_X86_ATT_DISABLE)
handle->printer = X86_ATT_printInst;
handle->syntax = CS_OPT_SYNTAX_ATT;
break;
#elif !defined(CAPSTONE_DIET) && defined(CAPSTONE_X86_ATT_DISABLE)
// ATT syntax is unsupported
handle->errnum = CS_ERR_X86_ATT;
return CS_ERR_X86_ATT;
#else // CAPSTONE_DIET
// this is irrelevant in CAPSTONE_DIET mode
handle->errnum = CS_ERR_DIET;
return CS_ERR_DIET;
#endif
}
break;
}
return CS_ERR_OK;
}
#endif

12
thirdparty/capstone/arch/X86/X86Module.h vendored Normal file
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/* Capstone Disassembly Engine */
/* By Travis Finkenauer <tmfinken@gmail.com>, 2018 */
#ifndef CS_X86_MODULE_H
#define CS_X86_MODULE_H
#include "../../utils.h"
cs_err X86_global_init(cs_struct *ud);
cs_err X86_option(cs_struct *handle, cs_opt_type type, size_t value);
#endif