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https://github.com/hedge-dev/XenonRecomp.git
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Implement bitwise rotation instructions.
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8
thirdparty/disasm/ppc-dis.c
vendored
8
thirdparty/disasm/ppc-dis.c
vendored
@@ -2234,10 +2234,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MACLHWUO },
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{ "mulchw", XRC(4,168,0), X_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MULCHW },
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{ "mulchw.", XRC(4,168,1), X_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MULCHW },
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{ "mulchwu", XRC(4,136,0), X_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MULCHWU },
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{ "mulchwu.", XRC(4,136,1), X_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MULCHWU },
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{ "mulhhw", XRC(4,40,0), X_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MULHHW },
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{ "mulhhw.", XRC(4,40,1), X_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MULHHW },
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//{ "mulchwu", XRC(4,136,0), X_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MULCHWU },
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//{ "mulchwu.", XRC(4,136,1), X_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MULCHWU },
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//{ "mulhhw", XRC(4,40,0), X_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MULHHW },
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//{ "mulhhw.", XRC(4,40,1), X_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MULHHW },
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{ "mulhhwu", XRC(4,8,0), X_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MULHHWU },
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{ "mulhhwu.", XRC(4,8,1), X_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MULHHWU },
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{ "mullhw", XRC(4,424,0), X_MASK, PPC405 | PPC440, { RT, RA, RB }, PPC_INST_MULLHW },
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