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Implement even more vector instructions & add missing ones.

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Skyth
2024-09-16 16:03:23 +03:00
parent 3a887e6e2c
commit ee4cab12b8
4 changed files with 74 additions and 8 deletions
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6
thirdparty/disasm/ppc-dis.c vendored
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@@ -1825,10 +1825,10 @@ extract_vperm (unsigned long insn,
#define VXR_MASK VXR(0x3f, 0x3ff, 1)
/* An VX128 form instruction. */
#define VX128(op, xop) (OP(op) | (((unsigned long)(xop)) & 0x3d0))
#define VX128(op, xop) (OP(op) | (((unsigned long)(xop)) & 0x7d0))
/* The mask for an VX form instruction. */
#define VX128_MASK VX(0x3f, 0x3d0)
#define VX128_MASK VX(0x3f, 0x7d0)
/* An VX128 form instruction. */
#define VX128_1(op, xop) (OP(op) | (((unsigned long)(xop)) & 0x7f3))
@@ -2543,6 +2543,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{ "vmrglw128", VX128(6, 832), VX128_MASK, PPCVEC128, { VD128, VA128, VB128 }, PPC_INST_VMRGLW128 },
{ "vupkhsb128", VX128(6, 896), VX128_MASK, PPCVEC128, { VD128, VB128 }, PPC_INST_VUPKHSB128 },
{ "vupklsb128", VX128(6, 960), VX128_MASK, PPCVEC128, { VD128, VB128 }, PPC_INST_VUPKLSB128 },
{ "vupkhsh128", VX128(6, 1952), VX128_MASK, PPCVEC128, { VD128, VB128 }, PPC_INST_VUPKHSH128 },
{ "vupklsh128", VX128(6, 2016), VX128_MASK, PPCVEC128, { VD128, VB128 }, PPC_INST_VUPKLSH128 },
{ "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB }, PPC_INST_EVADDW },

2
thirdparty/disasm/ppc-inst.h vendored
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@@ -1844,3 +1844,5 @@
#define PPC_INST_DENBCDQ 1842
#define PPC_INST_FCFID 1843
#define PPC_INST_DIEXQ 1844
#define PPC_INST_VUPKHSH128 1845
#define PPC_INST_VUPKLSH128 1846