mirror of
https://github.com/hedge-dev/XenonRecomp.git
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426 lines
12 KiB
C
426 lines
12 KiB
C
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|* *|
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|* Target Register Enum Values *|
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|* *|
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|* Automatically generated file, do not edit! *|
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|* *|
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\*===----------------------------------------------------------------------===*/
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/* Capstone Disassembly Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
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#ifdef GET_REGINFO_ENUM
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#undef GET_REGINFO_ENUM
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enum {
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RISCV_NoRegister,
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RISCV_X0 = 1,
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RISCV_X1 = 2,
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RISCV_X2 = 3,
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RISCV_X3 = 4,
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RISCV_X4 = 5,
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RISCV_X5 = 6,
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RISCV_X6 = 7,
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RISCV_X7 = 8,
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RISCV_X8 = 9,
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RISCV_X9 = 10,
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RISCV_X10 = 11,
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RISCV_X11 = 12,
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RISCV_X12 = 13,
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RISCV_X13 = 14,
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RISCV_X14 = 15,
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RISCV_X15 = 16,
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RISCV_X16 = 17,
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RISCV_X17 = 18,
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RISCV_X18 = 19,
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RISCV_X19 = 20,
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RISCV_X20 = 21,
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RISCV_X21 = 22,
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RISCV_X22 = 23,
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RISCV_X23 = 24,
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RISCV_X24 = 25,
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RISCV_X25 = 26,
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RISCV_X26 = 27,
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RISCV_X27 = 28,
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RISCV_X28 = 29,
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RISCV_X29 = 30,
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RISCV_X30 = 31,
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RISCV_X31 = 32,
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RISCV_F0_32 = 33,
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RISCV_F0_64 = 34,
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RISCV_F1_32 = 35,
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RISCV_F1_64 = 36,
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RISCV_F2_32 = 37,
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RISCV_F2_64 = 38,
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RISCV_F3_32 = 39,
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RISCV_F3_64 = 40,
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RISCV_F4_32 = 41,
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RISCV_F4_64 = 42,
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RISCV_F5_32 = 43,
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RISCV_F5_64 = 44,
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RISCV_F6_32 = 45,
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RISCV_F6_64 = 46,
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RISCV_F7_32 = 47,
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RISCV_F7_64 = 48,
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RISCV_F8_32 = 49,
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RISCV_F8_64 = 50,
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RISCV_F9_32 = 51,
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RISCV_F9_64 = 52,
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RISCV_F10_32 = 53,
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RISCV_F10_64 = 54,
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RISCV_F11_32 = 55,
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RISCV_F11_64 = 56,
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RISCV_F12_32 = 57,
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RISCV_F12_64 = 58,
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RISCV_F13_32 = 59,
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RISCV_F13_64 = 60,
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RISCV_F14_32 = 61,
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RISCV_F14_64 = 62,
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RISCV_F15_32 = 63,
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RISCV_F15_64 = 64,
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RISCV_F16_32 = 65,
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RISCV_F16_64 = 66,
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RISCV_F17_32 = 67,
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RISCV_F17_64 = 68,
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RISCV_F18_32 = 69,
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RISCV_F18_64 = 70,
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RISCV_F19_32 = 71,
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RISCV_F19_64 = 72,
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RISCV_F20_32 = 73,
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RISCV_F20_64 = 74,
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RISCV_F21_32 = 75,
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RISCV_F21_64 = 76,
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RISCV_F22_32 = 77,
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RISCV_F22_64 = 78,
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RISCV_F23_32 = 79,
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RISCV_F23_64 = 80,
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RISCV_F24_32 = 81,
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RISCV_F24_64 = 82,
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RISCV_F25_32 = 83,
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RISCV_F25_64 = 84,
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RISCV_F26_32 = 85,
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RISCV_F26_64 = 86,
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RISCV_F27_32 = 87,
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RISCV_F27_64 = 88,
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RISCV_F28_32 = 89,
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RISCV_F28_64 = 90,
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RISCV_F29_32 = 91,
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RISCV_F29_64 = 92,
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RISCV_F30_32 = 93,
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RISCV_F30_64 = 94,
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RISCV_F31_32 = 95,
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RISCV_F31_64 = 96,
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RISCV_NUM_TARGET_REGS // 97
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};
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// Register classes
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enum {
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RISCV_FPR32RegClassID = 0,
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RISCV_GPRRegClassID = 1,
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RISCV_GPRNoX0RegClassID = 2,
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RISCV_GPRNoX0X2RegClassID = 3,
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RISCV_GPRTCRegClassID = 4,
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RISCV_FPR32CRegClassID = 5,
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RISCV_GPRCRegClassID = 6,
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RISCV_GPRC_and_GPRTCRegClassID = 7,
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RISCV_SPRegClassID = 8,
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RISCV_FPR64RegClassID = 9,
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RISCV_FPR64CRegClassID = 10,
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};
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// Register alternate name indices
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enum {
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RISCV_ABIRegAltName, // 0
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RISCV_NoRegAltName, // 1
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RISCV_NUM_TARGET_REG_ALT_NAMES = 2
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};
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// Subregister indices
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enum {
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RISCV_NoSubRegister,
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RISCV_sub_32, // 1
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RISCV_NUM_TARGET_SUBREGS
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};
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#endif // GET_REGINFO_ENUM
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|* *|
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|* MC Register Information *|
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|* *|
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|* Automatically generated file, do not edit! *|
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|* *|
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\*===----------------------------------------------------------------------===*/
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#ifdef GET_REGINFO_MC_DESC
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#undef GET_REGINFO_MC_DESC
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static const MCPhysReg RISCVRegDiffLists[] = {
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/* 0 */ 1, 0,
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/* 2 */ 32, 0,
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/* 4 */ 33, 0,
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/* 6 */ 34, 0,
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/* 8 */ 35, 0,
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/* 10 */ 36, 0,
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/* 12 */ 37, 0,
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/* 14 */ 38, 0,
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/* 16 */ 39, 0,
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/* 18 */ 40, 0,
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/* 20 */ 41, 0,
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/* 22 */ 42, 0,
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/* 24 */ 43, 0,
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/* 26 */ 44, 0,
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/* 28 */ 45, 0,
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/* 30 */ 46, 0,
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/* 32 */ 47, 0,
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/* 34 */ 48, 0,
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/* 36 */ 49, 0,
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/* 38 */ 50, 0,
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/* 40 */ 51, 0,
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/* 42 */ 52, 0,
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/* 44 */ 53, 0,
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/* 46 */ 54, 0,
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/* 48 */ 55, 0,
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/* 50 */ 56, 0,
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/* 52 */ 57, 0,
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/* 54 */ 58, 0,
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/* 56 */ 59, 0,
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/* 58 */ 60, 0,
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/* 60 */ 61, 0,
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/* 62 */ 62, 0,
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/* 64 */ 63, 0,
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/* 66 */ -1, 0,
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};
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static const uint16_t RISCVSubRegIdxLists[] = {
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/* 0 */ 1, 0,
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};
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static const MCRegisterDesc RISCVRegDesc[] = { // Descriptors
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{ 3, 0, 0, 0, 0, 0 },
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{ 12, 1, 1, 1, 1057, 0 },
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{ 27, 1, 1, 1, 1057, 0 },
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{ 252, 1, 1, 1, 1057, 0 },
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{ 263, 1, 1, 1, 1057, 0 },
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{ 488, 1, 1, 1, 1057, 0 },
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{ 499, 1, 1, 1, 1057, 0 },
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{ 510, 1, 1, 1, 1057, 0 },
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{ 521, 1, 1, 1, 1057, 0 },
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{ 532, 1, 1, 1, 1057, 0 },
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{ 543, 1, 1, 1, 1057, 0 },
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{ 0, 1, 1, 1, 1057, 0 },
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{ 15, 1, 1, 1, 1057, 0 },
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{ 30, 1, 1, 1, 1057, 0 },
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{ 255, 1, 1, 1, 1057, 0 },
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{ 266, 1, 1, 1, 1057, 0 },
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{ 491, 1, 1, 1, 1057, 0 },
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{ 502, 1, 1, 1, 1057, 0 },
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{ 513, 1, 1, 1, 1057, 0 },
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{ 524, 1, 1, 1, 1057, 0 },
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{ 535, 1, 1, 1, 1057, 0 },
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{ 4, 1, 1, 1, 1057, 0 },
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{ 19, 1, 1, 1, 1057, 0 },
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{ 34, 1, 1, 1, 1057, 0 },
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{ 259, 1, 1, 1, 1057, 0 },
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{ 270, 1, 1, 1, 1057, 0 },
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{ 495, 1, 1, 1, 1057, 0 },
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{ 506, 1, 1, 1, 1057, 0 },
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{ 517, 1, 1, 1, 1057, 0 },
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{ 528, 1, 1, 1, 1057, 0 },
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{ 539, 1, 1, 1, 1057, 0 },
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{ 8, 1, 1, 1, 1057, 0 },
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{ 23, 1, 1, 1, 1057, 0 },
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{ 59, 1, 0, 1, 32, 0 },
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{ 295, 66, 1, 0, 32, 2 },
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{ 86, 1, 0, 1, 64, 0 },
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{ 322, 66, 1, 0, 64, 2 },
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{ 106, 1, 0, 1, 96, 0 },
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{ 342, 66, 1, 0, 96, 2 },
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{ 126, 1, 0, 1, 128, 0 },
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{ 362, 66, 1, 0, 128, 2 },
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{ 146, 1, 0, 1, 160, 0 },
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{ 382, 66, 1, 0, 160, 2 },
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{ 166, 1, 0, 1, 192, 0 },
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{ 402, 66, 1, 0, 192, 2 },
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{ 186, 1, 0, 1, 224, 0 },
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{ 422, 66, 1, 0, 224, 2 },
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{ 206, 1, 0, 1, 256, 0 },
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{ 442, 66, 1, 0, 256, 2 },
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{ 226, 1, 0, 1, 288, 0 },
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{ 462, 66, 1, 0, 288, 2 },
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{ 246, 1, 0, 1, 320, 0 },
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{ 482, 66, 1, 0, 320, 2 },
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{ 38, 1, 0, 1, 352, 0 },
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{ 274, 66, 1, 0, 352, 2 },
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{ 65, 1, 0, 1, 384, 0 },
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{ 301, 66, 1, 0, 384, 2 },
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{ 92, 1, 0, 1, 416, 0 },
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{ 328, 66, 1, 0, 416, 2 },
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{ 112, 1, 0, 1, 448, 0 },
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{ 348, 66, 1, 0, 448, 2 },
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{ 132, 1, 0, 1, 480, 0 },
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{ 368, 66, 1, 0, 480, 2 },
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{ 152, 1, 0, 1, 512, 0 },
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{ 388, 66, 1, 0, 512, 2 },
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{ 172, 1, 0, 1, 544, 0 },
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{ 408, 66, 1, 0, 544, 2 },
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{ 192, 1, 0, 1, 576, 0 },
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{ 428, 66, 1, 0, 576, 2 },
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{ 212, 1, 0, 1, 608, 0 },
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{ 448, 66, 1, 0, 608, 2 },
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{ 232, 1, 0, 1, 640, 0 },
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{ 468, 66, 1, 0, 640, 2 },
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{ 45, 1, 0, 1, 672, 0 },
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{ 281, 66, 1, 0, 672, 2 },
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{ 72, 1, 0, 1, 704, 0 },
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{ 308, 66, 1, 0, 704, 2 },
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{ 99, 1, 0, 1, 736, 0 },
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{ 335, 66, 1, 0, 736, 2 },
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{ 119, 1, 0, 1, 768, 0 },
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{ 355, 66, 1, 0, 768, 2 },
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{ 139, 1, 0, 1, 800, 0 },
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{ 375, 66, 1, 0, 800, 2 },
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{ 159, 1, 0, 1, 832, 0 },
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{ 395, 66, 1, 0, 832, 2 },
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{ 179, 1, 0, 1, 864, 0 },
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{ 415, 66, 1, 0, 864, 2 },
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{ 199, 1, 0, 1, 896, 0 },
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{ 435, 66, 1, 0, 896, 2 },
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{ 219, 1, 0, 1, 928, 0 },
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{ 455, 66, 1, 0, 928, 2 },
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{ 239, 1, 0, 1, 960, 0 },
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{ 475, 66, 1, 0, 960, 2 },
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{ 52, 1, 0, 1, 992, 0 },
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{ 288, 66, 1, 0, 992, 2 },
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{ 79, 1, 0, 1, 1024, 0 },
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{ 315, 66, 1, 0, 1024, 2 },
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};
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// FPR32 Register Class...
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static const MCPhysReg FPR32[] = {
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RISCV_F0_32, RISCV_F1_32, RISCV_F2_32, RISCV_F3_32, RISCV_F4_32, RISCV_F5_32, RISCV_F6_32, RISCV_F7_32, RISCV_F10_32, RISCV_F11_32, RISCV_F12_32, RISCV_F13_32, RISCV_F14_32, RISCV_F15_32, RISCV_F16_32, RISCV_F17_32, RISCV_F28_32, RISCV_F29_32, RISCV_F30_32, RISCV_F31_32, RISCV_F8_32, RISCV_F9_32, RISCV_F18_32, RISCV_F19_32, RISCV_F20_32, RISCV_F21_32, RISCV_F22_32, RISCV_F23_32, RISCV_F24_32, RISCV_F25_32, RISCV_F26_32, RISCV_F27_32,
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};
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// FPR32 Bit set.
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static const uint8_t FPR32Bits[] = {
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0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
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};
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// GPR Register Class...
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static const MCPhysReg GPR[] = {
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RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, RISCV_X16, RISCV_X17, RISCV_X5, RISCV_X6, RISCV_X7, RISCV_X28, RISCV_X29, RISCV_X30, RISCV_X31, RISCV_X8, RISCV_X9, RISCV_X18, RISCV_X19, RISCV_X20, RISCV_X21, RISCV_X22, RISCV_X23, RISCV_X24, RISCV_X25, RISCV_X26, RISCV_X27, RISCV_X0, RISCV_X1, RISCV_X2, RISCV_X3, RISCV_X4,
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};
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// GPR Bit set.
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static const uint8_t GPRBits[] = {
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0xfe, 0xff, 0xff, 0xff, 0x01,
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};
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// GPRNoX0 Register Class...
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static const MCPhysReg GPRNoX0[] = {
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RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, RISCV_X16, RISCV_X17, RISCV_X5, RISCV_X6, RISCV_X7, RISCV_X28, RISCV_X29, RISCV_X30, RISCV_X31, RISCV_X8, RISCV_X9, RISCV_X18, RISCV_X19, RISCV_X20, RISCV_X21, RISCV_X22, RISCV_X23, RISCV_X24, RISCV_X25, RISCV_X26, RISCV_X27, RISCV_X1, RISCV_X2, RISCV_X3, RISCV_X4,
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};
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// GPRNoX0 Bit set.
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static const uint8_t GPRNoX0Bits[] = {
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0xfc, 0xff, 0xff, 0xff, 0x01,
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};
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// GPRNoX0X2 Register Class...
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static const MCPhysReg GPRNoX0X2[] = {
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RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, RISCV_X16, RISCV_X17, RISCV_X5, RISCV_X6, RISCV_X7, RISCV_X28, RISCV_X29, RISCV_X30, RISCV_X31, RISCV_X8, RISCV_X9, RISCV_X18, RISCV_X19, RISCV_X20, RISCV_X21, RISCV_X22, RISCV_X23, RISCV_X24, RISCV_X25, RISCV_X26, RISCV_X27, RISCV_X1, RISCV_X3, RISCV_X4,
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};
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// GPRNoX0X2 Bit set.
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static const uint8_t GPRNoX0X2Bits[] = {
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0xf4, 0xff, 0xff, 0xff, 0x01,
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};
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// GPRTC Register Class...
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static const MCPhysReg GPRTC[] = {
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RISCV_X5, RISCV_X6, RISCV_X7, RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, RISCV_X16, RISCV_X17, RISCV_X28, RISCV_X29, RISCV_X30, RISCV_X31,
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};
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// GPRTC Bit set.
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static const uint8_t GPRTCBits[] = {
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0xc0, 0xf9, 0x07, 0xe0, 0x01,
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};
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// FPR32C Register Class...
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static const MCPhysReg FPR32C[] = {
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RISCV_F10_32, RISCV_F11_32, RISCV_F12_32, RISCV_F13_32, RISCV_F14_32, RISCV_F15_32, RISCV_F8_32, RISCV_F9_32,
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};
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// FPR32C Bit set.
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static const uint8_t FPR32CBits[] = {
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa,
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};
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// GPRC Register Class...
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static const MCPhysReg GPRC[] = {
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RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, RISCV_X8, RISCV_X9,
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};
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// GPRC Bit set.
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static const uint8_t GPRCBits[] = {
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0x00, 0xfe, 0x01,
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};
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// GPRC_and_GPRTC Register Class...
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static const MCPhysReg GPRC_and_GPRTC[] = {
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RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15,
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};
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// GPRC_and_GPRTC Bit set.
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static const uint8_t GPRC_and_GPRTCBits[] = {
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0x00, 0xf8, 0x01,
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};
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// SP Register Class...
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static const MCPhysReg SP[] = {
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RISCV_X2,
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};
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// SP Bit set.
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static const uint8_t SPBits[] = {
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0x08,
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};
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// FPR64 Register Class...
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static const MCPhysReg FPR64[] = {
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RISCV_F0_64, RISCV_F1_64, RISCV_F2_64, RISCV_F3_64, RISCV_F4_64, RISCV_F5_64, RISCV_F6_64, RISCV_F7_64, RISCV_F10_64, RISCV_F11_64, RISCV_F12_64, RISCV_F13_64, RISCV_F14_64, RISCV_F15_64, RISCV_F16_64, RISCV_F17_64, RISCV_F28_64, RISCV_F29_64, RISCV_F30_64, RISCV_F31_64, RISCV_F8_64, RISCV_F9_64, RISCV_F18_64, RISCV_F19_64, RISCV_F20_64, RISCV_F21_64, RISCV_F22_64, RISCV_F23_64, RISCV_F24_64, RISCV_F25_64, RISCV_F26_64, RISCV_F27_64,
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};
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// FPR64 Bit set.
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static const uint8_t FPR64Bits[] = {
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0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x01,
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};
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// FPR64C Register Class...
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static const MCPhysReg FPR64C[] = {
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RISCV_F10_64, RISCV_F11_64, RISCV_F12_64, RISCV_F13_64, RISCV_F14_64, RISCV_F15_64, RISCV_F8_64, RISCV_F9_64,
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};
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// FPR64C Bit set.
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static const uint8_t FPR64CBits[] = {
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x01,
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};
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static const MCRegisterClass RISCVMCRegisterClasses[] = {
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{ FPR32, FPR32Bits, sizeof(FPR32Bits) },
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{ GPR, GPRBits, sizeof(GPRBits) },
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{ GPRNoX0, GPRNoX0Bits, sizeof(GPRNoX0Bits) },
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{ GPRNoX0X2, GPRNoX0X2Bits, sizeof(GPRNoX0X2Bits) },
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{ GPRTC, GPRTCBits, sizeof(GPRTCBits) },
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{ FPR32C, FPR32CBits, sizeof(FPR32CBits) },
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{ GPRC, GPRCBits, sizeof(GPRCBits) },
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{ GPRC_and_GPRTC, GPRC_and_GPRTCBits, sizeof(GPRC_and_GPRTCBits) },
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{ SP, SPBits, sizeof(SPBits) },
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{ FPR64, FPR64Bits, sizeof(FPR64Bits) },
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{ FPR64C, FPR64CBits, sizeof(FPR64CBits) },
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};
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#endif // GET_REGINFO_MC_DESC
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