Initial Commit

thirdparty/capstone/arch/PowerPC/PPCDisassembler.c

@@ -0,0 +1,532 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically translated source file from LLVM. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Only small edits allowed. */
+/* For multiple similar edits, please create a Patch for the translator. */
+
+/* Capstone's C++ file translator: */
+/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
+
+//===------ PPCDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include <capstone/platform.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "../../LEB128.h"
+#include "../../MCDisassembler.h"
+#include "../../MCFixedLenDisassembler.h"
+#include "../../MCInst.h"
+#include "../../MCInstPrinter.h"
+#include "../../MCInstrDesc.h"
+#include "../../MCRegisterInfo.h"
+#include "../../SStream.h"
+#include "../../utils.h"
+#include "PPCLinkage.h"
+#include "PPCMapping.h"
+#include "PPCMCTargetDesc.h"
+#include "PPCPredicates.h"
+
+#define CONCAT(a, b) CONCAT_(a, b)
+#define CONCAT_(a, b) a##_##b
+
+DEFINE_PPC_REGCLASSES
+
+#define DEBUG_TYPE "ppc-disassembler"
+
+DecodeStatus getInstruction(csh ud, const uint8_t *Bytes, size_t BytesLen,
+			    MCInst *MI, uint16_t *Size, uint64_t Address,
+			    void *Info);
+// end anonymous namespace
+
+static DecodeStatus decodeCondBrTarget(MCInst *Inst, unsigned Imm,
+				       uint64_t Address, const void *Decoder)
+{
+	MCOperand_CreateImm0(Inst, (SignExtend32((Imm), 14)));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus decodeDirectBrTarget(MCInst *Inst, unsigned Imm,
+					 uint64_t Address, const void *Decoder)
+{
+	int32_t Offset = SignExtend32((Imm), 24);
+	MCOperand_CreateImm0(Inst, (Offset));
+	return MCDisassembler_Success;
+}
+
+// FIXME: These can be generated by TableGen from the existing register
+// encoding values!
+
+static DecodeStatus decodeRegisterClass(MCInst *Inst, uint64_t RegNo,
+					const MCPhysReg *Regs)
+{
+	MCOperand_CreateReg0(Inst, (Regs[RegNo]));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeCRRCRegisterClass(MCInst *Inst, uint64_t RegNo,
+					    uint64_t Address,
+					    const void *Decoder)
+{
+	return decodeRegisterClass(Inst, RegNo, CRRegs);
+}
+
+static DecodeStatus DecodeCRBITRCRegisterClass(MCInst *Inst, uint64_t RegNo,
+					       uint64_t Address,
+					       const void *Decoder)
+{
+	return decodeRegisterClass(Inst, RegNo, CRBITRegs);
+}
+
+static DecodeStatus DecodeF4RCRegisterClass(MCInst *Inst, uint64_t RegNo,
+					    uint64_t Address,
+					    const void *Decoder)
+{
+	return decodeRegisterClass(Inst, RegNo, FRegs);
+}
+
+static DecodeStatus DecodeF8RCRegisterClass(MCInst *Inst, uint64_t RegNo,
+					    uint64_t Address,
+					    const void *Decoder)
+{
+	return decodeRegisterClass(Inst, RegNo, FRegs);
+}
+
+static DecodeStatus DecodeVFRCRegisterClass(MCInst *Inst, uint64_t RegNo,
+					    uint64_t Address,
+					    const void *Decoder)
+{
+	return decodeRegisterClass(Inst, RegNo, VFRegs);
+}
+
+static DecodeStatus DecodeVRRCRegisterClass(MCInst *Inst, uint64_t RegNo,
+					    uint64_t Address,
+					    const void *Decoder)
+{
+	return decodeRegisterClass(Inst, RegNo, VRegs);
+}
+
+static DecodeStatus DecodeVSRCRegisterClass(MCInst *Inst, uint64_t RegNo,
+					    uint64_t Address,
+					    const void *Decoder)
+{
+	return decodeRegisterClass(Inst, RegNo, VSRegs);
+}
+
+static DecodeStatus DecodeVSFRCRegisterClass(MCInst *Inst, uint64_t RegNo,
+					     uint64_t Address,
+					     const void *Decoder)
+{
+	return decodeRegisterClass(Inst, RegNo, VSFRegs);
+}
+
+static DecodeStatus DecodeVSSRCRegisterClass(MCInst *Inst, uint64_t RegNo,
+					     uint64_t Address,
+					     const void *Decoder)
+{
+	return decodeRegisterClass(Inst, RegNo, VSSRegs);
+}
+
+static DecodeStatus DecodeGPRCRegisterClass(MCInst *Inst, uint64_t RegNo,
+					    uint64_t Address,
+					    const void *Decoder)
+{
+	return decodeRegisterClass(Inst, RegNo, RRegs);
+}
+
+static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst *Inst, uint64_t RegNo,
+						 uint64_t Address,
+						 const void *Decoder)
+{
+	return decodeRegisterClass(Inst, RegNo, RRegsNoR0);
+}
+
+static DecodeStatus DecodeG8RCRegisterClass(MCInst *Inst, uint64_t RegNo,
+					    uint64_t Address,
+					    const void *Decoder)
+{
+	return decodeRegisterClass(Inst, RegNo, XRegs);
+}
+
+static DecodeStatus DecodeG8pRCRegisterClass(MCInst *Inst, uint64_t RegNo,
+					     uint64_t Address,
+					     const void *Decoder)
+{
+	return decodeRegisterClass(Inst, RegNo, XRegs);
+}
+
+static DecodeStatus DecodeG8RC_NOX0RegisterClass(MCInst *Inst, uint64_t RegNo,
+						 uint64_t Address,
+						 const void *Decoder)
+{
+	return decodeRegisterClass(Inst, RegNo, XRegsNoX0);
+}
+
+#define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass
+#define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass
+
+static DecodeStatus DecodeSPERCRegisterClass(MCInst *Inst, uint64_t RegNo,
+					     uint64_t Address,
+					     const void *Decoder)
+{
+	return decodeRegisterClass(Inst, RegNo, SPERegs);
+}
+
+static DecodeStatus DecodeACCRCRegisterClass(MCInst *Inst, uint64_t RegNo,
+					     uint64_t Address,
+					     const void *Decoder)
+{
+	return decodeRegisterClass(Inst, RegNo, ACCRegs);
+}
+
+static DecodeStatus DecodeWACCRCRegisterClass(MCInst *Inst, uint64_t RegNo,
+					      uint64_t Address,
+					      const void *Decoder)
+{
+	return decodeRegisterClass(Inst, RegNo, WACCRegs);
+}
+
+static DecodeStatus DecodeWACC_HIRCRegisterClass(MCInst *Inst, uint64_t RegNo,
+						 uint64_t Address,
+						 const void *Decoder)
+{
+	return decodeRegisterClass(Inst, RegNo, WACC_HIRegs);
+}
+
+// TODO: Make this function static when the register class is used by a new
+//       instruction.
+DecodeStatus DecodeDMRROWRCRegisterClass(MCInst *Inst, uint64_t RegNo,
+					 uint64_t Address, const void *Decoder)
+{
+	return decodeRegisterClass(Inst, RegNo, DMRROWRegs);
+}
+
+static DecodeStatus DecodeDMRROWpRCRegisterClass(MCInst *Inst, uint64_t RegNo,
+						 uint64_t Address,
+						 const void *Decoder)
+{
+	return decodeRegisterClass(Inst, RegNo, DMRROWpRegs);
+}
+
+static DecodeStatus DecodeDMRRCRegisterClass(MCInst *Inst, uint64_t RegNo,
+					     uint64_t Address,
+					     const void *Decoder)
+{
+	return decodeRegisterClass(Inst, RegNo, DMRRegs);
+}
+
+// TODO: Make this function static when the register class is used by a new
+//       instruction.
+DecodeStatus DecodeDMRpRCRegisterClass(MCInst *Inst, uint64_t RegNo,
+				       uint64_t Address, const void *Decoder)
+{
+	return decodeRegisterClass(Inst, RegNo, DMRpRegs);
+}
+
+static DecodeStatus DecodeVSRpRCRegisterClass(MCInst *Inst, uint64_t RegNo,
+					      uint64_t Address,
+					      const void *Decoder)
+{
+	return decodeRegisterClass(Inst, RegNo, VSRpRegs);
+}
+
+#define DecodeQSRCRegisterClass DecodeQFRCRegisterClass
+#define DecodeQBRCRegisterClass DecodeQFRCRegisterClass
+
+static DecodeStatus DecodeQFRCRegisterClass(MCInst *Inst, uint64_t RegNo,
+					    uint64_t Address,
+					    const void *Decoder)
+{
+	return decodeRegisterClass(Inst, RegNo, QFRegs);
+}
+
+#define DEFINE_decodeUImmOperand(N) \
+	static DecodeStatus CONCAT(decodeUImmOperand, \
+				   N)(MCInst * Inst, uint64_t Imm, \
+				      int64_t Address, const void *Decoder) \
+	{ \
+		MCOperand_CreateImm0(Inst, (Imm)); \
+		return MCDisassembler_Success; \
+	}
+DEFINE_decodeUImmOperand(5) DEFINE_decodeUImmOperand(16)
+	DEFINE_decodeUImmOperand(6) DEFINE_decodeUImmOperand(10)
+		DEFINE_decodeUImmOperand(8) DEFINE_decodeUImmOperand(7)
+			DEFINE_decodeUImmOperand(12)
+
+#define DEFINE_decodeSImmOperand(N) \
+	static DecodeStatus CONCAT(decodeSImmOperand, \
+				   N)(MCInst * Inst, uint64_t Imm, \
+				      int64_t Address, const void *Decoder) \
+	{ \
+		MCOperand_CreateImm0(Inst, (SignExtend64(Imm, N))); \
+		return MCDisassembler_Success; \
+	}
+				DEFINE_decodeSImmOperand(16)
+					DEFINE_decodeSImmOperand(5)
+						DEFINE_decodeSImmOperand(34)
+
+							static DecodeStatus
+	decodeImmZeroOperand(MCInst *Inst, uint64_t Imm, int64_t Address,
+			     const void *Decoder)
+{
+	if (Imm != 0)
+		return MCDisassembler_Fail;
+	MCOperand_CreateImm0(Inst, (Imm));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus decodeVSRpEvenOperands(MCInst *Inst, uint64_t RegNo,
+					   uint64_t Address,
+					   const void *Decoder)
+{
+	if (RegNo & 1)
+		return MCDisassembler_Fail;
+	MCOperand_CreateReg0(Inst, (VSRpRegs[RegNo >> 1]));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus decodeMemRIOperands(MCInst *Inst, uint64_t Imm,
+					int64_t Address, const void *Decoder)
+{
+	// Decode the memri field (imm, reg), which has the low 16-bits as the
+	// displacement and the next 5 bits as the register #.
+
+	uint64_t Base = Imm >> 16;
+	uint64_t Disp = Imm & 0xFFFF;
+
+	switch (MCInst_getOpcode(Inst)) {
+	default:
+		break;
+	case PPC_LBZU:
+	case PPC_LHAU:
+	case PPC_LHZU:
+	case PPC_LWZU:
+	case PPC_LFSU:
+	case PPC_LFDU:
+		// Add the tied output operand.
+		MCOperand_CreateReg0(Inst, (RRegsNoR0[Base]));
+		break;
+	case PPC_STBU:
+	case PPC_STHU:
+	case PPC_STWU:
+	case PPC_STFSU:
+	case PPC_STFDU:
+		MCInst_insert0(Inst, 0,
+			       MCOperand_CreateReg1(Inst, RRegsNoR0[Base]));
+		break;
+	}
+
+	MCOperand_CreateImm0(Inst, (SignExtend64(Disp, 16)));
+	MCOperand_CreateReg0(Inst, (RRegsNoR0[Base]));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus decodeMemRIXOperands(MCInst *Inst, uint64_t Imm,
+					 int64_t Address, const void *Decoder)
+{
+	// Decode the memrix field (imm, reg), which has the low 14-bits as the
+	// displacement and the next 5 bits as the register #.
+
+	uint64_t Base = Imm >> 14;
+	uint64_t Disp = Imm & 0x3FFF;
+
+	if (MCInst_getOpcode(Inst) == PPC_LDU)
+		// Add the tied output operand.
+		MCOperand_CreateReg0(Inst, (RRegsNoR0[Base]));
+	else if (MCInst_getOpcode(Inst) == PPC_STDU)
+		MCInst_insert0(Inst, 0,
+			       MCOperand_CreateReg1(Inst, RRegsNoR0[Base]));
+
+	MCOperand_CreateImm0(Inst, (SignExtend64(Disp << 2, 16)));
+	MCOperand_CreateReg0(Inst, (RRegsNoR0[Base]));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus decodeMemRIHashOperands(MCInst *Inst, uint64_t Imm,
+					    int64_t Address,
+					    const void *Decoder)
+{
+	// Decode the memrix field for a hash store or hash check operation.
+	// The field is composed of a register and an immediate value that is 6 bits
+	// and covers the range -8 to -512. The immediate is always negative and 2s
+	// complement which is why we sign extend a 7 bit value.
+	const uint64_t Base = Imm >> 6;
+	const int64_t Disp = SignExtend64((Imm & 0x3F) + 64, 7) * 8;
+
+	MCOperand_CreateImm0(Inst, (Disp));
+	MCOperand_CreateReg0(Inst, (RRegs[Base]));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus decodeMemRIX16Operands(MCInst *Inst, uint64_t Imm,
+					   int64_t Address, const void *Decoder)
+{
+	// Decode the memrix16 field (imm, reg), which has the low 12-bits as the
+	// displacement with 16-byte aligned, and the next 5 bits as the register #.
+
+	uint64_t Base = Imm >> 12;
+	uint64_t Disp = Imm & 0xFFF;
+
+	MCOperand_CreateImm0(Inst, (SignExtend64(Disp << 4, 16)));
+	MCOperand_CreateReg0(Inst, (RRegsNoR0[Base]));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus decodeMemRI34PCRelOperands(MCInst *Inst, uint64_t Imm,
+					       int64_t Address,
+					       const void *Decoder)
+{
+	// Decode the memri34_pcrel field (imm, reg), which has the low 34-bits as
+	// the displacement, and the next 5 bits as an immediate 0.
+	uint64_t Base = Imm >> 34;
+	uint64_t Disp = Imm & 0x3FFFFFFFFUL;
+
+	MCOperand_CreateImm0(Inst, (SignExtend64(Disp, 34)));
+	return decodeImmZeroOperand(Inst, Base, Address, Decoder);
+}
+
+static DecodeStatus decodeMemRI34Operands(MCInst *Inst, uint64_t Imm,
+					  int64_t Address, const void *Decoder)
+{
+	// Decode the memri34 field (imm, reg), which has the low 34-bits as the
+	// displacement, and the next 5 bits as the register #.
+	uint64_t Base = Imm >> 34;
+	uint64_t Disp = Imm & 0x3FFFFFFFFUL;
+
+	MCOperand_CreateImm0(Inst, (SignExtend64(Disp, 34)));
+	MCOperand_CreateReg0(Inst, (RRegsNoR0[Base]));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus decodeSPE8Operands(MCInst *Inst, uint64_t Imm,
+				       int64_t Address, const void *Decoder)
+{
+	// Decode the spe8disp field (imm, reg), which has the low 5-bits as the
+	// displacement with 8-byte aligned, and the next 5 bits as the register #.
+
+	uint64_t Base = Imm >> 5;
+	uint64_t Disp = Imm & 0x1F;
+
+	MCOperand_CreateImm0(Inst, (Disp << 3));
+	MCOperand_CreateReg0(Inst, (RRegsNoR0[Base]));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus decodeSPE4Operands(MCInst *Inst, uint64_t Imm,
+				       int64_t Address, const void *Decoder)
+{
+	// Decode the spe4disp field (imm, reg), which has the low 5-bits as the
+	// displacement with 4-byte aligned, and the next 5 bits as the register #.
+
+	uint64_t Base = Imm >> 5;
+	uint64_t Disp = Imm & 0x1F;
+
+	MCOperand_CreateImm0(Inst, (Disp << 2));
+	MCOperand_CreateReg0(Inst, (RRegsNoR0[Base]));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus decodeSPE2Operands(MCInst *Inst, uint64_t Imm,
+				       int64_t Address, const void *Decoder)
+{
+	// Decode the spe2disp field (imm, reg), which has the low 5-bits as the
+	// displacement with 2-byte aligned, and the next 5 bits as the register #.
+
+	uint64_t Base = Imm >> 5;
+	uint64_t Disp = Imm & 0x1F;
+
+	MCOperand_CreateImm0(Inst, (Disp << 1));
+	MCOperand_CreateReg0(Inst, (RRegsNoR0[Base]));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus decodeCRBitMOperand(MCInst *Inst, uint64_t Imm,
+					int64_t Address, const void *Decoder)
+{
+	// The cr bit encoding is 0x80 >> cr_reg_num.
+
+	unsigned Zeros = CountTrailingZeros_32(Imm);
+	if (Zeros >= 8)
+		return MCDisassembler_Fail;
+
+	MCOperand_CreateReg0(Inst, (CRRegs[7 - Zeros]));
+	return MCDisassembler_Success;
+}
+
+#include "PPCGenDisassemblerTables.inc"
+
+DecodeStatus getInstruction(csh ud, const uint8_t *Bytes, size_t BytesLen,
+			    MCInst *MI, uint16_t *Size, uint64_t Address,
+			    void *Info)
+{
+	// If this is an 8-byte prefixed instruction, handle it here.
+	// Note: prefixed instructions aren't technically 8-byte entities - the
+	// prefix
+	//       appears in memory at an address 4 bytes prior to that of the base
+	//       instruction regardless of endianness. So we read the two pieces and
+	//       rebuild the 8-byte instruction.
+	// TODO: In this function we call decodeInstruction several times with
+	//       different decoder tables. It may be possible to only call once by
+	//       looking at the top 6 bits of the instruction.
+	if (PPC_getFeatureBits(MI->csh->mode, PPC_FeaturePrefixInstrs) &&
+	    BytesLen >= 8) {
+		uint32_t Prefix = readBytes32(MI, Bytes);
+		uint32_t BaseInst = readBytes32(MI, Bytes + 4);
+		uint64_t Inst = BaseInst | (uint64_t)Prefix << 32;
+		DecodeStatus result =
+			decodeInstruction_4(DecoderTable64, MI, Inst, Address);
+		if (result != MCDisassembler_Fail) {
+			*Size = 8;
+			return result;
+		}
+	}
+
+	// Get the four bytes of the instruction.
+	*Size = 4;
+	if (BytesLen < 4) {
+		*Size = 0;
+		return MCDisassembler_Fail;
+	}
+
+	// Read the instruction in the proper endianness.
+	uint64_t Inst = readBytes32(MI, Bytes);
+
+	if (PPC_getFeatureBits(MI->csh->mode, PPC_FeatureQPX)) {
+		DecodeStatus result = decodeInstruction_4(DecoderTableQPX32, MI,
+							  Inst, Address);
+		if (result != MCDisassembler_Fail)
+			return result;
+	} else if (PPC_getFeatureBits(MI->csh->mode, PPC_FeatureSPE)) {
+		DecodeStatus result = decodeInstruction_4(DecoderTableSPE32, MI,
+							  Inst, Address);
+		if (result != MCDisassembler_Fail)
+			return result;
+	} else if (PPC_getFeatureBits(MI->csh->mode, PPC_FeaturePS)) {
+		DecodeStatus result = decodeInstruction_4(DecoderTablePS32, MI,
+							  Inst, Address);
+		if (result != MCDisassembler_Fail)
+			return result;
+	}
+
+	return decodeInstruction_4(DecoderTable32, MI, Inst, Address);
+}
+
+DecodeStatus PPC_LLVM_getInstruction(csh handle, const uint8_t *Bytes,
+				     size_t BytesLen, MCInst *MI,
+				     uint16_t *Size, uint64_t Address,
+				     void *Info)
+{
+	return getInstruction(handle, Bytes, BytesLen, MI, Size, Address, Info);
+}

thirdparty/capstone/arch/PowerPC/PPCGenCSAliasMnemMap.inc

@@ -0,0 +1,687 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+	{ PPC_INS_ALIAS_RFEBB, "rfebb" },
+	{ PPC_INS_ALIAS_LI, "li" },
+	{ PPC_INS_ALIAS_LIS, "lis" },
+	{ PPC_INS_ALIAS_MR, "mr" },
+	{ PPC_INS_ALIAS_MR_, "mr." },
+	{ PPC_INS_ALIAS_NOT, "not" },
+	{ PPC_INS_ALIAS_NOT_, "not." },
+	{ PPC_INS_ALIAS_NOP, "nop" },
+	{ PPC_INS_ALIAS_MTUDSCR, "mtudscr" },
+	{ PPC_INS_ALIAS_MFUDSCR, "mfudscr" },
+	{ PPC_INS_ALIAS_MTVRSAVE, "mtvrsave" },
+	{ PPC_INS_ALIAS_MFVRSAVE, "mfvrsave" },
+	{ PPC_INS_ALIAS_MTCR, "mtcr" },
+	{ PPC_INS_ALIAS_SUB, "sub" },
+	{ PPC_INS_ALIAS_SUB_, "sub." },
+	{ PPC_INS_ALIAS_SUBC, "subc" },
+	{ PPC_INS_ALIAS_SUBC_, "subc." },
+	{ PPC_INS_ALIAS_VMR, "vmr" },
+	{ PPC_INS_ALIAS_VNOT, "vnot" },
+	{ PPC_INS_ALIAS_ROTLWI, "rotlwi" },
+	{ PPC_INS_ALIAS_ROTLWI_, "rotlwi." },
+	{ PPC_INS_ALIAS_ROTLW, "rotlw" },
+	{ PPC_INS_ALIAS_ROTLW_, "rotlw." },
+	{ PPC_INS_ALIAS_CLRLWI, "clrlwi" },
+	{ PPC_INS_ALIAS_CLRLWI_, "clrlwi." },
+	{ PPC_INS_ALIAS_ISELLT, "isellt" },
+	{ PPC_INS_ALIAS_ISELGT, "iselgt" },
+	{ PPC_INS_ALIAS_ISELEQ, "iseleq" },
+	{ PPC_INS_ALIAS_XNOP, "xnop" },
+	{ PPC_INS_ALIAS_CNTLZW, "cntlzw" },
+	{ PPC_INS_ALIAS_CNTLZW_, "cntlzw." },
+	{ PPC_INS_ALIAS_MTXER, "mtxer" },
+	{ PPC_INS_ALIAS_MFXER, "mfxer" },
+	{ PPC_INS_ALIAS_MFRTCU, "mfrtcu" },
+	{ PPC_INS_ALIAS_MFRTCL, "mfrtcl" },
+	{ PPC_INS_ALIAS_MTLR, "mtlr" },
+	{ PPC_INS_ALIAS_MFLR, "mflr" },
+	{ PPC_INS_ALIAS_MTCTR, "mtctr" },
+	{ PPC_INS_ALIAS_MFCTR, "mfctr" },
+	{ PPC_INS_ALIAS_MTUAMR, "mtuamr" },
+	{ PPC_INS_ALIAS_MFUAMR, "mfuamr" },
+	{ PPC_INS_ALIAS_MTDSCR, "mtdscr" },
+	{ PPC_INS_ALIAS_MFDSCR, "mfdscr" },
+	{ PPC_INS_ALIAS_MTDSISR, "mtdsisr" },
+	{ PPC_INS_ALIAS_MFDSISR, "mfdsisr" },
+	{ PPC_INS_ALIAS_MTDAR, "mtdar" },
+	{ PPC_INS_ALIAS_MFDAR, "mfdar" },
+	{ PPC_INS_ALIAS_MTDEC, "mtdec" },
+	{ PPC_INS_ALIAS_MFDEC, "mfdec" },
+	{ PPC_INS_ALIAS_MTSDR1, "mtsdr1" },
+	{ PPC_INS_ALIAS_MFSDR1, "mfsdr1" },
+	{ PPC_INS_ALIAS_MTSRR0, "mtsrr0" },
+	{ PPC_INS_ALIAS_MFSRR0, "mfsrr0" },
+	{ PPC_INS_ALIAS_MTSRR1, "mtsrr1" },
+	{ PPC_INS_ALIAS_MFSRR1, "mfsrr1" },
+	{ PPC_INS_ALIAS_MTCFAR, "mtcfar" },
+	{ PPC_INS_ALIAS_MFCFAR, "mfcfar" },
+	{ PPC_INS_ALIAS_MTAMR, "mtamr" },
+	{ PPC_INS_ALIAS_MFAMR, "mfamr" },
+	{ PPC_INS_ALIAS_MFSPRG, "mfsprg" },
+	{ PPC_INS_ALIAS_MFSPRG0, "mfsprg0" },
+	{ PPC_INS_ALIAS_MTSPRG, "mtsprg" },
+	{ PPC_INS_ALIAS_MTSPRG0, "mtsprg0" },
+	{ PPC_INS_ALIAS_MFSPRG1, "mfsprg1" },
+	{ PPC_INS_ALIAS_MTSPRG1, "mtsprg1" },
+	{ PPC_INS_ALIAS_MFSPRG2, "mfsprg2" },
+	{ PPC_INS_ALIAS_MTSPRG2, "mtsprg2" },
+	{ PPC_INS_ALIAS_MFSPRG3, "mfsprg3" },
+	{ PPC_INS_ALIAS_MTSPRG3, "mtsprg3" },
+	{ PPC_INS_ALIAS_MFASR, "mfasr" },
+	{ PPC_INS_ALIAS_MTASR, "mtasr" },
+	{ PPC_INS_ALIAS_MTTBL, "mttbl" },
+	{ PPC_INS_ALIAS_MTTBU, "mttbu" },
+	{ PPC_INS_ALIAS_MFPVR, "mfpvr" },
+	{ PPC_INS_ALIAS_MFSPEFSCR, "mfspefscr" },
+	{ PPC_INS_ALIAS_MTSPEFSCR, "mtspefscr" },
+	{ PPC_INS_ALIAS_XVMOVDP, "xvmovdp" },
+	{ PPC_INS_ALIAS_XVMOVSP, "xvmovsp" },
+	{ PPC_INS_ALIAS_XXSPLTD, "xxspltd" },
+	{ PPC_INS_ALIAS_XXMRGHD, "xxmrghd" },
+	{ PPC_INS_ALIAS_XXMRGLD, "xxmrgld" },
+	{ PPC_INS_ALIAS_XXSWAPD, "xxswapd" },
+	{ PPC_INS_ALIAS_MFFPRD, "mffprd" },
+	{ PPC_INS_ALIAS_MTFPRD, "mtfprd" },
+	{ PPC_INS_ALIAS_MFFPRWZ, "mffprwz" },
+	{ PPC_INS_ALIAS_MTFPRWA, "mtfprwa" },
+	{ PPC_INS_ALIAS_MTFPRWZ, "mtfprwz" },
+	{ PPC_INS_ALIAS_TEND_, "tend." },
+	{ PPC_INS_ALIAS_TENDALL_, "tendall." },
+	{ PPC_INS_ALIAS_TSUSPEND_, "tsuspend." },
+	{ PPC_INS_ALIAS_TRESUME_, "tresume." },
+	{ PPC_INS_ALIAS_DCI, "dci" },
+	{ PPC_INS_ALIAS_DCCCI, "dccci" },
+	{ PPC_INS_ALIAS_ICI, "ici" },
+	{ PPC_INS_ALIAS_ICCCI, "iccci" },
+	{ PPC_INS_ALIAS_MTFSFI, "mtfsfi" },
+	{ PPC_INS_ALIAS_MTFSFI_, "mtfsfi." },
+	{ PPC_INS_ALIAS_MTFSF, "mtfsf" },
+	{ PPC_INS_ALIAS_MTFSF_, "mtfsf." },
+	{ PPC_INS_ALIAS_SC, "sc" },
+	{ PPC_INS_ALIAS_SYNC, "sync" },
+	{ PPC_INS_ALIAS_LWSYNC, "lwsync" },
+	{ PPC_INS_ALIAS_PTESYNC, "ptesync" },
+	{ PPC_INS_ALIAS_WAIT, "wait" },
+	{ PPC_INS_ALIAS_WAITRSV, "waitrsv" },
+	{ PPC_INS_ALIAS_WAITIMPL, "waitimpl" },
+	{ PPC_INS_ALIAS_MBAR, "mbar" },
+	{ PPC_INS_ALIAS_CRSET, "crset" },
+	{ PPC_INS_ALIAS_CRCLR, "crclr" },
+	{ PPC_INS_ALIAS_CRMOVE, "crmove" },
+	{ PPC_INS_ALIAS_CRNOT, "crnot" },
+	{ PPC_INS_ALIAS_MFTB, "mftb" },
+	{ PPC_INS_ALIAS_MFTBL, "mftbl" },
+	{ PPC_INS_ALIAS_MFTBU, "mftbu" },
+	{ PPC_INS_ALIAS_MFBR0, "mfbr0" },
+	{ PPC_INS_ALIAS_MTBR0, "mtbr0" },
+	{ PPC_INS_ALIAS_MFBR1, "mfbr1" },
+	{ PPC_INS_ALIAS_MTBR1, "mtbr1" },
+	{ PPC_INS_ALIAS_MFBR2, "mfbr2" },
+	{ PPC_INS_ALIAS_MTBR2, "mtbr2" },
+	{ PPC_INS_ALIAS_MFBR3, "mfbr3" },
+	{ PPC_INS_ALIAS_MTBR3, "mtbr3" },
+	{ PPC_INS_ALIAS_MFBR4, "mfbr4" },
+	{ PPC_INS_ALIAS_MTBR4, "mtbr4" },
+	{ PPC_INS_ALIAS_MFBR5, "mfbr5" },
+	{ PPC_INS_ALIAS_MTBR5, "mtbr5" },
+	{ PPC_INS_ALIAS_MFBR6, "mfbr6" },
+	{ PPC_INS_ALIAS_MTBR6, "mtbr6" },
+	{ PPC_INS_ALIAS_MFBR7, "mfbr7" },
+	{ PPC_INS_ALIAS_MTBR7, "mtbr7" },
+	{ PPC_INS_ALIAS_MTMSRD, "mtmsrd" },
+	{ PPC_INS_ALIAS_MTMSR, "mtmsr" },
+	{ PPC_INS_ALIAS_MTPID, "mtpid" },
+	{ PPC_INS_ALIAS_MFPID, "mfpid" },
+	{ PPC_INS_ALIAS_MFSPRG4, "mfsprg4" },
+	{ PPC_INS_ALIAS_MTSPRG4, "mtsprg4" },
+	{ PPC_INS_ALIAS_MFSPRG5, "mfsprg5" },
+	{ PPC_INS_ALIAS_MTSPRG5, "mtsprg5" },
+	{ PPC_INS_ALIAS_MFSPRG6, "mfsprg6" },
+	{ PPC_INS_ALIAS_MTSPRG6, "mtsprg6" },
+	{ PPC_INS_ALIAS_MFSPRG7, "mfsprg7" },
+	{ PPC_INS_ALIAS_MTSPRG7, "mtsprg7" },
+	{ PPC_INS_ALIAS_MTDBATU, "mtdbatu" },
+	{ PPC_INS_ALIAS_MFDBATU, "mfdbatu" },
+	{ PPC_INS_ALIAS_MTDBATL, "mtdbatl" },
+	{ PPC_INS_ALIAS_MFDBATL, "mfdbatl" },
+	{ PPC_INS_ALIAS_MTIBATU, "mtibatu" },
+	{ PPC_INS_ALIAS_MFIBATU, "mfibatu" },
+	{ PPC_INS_ALIAS_MTIBATL, "mtibatl" },
+	{ PPC_INS_ALIAS_MFIBATL, "mfibatl" },
+	{ PPC_INS_ALIAS_MTPPR, "mtppr" },
+	{ PPC_INS_ALIAS_MFPPR, "mfppr" },
+	{ PPC_INS_ALIAS_MTESR, "mtesr" },
+	{ PPC_INS_ALIAS_MFESR, "mfesr" },
+	{ PPC_INS_ALIAS_MTDEAR, "mtdear" },
+	{ PPC_INS_ALIAS_MFDEAR, "mfdear" },
+	{ PPC_INS_ALIAS_MTTCR, "mttcr" },
+	{ PPC_INS_ALIAS_MFTCR, "mftcr" },
+	{ PPC_INS_ALIAS_MFTBHI, "mftbhi" },
+	{ PPC_INS_ALIAS_MTTBHI, "mttbhi" },
+	{ PPC_INS_ALIAS_MFTBLO, "mftblo" },
+	{ PPC_INS_ALIAS_MTTBLO, "mttblo" },
+	{ PPC_INS_ALIAS_MTSRR2, "mtsrr2" },
+	{ PPC_INS_ALIAS_MFSRR2, "mfsrr2" },
+	{ PPC_INS_ALIAS_MTSRR3, "mtsrr3" },
+	{ PPC_INS_ALIAS_MFSRR3, "mfsrr3" },
+	{ PPC_INS_ALIAS_MTDCCR, "mtdccr" },
+	{ PPC_INS_ALIAS_MFDCCR, "mfdccr" },
+	{ PPC_INS_ALIAS_MTICCR, "mticcr" },
+	{ PPC_INS_ALIAS_MFICCR, "mficcr" },
+	{ PPC_INS_ALIAS_TLBIE, "tlbie" },
+	{ PPC_INS_ALIAS_TLBREHI, "tlbrehi" },
+	{ PPC_INS_ALIAS_TLBRELO, "tlbrelo" },
+	{ PPC_INS_ALIAS_TLBWEHI, "tlbwehi" },
+	{ PPC_INS_ALIAS_TLBWELO, "tlbwelo" },
+	{ PPC_INS_ALIAS_ROTLDI, "rotldi" },
+	{ PPC_INS_ALIAS_ROTLDI_, "rotldi." },
+	{ PPC_INS_ALIAS_ROTLD, "rotld" },
+	{ PPC_INS_ALIAS_ROTLD_, "rotld." },
+	{ PPC_INS_ALIAS_CLRLDI, "clrldi" },
+	{ PPC_INS_ALIAS_CLRLDI_, "clrldi." },
+	{ PPC_INS_ALIAS_LNIA, "lnia" },
+	{ PPC_INS_ALIAS_BCp, "bc+" },
+	{ PPC_INS_ALIAS_BCAp, "bca+" },
+	{ PPC_INS_ALIAS_BCLp, "bcl+" },
+	{ PPC_INS_ALIAS_BCLAp, "bcla+" },
+	{ PPC_INS_ALIAS_BCm, "bc-" },
+	{ PPC_INS_ALIAS_BCAm, "bca-" },
+	{ PPC_INS_ALIAS_BCLm, "bcl-" },
+	{ PPC_INS_ALIAS_BCLAm, "bcla-" },
+	{ PPC_INS_ALIAS_BT, "bt" },
+	{ PPC_INS_ALIAS_BTA, "bta" },
+	{ PPC_INS_ALIAS_BTLR, "btlr" },
+	{ PPC_INS_ALIAS_BTL, "btl" },
+	{ PPC_INS_ALIAS_BTLA, "btla" },
+	{ PPC_INS_ALIAS_BTLRL, "btlrl" },
+	{ PPC_INS_ALIAS_BTCTR, "btctr" },
+	{ PPC_INS_ALIAS_BTCTRL, "btctrl" },
+	{ PPC_INS_ALIAS_BDZLR, "bdzlr" },
+	{ PPC_INS_ALIAS_BDZLRL, "bdzlrl" },
+	{ PPC_INS_ALIAS_BDZL, "bdzl" },
+	{ PPC_INS_ALIAS_BDZLA, "bdzla" },
+	{ PPC_INS_ALIAS_BDZ, "bdz" },
+	{ PPC_INS_ALIAS_BDNZL, "bdnzl" },
+	{ PPC_INS_ALIAS_BDNZLA, "bdnzla" },
+	{ PPC_INS_ALIAS_BDNZ, "bdnz" },
+	{ PPC_INS_ALIAS_BDZLp, "bdzl+" },
+	{ PPC_INS_ALIAS_BDZLAp, "bdzla+" },
+	{ PPC_INS_ALIAS_BDZp, "bdz+" },
+	{ PPC_INS_ALIAS_BDNZLp, "bdnzl+" },
+	{ PPC_INS_ALIAS_BDNZLAp, "bdnzla+" },
+	{ PPC_INS_ALIAS_BDNZp, "bdnz+" },
+	{ PPC_INS_ALIAS_BDZLm, "bdzl-" },
+	{ PPC_INS_ALIAS_BDZLAm, "bdzla-" },
+	{ PPC_INS_ALIAS_BDZm, "bdz-" },
+	{ PPC_INS_ALIAS_BDNZLm, "bdnzl-" },
+	{ PPC_INS_ALIAS_BDNZLAm, "bdnzla-" },
+	{ PPC_INS_ALIAS_BDNZm, "bdnz-" },
+	{ PPC_INS_ALIAS_BDNZLR, "bdnzlr" },
+	{ PPC_INS_ALIAS_BDNZLRL, "bdnzlrl" },
+	{ PPC_INS_ALIAS_BDZLRp, "bdzlr+" },
+	{ PPC_INS_ALIAS_BDZLRLp, "bdzlrl+" },
+	{ PPC_INS_ALIAS_BDNZLRp, "bdnzlr+" },
+	{ PPC_INS_ALIAS_BDNZLRLp, "bdnzlrl+" },
+	{ PPC_INS_ALIAS_BDZLRm, "bdzlr-" },
+	{ PPC_INS_ALIAS_BDZLRLm, "bdzlrl-" },
+	{ PPC_INS_ALIAS_BDNZLRm, "bdnzlr-" },
+	{ PPC_INS_ALIAS_BDNZLRLm, "bdnzlrl-" },
+	{ PPC_INS_ALIAS_BF, "bf" },
+	{ PPC_INS_ALIAS_BFA, "bfa" },
+	{ PPC_INS_ALIAS_BFLR, "bflr" },
+	{ PPC_INS_ALIAS_BFL, "bfl" },
+	{ PPC_INS_ALIAS_BFLA, "bfla" },
+	{ PPC_INS_ALIAS_BFLRL, "bflrl" },
+	{ PPC_INS_ALIAS_BFCTR, "bfctr" },
+	{ PPC_INS_ALIAS_BFCTRL, "bfctrl" },
+	{ PPC_INS_ALIAS_BTm, "bt-" },
+	{ PPC_INS_ALIAS_BTAm, "bta-" },
+	{ PPC_INS_ALIAS_BTLRm, "btlr-" },
+	{ PPC_INS_ALIAS_BTLm, "btl-" },
+	{ PPC_INS_ALIAS_BTLAm, "btla-" },
+	{ PPC_INS_ALIAS_BTLRLm, "btlrl-" },
+	{ PPC_INS_ALIAS_BTCTRm, "btctr-" },
+	{ PPC_INS_ALIAS_BTCTRLm, "btctrl-" },
+	{ PPC_INS_ALIAS_BFm, "bf-" },
+	{ PPC_INS_ALIAS_BFAm, "bfa-" },
+	{ PPC_INS_ALIAS_BFLRm, "bflr-" },
+	{ PPC_INS_ALIAS_BFLm, "bfl-" },
+	{ PPC_INS_ALIAS_BFLAm, "bfla-" },
+	{ PPC_INS_ALIAS_BFLRLm, "bflrl-" },
+	{ PPC_INS_ALIAS_BFCTRm, "bfctr-" },
+	{ PPC_INS_ALIAS_BFCTRLm, "bfctrl-" },
+	{ PPC_INS_ALIAS_BTp, "bt+" },
+	{ PPC_INS_ALIAS_BTAp, "bta+" },
+	{ PPC_INS_ALIAS_BTLRp, "btlr+" },
+	{ PPC_INS_ALIAS_BTLp, "btl+" },
+	{ PPC_INS_ALIAS_BTLAp, "btla+" },
+	{ PPC_INS_ALIAS_BTLRLp, "btlrl+" },
+	{ PPC_INS_ALIAS_BTCTRp, "btctr+" },
+	{ PPC_INS_ALIAS_BTCTRLp, "btctrl+" },
+	{ PPC_INS_ALIAS_BFp, "bf+" },
+	{ PPC_INS_ALIAS_BFAp, "bfa+" },
+	{ PPC_INS_ALIAS_BFLRp, "bflr+" },
+	{ PPC_INS_ALIAS_BFLp, "bfl+" },
+	{ PPC_INS_ALIAS_BFLAp, "bfla+" },
+	{ PPC_INS_ALIAS_BFLRLp, "bflrl+" },
+	{ PPC_INS_ALIAS_BFCTRp, "bfctr+" },
+	{ PPC_INS_ALIAS_BFCTRLp, "bfctrl+" },
+	{ PPC_INS_ALIAS_BDNZT, "bdnzt" },
+	{ PPC_INS_ALIAS_BDNZTA, "bdnzta" },
+	{ PPC_INS_ALIAS_BDNZTLR, "bdnztlr" },
+	{ PPC_INS_ALIAS_BDNZTL, "bdnztl" },
+	{ PPC_INS_ALIAS_BDNZTLA, "bdnztla" },
+	{ PPC_INS_ALIAS_BDNZTLRL, "bdnztlrl" },
+	{ PPC_INS_ALIAS_BDNZF, "bdnzf" },
+	{ PPC_INS_ALIAS_BDNZFA, "bdnzfa" },
+	{ PPC_INS_ALIAS_BDNZFLR, "bdnzflr" },
+	{ PPC_INS_ALIAS_BDNZFL, "bdnzfl" },
+	{ PPC_INS_ALIAS_BDNZFLA, "bdnzfla" },
+	{ PPC_INS_ALIAS_BDNZFLRL, "bdnzflrl" },
+	{ PPC_INS_ALIAS_BDZT, "bdzt" },
+	{ PPC_INS_ALIAS_BDZTA, "bdzta" },
+	{ PPC_INS_ALIAS_BDZTLR, "bdztlr" },
+	{ PPC_INS_ALIAS_BDZTL, "bdztl" },
+	{ PPC_INS_ALIAS_BDZTLA, "bdztla" },
+	{ PPC_INS_ALIAS_BDZTLRL, "bdztlrl" },
+	{ PPC_INS_ALIAS_BDZF, "bdzf" },
+	{ PPC_INS_ALIAS_BDZFA, "bdzfa" },
+	{ PPC_INS_ALIAS_BDZFLR, "bdzflr" },
+	{ PPC_INS_ALIAS_BDZFL, "bdzfl" },
+	{ PPC_INS_ALIAS_BDZFLA, "bdzfla" },
+	{ PPC_INS_ALIAS_BDZFLRL, "bdzflrl" },
+	{ PPC_INS_ALIAS_B, "b" },
+	{ PPC_INS_ALIAS_BA, "ba" },
+	{ PPC_INS_ALIAS_BL, "bl" },
+	{ PPC_INS_ALIAS_BLA, "bla" },
+	{ PPC_INS_ALIAS_BLR, "blr" },
+	{ PPC_INS_ALIAS_BLRL, "blrl" },
+	{ PPC_INS_ALIAS_BCTR, "bctr" },
+	{ PPC_INS_ALIAS_BCTRL, "bctrl" },
+	{ PPC_INS_ALIAS_BLT, "blt" },
+	{ PPC_INS_ALIAS_BLTA, "blta" },
+	{ PPC_INS_ALIAS_BLTLR, "bltlr" },
+	{ PPC_INS_ALIAS_BLTCTR, "bltctr" },
+	{ PPC_INS_ALIAS_BLTL, "bltl" },
+	{ PPC_INS_ALIAS_BLTLA, "bltla" },
+	{ PPC_INS_ALIAS_BLTLRL, "bltlrl" },
+	{ PPC_INS_ALIAS_BLTCTRL, "bltctrl" },
+	{ PPC_INS_ALIAS_BLTm, "blt-" },
+	{ PPC_INS_ALIAS_BLTAm, "blta-" },
+	{ PPC_INS_ALIAS_BLTLRm, "bltlr-" },
+	{ PPC_INS_ALIAS_BLTCTRm, "bltctr-" },
+	{ PPC_INS_ALIAS_BLTLm, "bltl-" },
+	{ PPC_INS_ALIAS_BLTLAm, "bltla-" },
+	{ PPC_INS_ALIAS_BLTLRLm, "bltlrl-" },
+	{ PPC_INS_ALIAS_BLTCTRLm, "bltctrl-" },
+	{ PPC_INS_ALIAS_BLTp, "blt+" },
+	{ PPC_INS_ALIAS_BLTAp, "blta+" },
+	{ PPC_INS_ALIAS_BLTLRp, "bltlr+" },
+	{ PPC_INS_ALIAS_BLTCTRp, "bltctr+" },
+	{ PPC_INS_ALIAS_BLTLp, "bltl+" },
+	{ PPC_INS_ALIAS_BLTLAp, "bltla+" },
+	{ PPC_INS_ALIAS_BLTLRLp, "bltlrl+" },
+	{ PPC_INS_ALIAS_BLTCTRLp, "bltctrl+" },
+	{ PPC_INS_ALIAS_BGT, "bgt" },
+	{ PPC_INS_ALIAS_BGTA, "bgta" },
+	{ PPC_INS_ALIAS_BGTLR, "bgtlr" },
+	{ PPC_INS_ALIAS_BGTCTR, "bgtctr" },
+	{ PPC_INS_ALIAS_BGTL, "bgtl" },
+	{ PPC_INS_ALIAS_BGTLA, "bgtla" },
+	{ PPC_INS_ALIAS_BGTLRL, "bgtlrl" },
+	{ PPC_INS_ALIAS_BGTCTRL, "bgtctrl" },
+	{ PPC_INS_ALIAS_BGTm, "bgt-" },
+	{ PPC_INS_ALIAS_BGTAm, "bgta-" },
+	{ PPC_INS_ALIAS_BGTLRm, "bgtlr-" },
+	{ PPC_INS_ALIAS_BGTCTRm, "bgtctr-" },
+	{ PPC_INS_ALIAS_BGTLm, "bgtl-" },
+	{ PPC_INS_ALIAS_BGTLAm, "bgtla-" },
+	{ PPC_INS_ALIAS_BGTLRLm, "bgtlrl-" },
+	{ PPC_INS_ALIAS_BGTCTRLm, "bgtctrl-" },
+	{ PPC_INS_ALIAS_BGTp, "bgt+" },
+	{ PPC_INS_ALIAS_BGTAp, "bgta+" },
+	{ PPC_INS_ALIAS_BGTLRp, "bgtlr+" },
+	{ PPC_INS_ALIAS_BGTCTRp, "bgtctr+" },
+	{ PPC_INS_ALIAS_BGTLp, "bgtl+" },
+	{ PPC_INS_ALIAS_BGTLAp, "bgtla+" },
+	{ PPC_INS_ALIAS_BGTLRLp, "bgtlrl+" },
+	{ PPC_INS_ALIAS_BGTCTRLp, "bgtctrl+" },
+	{ PPC_INS_ALIAS_BEQ, "beq" },
+	{ PPC_INS_ALIAS_BEQA, "beqa" },
+	{ PPC_INS_ALIAS_BEQLR, "beqlr" },
+	{ PPC_INS_ALIAS_BEQCTR, "beqctr" },
+	{ PPC_INS_ALIAS_BEQL, "beql" },
+	{ PPC_INS_ALIAS_BEQLA, "beqla" },
+	{ PPC_INS_ALIAS_BEQLRL, "beqlrl" },
+	{ PPC_INS_ALIAS_BEQCTRL, "beqctrl" },
+	{ PPC_INS_ALIAS_BEQm, "beq-" },
+	{ PPC_INS_ALIAS_BEQAm, "beqa-" },
+	{ PPC_INS_ALIAS_BEQLRm, "beqlr-" },
+	{ PPC_INS_ALIAS_BEQCTRm, "beqctr-" },
+	{ PPC_INS_ALIAS_BEQLm, "beql-" },
+	{ PPC_INS_ALIAS_BEQLAm, "beqla-" },
+	{ PPC_INS_ALIAS_BEQLRLm, "beqlrl-" },
+	{ PPC_INS_ALIAS_BEQCTRLm, "beqctrl-" },
+	{ PPC_INS_ALIAS_BEQp, "beq+" },
+	{ PPC_INS_ALIAS_BEQAp, "beqa+" },
+	{ PPC_INS_ALIAS_BEQLRp, "beqlr+" },
+	{ PPC_INS_ALIAS_BEQCTRp, "beqctr+" },
+	{ PPC_INS_ALIAS_BEQLp, "beql+" },
+	{ PPC_INS_ALIAS_BEQLAp, "beqla+" },
+	{ PPC_INS_ALIAS_BEQLRLp, "beqlrl+" },
+	{ PPC_INS_ALIAS_BEQCTRLp, "beqctrl+" },
+	{ PPC_INS_ALIAS_BUN, "bun" },
+	{ PPC_INS_ALIAS_BUNA, "buna" },
+	{ PPC_INS_ALIAS_BUNLR, "bunlr" },
+	{ PPC_INS_ALIAS_BUNCTR, "bunctr" },
+	{ PPC_INS_ALIAS_BUNL, "bunl" },
+	{ PPC_INS_ALIAS_BUNLA, "bunla" },
+	{ PPC_INS_ALIAS_BUNLRL, "bunlrl" },
+	{ PPC_INS_ALIAS_BUNCTRL, "bunctrl" },
+	{ PPC_INS_ALIAS_BUNm, "bun-" },
+	{ PPC_INS_ALIAS_BUNAm, "buna-" },
+	{ PPC_INS_ALIAS_BUNLRm, "bunlr-" },
+	{ PPC_INS_ALIAS_BUNCTRm, "bunctr-" },
+	{ PPC_INS_ALIAS_BUNLm, "bunl-" },
+	{ PPC_INS_ALIAS_BUNLAm, "bunla-" },
+	{ PPC_INS_ALIAS_BUNLRLm, "bunlrl-" },
+	{ PPC_INS_ALIAS_BUNCTRLm, "bunctrl-" },
+	{ PPC_INS_ALIAS_BUNp, "bun+" },
+	{ PPC_INS_ALIAS_BUNAp, "buna+" },
+	{ PPC_INS_ALIAS_BUNLRp, "bunlr+" },
+	{ PPC_INS_ALIAS_BUNCTRp, "bunctr+" },
+	{ PPC_INS_ALIAS_BUNLp, "bunl+" },
+	{ PPC_INS_ALIAS_BUNLAp, "bunla+" },
+	{ PPC_INS_ALIAS_BUNLRLp, "bunlrl+" },
+	{ PPC_INS_ALIAS_BUNCTRLp, "bunctrl+" },
+	{ PPC_INS_ALIAS_BSO, "bso" },
+	{ PPC_INS_ALIAS_BSOA, "bsoa" },
+	{ PPC_INS_ALIAS_BSOLR, "bsolr" },
+	{ PPC_INS_ALIAS_BSOCTR, "bsoctr" },
+	{ PPC_INS_ALIAS_BSOL, "bsol" },
+	{ PPC_INS_ALIAS_BSOLA, "bsola" },
+	{ PPC_INS_ALIAS_BSOLRL, "bsolrl" },
+	{ PPC_INS_ALIAS_BSOCTRL, "bsoctrl" },
+	{ PPC_INS_ALIAS_BSOm, "bso-" },
+	{ PPC_INS_ALIAS_BSOAm, "bsoa-" },
+	{ PPC_INS_ALIAS_BSOLRm, "bsolr-" },
+	{ PPC_INS_ALIAS_BSOCTRm, "bsoctr-" },
+	{ PPC_INS_ALIAS_BSOLm, "bsol-" },
+	{ PPC_INS_ALIAS_BSOLAm, "bsola-" },
+	{ PPC_INS_ALIAS_BSOLRLm, "bsolrl-" },
+	{ PPC_INS_ALIAS_BSOCTRLm, "bsoctrl-" },
+	{ PPC_INS_ALIAS_BSOp, "bso+" },
+	{ PPC_INS_ALIAS_BSOAp, "bsoa+" },
+	{ PPC_INS_ALIAS_BSOLRp, "bsolr+" },
+	{ PPC_INS_ALIAS_BSOCTRp, "bsoctr+" },
+	{ PPC_INS_ALIAS_BSOLp, "bsol+" },
+	{ PPC_INS_ALIAS_BSOLAp, "bsola+" },
+	{ PPC_INS_ALIAS_BSOLRLp, "bsolrl+" },
+	{ PPC_INS_ALIAS_BSOCTRLp, "bsoctrl+" },
+	{ PPC_INS_ALIAS_BGE, "bge" },
+	{ PPC_INS_ALIAS_BGEA, "bgea" },
+	{ PPC_INS_ALIAS_BGELR, "bgelr" },
+	{ PPC_INS_ALIAS_BGECTR, "bgectr" },
+	{ PPC_INS_ALIAS_BGEL, "bgel" },
+	{ PPC_INS_ALIAS_BGELA, "bgela" },
+	{ PPC_INS_ALIAS_BGELRL, "bgelrl" },
+	{ PPC_INS_ALIAS_BGECTRL, "bgectrl" },
+	{ PPC_INS_ALIAS_BGEm, "bge-" },
+	{ PPC_INS_ALIAS_BGEAm, "bgea-" },
+	{ PPC_INS_ALIAS_BGELRm, "bgelr-" },
+	{ PPC_INS_ALIAS_BGECTRm, "bgectr-" },
+	{ PPC_INS_ALIAS_BGELm, "bgel-" },
+	{ PPC_INS_ALIAS_BGELAm, "bgela-" },
+	{ PPC_INS_ALIAS_BGELRLm, "bgelrl-" },
+	{ PPC_INS_ALIAS_BGECTRLm, "bgectrl-" },
+	{ PPC_INS_ALIAS_BGEp, "bge+" },
+	{ PPC_INS_ALIAS_BGEAp, "bgea+" },
+	{ PPC_INS_ALIAS_BGELRp, "bgelr+" },
+	{ PPC_INS_ALIAS_BGECTRp, "bgectr+" },
+	{ PPC_INS_ALIAS_BGELp, "bgel+" },
+	{ PPC_INS_ALIAS_BGELAp, "bgela+" },
+	{ PPC_INS_ALIAS_BGELRLp, "bgelrl+" },
+	{ PPC_INS_ALIAS_BGECTRLp, "bgectrl+" },
+	{ PPC_INS_ALIAS_BNL, "bnl" },
+	{ PPC_INS_ALIAS_BNLA, "bnla" },
+	{ PPC_INS_ALIAS_BNLLR, "bnllr" },
+	{ PPC_INS_ALIAS_BNLCTR, "bnlctr" },
+	{ PPC_INS_ALIAS_BNLL, "bnll" },
+	{ PPC_INS_ALIAS_BNLLA, "bnlla" },
+	{ PPC_INS_ALIAS_BNLLRL, "bnllrl" },
+	{ PPC_INS_ALIAS_BNLCTRL, "bnlctrl" },
+	{ PPC_INS_ALIAS_BNLm, "bnl-" },
+	{ PPC_INS_ALIAS_BNLAm, "bnla-" },
+	{ PPC_INS_ALIAS_BNLLRm, "bnllr-" },
+	{ PPC_INS_ALIAS_BNLCTRm, "bnlctr-" },
+	{ PPC_INS_ALIAS_BNLLm, "bnll-" },
+	{ PPC_INS_ALIAS_BNLLAm, "bnlla-" },
+	{ PPC_INS_ALIAS_BNLLRLm, "bnllrl-" },
+	{ PPC_INS_ALIAS_BNLCTRLm, "bnlctrl-" },
+	{ PPC_INS_ALIAS_BNLp, "bnl+" },
+	{ PPC_INS_ALIAS_BNLAp, "bnla+" },
+	{ PPC_INS_ALIAS_BNLLRp, "bnllr+" },
+	{ PPC_INS_ALIAS_BNLCTRp, "bnlctr+" },
+	{ PPC_INS_ALIAS_BNLLp, "bnll+" },
+	{ PPC_INS_ALIAS_BNLLAp, "bnlla+" },
+	{ PPC_INS_ALIAS_BNLLRLp, "bnllrl+" },
+	{ PPC_INS_ALIAS_BNLCTRLp, "bnlctrl+" },
+	{ PPC_INS_ALIAS_BLE, "ble" },
+	{ PPC_INS_ALIAS_BLEA, "blea" },
+	{ PPC_INS_ALIAS_BLELR, "blelr" },
+	{ PPC_INS_ALIAS_BLECTR, "blectr" },
+	{ PPC_INS_ALIAS_BLEL, "blel" },
+	{ PPC_INS_ALIAS_BLELA, "blela" },
+	{ PPC_INS_ALIAS_BLELRL, "blelrl" },
+	{ PPC_INS_ALIAS_BLECTRL, "blectrl" },
+	{ PPC_INS_ALIAS_BLEm, "ble-" },
+	{ PPC_INS_ALIAS_BLEAm, "blea-" },
+	{ PPC_INS_ALIAS_BLELRm, "blelr-" },
+	{ PPC_INS_ALIAS_BLECTRm, "blectr-" },
+	{ PPC_INS_ALIAS_BLELm, "blel-" },
+	{ PPC_INS_ALIAS_BLELAm, "blela-" },
+	{ PPC_INS_ALIAS_BLELRLm, "blelrl-" },
+	{ PPC_INS_ALIAS_BLECTRLm, "blectrl-" },
+	{ PPC_INS_ALIAS_BLEp, "ble+" },
+	{ PPC_INS_ALIAS_BLEAp, "blea+" },
+	{ PPC_INS_ALIAS_BLELRp, "blelr+" },
+	{ PPC_INS_ALIAS_BLECTRp, "blectr+" },
+	{ PPC_INS_ALIAS_BLELp, "blel+" },
+	{ PPC_INS_ALIAS_BLELAp, "blela+" },
+	{ PPC_INS_ALIAS_BLELRLp, "blelrl+" },
+	{ PPC_INS_ALIAS_BLECTRLp, "blectrl+" },
+	{ PPC_INS_ALIAS_BNG, "bng" },
+	{ PPC_INS_ALIAS_BNGA, "bnga" },
+	{ PPC_INS_ALIAS_BNGLR, "bnglr" },
+	{ PPC_INS_ALIAS_BNGCTR, "bngctr" },
+	{ PPC_INS_ALIAS_BNGL, "bngl" },
+	{ PPC_INS_ALIAS_BNGLA, "bngla" },
+	{ PPC_INS_ALIAS_BNGLRL, "bnglrl" },
+	{ PPC_INS_ALIAS_BNGCTRL, "bngctrl" },
+	{ PPC_INS_ALIAS_BNGm, "bng-" },
+	{ PPC_INS_ALIAS_BNGAm, "bnga-" },
+	{ PPC_INS_ALIAS_BNGLRm, "bnglr-" },
+	{ PPC_INS_ALIAS_BNGCTRm, "bngctr-" },
+	{ PPC_INS_ALIAS_BNGLm, "bngl-" },
+	{ PPC_INS_ALIAS_BNGLAm, "bngla-" },
+	{ PPC_INS_ALIAS_BNGLRLm, "bnglrl-" },
+	{ PPC_INS_ALIAS_BNGCTRLm, "bngctrl-" },
+	{ PPC_INS_ALIAS_BNGp, "bng+" },
+	{ PPC_INS_ALIAS_BNGAp, "bnga+" },
+	{ PPC_INS_ALIAS_BNGLRp, "bnglr+" },
+	{ PPC_INS_ALIAS_BNGCTRp, "bngctr+" },
+	{ PPC_INS_ALIAS_BNGLp, "bngl+" },
+	{ PPC_INS_ALIAS_BNGLAp, "bngla+" },
+	{ PPC_INS_ALIAS_BNGLRLp, "bnglrl+" },
+	{ PPC_INS_ALIAS_BNGCTRLp, "bngctrl+" },
+	{ PPC_INS_ALIAS_BNE, "bne" },
+	{ PPC_INS_ALIAS_BNEA, "bnea" },
+	{ PPC_INS_ALIAS_BNELR, "bnelr" },
+	{ PPC_INS_ALIAS_BNECTR, "bnectr" },
+	{ PPC_INS_ALIAS_BNEL, "bnel" },
+	{ PPC_INS_ALIAS_BNELA, "bnela" },
+	{ PPC_INS_ALIAS_BNELRL, "bnelrl" },
+	{ PPC_INS_ALIAS_BNECTRL, "bnectrl" },
+	{ PPC_INS_ALIAS_BNEm, "bne-" },
+	{ PPC_INS_ALIAS_BNEAm, "bnea-" },
+	{ PPC_INS_ALIAS_BNELRm, "bnelr-" },
+	{ PPC_INS_ALIAS_BNECTRm, "bnectr-" },
+	{ PPC_INS_ALIAS_BNELm, "bnel-" },
+	{ PPC_INS_ALIAS_BNELAm, "bnela-" },
+	{ PPC_INS_ALIAS_BNELRLm, "bnelrl-" },
+	{ PPC_INS_ALIAS_BNECTRLm, "bnectrl-" },
+	{ PPC_INS_ALIAS_BNEp, "bne+" },
+	{ PPC_INS_ALIAS_BNEAp, "bnea+" },
+	{ PPC_INS_ALIAS_BNELRp, "bnelr+" },
+	{ PPC_INS_ALIAS_BNECTRp, "bnectr+" },
+	{ PPC_INS_ALIAS_BNELp, "bnel+" },
+	{ PPC_INS_ALIAS_BNELAp, "bnela+" },
+	{ PPC_INS_ALIAS_BNELRLp, "bnelrl+" },
+	{ PPC_INS_ALIAS_BNECTRLp, "bnectrl+" },
+	{ PPC_INS_ALIAS_BNU, "bnu" },
+	{ PPC_INS_ALIAS_BNUA, "bnua" },
+	{ PPC_INS_ALIAS_BNULR, "bnulr" },
+	{ PPC_INS_ALIAS_BNUCTR, "bnuctr" },
+	{ PPC_INS_ALIAS_BNUL, "bnul" },
+	{ PPC_INS_ALIAS_BNULA, "bnula" },
+	{ PPC_INS_ALIAS_BNULRL, "bnulrl" },
+	{ PPC_INS_ALIAS_BNUCTRL, "bnuctrl" },
+	{ PPC_INS_ALIAS_BNUm, "bnu-" },
+	{ PPC_INS_ALIAS_BNUAm, "bnua-" },
+	{ PPC_INS_ALIAS_BNULRm, "bnulr-" },
+	{ PPC_INS_ALIAS_BNUCTRm, "bnuctr-" },
+	{ PPC_INS_ALIAS_BNULm, "bnul-" },
+	{ PPC_INS_ALIAS_BNULAm, "bnula-" },
+	{ PPC_INS_ALIAS_BNULRLm, "bnulrl-" },
+	{ PPC_INS_ALIAS_BNUCTRLm, "bnuctrl-" },
+	{ PPC_INS_ALIAS_BNUp, "bnu+" },
+	{ PPC_INS_ALIAS_BNUAp, "bnua+" },
+	{ PPC_INS_ALIAS_BNULRp, "bnulr+" },
+	{ PPC_INS_ALIAS_BNUCTRp, "bnuctr+" },
+	{ PPC_INS_ALIAS_BNULp, "bnul+" },
+	{ PPC_INS_ALIAS_BNULAp, "bnula+" },
+	{ PPC_INS_ALIAS_BNULRLp, "bnulrl+" },
+	{ PPC_INS_ALIAS_BNUCTRLp, "bnuctrl+" },
+	{ PPC_INS_ALIAS_BNS, "bns" },
+	{ PPC_INS_ALIAS_BNSA, "bnsa" },
+	{ PPC_INS_ALIAS_BNSLR, "bnslr" },
+	{ PPC_INS_ALIAS_BNSCTR, "bnsctr" },
+	{ PPC_INS_ALIAS_BNSL, "bnsl" },
+	{ PPC_INS_ALIAS_BNSLA, "bnsla" },
+	{ PPC_INS_ALIAS_BNSLRL, "bnslrl" },
+	{ PPC_INS_ALIAS_BNSCTRL, "bnsctrl" },
+	{ PPC_INS_ALIAS_BNSm, "bns-" },
+	{ PPC_INS_ALIAS_BNSAm, "bnsa-" },
+	{ PPC_INS_ALIAS_BNSLRm, "bnslr-" },
+	{ PPC_INS_ALIAS_BNSCTRm, "bnsctr-" },
+	{ PPC_INS_ALIAS_BNSLm, "bnsl-" },
+	{ PPC_INS_ALIAS_BNSLAm, "bnsla-" },
+	{ PPC_INS_ALIAS_BNSLRLm, "bnslrl-" },
+	{ PPC_INS_ALIAS_BNSCTRLm, "bnsctrl-" },
+	{ PPC_INS_ALIAS_BNSp, "bns+" },
+	{ PPC_INS_ALIAS_BNSAp, "bnsa+" },
+	{ PPC_INS_ALIAS_BNSLRp, "bnslr+" },
+	{ PPC_INS_ALIAS_BNSCTRp, "bnsctr+" },
+	{ PPC_INS_ALIAS_BNSLp, "bnsl+" },
+	{ PPC_INS_ALIAS_BNSLAp, "bnsla+" },
+	{ PPC_INS_ALIAS_BNSLRLp, "bnslrl+" },
+	{ PPC_INS_ALIAS_BNSCTRLp, "bnsctrl+" },
+	{ PPC_INS_ALIAS_CMPWI, "cmpwi" },
+	{ PPC_INS_ALIAS_CMPW, "cmpw" },
+	{ PPC_INS_ALIAS_CMPLWI, "cmplwi" },
+	{ PPC_INS_ALIAS_CMPLW, "cmplw" },
+	{ PPC_INS_ALIAS_CMPDI, "cmpdi" },
+	{ PPC_INS_ALIAS_CMPD, "cmpd" },
+	{ PPC_INS_ALIAS_CMPLDI, "cmpldi" },
+	{ PPC_INS_ALIAS_CMPLD, "cmpld" },
+	{ PPC_INS_ALIAS_CMPI, "cmpi" },
+	{ PPC_INS_ALIAS_CMP, "cmp" },
+	{ PPC_INS_ALIAS_CMPLI, "cmpli" },
+	{ PPC_INS_ALIAS_CMPL, "cmpl" },
+	{ PPC_INS_ALIAS_TRAP, "trap" },
+	{ PPC_INS_ALIAS_TDLTI, "tdlti" },
+	{ PPC_INS_ALIAS_TDLT, "tdlt" },
+	{ PPC_INS_ALIAS_TWLTI, "twlti" },
+	{ PPC_INS_ALIAS_TWLT, "twlt" },
+	{ PPC_INS_ALIAS_TDLEI, "tdlei" },
+	{ PPC_INS_ALIAS_TDLE, "tdle" },
+	{ PPC_INS_ALIAS_TWLEI, "twlei" },
+	{ PPC_INS_ALIAS_TWLE, "twle" },
+	{ PPC_INS_ALIAS_TDEQI, "tdeqi" },
+	{ PPC_INS_ALIAS_TDEQ, "tdeq" },
+	{ PPC_INS_ALIAS_TWEQI, "tweqi" },
+	{ PPC_INS_ALIAS_TWEQ, "tweq" },
+	{ PPC_INS_ALIAS_TDGEI, "tdgei" },
+	{ PPC_INS_ALIAS_TDGE, "tdge" },
+	{ PPC_INS_ALIAS_TWGEI, "twgei" },
+	{ PPC_INS_ALIAS_TWGE, "twge" },
+	{ PPC_INS_ALIAS_TDGTI, "tdgti" },
+	{ PPC_INS_ALIAS_TDGT, "tdgt" },
+	{ PPC_INS_ALIAS_TWGTI, "twgti" },
+	{ PPC_INS_ALIAS_TWGT, "twgt" },
+	{ PPC_INS_ALIAS_TDNLI, "tdnli" },
+	{ PPC_INS_ALIAS_TDNL, "tdnl" },
+	{ PPC_INS_ALIAS_TWNLI, "twnli" },
+	{ PPC_INS_ALIAS_TWNL, "twnl" },
+	{ PPC_INS_ALIAS_TDNEI, "tdnei" },
+	{ PPC_INS_ALIAS_TDNE, "tdne" },
+	{ PPC_INS_ALIAS_TWNEI, "twnei" },
+	{ PPC_INS_ALIAS_TWNE, "twne" },
+	{ PPC_INS_ALIAS_TDNGI, "tdngi" },
+	{ PPC_INS_ALIAS_TDNG, "tdng" },
+	{ PPC_INS_ALIAS_TWNGI, "twngi" },
+	{ PPC_INS_ALIAS_TWNG, "twng" },
+	{ PPC_INS_ALIAS_TDLLTI, "tdllti" },
+	{ PPC_INS_ALIAS_TDLLT, "tdllt" },
+	{ PPC_INS_ALIAS_TWLLTI, "twllti" },
+	{ PPC_INS_ALIAS_TWLLT, "twllt" },
+	{ PPC_INS_ALIAS_TDLLEI, "tdllei" },
+	{ PPC_INS_ALIAS_TDLLE, "tdlle" },
+	{ PPC_INS_ALIAS_TWLLEI, "twllei" },
+	{ PPC_INS_ALIAS_TWLLE, "twlle" },
+	{ PPC_INS_ALIAS_TDLGEI, "tdlgei" },
+	{ PPC_INS_ALIAS_TDLGE, "tdlge" },
+	{ PPC_INS_ALIAS_TWLGEI, "twlgei" },
+	{ PPC_INS_ALIAS_TWLGE, "twlge" },
+	{ PPC_INS_ALIAS_TDLGTI, "tdlgti" },
+	{ PPC_INS_ALIAS_TDLGT, "tdlgt" },
+	{ PPC_INS_ALIAS_TWLGTI, "twlgti" },
+	{ PPC_INS_ALIAS_TWLGT, "twlgt" },
+	{ PPC_INS_ALIAS_TDLNLI, "tdlnli" },
+	{ PPC_INS_ALIAS_TDLNL, "tdlnl" },
+	{ PPC_INS_ALIAS_TWLNLI, "twlnli" },
+	{ PPC_INS_ALIAS_TWLNL, "twlnl" },
+	{ PPC_INS_ALIAS_TDLNGI, "tdlngi" },
+	{ PPC_INS_ALIAS_TDLNG, "tdlng" },
+	{ PPC_INS_ALIAS_TWLNGI, "twlngi" },
+	{ PPC_INS_ALIAS_TWLNG, "twlng" },
+	{ PPC_INS_ALIAS_TDUI, "tdui" },
+	{ PPC_INS_ALIAS_TDU, "tdu" },
+	{ PPC_INS_ALIAS_TWUI, "twui" },
+	{ PPC_INS_ALIAS_TWU, "twu" },
+	{ PPC_INS_ALIAS_PASTE_, "paste." },
+	{ PPC_INS_ALIAS_QVFCLR, "qvfclr" },
+	{ PPC_INS_ALIAS_QVFAND, "qvfand" },
+	{ PPC_INS_ALIAS_QVFANDC, "qvfandc" },
+	{ PPC_INS_ALIAS_QVFCTFB, "qvfctfb" },
+	{ PPC_INS_ALIAS_QVFXOR, "qvfxor" },
+	{ PPC_INS_ALIAS_QVFOR, "qvfor" },
+	{ PPC_INS_ALIAS_QVFNOR, "qvfnor" },
+	{ PPC_INS_ALIAS_QVFEQU, "qvfequ" },
+	{ PPC_INS_ALIAS_QVFNOT, "qvfnot" },
+	{ PPC_INS_ALIAS_QVFORC, "qvforc" },
+	{ PPC_INS_ALIAS_QVFNAND, "qvfnand" },
+	{ PPC_INS_ALIAS_QVFSET, "qvfset" },

thirdparty/capstone/arch/PowerPC/PPCGenCSFeatureName.inc

@@ -0,0 +1,32 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
+/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+{ PPC_FEATURE_IsNotISAFuture, "IsNotISAFuture" },
+{ PPC_FEATURE_IsISA3_0, "IsISA3_0" },
+{ PPC_FEATURE_In64BitMode, "In64BitMode" },
+{ PPC_FEATURE_In32BitMode, "In32BitMode" },
+{ PPC_FEATURE_PCRelativeMemops, "PCRelativeMemops" },
+{ PPC_FEATURE_HasBPERMD, "HasBPERMD" },
+{ PPC_FEATURE_HasSPE, "HasSPE" },
+{ PPC_FEATURE_IsE500, "IsE500" },
+{ PPC_FEATURE_IsPPC4xx, "IsPPC4xx" },
+{ PPC_FEATURE_HasExtDiv, "HasExtDiv" },
+{ PPC_FEATURE_IsISAFuture, "IsISAFuture" },
+{ PPC_FEATURE_HasFPU, "HasFPU" },
+{ PPC_FEATURE_HasICBT, "HasICBT" },
+{ PPC_FEATURE_HasPartwordAtomics, "HasPartwordAtomics" },
+{ PPC_FEATURE_IsISA2_06, "IsISA2_06" },
+{ PPC_FEATURE_IsBookE, "IsBookE" },
+{ PPC_FEATURE_HasPS, "HasPS" },
+{ PPC_FEATURE_HasQPX, "HasQPX" },
+{ PPC_FEATURE_IsPPC6xx, "IsPPC6xx" },

thirdparty/capstone/arch/PowerPC/PPCGenCSOpGroup.inc

@@ -0,0 +1,42 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+  PPC_OP_GROUP_S12ImmOperand = 0,
+  PPC_OP_GROUP_Operand = 1,
+  PPC_OP_GROUP_MemRegReg = 2,
+  PPC_OP_GROUP_U6ImmOperand = 3,
+  PPC_OP_GROUP_U5ImmOperand = 4,
+  PPC_OP_GROUP_MemRegImm = 5,
+  PPC_OP_GROUP_S16ImmOperand = 6,
+  PPC_OP_GROUP_U2ImmOperand = 7,
+  PPC_OP_GROUP_U16ImmOperand = 8,
+  PPC_OP_GROUP_BranchOperand = 9,
+  PPC_OP_GROUP_AbsBranchOperand = 10,
+  PPC_OP_GROUP_PredicateOperand = 11,
+  PPC_OP_GROUP_U1ImmOperand = 12,
+  PPC_OP_GROUP_TLSCall = 13,
+  PPC_OP_GROUP_U3ImmOperand = 14,
+  PPC_OP_GROUP_S5ImmOperand = 15,
+  PPC_OP_GROUP_MemRegImmHash = 16,
+  PPC_OP_GROUP_U4ImmOperand = 17,
+  PPC_OP_GROUP_U10ImmOperand = 18,
+  PPC_OP_GROUP_crbitm = 19,
+  PPC_OP_GROUP_S34ImmOperand = 20,
+  PPC_OP_GROUP_ImmZeroOperand = 21,
+  PPC_OP_GROUP_MemRegImm34 = 22,
+  PPC_OP_GROUP_MemRegImm34PCRel = 23,
+  PPC_OP_GROUP_U8ImmOperand = 24,
+  PPC_OP_GROUP_MemRegImmPS = 25,
+  PPC_OP_GROUP_U12ImmOperand = 26,
+  PPC_OP_GROUP_U7ImmOperand = 27,
+  PPC_OP_GROUP_ATBitsAsHint = 28,

thirdparty/capstone/arch/PowerPC/PPCGenSubtargetInfo.inc

@@ -0,0 +1,134 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
+/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+#ifdef GET_SUBTARGETINFO_ENUM
+#undef GET_SUBTARGETINFO_ENUM
+
+enum {
+  PPC_AIXOS = 0,
+  PPC_DeprecatedDST = 1,
+  PPC_Directive32 = 2,
+  PPC_Directive64 = 3,
+  PPC_Directive440 = 4,
+  PPC_Directive601 = 5,
+  PPC_Directive602 = 6,
+  PPC_Directive603 = 7,
+  PPC_Directive604 = 8,
+  PPC_Directive620 = 9,
+  PPC_Directive750 = 10,
+  PPC_Directive970 = 11,
+  PPC_Directive7400 = 12,
+  PPC_DirectiveA2 = 13,
+  PPC_DirectiveE500 = 14,
+  PPC_DirectiveE500mc = 15,
+  PPC_DirectiveE5500 = 16,
+  PPC_DirectivePwr3 = 17,
+  PPC_DirectivePwr4 = 18,
+  PPC_DirectivePwr5 = 19,
+  PPC_DirectivePwr5x = 20,
+  PPC_DirectivePwr6 = 21,
+  PPC_DirectivePwr6x = 22,
+  PPC_DirectivePwr7 = 23,
+  PPC_DirectivePwr8 = 24,
+  PPC_DirectivePwr9 = 25,
+  PPC_DirectivePwr10 = 26,
+  PPC_DirectivePwrFuture = 27,
+  PPC_Feature64Bit = 28,
+  PPC_Feature64BitRegs = 29,
+  PPC_FeatureAddLogicalFusion = 30,
+  PPC_FeatureAddiLoadFusion = 31,
+  PPC_FeatureAddisLoadFusion = 32,
+  PPC_FeatureAltivec = 33,
+  PPC_FeatureArithAddFusion = 34,
+  PPC_FeatureBPERMD = 35,
+  PPC_FeatureBack2BackFusion = 36,
+  PPC_FeatureBookE = 37,
+  PPC_FeatureCMPB = 38,
+  PPC_FeatureCRBits = 39,
+  PPC_FeatureCompareFusion = 40,
+  PPC_FeatureDirectMove = 41,
+  PPC_FeatureE500 = 42,
+  PPC_FeatureEFPU2 = 43,
+  PPC_FeatureExtDiv = 44,
+  PPC_FeatureFCPSGN = 45,
+  PPC_FeatureFPCVT = 46,
+  PPC_FeatureFPRND = 47,
+  PPC_FeatureFPU = 48,
+  PPC_FeatureFRE = 49,
+  PPC_FeatureFRES = 50,
+  PPC_FeatureFRSQRTE = 51,
+  PPC_FeatureFRSQRTES = 52,
+  PPC_FeatureFSqrt = 53,
+  PPC_FeatureFastMFLR = 54,
+  PPC_FeatureFloat128 = 55,
+  PPC_FeatureFusion = 56,
+  PPC_FeatureHTM = 57,
+  PPC_FeatureHardFloat = 58,
+  PPC_FeatureICBT = 59,
+  PPC_FeatureISA2_06 = 60,
+  PPC_FeatureISA2_07 = 61,
+  PPC_FeatureISA3_0 = 62,
+  PPC_FeatureISA3_1 = 63,
+  PPC_FeatureISAFuture = 64,
+  PPC_FeatureISEL = 65,
+  PPC_FeatureInvariantFunctionDescriptors = 66,
+  PPC_FeatureLDBRX = 67,
+  PPC_FeatureLFIWAX = 68,
+  PPC_FeatureLogicalAddFusion = 69,
+  PPC_FeatureLogicalFusion = 70,
+  PPC_FeatureLongCall = 71,
+  PPC_FeatureMFOCRF = 72,
+  PPC_FeatureMFTB = 73,
+  PPC_FeatureMMA = 74,
+  PPC_FeatureMSYNC = 75,
+  PPC_FeatureModernAIXAs = 76,
+  PPC_FeatureP8Altivec = 77,
+  PPC_FeatureP8Crypto = 78,
+  PPC_FeatureP8Vector = 79,
+  PPC_FeatureP9Altivec = 80,
+  PPC_FeatureP9Vector = 81,
+  PPC_FeatureP10Vector = 82,
+  PPC_FeaturePCRelativeMemops = 83,
+  PPC_FeaturePOPCNTD = 84,
+  PPC_FeaturePPC4xx = 85,
+  PPC_FeaturePPC6xx = 86,
+  PPC_FeaturePPCPostRASched = 87,
+  PPC_FeaturePPCPreRASched = 88,
+  PPC_FeaturePS = 89,
+  PPC_FeaturePairedVectorMemops = 90,
+  PPC_FeaturePartwordAtomic = 91,
+  PPC_FeaturePredictableSelectIsExpensive = 92,
+  PPC_FeaturePrefixInstrs = 93,
+  PPC_FeaturePrivileged = 94,
+  PPC_FeatureQPX = 95,
+  PPC_FeatureQuadwordAtomic = 96,
+  PPC_FeatureROPProtect = 97,
+  PPC_FeatureRecipPrec = 98,
+  PPC_FeatureSPE = 99,
+  PPC_FeatureSTFIWX = 100,
+  PPC_FeatureSecurePlt = 101,
+  PPC_FeatureSha3Fusion = 102,
+  PPC_FeatureSlowPOPCNTD = 103,
+  PPC_FeatureStoreFusion = 104,
+  PPC_FeatureTwoConstNR = 105,
+  PPC_FeatureUnalignedFloats = 106,
+  PPC_FeatureVSX = 107,
+  PPC_FeatureVectorsUseTwoUnits = 108,
+  PPC_FeatureWideImmFusion = 109,
+  PPC_FeatureZeroMoveFusion = 110,
+  PPC_NumSubtargetFeatures = 111
+};
+#endif // GET_SUBTARGETINFO_ENUM
+
+
+

thirdparty/capstone/arch/PowerPC/PPCInstPrinter.c

@@ -0,0 +1,755 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically translated source file from LLVM. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Only small edits allowed. */
+/* For multiple similar edits, please create a Patch for the translator. */
+
+/* Capstone's C++ file translator: */
+/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
+
+//===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This class prints an PPC MCInst to a .s file.
+//
+//===----------------------------------------------------------------------===//
+
+#include <capstone/platform.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "../../LEB128.h"
+#include "../../Mapping.h"
+#include "../../MCInst.h"
+#include "../../MCInstPrinter.h"
+#include "../../MCInstrDesc.h"
+#include "../../MCRegisterInfo.h"
+#include "PPCInstrInfo.h"
+#include "PPCInstPrinter.h"
+#include "PPCLinkage.h"
+#include "PPCMCTargetDesc.h"
+#include "PPCMapping.h"
+#include "PPCPredicates.h"
+#include "PPCRegisterInfo.h"
+
+#define CONCAT(a, b) CONCAT_(a, b)
+#define CONCAT_(a, b) a##_##b
+
+#define DEBUG_TYPE "asm-printer"
+
+// Static function declarations. These are functions which have the same identifiers
+// over all architectures. Therefor they need to be static.
+#ifndef CAPSTONE_DIET
+static void printCustomAliasOperand(MCInst *MI, uint64_t Address,
+				    unsigned OpIdx, unsigned PrintMethodIdx,
+				    SStream *O);
+#endif
+static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
+static void printPredicateOperand(MCInst *MI, unsigned OpNo, SStream *O,
+				  const char *Modifier);
+static void printInst(MCInst *MI, uint64_t Address, const char *Annot,
+		      SStream *O);
+
+#define PRINT_ALIAS_INSTR
+#include "PPCGenAsmWriter.inc"
+
+static void printInst(MCInst *MI, uint64_t Address, const char *Annot,
+		      SStream *O)
+{
+	bool isAlias = false;
+	bool useAliasDetails = false;
+	// Customize printing of the addis instruction on AIX. When an operand is a
+	// symbol reference, the instruction syntax is changed to look like a load
+	// operation, i.e:
+	//     Transform:  addis $rD, $rA, $src --> addis $rD, $src($rA).
+	if (PPC_getFeatureBits(MI->csh->mode, PPC_FeatureModernAIXAs) &&
+	    (MCInst_getOpcode(MI) == PPC_ADDIS8 ||
+	     MCInst_getOpcode(MI) == PPC_ADDIS) &&
+	    MCOperand_isExpr(MCInst_getOperand(MI, (2)))) {
+		SStream_concat0(O, "\taddis ");
+		printOperand(MI, 0, O);
+		SStream_concat0(O, ", ");
+		printOperand(MI, 2, O);
+		SStream_concat0(O, "(");
+		printOperand(MI, 1, O);
+		SStream_concat0(O, ")");
+		return;
+	}
+
+	// Check if the last operand is an expression with the variant kind
+	// VK_PPC_PCREL_OPT. If this is the case then this is a linker optimization
+	// relocation and the .reloc directive needs to be added.
+	unsigned LastOp = MCInst_getNumOperands(MI) - 1;
+	if (MCInst_getNumOperands(MI) > 1) {
+		MCOperand *Operand = MCInst_getOperand(MI, (LastOp));
+		if (MCOperand_isExpr(Operand)) {
+			assert(0 && "Expressions not supported.");
+		}
+	}
+
+	// Check for slwi/srwi mnemonics.
+	if (MCInst_getOpcode(MI) == PPC_RLWINM) {
+		unsigned char SH = MCOperand_getImm(MCInst_getOperand(MI, (2)));
+		unsigned char MB = MCOperand_getImm(MCInst_getOperand(MI, (3)));
+		unsigned char ME = MCOperand_getImm(MCInst_getOperand(MI, (4)));
+		bool useSubstituteMnemonic = false;
+		if (SH <= 31 && MB == 0 && ME == (31 - SH)) {
+			SStream_concat0(O, "slwi ");
+			useSubstituteMnemonic = true;
+		}
+		if (SH <= 31 && MB == (32 - SH) && ME == 31) {
+			SStream_concat0(O, "srwi ");
+			useSubstituteMnemonic = true;
+			SH = 32 - SH;
+		}
+		useAliasDetails |= map_use_alias_details(MI);
+		map_set_fill_detail_ops(MI, useAliasDetails &&
+						    useSubstituteMnemonic);
+		if (useSubstituteMnemonic) {
+			isAlias |= true;
+			MCInst_setIsAlias(MI, isAlias);
+
+			printOperand(MI, 0, O);
+			SStream_concat0(O, ", ");
+			printOperand(MI, 1, O);
+			SStream_concat(O, "%s", ", ");
+			printUInt32(O, (unsigned int)SH);
+			PPC_insert_detail_op_imm_at(MI, 2, SH, CS_AC_READ);
+
+			if (useAliasDetails)
+				return;
+		}
+	}
+
+	if (MCInst_getOpcode(MI) == PPC_RLDICR ||
+	    MCInst_getOpcode(MI) == PPC_RLDICR_32) {
+		unsigned char SH = MCOperand_getImm(MCInst_getOperand(MI, (2)));
+		unsigned char ME = MCOperand_getImm(MCInst_getOperand(MI, (3)));
+
+		useAliasDetails |= map_use_alias_details(MI);
+		map_set_fill_detail_ops(MI, useAliasDetails && 63 - SH == ME);
+		// rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
+		if (63 - SH == ME) {
+			isAlias |= true;
+			MCInst_setIsAlias(MI, isAlias);
+			SStream_concat0(O, "sldi ");
+			printOperand(MI, 0, O);
+			SStream_concat0(O, ", ");
+			printOperand(MI, 1, O);
+			SStream_concat(O, "%s", ", ");
+			printUInt32(O, (unsigned int)SH);
+			PPC_insert_detail_op_imm_at(MI, 2, SH, CS_AC_READ);
+
+			if (useAliasDetails)
+				return;
+		}
+	}
+
+	// dcbt[st] is printed manually here because:
+	//  1. The assembly syntax is different between embedded and server targets
+	//  2. We must print the short mnemonics for TH == 0 because the
+	//     embedded/server syntax default will not be stable across assemblers
+	//  The syntax for dcbt is:
+	//    dcbt ra, rb, th [server]
+	//    dcbt th, ra, rb [embedded]
+	//  where th can be omitted when it is 0. dcbtst is the same.
+	// On AIX, only emit the extended mnemonics for dcbt and dcbtst if
+	// the "modern assembler" is available.
+	if ((MCInst_getOpcode(MI) == PPC_DCBT ||
+	     MCInst_getOpcode(MI) == PPC_DCBTST) &&
+	    (!PPC_getFeatureBits(MI->csh->mode, PPC_FeatureModernAIXAs))) {
+		unsigned char TH = MCOperand_getImm(MCInst_getOperand(MI, (0)));
+		SStream_concat0(O, "\tdcbt");
+		if (MCInst_getOpcode(MI) == PPC_DCBTST)
+			SStream_concat0(O, "st");
+		if (TH == 16)
+			SStream_concat0(O, "t");
+		SStream_concat0(O, " ");
+
+		bool IsBookE =
+			PPC_getFeatureBits(MI->csh->mode, PPC_FeatureBookE);
+		if (IsBookE && TH != 0 && TH != 16) {
+			SStream_concat(O, "%s", (unsigned int)TH);
+			SStream_concat0(O, ", ");
+			PPC_set_detail_op_imm(MI, 0, TH);
+		}
+		set_mem_access(MI, true);
+		printOperand(MI, 1, O);
+		SStream_concat0(O, ", ");
+		printOperand(MI, 2, O);
+		set_mem_access(MI, false);
+
+		if (!IsBookE && TH != 0 && TH != 16) {
+			SStream_concat(O, "%s", ", ");
+			printUInt32(O, (unsigned int)TH);
+			PPC_set_detail_op_imm(MI, 0, TH);
+		}
+
+		return;
+	}
+
+	if (MCInst_getOpcode(MI) == PPC_DCBF) {
+		unsigned char L = MCOperand_getImm(MCInst_getOperand(MI, (0)));
+		if (!L || L == 1 || L == 3 || L == 4 || L == 6) {
+			SStream_concat0(O, "\tdcb");
+			if (L != 6)
+				SStream_concat0(O, "f");
+			if (L == 1)
+				SStream_concat0(O, "l");
+			if (L == 3)
+				SStream_concat0(O, "lp");
+			if (L == 4)
+				SStream_concat0(O, "ps");
+			if (L == 6)
+				SStream_concat0(O, "stps");
+			SStream_concat0(O, " ");
+
+			printOperand(MI, 1, O);
+			SStream_concat0(O, ", ");
+			printOperand(MI, 2, O);
+
+			return;
+		}
+	}
+
+	// isAlias/useAliasDetails could have been set before.
+	useAliasDetails |= map_use_alias_details(MI);
+	map_set_fill_detail_ops(MI, useAliasDetails);
+	isAlias |= printAliasInstr(MI, Address, O);
+	MCInst_setIsAlias(MI, isAlias);
+
+	if (!isAlias || !useAliasDetails) {
+		map_set_fill_detail_ops(MI, true);
+		if (isAlias)
+			SStream_Close(O);
+		printInstruction(MI, Address, O);
+		if (isAlias)
+			SStream_Open(O);
+	}
+}
+
+void printPredicateOperand(MCInst *MI, unsigned OpNo, SStream *O,
+			   const char *Modifier)
+{
+	add_cs_detail(MI, PPC_OP_GROUP_PredicateOperand, OpNo, Modifier);
+	unsigned Code = MCOperand_getImm(MCInst_getOperand(MI, (OpNo)));
+
+	if (strcmp(Modifier, "cc") == 0) {
+		switch ((PPC_Predicate)Code) {
+		default:
+			assert(0 && "Invalid predicate code");
+		case PPC_PRED_LT_MINUS:
+		case PPC_PRED_LT_PLUS:
+		case PPC_PRED_LT:
+			SStream_concat0(O, "lt");
+			return;
+		case PPC_PRED_LE_MINUS:
+		case PPC_PRED_LE_PLUS:
+		case PPC_PRED_LE:
+			SStream_concat0(O, "le");
+			return;
+		case PPC_PRED_EQ_MINUS:
+		case PPC_PRED_EQ_PLUS:
+		case PPC_PRED_EQ:
+			SStream_concat0(O, "eq");
+			return;
+		case PPC_PRED_GE_MINUS:
+		case PPC_PRED_GE_PLUS:
+		case PPC_PRED_GE:
+			SStream_concat0(O, "ge");
+			return;
+		case PPC_PRED_GT_MINUS:
+		case PPC_PRED_GT_PLUS:
+		case PPC_PRED_GT:
+			SStream_concat0(O, "gt");
+			return;
+		case PPC_PRED_NE_MINUS:
+		case PPC_PRED_NE_PLUS:
+		case PPC_PRED_NE:
+			SStream_concat0(O, "ne");
+			return;
+		case PPC_PRED_UN_MINUS:
+		case PPC_PRED_UN_PLUS:
+		case PPC_PRED_UN:
+			SStream_concat0(O, "un");
+			return;
+		case PPC_PRED_NU_MINUS:
+		case PPC_PRED_NU_PLUS:
+		case PPC_PRED_NU:
+			SStream_concat0(O, "nu");
+			return;
+		case PPC_PRED_BIT_SET:
+		case PPC_PRED_BIT_UNSET:
+			assert(0 && "Invalid use of bit predicate code");
+		}
+		assert(0 && "Invalid predicate code");
+	}
+
+	if (strcmp(Modifier, "pm") == 0) {
+		switch ((PPC_Predicate)Code) {
+		default:
+			assert(0 && "Invalid predicate code");
+		case PPC_PRED_LT:
+		case PPC_PRED_LE:
+		case PPC_PRED_EQ:
+		case PPC_PRED_GE:
+		case PPC_PRED_GT:
+		case PPC_PRED_NE:
+		case PPC_PRED_UN:
+		case PPC_PRED_NU:
+			return;
+		case PPC_PRED_LT_MINUS:
+		case PPC_PRED_LE_MINUS:
+		case PPC_PRED_EQ_MINUS:
+		case PPC_PRED_GE_MINUS:
+		case PPC_PRED_GT_MINUS:
+		case PPC_PRED_NE_MINUS:
+		case PPC_PRED_UN_MINUS:
+		case PPC_PRED_NU_MINUS:
+			SStream_concat0(O, "-");
+			return;
+		case PPC_PRED_LT_PLUS:
+		case PPC_PRED_LE_PLUS:
+		case PPC_PRED_EQ_PLUS:
+		case PPC_PRED_GE_PLUS:
+		case PPC_PRED_GT_PLUS:
+		case PPC_PRED_NE_PLUS:
+		case PPC_PRED_UN_PLUS:
+		case PPC_PRED_NU_PLUS:
+			SStream_concat0(O, "+");
+			return;
+		case PPC_PRED_BIT_SET:
+		case PPC_PRED_BIT_UNSET:
+			assert(0 && "Invalid use of bit predicate code");
+		}
+		assert(0 && "Invalid predicate code");
+	}
+
+	printOperand(MI, OpNo + 1, O);
+}
+
+void printATBitsAsHint(MCInst *MI, unsigned OpNo, SStream *O)
+{
+	add_cs_detail(MI, PPC_OP_GROUP_ATBitsAsHint, OpNo);
+	unsigned Code = MCOperand_getImm(MCInst_getOperand(MI, (OpNo)));
+	if (Code == 2)
+		SStream_concat0(O, "-");
+	else if (Code == 3)
+		SStream_concat0(O, "+");
+}
+
+void printU1ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
+{
+	add_cs_detail(MI, PPC_OP_GROUP_U1ImmOperand, OpNo);
+	unsigned int Value = MCOperand_getImm(MCInst_getOperand(MI, (OpNo)));
+
+	printUInt32(O, (unsigned int)Value);
+}
+
+void printU2ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
+{
+	add_cs_detail(MI, PPC_OP_GROUP_U2ImmOperand, OpNo);
+	unsigned int Value = MCOperand_getImm(MCInst_getOperand(MI, (OpNo)));
+
+	printUInt32(O, (unsigned int)Value);
+}
+
+void printU3ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
+{
+	add_cs_detail(MI, PPC_OP_GROUP_U3ImmOperand, OpNo);
+	unsigned int Value = MCOperand_getImm(MCInst_getOperand(MI, (OpNo)));
+
+	printUInt32(O, (unsigned int)Value);
+}
+
+void printU4ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
+{
+	add_cs_detail(MI, PPC_OP_GROUP_U4ImmOperand, OpNo);
+	unsigned int Value = MCOperand_getImm(MCInst_getOperand(MI, (OpNo)));
+
+	printUInt32(O, (unsigned int)Value);
+}
+
+void printS5ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
+{
+	add_cs_detail(MI, PPC_OP_GROUP_S5ImmOperand, OpNo);
+	int Value = MCOperand_getImm(MCInst_getOperand(MI, (OpNo)));
+	Value = SignExtend32((Value), 5);
+	printInt32(O, (int)Value);
+}
+
+void printImmZeroOperand(MCInst *MI, unsigned OpNo, SStream *O)
+{
+	add_cs_detail(MI, PPC_OP_GROUP_ImmZeroOperand, OpNo);
+	unsigned int Value = MCOperand_getImm(MCInst_getOperand(MI, (OpNo)));
+
+	printUInt32(O, (unsigned int)Value);
+}
+
+void printU5ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
+{
+	add_cs_detail(MI, PPC_OP_GROUP_U5ImmOperand, OpNo);
+	unsigned int Value = MCOperand_getImm(MCInst_getOperand(MI, (OpNo)));
+
+	printUInt32(O, (unsigned int)Value);
+}
+
+void printU6ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
+{
+	add_cs_detail(MI, PPC_OP_GROUP_U6ImmOperand, OpNo);
+	unsigned int Value = MCOperand_getImm(MCInst_getOperand(MI, (OpNo)));
+
+	printUInt32(O, (unsigned int)Value);
+}
+
+void printU7ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
+{
+	add_cs_detail(MI, PPC_OP_GROUP_U7ImmOperand, OpNo);
+	unsigned int Value = MCOperand_getImm(MCInst_getOperand(MI, (OpNo)));
+
+	printUInt32(O, (unsigned int)Value);
+}
+
+// Operands of BUILD_VECTOR are signed and we use this to print operands
+// of XXSPLTIB which are unsigned. So we simply truncate to 8 bits and
+// print as unsigned.
+void printU8ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
+{
+	add_cs_detail(MI, PPC_OP_GROUP_U8ImmOperand, OpNo);
+	unsigned char Value = MCOperand_getImm(MCInst_getOperand(MI, (OpNo)));
+	printUInt32(O, (unsigned int)Value);
+}
+
+void printU10ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
+{
+	add_cs_detail(MI, PPC_OP_GROUP_U10ImmOperand, OpNo);
+	unsigned short Value = MCOperand_getImm(MCInst_getOperand(MI, (OpNo)));
+
+	printUInt32(O, (unsigned short)Value);
+}
+
+void printU12ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
+{
+	add_cs_detail(MI, PPC_OP_GROUP_U12ImmOperand, OpNo);
+	unsigned short Value = MCOperand_getImm(MCInst_getOperand(MI, (OpNo)));
+
+	printUInt32(O, (unsigned short)Value);
+}
+
+void printS12ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
+{
+	add_cs_detail(MI, PPC_OP_GROUP_S12ImmOperand, OpNo);
+	if (MCOperand_isImm(MCInst_getOperand(MI, OpNo))) {
+		int Imm = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
+		Imm = SignExtend32(Imm, 12);
+		printInt32(O, Imm);
+	} else
+		printOperand(MI, OpNo, O);
+}
+
+void printMemRegImmPS(MCInst *MI, unsigned OpNo, SStream *O)
+{
+	set_mem_access(MI, true);
+
+	printS12ImmOperand(MI, OpNo, O);
+	SStream_concat0(O, "(");
+	printOperand(MI, OpNo + 1, O);
+	SStream_concat0(O, ")");
+
+	set_mem_access(MI, false);
+}
+
+void printS16ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
+{
+	add_cs_detail(MI, PPC_OP_GROUP_S16ImmOperand, OpNo);
+	if (MCOperand_isImm(MCInst_getOperand(MI, (OpNo))))
+		printInt32(O, (short)MCOperand_getImm(
+				      MCInst_getOperand(MI, (OpNo))));
+	else
+		printOperand(MI, OpNo, O);
+}
+
+void printS34ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
+{
+	add_cs_detail(MI, PPC_OP_GROUP_S34ImmOperand, OpNo);
+	if (MCOperand_isImm(MCInst_getOperand(MI, (OpNo)))) {
+		long long Value =
+			MCOperand_getImm(MCInst_getOperand(MI, (OpNo)));
+
+		printInt64(O, (long long)Value);
+	} else
+		printOperand(MI, OpNo, O);
+}
+
+void printU16ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
+{
+	add_cs_detail(MI, PPC_OP_GROUP_U16ImmOperand, OpNo);
+	if (MCOperand_isImm(MCInst_getOperand(MI, (OpNo))))
+		printUInt32(O, (unsigned short)MCOperand_getImm(
+				       MCInst_getOperand(MI, (OpNo))));
+	else
+		printOperand(MI, OpNo, O);
+}
+
+void printBranchOperand(MCInst *MI, uint64_t Address, unsigned OpNo, SStream *O)
+{
+	add_cs_detail(MI, PPC_OP_GROUP_BranchOperand, OpNo);
+	if (!MCOperand_isImm(MCInst_getOperand(MI, (OpNo)))) {
+		printOperand(MI, OpNo, O);
+		return;
+	}
+	int32_t Imm = SignExtend32(
+		((unsigned)MCOperand_getImm(MCInst_getOperand(MI, (OpNo)))
+		 << 2),
+		32);
+	if (!MI->csh->PrintBranchImmNotAsAddress) {
+		uint64_t Target = Address + Imm;
+		if (!IS_64BIT(MI->csh->mode))
+			Target &= 0xffffffff;
+		printUInt64(O, (Target));
+	} else {
+		// Branches can take an immediate operand. This is used by the branch
+		// selection pass to print, for example `.+8` (for ELF) or `$+8` (for
+		// AIX) to express an eight byte displacement from the program counter.
+		if (!PPC_getFeatureBits(MI->csh->mode, PPC_FeatureModernAIXAs))
+			SStream_concat0(O, ".");
+		else
+			SStream_concat0(O, "$");
+
+		if (Imm >= 0)
+			SStream_concat0(O, "+");
+		printInt32(O, Imm);
+	}
+}
+
+void printAbsBranchOperand(MCInst *MI, unsigned OpNo, SStream *O)
+{
+	add_cs_detail(MI, PPC_OP_GROUP_AbsBranchOperand, OpNo);
+	if (!MCOperand_isImm(MCInst_getOperand(MI, (OpNo)))) {
+		printOperand(MI, OpNo, O);
+		return;
+	}
+
+	printInt32(O, SignExtend32(((unsigned)MCOperand_getImm(
+					    MCInst_getOperand(MI, (OpNo)))
+				    << 2),
+				   32));
+}
+
+void printcrbitm(MCInst *MI, unsigned OpNo, SStream *O)
+{
+	add_cs_detail(MI, PPC_OP_GROUP_crbitm, OpNo);
+	unsigned CCReg = MCOperand_getReg(MCInst_getOperand(MI, (OpNo)));
+	unsigned RegNo;
+	switch (CCReg) {
+	default:
+		assert(0 && "Unknown CR register");
+	case PPC_CR0:
+		RegNo = 0;
+		break;
+	case PPC_CR1:
+		RegNo = 1;
+		break;
+	case PPC_CR2:
+		RegNo = 2;
+		break;
+	case PPC_CR3:
+		RegNo = 3;
+		break;
+	case PPC_CR4:
+		RegNo = 4;
+		break;
+	case PPC_CR5:
+		RegNo = 5;
+		break;
+	case PPC_CR6:
+		RegNo = 6;
+		break;
+	case PPC_CR7:
+		RegNo = 7;
+		break;
+	}
+	printUInt32(O, (0x80 >> RegNo));
+}
+
+void printMemRegImm(MCInst *MI, unsigned OpNo, SStream *O)
+{
+	set_mem_access(MI, true);
+	add_cs_detail(MI, PPC_OP_GROUP_MemRegImm, OpNo);
+	printS16ImmOperand(MI, OpNo, O);
+	SStream_concat0(O, "(");
+
+	if (MCOperand_getReg(MCInst_getOperand(MI, (OpNo + 1))) == PPC_R0)
+		SStream_concat0(O, "0");
+	else
+		printOperand(MI, OpNo + 1, O);
+	SStream_concat0(O, ")");
+	set_mem_access(MI, false);
+}
+
+void printMemRegImmHash(MCInst *MI, unsigned OpNo, SStream *O)
+{
+	set_mem_access(MI, true);
+	add_cs_detail(MI, PPC_OP_GROUP_MemRegImmHash, OpNo);
+	printInt32(O, MCOperand_getImm(MCInst_getOperand(MI, (OpNo))));
+	SStream_concat0(O, "(");
+
+	printOperand(MI, OpNo + 1, O);
+	SStream_concat0(O, ")");
+	set_mem_access(MI, false);
+}
+
+void printMemRegImm34PCRel(MCInst *MI, unsigned OpNo, SStream *O)
+{
+	set_mem_access(MI, true);
+	add_cs_detail(MI, PPC_OP_GROUP_MemRegImm34PCRel, OpNo);
+	printS34ImmOperand(MI, OpNo, O);
+	SStream_concat0(O, "(");
+
+	printImmZeroOperand(MI, OpNo + 1, O);
+	SStream_concat0(O, ")");
+	set_mem_access(MI, false);
+}
+
+void printMemRegImm34(MCInst *MI, unsigned OpNo, SStream *O)
+{
+	set_mem_access(MI, true);
+	add_cs_detail(MI, PPC_OP_GROUP_MemRegImm34, OpNo);
+	printS34ImmOperand(MI, OpNo, O);
+	SStream_concat0(O, "(");
+
+	printOperand(MI, OpNo + 1, O);
+	SStream_concat0(O, ")");
+	set_mem_access(MI, false);
+}
+
+void printMemRegReg(MCInst *MI, unsigned OpNo, SStream *O)
+{
+	set_mem_access(MI, true);
+	add_cs_detail(MI, PPC_OP_GROUP_MemRegReg, OpNo);
+	// When used as the base register, r0 reads constant zero rather than
+	// the value contained in the register.  For this reason, the darwin
+	// assembler requires that we print r0 as 0 (no r) when used as the base.
+	if (MCOperand_getReg(MCInst_getOperand(MI, (OpNo))) == PPC_R0)
+		SStream_concat0(O, "0");
+	else
+		printOperand(MI, OpNo, O);
+	SStream_concat0(O, ", ");
+	printOperand(MI, OpNo + 1, O);
+	set_mem_access(MI, false);
+}
+
+void printTLSCall(MCInst *MI, unsigned OpNo, SStream *O)
+{
+	add_cs_detail(MI, PPC_OP_GROUP_TLSCall, OpNo);
+
+	// Expression logic removed.
+
+	set_mem_access(MI, true);
+	SStream_concat0(O, "(");
+
+	printOperand(MI, OpNo + 1, O);
+	SStream_concat0(O, ")");
+	set_mem_access(MI, false);
+}
+
+/// showRegistersWithPercentPrefix - Check if this register name should be
+/// printed with a percentage symbol as prefix.
+bool showRegistersWithPercentPrefix(const MCInst *MI, const char *RegName)
+{
+	if ((MI->csh->syntax & CS_OPT_SYNTAX_NOREGNAME) ||
+	    !(MI->csh->syntax & CS_OPT_SYNTAX_PERCENT) ||
+	    PPC_getFeatureBits(MI->csh->mode, PPC_FeatureModernAIXAs))
+		return false;
+
+	switch (RegName[0]) {
+	default:
+		return false;
+	case 'r':
+	case 'f':
+	case 'q':
+	case 'v':
+	case 'c':
+		return true;
+	}
+}
+
+/// getVerboseConditionalRegName - This method expands the condition register
+/// when requested explicitly or targeting Darwin.
+const char *getVerboseConditionRegName(const MCInst *MI, unsigned RegNum,
+				       unsigned RegEncoding)
+{
+	if (MI->csh->syntax & CS_OPT_SYNTAX_NOREGNAME)
+		return NULL;
+	if (RegNum < PPC_CR0EQ || RegNum > PPC_CR7UN)
+		return NULL;
+	const char *CRBits[] = {
+		"lt",	    "gt",	"eq",	    "un",	"4*cr1+lt",
+		"4*cr1+gt", "4*cr1+eq", "4*cr1+un", "4*cr2+lt", "4*cr2+gt",
+		"4*cr2+eq", "4*cr2+un", "4*cr3+lt", "4*cr3+gt", "4*cr3+eq",
+		"4*cr3+un", "4*cr4+lt", "4*cr4+gt", "4*cr4+eq", "4*cr4+un",
+		"4*cr5+lt", "4*cr5+gt", "4*cr5+eq", "4*cr5+un", "4*cr6+lt",
+		"4*cr6+gt", "4*cr6+eq", "4*cr6+un", "4*cr7+lt", "4*cr7+gt",
+		"4*cr7+eq", "4*cr7+un"
+	};
+	return CRBits[RegEncoding];
+}
+
+// showRegistersWithPrefix - This method determines whether registers
+// should be number-only or include the prefix.
+bool showRegistersWithPrefix(const MCInst *MI)
+{
+	return !(MI->csh->syntax & CS_OPT_SYNTAX_NOREGNAME);
+}
+
+void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
+{
+	add_cs_detail(MI, PPC_OP_GROUP_Operand, OpNo);
+	MCOperand *Op = MCInst_getOperand(MI, (OpNo));
+	if (MCOperand_isReg(Op)) {
+		unsigned Reg = MCOperand_getReg(Op);
+		if (!MI->csh->ShowVSRNumsAsVR)
+			Reg = PPCInstrInfo_getRegNumForOperand(
+				&PPCInsts[MCInst_getOpcode(MI)], Reg, OpNo);
+
+		const char *RegName;
+		RegName = getVerboseConditionRegName(
+			MI, Reg, MI->MRI->RegEncodingTable[Reg]);
+		if (RegName == NULL)
+			RegName = getRegisterName(Reg);
+		if (showRegistersWithPercentPrefix(MI, RegName))
+			SStream_concat0(O, "%");
+		if (!showRegistersWithPrefix(MI))
+			RegName = PPCRegisterInfo_stripRegisterPrefix(RegName);
+
+		SStream_concat0(O, RegName);
+		return;
+	}
+
+	if (MCOperand_isImm(Op)) {
+		printInt64(O, MCOperand_getImm(Op));
+		return;
+	}
+}
+
+const char *PPC_LLVM_getRegisterName(unsigned RegNo)
+{
+	return getRegisterName(RegNo);
+}
+
+void PPC_LLVM_printInst(MCInst *MI, uint64_t Address, const char *Annot,
+			SStream *O)
+{
+	printInst(MI, Address, Annot, O);
+}

thirdparty/capstone/arch/PowerPC/PPCInstPrinter.h

@@ -0,0 +1,79 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically translated source file from LLVM. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Only small edits allowed. */
+/* For multiple similar edits, please create a Patch for the translator. */
+
+/* Capstone's C++ file translator: */
+/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
+
+//===- PPCInstPrinter.h - Convert PPC MCInst to assembly syntax -*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This class prints an PPC MCInst to a .s file.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef CS_PPC_INSTPRINTER_H
+#define CS_PPC_INSTPRINTER_H
+
+#include <capstone/platform.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "../../LEB128.h"
+#include "../../MCDisassembler.h"
+#include "../../MCInst.h"
+#include "../../MCInstrDesc.h"
+#include "../../MCRegisterInfo.h"
+#include "../../SStream.h"
+#include "PPCMCTargetDesc.h"
+#define CONCAT(a, b) CONCAT_(a, b)
+#define CONCAT_(a, b) a##_##b
+
+bool showRegistersWithPercentPrefix(const MCInst *MI, const char *RegName);
+bool showRegistersWithPrefix(const MCInst *MI);
+// Autogenerated by tblgen.
+void printATBitsAsHint(MCInst *MI, unsigned OpNo, SStream *O);
+void printU1ImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
+void printU2ImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
+void printU3ImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
+void printU4ImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
+void printS5ImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
+void printU5ImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
+void printU6ImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
+void printU7ImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
+void printU8ImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
+void printU10ImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
+void printU12ImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
+void printS12ImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
+void printS16ImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
+void printS34ImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
+void printU16ImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
+void printImmZeroOperand(MCInst *MI, unsigned OpNo, SStream *O);
+void printBranchOperand(MCInst *MI, uint64_t Address, unsigned OpNo,
+			SStream *O);
+void printAbsBranchOperand(MCInst *MI, unsigned OpNo, SStream *O);
+void printTLSCall(MCInst *MI, unsigned OpNo, SStream *O);
+void printcrbitm(MCInst *MI, unsigned OpNo, SStream *O);
+void printMemRegImm(MCInst *MI, unsigned OpNo, SStream *O);
+void printMemRegImmPS(MCInst *MI, unsigned OpNo, SStream *O);
+void printMemRegImmHash(MCInst *MI, unsigned OpNo, SStream *O);
+void printMemRegImm34PCRel(MCInst *MI, unsigned OpNo, SStream *O);
+void printMemRegImm34(MCInst *MI, unsigned OpNo, SStream *O);
+void printMemRegReg(MCInst *MI, unsigned OpNo, SStream *O);
+;
+// end namespace llvm
+
+#endif // CS_PPC_INSTPRINTER_H

thirdparty/capstone/arch/PowerPC/PPCInstrInfo.h

@@ -0,0 +1,53 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Rot127 <unisono@quyllur.org> 2022-2023 */
+
+#ifndef CS_PPC_INSTRINFO_H
+#define CS_PPC_INSTRINFO_H
+
+#include "PPCMCTargetDesc.h"
+
+extern const MCInstrDesc PPCInsts[];
+
+static bool isVFRegister(unsigned Reg)
+{
+	return Reg >= PPC_VF0 && Reg <= PPC_VF31;
+}
+static bool isVRRegister(unsigned Reg)
+{
+	return Reg >= PPC_V0 && Reg <= PPC_V31;
+}
+
+/// getRegNumForOperand - some operands use different numbering schemes
+/// for the same registers. For example, a VSX instruction may have any of
+/// vs0-vs63 allocated whereas an Altivec instruction could only have
+/// vs32-vs63 allocated (numbered as v0-v31). This function returns the actual
+/// register number needed for the opcode/operand number combination.
+/// The operand number argument will be useful when we need to extend this
+/// to instructions that use both Altivec and VSX numbering (for different
+/// operands).
+static unsigned PPCInstrInfo_getRegNumForOperand(const MCInstrDesc *Desc,
+						 unsigned Reg, unsigned OpNo)
+{
+	int16_t regClass = Desc->OpInfo[OpNo].RegClass;
+	switch (regClass) {
+	// We store F0-F31, VF0-VF31 in MCOperand and it should be F0-F31,
+	// VSX32-VSX63 during encoding/disassembling
+	case PPC_VSSRCRegClassID:
+	case PPC_VSFRCRegClassID:
+		if (isVFRegister(Reg))
+			return PPC_VSX32 + (Reg - PPC_VF0);
+		break;
+	// We store VSL0-VSL31, V0-V31 in MCOperand and it should be VSL0-VSL31,
+	// VSX32-VSX63 during encoding/disassembling
+	case PPC_VSRCRegClassID:
+		if (isVRRegister(Reg))
+			return PPC_VSX32 + (Reg - PPC_V0);
+		break;
+	// Other RegClass doesn't need mapping
+	default:
+		break;
+	}
+	return Reg;
+}
+
+#endif // CS_PPC_INSTRINFO_H

thirdparty/capstone/arch/PowerPC/PPCLinkage.h

@@ -0,0 +1,22 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+
+#ifndef CS_PPC_LINKAGE_H
+#define CS_PPC_LINKAGE_H
+
+// Function definitions to call static LLVM functions.
+
+#include "../../MCDisassembler.h"
+#include "../../MCInst.h"
+#include "../../MCRegisterInfo.h"
+#include "../../SStream.h"
+#include "capstone/capstone.h"
+
+DecodeStatus PPC_LLVM_getInstruction(csh handle, const uint8_t *Bytes,
+				     size_t ByteLen, MCInst *MI, uint16_t *Size,
+				     uint64_t Address, void *Info);
+const char *PPC_LLVM_getRegisterName(unsigned RegNo);
+void PPC_LLVM_printInst(MCInst *MI, uint64_t Address, const char *Annot,
+			SStream *O);
+
+#endif // CS_PPC_LINKAGE_H

thirdparty/capstone/arch/PowerPC/PPCMCTargetDesc.h

@@ -0,0 +1,222 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically translated source file from LLVM. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Only small edits allowed. */
+/* For multiple similar edits, please create a Patch for the translator. */
+
+/* Capstone's C++ file translator: */
+/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
+
+//===-- PPCMCTargetDesc.h - PowerPC Target Descriptions ---------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file provides PowerPC specific target descriptions.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef CS_PPC_MCTARGETDESC_H
+#define CS_PPC_MCTARGETDESC_H
+
+// GCC #defines PPC on Linux but we use it as our namespace name
+#undef PPC
+
+#include <capstone/platform.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "../../LEB128.h"
+#include "../../MathExtras.h"
+#include "../../MCInst.h"
+#include "../../MCInstrDesc.h"
+#include "../../MCRegisterInfo.h"
+#define CONCAT(a, b) CONCAT_(a, b)
+#define CONCAT_(a, b) a##_##b
+
+/// Returns true iff Val consists of one contiguous run of 1s with any number of
+/// 0s on either side.  The 1s are allowed to wrap from LSB to MSB, so
+/// 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs.  0x0F0F0000 is not,
+/// since all 1s are not contiguous.
+static inline bool isRunOfOnes(unsigned Val, unsigned *MB, unsigned *ME)
+{
+	if (!Val)
+		return false;
+
+	if (isShiftedMask_32(Val)) {
+		// look for the first non-zero bit
+		*MB = countLeadingZeros(Val);
+		// look for the first zero bit after the run of ones
+		*ME = countLeadingZeros((Val - 1) ^ Val);
+		return true;
+	} else {
+		Val = ~Val; // invert mask
+		if (isShiftedMask_32(Val)) {
+			// effectively look for the first zero bit
+			*ME = countLeadingZeros(Val) - 1;
+			// effectively look for the first one bit after the run of zeros
+			*MB = countLeadingZeros((Val - 1) ^ Val) + 1;
+			return true;
+		}
+	}
+	// no run present
+	return false;
+}
+
+static inline bool isRunOfOnes64(uint64_t Val, unsigned *MB, unsigned *ME)
+{
+	if (!Val)
+		return false;
+
+	if (isShiftedMask_64(Val)) {
+		// look for the first non-zero bit
+		*MB = countLeadingZeros(Val);
+		// look for the first zero bit after the run of ones
+		*ME = countLeadingZeros((Val - 1) ^ Val);
+		return true;
+	} else {
+		Val = ~Val; // invert mask
+		if (isShiftedMask_64(Val)) {
+			// effectively look for the first zero bit
+			*ME = countLeadingZeros(Val) - 1;
+			// effectively look for the first one bit after the run of zeros
+			*MB = countLeadingZeros((Val - 1) ^ Val) + 1;
+			return true;
+		}
+	}
+	// no run present
+	return false;
+}
+
+// end namespace llvm
+
+// Generated files will use "namespace PPC". To avoid symbol clash,
+// undefine PPC here. PPC may be predefined on some hosts.
+#undef PPC
+
+// Defines symbolic names for PowerPC registers.  This defines a mapping from
+// register name to register number.
+//
+#define GET_REGINFO_ENUM
+#include "PPCGenRegisterInfo.inc"
+
+// Defines symbolic names for the PowerPC instructions.
+//
+#define GET_INSTRINFO_ENUM
+#define GET_INSTRINFO_SCHED_ENUM
+#define GET_INSTRINFO_MC_HELPER_DECLS
+#define GET_INSTRINFO_MC_DESC
+#include "PPCGenInstrInfo.inc"
+
+#define GET_SUBTARGETINFO_ENUM
+#include "PPCGenSubtargetInfo.inc"
+
+#define PPC_REGS0_7(X) \
+	{ \
+		X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7 \
+	}
+
+#define PPC_REGS0_31(X) \
+	{ \
+		X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, \
+			X##10, X##11, X##12, X##13, X##14, X##15, X##16, \
+			X##17, X##18, X##19, X##20, X##21, X##22, X##23, \
+			X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31 \
+	}
+
+#define PPC_REGS0_63(X) \
+	{ \
+		X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, \
+			X##10, X##11, X##12, X##13, X##14, X##15, X##16, \
+			X##17, X##18, X##19, X##20, X##21, X##22, X##23, \
+			X##24, X##25, X##26, X##27, X##28, X##29, X##30, \
+			X##31, X##32, X##33, X##34, X##35, X##36, X##37, \
+			X##38, X##39, X##40, X##41, X##42, X##43, X##44, \
+			X##45, X##46, X##47, X##48, X##49, X##50, X##51, \
+			X##52, X##53, X##54, X##55, X##56, X##57, X##58, \
+			X##59, X##60, X##61, X##62, X##63 \
+	}
+
+#define PPC_REGS_NO0_31(Z, X) \
+	{ \
+		Z, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, \
+			X##10, X##11, X##12, X##13, X##14, X##15, X##16, \
+			X##17, X##18, X##19, X##20, X##21, X##22, X##23, \
+			X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31 \
+	}
+
+#define PPC_REGS_LO_HI(LO, HI) \
+	{ \
+		LO##0, LO##1, LO##2, LO##3, LO##4, LO##5, LO##6, LO##7, LO##8, \
+			LO##9, LO##10, LO##11, LO##12, LO##13, LO##14, LO##15, \
+			LO##16, LO##17, LO##18, LO##19, LO##20, LO##21, \
+			LO##22, LO##23, LO##24, LO##25, LO##26, LO##27, \
+			LO##28, LO##29, LO##30, LO##31, HI##0, HI##1, HI##2, \
+			HI##3, HI##4, HI##5, HI##6, HI##7, HI##8, HI##9, \
+			HI##10, HI##11, HI##12, HI##13, HI##14, HI##15, \
+			HI##16, HI##17, HI##18, HI##19, HI##20, HI##21, \
+			HI##22, HI##23, HI##24, HI##25, HI##26, HI##27, \
+			HI##28, HI##29, HI##30, HI##31 \
+	}
+
+#define PPC_REGS0_7(X) \
+	{ \
+		X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7 \
+	}
+
+#define PPC_REGS0_3(X) \
+	{ \
+		X##0, X##1, X##2, X##3 \
+	}
+
+#define DEFINE_PPC_REGCLASSES \
+	static const MCPhysReg RRegs[32] = PPC_REGS0_31(PPC_R); \
+	static const MCPhysReg XRegs[32] = PPC_REGS0_31(PPC_X); \
+	static const MCPhysReg FRegs[32] = PPC_REGS0_31(PPC_F); \
+	static const MCPhysReg VSRpRegs[32] = PPC_REGS0_31(PPC_VSRp); \
+	static const MCPhysReg SPERegs[32] = PPC_REGS0_31(PPC_S); \
+	static const MCPhysReg VFRegs[32] = PPC_REGS0_31(PPC_VF); \
+	static const MCPhysReg VRegs[32] = PPC_REGS0_31(PPC_V); \
+	static const MCPhysReg RRegsNoR0[32] = \
+		PPC_REGS_NO0_31(PPC_ZERO, PPC_R); \
+	static const MCPhysReg XRegsNoX0[32] = \
+		PPC_REGS_NO0_31(PPC_ZERO8, PPC_X); \
+	static const MCPhysReg VSRegs[64] = PPC_REGS_LO_HI(PPC_VSL, PPC_V); \
+	static const MCPhysReg VSFRegs[64] = PPC_REGS_LO_HI(PPC_F, PPC_VF); \
+	static const MCPhysReg VSSRegs[64] = PPC_REGS_LO_HI(PPC_F, PPC_VF); \
+	static const MCPhysReg CRBITRegs[32] = { \
+		PPC_CR0LT, PPC_CR0GT, PPC_CR0EQ, PPC_CR0UN, PPC_CR1LT, \
+		PPC_CR1GT, PPC_CR1EQ, PPC_CR1UN, PPC_CR2LT, PPC_CR2GT, \
+		PPC_CR2EQ, PPC_CR2UN, PPC_CR3LT, PPC_CR3GT, PPC_CR3EQ, \
+		PPC_CR3UN, PPC_CR4LT, PPC_CR4GT, PPC_CR4EQ, PPC_CR4UN, \
+		PPC_CR5LT, PPC_CR5GT, PPC_CR5EQ, PPC_CR5UN, PPC_CR6LT, \
+		PPC_CR6GT, PPC_CR6EQ, PPC_CR6UN, PPC_CR7LT, PPC_CR7GT, \
+		PPC_CR7EQ, PPC_CR7UN \
+	}; \
+	static const MCPhysReg CRRegs[8] = PPC_REGS0_7(PPC_CR); \
+	static const MCPhysReg ACCRegs[8] = PPC_REGS0_7(PPC_ACC); \
+	static const MCPhysReg WACCRegs[8] = PPC_REGS0_7(PPC_WACC); \
+	static const MCPhysReg WACC_HIRegs[8] = PPC_REGS0_7(PPC_WACC_HI); \
+	static const MCPhysReg DMRROWpRegs[32] = PPC_REGS0_31(PPC_DMRROWp); \
+	static const MCPhysReg DMRROWRegs[64] = PPC_REGS0_63(PPC_DMRROW); \
+	static const MCPhysReg DMRRegs[8] = PPC_REGS0_7(PPC_DMR); \
+	static const MCPhysReg DMRpRegs[4] = PPC_REGS0_3(PPC_DMRp);
+
+static const MCPhysReg QFRegs[] = {
+	PPC_QF0,  PPC_QF1,  PPC_QF2,  PPC_QF3,	PPC_QF4,  PPC_QF5,  PPC_QF6,
+	PPC_QF7,  PPC_QF8,  PPC_QF9,  PPC_QF10, PPC_QF11, PPC_QF12, PPC_QF13,
+	PPC_QF14, PPC_QF15, PPC_QF16, PPC_QF17, PPC_QF18, PPC_QF19, PPC_QF20,
+	PPC_QF21, PPC_QF22, PPC_QF23, PPC_QF24, PPC_QF25, PPC_QF26, PPC_QF27,
+	PPC_QF28, PPC_QF29, PPC_QF30, PPC_QF31
+};
+
+#endif // CS_PPC_MCTARGETDESC_H

thirdparty/capstone/arch/PowerPC/PPCMapping.c

@@ -0,0 +1,651 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#include "capstone/ppc.h"
+#ifdef CAPSTONE_HAS_POWERPC
+
+#include <stdio.h> // debug
+#include <string.h>
+
+#include "../../cs_simple_types.h"
+#include "../../Mapping.h"
+#include "../../MCDisassembler.h"
+#include "../../utils.h"
+
+#include "PPCLinkage.h"
+#include "PPCMapping.h"
+#include "PPCMCTargetDesc.h"
+
+#define GET_REGINFO_MC_DESC
+#include "PPCGenRegisterInfo.inc"
+
+void PPC_init_mri(MCRegisterInfo *MRI)
+{
+	MCRegisterInfo_InitMCRegisterInfo(MRI, PPCRegDesc, PPC_REG_ENDING, 0, 0,
+					  PPCMCRegisterClasses,
+					  ARR_SIZE(PPCMCRegisterClasses), 0, 0,
+					  PPCRegDiffLists, 0, PPCSubRegIdxLists,
+					  ARR_SIZE(PPCSubRegIdxLists),
+					  PPCRegEncodingTable);
+}
+
+const char *PPC_reg_name(csh handle, unsigned int reg)
+{
+	if (reg > PPC_REG_INVALID && reg < PPC_REG_ENDING)
+		return PPC_LLVM_getRegisterName(reg);
+	return NULL;
+}
+
+// given internal insn id, return public instruction info
+void PPC_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
+{
+	// We do this after Instruction disassembly.
+}
+
+#ifndef CAPSTONE_DIET
+
+static const char *const insn_name_maps[] = {
+#include "PPCGenCSMappingInsnName.inc"
+};
+
+static const name_map insn_alias_mnem_map[] = {
+#include "PPCGenCSAliasMnemMap.inc"
+	{ PPC_INS_ALIAS_SLWI, "slwi" },
+	{ PPC_INS_ALIAS_SRWI, "srwi" },
+	{ PPC_INS_ALIAS_SLDI, "sldi" },
+	{ PPC_INS_ALIAS_END, NULL },
+};
+
+#endif
+
+const char *PPC_insn_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	if (id < PPC_INS_ALIAS_END && id > PPC_INS_ALIAS_BEGIN) {
+		if (id - PPC_INS_ALIAS_BEGIN >= ARR_SIZE(insn_alias_mnem_map))
+			return NULL;
+
+		return insn_alias_mnem_map[id - PPC_INS_ALIAS_BEGIN - 1].name;
+	}
+	if (id >= PPC_INS_ENDING)
+		return NULL;
+
+	return insn_name_maps[id];
+#else
+	return NULL;
+#endif
+}
+
+#ifndef CAPSTONE_DIET
+static const name_map group_name_maps[] = {
+	// generic groups
+	{ PPC_GRP_INVALID, NULL },
+	{ PPC_GRP_JUMP, "jump" },
+	{ PPC_GRP_CALL, "call" },
+	{ PPC_GRP_INT, "int" },
+	{ PPC_GRP_PRIVILEGE, "privilege" },
+	{ PPC_GRP_BRANCH_RELATIVE, "branch_relative" },
+
+// architecture-specific groups
+#include "PPCGenCSFeatureName.inc"
+};
+#endif
+
+const char *PPC_group_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
+#else
+	return NULL;
+#endif
+}
+
+const insn_map ppc_insns[] = {
+#include "PPCGenCSMappingInsn.inc"
+};
+
+void PPC_check_updates_cr0(MCInst *MI)
+{
+#ifndef CAPSTONE_DIET
+	if (!detail_is_set(MI))
+		return;
+	cs_detail *detail = get_detail(MI);
+	for (int i = 0; i < detail->regs_write_count; ++i) {
+		if (detail->regs_write[i] == 0)
+			return;
+		if (detail->regs_write[i] == PPC_REG_CR0) {
+			PPC_get_detail(MI)->update_cr0 = true;
+			return;
+		}
+	}
+#endif // CAPSTONE_DIET
+}
+
+/// Parses and adds the branch predicate information and the BH field.
+static void PPC_add_branch_predicates(MCInst *MI, const uint8_t *Bytes,
+				      size_t BytesLen)
+{
+	if (!detail_is_set(MI))
+		return;
+#ifndef CAPSTONE_DIET
+	assert(MI && Bytes);
+	if (BytesLen < 4)
+		return;
+
+	ppc_insn_form form = ppc_insns[MI->Opcode].suppl_info.ppc.form;
+	bool b_form = ppc_is_b_form(form);
+	if (!(b_form || form == PPC_INSN_FORM_XLFORM_2))
+		return;
+
+	uint32_t Inst = readBytes32(MI, Bytes);
+
+	uint8_t bi = 0;
+	if (b_form)
+		bi = (Inst & PPC_INSN_FORM_B_BI_MASK) >> 16;
+	else
+		bi = (Inst & PPC_INSN_FORM_XL_BI_MASK) >> 16;
+
+	uint8_t bo = 0;
+	if (b_form)
+		bo = (Inst & PPC_INSN_FORM_B_BO_MASK) >> 21;
+	else
+		bo = (Inst & PPC_INSN_FORM_XL_BO_MASK) >> 21;
+
+	PPC_get_detail(MI)->bc.bo = bo;
+	PPC_get_detail(MI)->bc.bi = bi;
+	PPC_get_detail(MI)->bc.crX_bit = bi % 4;
+	PPC_get_detail(MI)->bc.crX = PPC_REG_CR0 + (bi / 4);
+	PPC_get_detail(MI)->bc.hint = PPC_get_hint(bo);
+	PPC_get_detail(MI)->bc.pred_cr = PPC_get_branch_pred(bi, bo, true);
+	PPC_get_detail(MI)->bc.pred_ctr = PPC_get_branch_pred(bi, bo, false);
+
+	if (ppc_is_b_form(form))
+		return;
+
+	uint8_t bh = (Inst & PPC_INSN_FORM_XL_BH_MASK) >> 11;
+	uint16_t xo = (Inst & PPC_INSN_FORM_XL_XO_MASK) >> 1;
+	// Pre-defined values for XO fields (PowerISA v3.1B)
+	uint16_t bcctr_xo_field = 528;
+	uint16_t bctar_xo_field = 560;
+	bool cond = (xo == bcctr_xo_field || xo == bctar_xo_field);
+	switch (bh) {
+	default:
+		assert(0 && "Invalid BH value.");
+	case 0:
+		PPC_get_detail(MI)->bc.bh = cond ? PPC_BH_NO_SUBROUTINE_RET :
+						   PPC_BH_SUBROUTINE_RET;
+		break;
+	case 1:
+		PPC_get_detail(MI)->bc.bh = cond ? PPC_BH_RESERVED :
+						   PPC_BH_NO_SUBROUTINE_RET;
+		break;
+	case 2:
+		PPC_get_detail(MI)->bc.bh = PPC_BH_RESERVED;
+		break;
+	case 3:
+		PPC_get_detail(MI)->bc.bh = PPC_BH_NOT_PREDICTABLE;
+		break;
+	}
+#endif // CAPSTONE_DIET
+}
+
+void PPC_set_instr_map_data(MCInst *MI, const uint8_t *Bytes, size_t BytesLen)
+{
+	map_cs_id(MI, ppc_insns, ARR_SIZE(ppc_insns));
+	map_implicit_reads(MI, ppc_insns);
+	map_implicit_writes(MI, ppc_insns);
+	map_groups(MI, ppc_insns);
+	PPC_add_branch_predicates(MI, Bytes, BytesLen);
+	PPC_check_updates_cr0(MI);
+	const ppc_suppl_info *suppl_info = map_get_suppl_info(MI, ppc_insns);
+	if (suppl_info) {
+		PPC_get_detail(MI)->format = suppl_info->form;
+	}
+}
+
+/// Initialize PPCs detail.
+void PPC_init_cs_detail(MCInst *MI)
+{
+	if (!detail_is_set(MI))
+		return;
+	memset(get_detail(MI), 0, offsetof(cs_detail, ppc) + sizeof(cs_ppc));
+	PPC_get_detail(MI)->bc.bi = UINT8_MAX;
+	PPC_get_detail(MI)->bc.bo = UINT8_MAX;
+	PPC_get_detail(MI)->bc.crX = PPC_REG_INVALID;
+	PPC_get_detail(MI)->bc.crX_bit = PPC_BI_INVALID;
+	PPC_get_detail(MI)->bc.pred_cr = PPC_PRED_INVALID;
+	PPC_get_detail(MI)->bc.pred_ctr = PPC_PRED_INVALID;
+	PPC_get_detail(MI)->bc.hint = PPC_BR_NOT_GIVEN;
+	PPC_get_detail(MI)->bc.bh = PPC_BH_INVALID;
+}
+
+void PPC_printer(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info)
+{
+	MI->MRI = (MCRegisterInfo *)info;
+	MI->fillDetailOps = detail_is_set(MI);
+	MI->flat_insn->usesAliasDetails = map_use_alias_details(MI);
+	PPC_LLVM_printInst(MI, MI->address, "", O);
+#ifndef CAPSTONE_DIET
+	map_set_alias_id(MI, O, insn_alias_mnem_map,
+			 ARR_SIZE(insn_alias_mnem_map));
+#endif
+}
+
+bool PPC_getInstruction(csh handle, const uint8_t *bytes, size_t bytes_len,
+			MCInst *instr, uint16_t *size, uint64_t address,
+			void *info)
+{
+	PPC_init_cs_detail(instr);
+	DecodeStatus result = PPC_LLVM_getInstruction(
+		handle, bytes, bytes_len, instr, size, address, info);
+	PPC_set_instr_map_data(instr, bytes, bytes_len);
+	return result != MCDisassembler_Fail;
+}
+
+bool PPC_getFeatureBits(unsigned int mode, unsigned int feature)
+{
+	if ((feature == PPC_FeatureQPX) && (mode & CS_MODE_QPX) == 0) {
+		return false;
+	} else if ((feature == PPC_FeatureSPE) && (mode & CS_MODE_SPE) == 0) {
+		return false;
+	} else if ((feature == PPC_FeatureBookE) &&
+		   (mode & CS_MODE_BOOKE) == 0) {
+		return false;
+	} else if ((feature == PPC_FeaturePS) && (mode & CS_MODE_PS) == 0) {
+		return false;
+	}
+
+	// No AIX support for now.
+	if (feature == PPC_FeatureModernAIXAs || feature == PPC_AIXOS)
+		return false;
+	// TODO Make it optional
+	if (feature == PPC_FeatureMSYNC)
+		return false;
+
+	// By default support everything
+	return true;
+}
+
+#ifndef CAPSTONE_DIET
+static const map_insn_ops insn_operands[] = {
+#include "PPCGenCSMappingInsnOp.inc"
+};
+#endif
+
+/// @brief Handles memory operands.
+/// @param MI The MCInst.
+/// @param OpNum The operand index.
+static void handle_memory_operand(MCInst *MI, unsigned OpNum)
+{
+	cs_op_type op_type = map_get_op_type(MI, OpNum) & ~CS_OP_MEM;
+
+	// If this is called from printOperand() we do not know if a
+	// register is a base or an offset reg (imm is always disponent).
+	// So we assume the base register is always added before the offset register
+	// and set the flag appropriately.
+	bool is_off_reg =
+		((op_type == CS_OP_REG) &&
+		 PPC_get_detail_op(MI, 0)->mem.base != PPC_REG_INVALID);
+	PPC_set_detail_op_mem(MI, OpNum, MCInst_getOpVal(MI, OpNum),
+			      is_off_reg);
+}
+
+static void add_cs_detail_general(MCInst *MI, ppc_op_group op_group,
+				  unsigned OpNum)
+{
+	if (!detail_is_set(MI))
+		return;
+
+	switch (op_group) {
+	default:
+		printf("General operand group %d not handled!\n", op_group);
+		return;
+	case PPC_OP_GROUP_Operand: {
+		cs_op_type op_type = map_get_op_type(MI, OpNum);
+
+		// Check for memory operands emitted via printOperand()
+		if (doing_mem(MI) && !(op_type & CS_OP_MEM)) {
+			// Close previous memory operand
+			set_mem_access(MI, false);
+		} else if (doing_mem(MI) || (op_type & CS_OP_MEM)) {
+			// The memory operands use printOperand() to
+			// emit their register and immediates.
+			if (!doing_mem(MI))
+				set_mem_access(MI, true);
+			handle_memory_operand(MI, OpNum);
+			return;
+		}
+
+		assert((op_type & CS_OP_MEM) ==
+		       0); // doing_mem should have been true.
+
+		if (op_type == CS_OP_REG)
+			PPC_set_detail_op_reg(MI, OpNum,
+					      MCInst_getOpVal(MI, OpNum));
+		else if (op_type == CS_OP_IMM)
+			PPC_set_detail_op_imm(MI, OpNum,
+					      MCInst_getOpVal(MI, OpNum));
+		else
+			assert(0 && "Operand type not handled.");
+		break;
+	}
+	case PPC_OP_GROUP_ImmZeroOperand:
+	case PPC_OP_GROUP_U1ImmOperand:
+	case PPC_OP_GROUP_U2ImmOperand:
+	case PPC_OP_GROUP_U3ImmOperand:
+	case PPC_OP_GROUP_U4ImmOperand:
+	case PPC_OP_GROUP_U5ImmOperand:
+	case PPC_OP_GROUP_U6ImmOperand:
+	case PPC_OP_GROUP_U7ImmOperand:
+	case PPC_OP_GROUP_U8ImmOperand:
+	case PPC_OP_GROUP_U10ImmOperand:
+	case PPC_OP_GROUP_U12ImmOperand:
+		PPC_set_detail_op_imm(MI, OpNum,
+				      (uint32_t)MCInst_getOpVal(MI, OpNum));
+		break;
+	case PPC_OP_GROUP_U16ImmOperand:
+		if (!MCOperand_isImm(MCInst_getOperand(MI, OpNum)))
+			// Handled in printOperand()
+			return;
+		PPC_set_detail_op_imm(MI, OpNum,
+				      (uint32_t)MCInst_getOpVal(MI, OpNum));
+		break;
+	case PPC_OP_GROUP_S5ImmOperand: {
+		int Imm = MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
+		Imm = SignExtend32((Imm), 5);
+		PPC_set_detail_op_imm(MI, OpNum, Imm);
+		break;
+	}
+	case PPC_OP_GROUP_S12ImmOperand: {
+		int64_t Imm = SignExtend64(
+			MCOperand_getImm(MCInst_getOperand(MI, (OpNum))), 12);
+		if (doing_mem(MI)) {
+			PPC_set_detail_op_mem(MI, OpNum, Imm, true);
+			break;
+		}
+		PPC_set_detail_op_imm(MI, OpNum, Imm);
+		break;
+	}
+	case PPC_OP_GROUP_S16ImmOperand: {
+		if (!MCOperand_isImm(MCInst_getOperand(MI, OpNum)))
+			// Handled in printOperand()
+			return;
+		int16_t Imm = MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
+		if (doing_mem(MI)) {
+			PPC_set_detail_op_mem(MI, OpNum, Imm, true);
+			break;
+		}
+		PPC_set_detail_op_imm(MI, OpNum, Imm);
+		break;
+	}
+	case PPC_OP_GROUP_S34ImmOperand: {
+		if (!MCOperand_isImm(MCInst_getOperand(MI, OpNum)))
+			// Handled in printOperand()
+			return;
+		int64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
+		if (doing_mem(MI)) {
+			PPC_set_detail_op_mem(MI, OpNum, Imm, true);
+			break;
+		}
+		PPC_set_detail_op_imm(MI, OpNum, Imm);
+		break;
+	}
+	case PPC_OP_GROUP_ATBitsAsHint: {
+		PPC_get_detail(MI)->bc.hint =
+			(ppc_br_hint)MCInst_getOpVal(MI, OpNum);
+		break;
+	}
+	case PPC_OP_GROUP_AbsBranchOperand: {
+		if (!MCOperand_isImm(MCInst_getOperand(MI, OpNum)))
+			// Handled in printOperand()
+			return;
+		unsigned Val = MCInst_getOpVal(MI, OpNum) << 2;
+		int32_t Imm = SignExtend32(Val, 32);
+		PPC_get_detail_op(MI, 0)->type = PPC_OP_IMM;
+		PPC_get_detail_op(MI, 0)->imm = Imm;
+		PPC_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
+		PPC_inc_op_count(MI);
+		break;
+	}
+	case PPC_OP_GROUP_TLSCall:
+		// Handled in PPCInstPrinter and printOperand.
+		return;
+	case PPC_OP_GROUP_crbitm: {
+		unsigned CCReg = MCInst_getOpVal(MI, OpNum);
+		PPC_set_detail_op_reg(MI, OpNum, CCReg);
+		break;
+	}
+	case PPC_OP_GROUP_BranchOperand: {
+		if (!MCOperand_isImm(MCInst_getOperand(MI, (OpNum))))
+			// Handled in printOperand()
+			return;
+		int32_t Imm = SignExtend32(
+			((unsigned)MCInst_getOpVal(MI, (OpNum)) << 2), 32);
+		uint64_t Address = MI->address + Imm;
+		if (IS_32BIT(MI->csh->mode))
+			Address &= 0xffffffff;
+		PPC_get_detail_op(MI, 0)->type = PPC_OP_IMM;
+		PPC_get_detail_op(MI, 0)->imm = Address;
+		PPC_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
+		PPC_inc_op_count(MI);
+		break;
+	}
+	// Memory operands have their `set_mem_access()` calls
+	// in PPCInstPrinter.
+	case PPC_OP_GROUP_MemRegImm:
+	case PPC_OP_GROUP_MemRegReg: {
+		// These cases print 0 if the base register is R0.
+		// So no printOperand() function is called.
+		// We must handle the zero case here.
+		unsigned OpNumReg = 0;
+		if (op_group == PPC_OP_GROUP_MemRegImm)
+			OpNumReg = OpNum + 1;
+		else
+			OpNumReg = OpNum;
+
+		MCOperand *Op = MCInst_getOperand(MI, OpNumReg);
+		if (MCOperand_isReg(Op) && MCOperand_getReg(Op) == PPC_R0) {
+			PPC_get_detail_op(MI, 0)->mem.base = PPC_REG_ZERO;
+			PPC_get_detail_op(MI, 0)->type = PPC_OP_MEM;
+			PPC_get_detail_op(MI, 0)->access =
+				map_get_op_access(MI, OpNum);
+		}
+		break;
+	}
+	case PPC_OP_GROUP_MemRegImmHash:
+	case PPC_OP_GROUP_MemRegImm34:
+	case PPC_OP_GROUP_MemRegImm34PCRel:
+		// Handled in other printOperand functions.
+		break;
+	}
+}
+
+/// Fills cs_detail with the data of the operand.
+/// Calls to this function should not be added by hand! Please checkout the
+/// patch `AddCSDetail` of the CppTranslator.
+void PPC_add_cs_detail(MCInst *MI, ppc_op_group op_group, va_list args)
+{
+	if (!detail_is_set(MI) || !map_fill_detail_ops(MI))
+		return;
+
+	switch (op_group) {
+	default:
+		printf("Operand group %d not handled!\n", op_group);
+		return;
+	case PPC_OP_GROUP_PredicateOperand: {
+		unsigned OpNum = va_arg(args, unsigned);
+		const char *Modifier = va_arg(args, const char *);
+		if ((strcmp(Modifier, "cc") == 0) ||
+		    (strcmp(Modifier, "pm") == 0)) {
+			unsigned Val = MCInst_getOpVal(MI, OpNum);
+			unsigned bo = Val & 0x1f;
+			unsigned bi = (Val & 0x1e0) >> 5;
+			PPC_get_detail(MI)->bc.bo = bo;
+			PPC_get_detail(MI)->bc.bi = bi;
+			PPC_get_detail(MI)->bc.crX_bit = bi % 4;
+			PPC_get_detail(MI)->bc.crX = PPC_REG_CR0 + (bi / 4);
+			PPC_get_detail(MI)->bc.pred_cr =
+				PPC_get_branch_pred(bi, bo, true);
+			PPC_get_detail(MI)->bc.pred_ctr =
+				PPC_get_branch_pred(bi, bo, false);
+			PPC_get_detail(MI)->bc.hint = PPC_get_hint(bo);
+		}
+		return;
+	}
+	case PPC_OP_GROUP_S12ImmOperand:
+	case PPC_OP_GROUP_Operand:
+	case PPC_OP_GROUP_MemRegReg:
+	case PPC_OP_GROUP_U6ImmOperand:
+	case PPC_OP_GROUP_U5ImmOperand:
+	case PPC_OP_GROUP_MemRegImm:
+	case PPC_OP_GROUP_S16ImmOperand:
+	case PPC_OP_GROUP_U2ImmOperand:
+	case PPC_OP_GROUP_U16ImmOperand:
+	case PPC_OP_GROUP_BranchOperand:
+	case PPC_OP_GROUP_AbsBranchOperand:
+	case PPC_OP_GROUP_U1ImmOperand:
+	case PPC_OP_GROUP_TLSCall:
+	case PPC_OP_GROUP_U3ImmOperand:
+	case PPC_OP_GROUP_S5ImmOperand:
+	case PPC_OP_GROUP_MemRegImmHash:
+	case PPC_OP_GROUP_U4ImmOperand:
+	case PPC_OP_GROUP_U10ImmOperand:
+	case PPC_OP_GROUP_crbitm:
+	case PPC_OP_GROUP_S34ImmOperand:
+	case PPC_OP_GROUP_ImmZeroOperand:
+	case PPC_OP_GROUP_MemRegImm34:
+	case PPC_OP_GROUP_MemRegImm34PCRel:
+	case PPC_OP_GROUP_U8ImmOperand:
+	case PPC_OP_GROUP_U12ImmOperand:
+	case PPC_OP_GROUP_U7ImmOperand:
+	case PPC_OP_GROUP_ATBitsAsHint: {
+		unsigned OpNum = va_arg(args, unsigned);
+		add_cs_detail_general(MI, op_group, OpNum);
+		return;
+	}
+	}
+}
+
+void PPC_set_detail_op_mem(MCInst *MI, unsigned OpNum, uint64_t Val,
+			   bool is_off_reg)
+{
+	if (!detail_is_set(MI))
+		return;
+
+	assert(map_get_op_type(MI, OpNum) & CS_OP_MEM);
+	cs_op_type secondary_type = map_get_op_type(MI, OpNum) & ~CS_OP_MEM;
+
+	switch (secondary_type) {
+	default:
+		assert(0 && "Secondary type not supported yet.");
+	case CS_OP_REG:
+		if (is_off_reg) {
+			PPC_get_detail_op(MI, 0)->mem.offset = Val;
+			if (PPC_get_detail_op(MI, 0)->mem.base != PPC_REG_INVALID)
+				set_mem_access(MI, false);
+		}	else {
+			PPC_get_detail_op(MI, 0)->mem.base = Val;
+			if (MCInst_opIsTying(MI, OpNum))
+				map_add_implicit_write(MI, MCInst_getOpVal(MI, OpNum));
+		}
+		break;
+	case CS_OP_IMM:
+		PPC_get_detail_op(MI, 0)->mem.disp = Val;
+		if (PPC_get_detail_op(MI, 0)->mem.base != PPC_REG_INVALID)
+			set_mem_access(MI, false);
+		break;
+	}
+
+	PPC_get_detail_op(MI, 0)->type = PPC_OP_MEM;
+	PPC_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
+}
+
+/// Adds a register PPC operand at position OpNum and increases the op_count by
+/// one.
+void PPC_set_detail_op_reg(MCInst *MI, unsigned OpNum, ppc_reg Reg)
+{
+	if (!detail_is_set(MI))
+		return;
+	assert(!(map_get_op_type(MI, OpNum) & CS_OP_MEM));
+	assert(map_get_op_type(MI, OpNum) == CS_OP_REG);
+
+	PPC_get_detail_op(MI, 0)->type = PPC_OP_REG;
+	PPC_get_detail_op(MI, 0)->reg = Reg;
+	PPC_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
+	PPC_inc_op_count(MI);
+}
+
+/// Adds an immediate PPC operand at position OpNum and increases the op_count
+/// by one.
+void PPC_set_detail_op_imm(MCInst *MI, unsigned OpNum, int64_t Imm)
+{
+	if (!detail_is_set(MI))
+		return;
+	assert(!(map_get_op_type(MI, OpNum) & CS_OP_MEM));
+	assert(map_get_op_type(MI, OpNum) == CS_OP_IMM);
+
+	PPC_get_detail_op(MI, 0)->type = PPC_OP_IMM;
+	PPC_get_detail_op(MI, 0)->imm = Imm;
+	PPC_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
+	PPC_inc_op_count(MI);
+}
+
+void PPC_set_mem_access(MCInst *MI, bool status)
+{
+	if (!detail_is_set(MI))
+		return;
+	if ((!status && !doing_mem(MI)) || (status && doing_mem(MI)))
+		return; // Nothing to do
+
+	set_doing_mem(MI, status);
+	if (status) {
+		PPC_get_detail_op(MI, 0)->type = PPC_OP_MEM;
+		PPC_get_detail_op(MI, 0)->mem.base = PPC_REG_INVALID;
+		PPC_get_detail_op(MI, 0)->mem.offset = PPC_REG_INVALID;
+		PPC_get_detail_op(MI, 0)->mem.disp = 0;
+
+#ifndef CAPSTONE_DIET
+		uint8_t access =
+			map_get_op_access(MI, PPC_get_detail(MI)->op_count);
+		PPC_get_detail_op(MI, 0)->access = access;
+#endif
+	} else {
+		// done, select the next operand slot
+		PPC_inc_op_count(MI);
+	}
+}
+
+void PPC_setup_op(cs_ppc_op *op)
+{
+	memset(op, 0, sizeof(cs_ppc_op));
+	op->type = PPC_OP_INVALID;
+}
+
+/// Inserts a immediate to the detail operands at @index.
+/// Already present operands are moved.
+void PPC_insert_detail_op_imm_at(MCInst *MI, unsigned index, int64_t Val,
+				 cs_ac_type access)
+{
+	if (!detail_is_set(MI) || !map_fill_detail_ops(MI))
+		return;
+
+	assert(PPC_get_detail(MI)->op_count < PPC_NUM_OPS);
+
+	cs_ppc_op op;
+	PPC_setup_op(&op);
+	op.type = PPC_OP_IMM;
+	op.imm = Val;
+	op.access = access;
+
+	cs_ppc_op *ops = PPC_get_detail(MI)->operands;
+	int i = PPC_get_detail(MI)->op_count - 1;
+	for (; i >= index; --i) {
+		ops[i + 1] = ops[i];
+		if (i == index)
+			break;
+	}
+	ops[index] = op;
+	PPC_inc_op_count(MI);
+}
+
+#endif

thirdparty/capstone/arch/PowerPC/PPCMapping.h

@@ -0,0 +1,74 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifndef CS_PPC_MAP_H
+#define CS_PPC_MAP_H
+
+#include "../../cs_priv.h"
+#include "../../MCDisassembler.h"
+#include "capstone/capstone.h"
+
+typedef enum {
+#include "PPCGenCSOpGroup.inc"
+} ppc_op_group;
+
+void PPC_init_mri(MCRegisterInfo *MRI);
+
+void PPC_init_cs_detail(MCInst *MI);
+
+// return name of register in friendly string
+const char *PPC_reg_name(csh handle, unsigned int reg);
+
+void PPC_printer(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info);
+bool PPC_getInstruction(csh handle, const uint8_t *code, size_t code_len,
+			MCInst *instr, uint16_t *size, uint64_t address,
+			void *info);
+
+// given internal insn id, return public instruction info
+void PPC_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
+
+const char *PPC_insn_name(csh handle, unsigned int id);
+const char *PPC_group_name(csh handle, unsigned int id);
+
+typedef struct {
+	unsigned int id; // instruction id
+	const char *mnem;
+} ppc_alias_id;
+
+void PPC_set_mem_access(MCInst *MI, bool status);
+static inline void set_mem_access(MCInst *MI, bool status)
+{
+	PPC_set_mem_access(MI, status);
+}
+
+// map internal raw register to 'public' register
+ppc_reg PPC_map_register(unsigned int r);
+
+bool PPC_getFeatureBits(unsigned int mode, unsigned int feature);
+
+void PPC_add_cs_detail(MCInst *MI, ppc_op_group op_group, va_list args);
+
+static inline void add_cs_detail(MCInst *MI, ppc_op_group op_group, ...)
+{
+	if (!MI->flat_insn->detail)
+		return;
+	va_list args;
+	va_start(args, op_group);
+	PPC_add_cs_detail(MI, op_group, args);
+	va_end(args);
+}
+
+void PPC_set_detail_op_reg(MCInst *MI, unsigned OpNum, ppc_reg Reg);
+void PPC_set_detail_op_imm(MCInst *MI, unsigned OpNum, int64_t Imm);
+void PPC_set_detail_op_mem(MCInst *MI, unsigned OpNum, uint64_t Val,
+			   bool is_off_reg);
+
+void PPC_insert_detail_op_imm_at(MCInst *MI, unsigned index, int64_t Val,
+				 cs_ac_type access);
+
+void PPC_setup_op(cs_ppc_op *op);
+
+void PPC_check_updates_cr0(MCInst *MI);
+void PPC_set_instr_map_data(MCInst *MI, const uint8_t *Bytes, size_t BytesLen);
+
+#endif

thirdparty/capstone/arch/PowerPC/PPCModule.c

@@ -0,0 +1,44 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifdef CAPSTONE_HAS_POWERPC
+
+#include "../../utils.h"
+#include "../../MCRegisterInfo.h"
+#include "PPCInstPrinter.h"
+#include "PPCMapping.h"
+#include "PPCModule.h"
+
+cs_err PPC_global_init(cs_struct *ud)
+{
+	MCRegisterInfo *mri;
+	mri = (MCRegisterInfo *)cs_mem_malloc(sizeof(*mri));
+
+	PPC_init_mri(mri);
+	ud->printer = PPC_printer;
+	ud->printer_info = mri;
+	ud->getinsn_info = mri;
+	ud->disasm = PPC_getInstruction;
+	ud->post_printer = NULL;
+
+	ud->reg_name = PPC_reg_name;
+	ud->insn_id = PPC_get_insn_id;
+	ud->insn_name = PPC_insn_name;
+	ud->group_name = PPC_group_name;
+
+	return CS_ERR_OK;
+}
+
+cs_err PPC_option(cs_struct *handle, cs_opt_type type, size_t value)
+{
+	if (type == CS_OPT_SYNTAX)
+		handle->syntax = (int)value;
+
+	if (type == CS_OPT_MODE) {
+		handle->mode |= (cs_mode)value;
+	}
+
+	return CS_ERR_OK;
+}
+
+#endif

thirdparty/capstone/arch/PowerPC/PPCModule.h

@@ -0,0 +1,12 @@
+/* Capstone Disassembly Engine */
+/* By Travis Finkenauer <tmfinken@gmail.com>, 2018 */
+
+#ifndef CS_POWERPC_MODULE_H
+#define CS_POWERPC_MODULE_H
+
+#include "../../utils.h"
+
+cs_err PPC_global_init(cs_struct *ud);
+cs_err PPC_option(cs_struct *handle, cs_opt_type type, size_t value);
+
+#endif

thirdparty/capstone/arch/PowerPC/PPCPredicates.h

@@ -0,0 +1,65 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically translated source file from LLVM. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Only small edits allowed. */
+/* For multiple similar edits, please create a Patch for the translator. */
+
+/* Capstone's C++ file translator: */
+/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
+
+//===-- PPCPredicates.h - PPC Branch Predicate Information ------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the PowerPC branch predicates.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef CS_PPC_PREDICATES_H
+#define CS_PPC_PREDICATES_H
+
+// GCC #defines PPC on Linux but we use it as our namespace name
+#include "capstone/ppc.h"
+#undef PPC
+
+// Generated files will use "namespace PPC". To avoid symbol clash,
+// undefine PPC here. PPC may be predefined on some hosts.
+#undef PPC
+
+// Predicates moved to ppc.h
+typedef ppc_pred PPC_Predicate;
+
+/// Invert the specified predicate.  != -> ==, < -> >=.
+PPC_Predicate InvertPredicate(PPC_Predicate Opcode);
+/// Assume the condition register is set by MI(a,b), return the predicate if
+/// we modify the instructions such that condition register is set by MI(b,a).
+PPC_Predicate getSwappedPredicate(PPC_Predicate Opcode);
+/// Return the condition without hint bits.
+static inline unsigned PPC_getPredicateCondition(PPC_Predicate Opcode)
+{
+	return (unsigned)(Opcode & ~PPC_BR_HINT_MASK);
+}
+
+/// Return the hint bits of the predicate.
+static inline unsigned PPC_getPredicateHint(PPC_Predicate Opcode)
+{
+	return (unsigned)(Opcode & PPC_BR_HINT_MASK);
+}
+
+/// Return predicate consisting of specified condition and hint bits.
+static inline PPC_Predicate PPC_getPredicate(unsigned Condition, unsigned Hint)
+{
+	return (PPC_Predicate)((Condition & ~PPC_BR_HINT_MASK) |
+			       (Hint & PPC_BR_HINT_MASK));
+}
+
+#endif // CS_PPC_PREDICATES_H

thirdparty/capstone/arch/PowerPC/PPCRegisterInfo.h

@@ -0,0 +1,61 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Rot127 <unisono@quyllur.org> 2022-2023 */
+
+#ifndef CS_PPC_REGISTERINFO_H
+#define CS_PPC_REGISTERINFO_H
+
+#include "PPCMCTargetDesc.h"
+
+/// stripRegisterPrefix - This method strips the character prefix from a
+/// register name so that only the number is left.  Used by for linux asm.
+static const char *PPCRegisterInfo_stripRegisterPrefix(const char *RegName)
+{
+	switch (RegName[0]) {
+	case 'a':
+		if (RegName[1] == 'c' && RegName[2] == 'c')
+			return RegName + 3;
+		break;
+	case 'r':
+	case 'f':
+	case 'v':
+		if (RegName[1] == 's') {
+			if (RegName[2] == 'p')
+				return RegName + 3;
+			return RegName + 2;
+		}
+		return RegName + 1;
+	case 'c':
+		if (RegName[1] == 'r')
+			return RegName + 2;
+		break;
+	case 'w':
+		// For wacc and wacc_hi
+		if (RegName[1] == 'a' && RegName[2] == 'c' &&
+		    RegName[3] == 'c') {
+			if (RegName[4] == '_')
+				return RegName + 7;
+			else
+				return RegName + 4;
+		}
+		break;
+	case 'd':
+		// For dmr, dmrp, dmrrow, dmrrowp
+		if (RegName[1] == 'm' && RegName[2] == 'r') {
+			if (RegName[3] == 'r' && RegName[4] == 'o' &&
+			    RegName[5] == 'w' && RegName[6] == 'p')
+				return RegName + 7;
+			else if (RegName[3] == 'r' && RegName[4] == 'o' &&
+				 RegName[5] == 'w')
+				return RegName + 6;
+			else if (RegName[3] == 'p')
+				return RegName + 4;
+			else
+				return RegName + 3;
+		}
+		break;
+	}
+
+	return RegName;
+}
+
+#endif // CS_PPC_REGISTERINFO_H